1 // SPDX-License-Identifier: GPL-2.0+
3 * SuperH SCIF device driver.
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
6 * Copyright (C) 2002 - 2008 Paul Mundt
14 #include <asm/processor.h>
16 #include <linux/compiler.h>
17 #include <dm/platform_data/serial_sh.h>
18 #include "serial_sh.h"
20 DECLARE_GLOBAL_DATA_PTR;
22 #if defined(CONFIG_CPU_SH7760) || \
23 defined(CONFIG_CPU_SH7780) || \
24 defined(CONFIG_CPU_SH7786)
25 static int scif_rxfill(struct uart_port *port)
27 return sci_in(port, SCRFDR) & 0xff;
29 #elif defined(CONFIG_CPU_SH7763)
30 static int scif_rxfill(struct uart_port *port)
32 if ((port->mapbase == 0xffe00000) ||
33 (port->mapbase == 0xffe08000)) {
35 return sci_in(port, SCRFDR) & 0xff;
38 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
41 #elif defined(CONFIG_ARCH_SH7372)
42 static int scif_rxfill(struct uart_port *port)
44 if (port->type == PORT_SCIFA)
45 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
47 return sci_in(port, SCRFDR);
50 static int scif_rxfill(struct uart_port *port)
52 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
56 static void sh_serial_init_generic(struct uart_port *port)
58 sci_out(port, SCSCR , SCSCR_INIT(port));
59 sci_out(port, SCSCR , SCSCR_INIT(port));
60 sci_out(port, SCSMR, 0);
61 sci_out(port, SCSMR, 0);
62 sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
64 sci_out(port, SCFCR, 0);
65 #if defined(CONFIG_RZA1)
66 sci_out(port, SCSPTR, 0x0003);
71 sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
73 if (port->clk_mode == EXT_CLK) {
74 unsigned short dl = DL_VALUE(baudrate, clk);
75 sci_out(port, DL, dl);
76 /* Need wait: Clock * 1/dl * 1/16 */
77 udelay((1000000 * dl * 16 / clk) * 1000 + 1);
79 sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
83 static void handle_error(struct uart_port *port)
86 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
88 sci_out(port, SCLSR, 0x00);
91 static int serial_raw_putc(struct uart_port *port, const char c)
93 /* Tx fifo is empty */
94 if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
97 sci_out(port, SCxTDR, c);
98 sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
103 static int serial_rx_fifo_level(struct uart_port *port)
105 return scif_rxfill(port);
108 static int sh_serial_tstc_generic(struct uart_port *port)
110 if (sci_in(port, SCxSR) & SCIF_ERRORS) {
115 return serial_rx_fifo_level(port) ? 1 : 0;
118 static int serial_getc_check(struct uart_port *port)
120 unsigned short status;
122 status = sci_in(port, SCxSR);
124 if (status & SCIF_ERRORS)
126 if (sci_in(port, SCLSR) & SCxSR_ORER(port))
128 return status & (SCIF_DR | SCxSR_RDxF(port));
131 static int sh_serial_getc_generic(struct uart_port *port)
133 unsigned short status;
136 if (!serial_getc_check(port))
139 ch = sci_in(port, SCxRDR);
140 status = sci_in(port, SCxSR);
142 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
144 if (status & SCIF_ERRORS)
147 if (sci_in(port, SCLSR) & SCxSR_ORER(port))
153 #if CONFIG_IS_ENABLED(DM_SERIAL)
155 static int sh_serial_pending(struct udevice *dev, bool input)
157 struct uart_port *priv = dev_get_priv(dev);
159 return sh_serial_tstc_generic(priv);
162 static int sh_serial_putc(struct udevice *dev, const char ch)
164 struct uart_port *priv = dev_get_priv(dev);
166 return serial_raw_putc(priv, ch);
169 static int sh_serial_getc(struct udevice *dev)
171 struct uart_port *priv = dev_get_priv(dev);
173 return sh_serial_getc_generic(priv);
176 static int sh_serial_setbrg(struct udevice *dev, int baudrate)
178 struct sh_serial_platdata *plat = dev_get_platdata(dev);
179 struct uart_port *priv = dev_get_priv(dev);
181 sh_serial_setbrg_generic(priv, plat->clk, baudrate);
186 static int sh_serial_probe(struct udevice *dev)
188 struct sh_serial_platdata *plat = dev_get_platdata(dev);
189 struct uart_port *priv = dev_get_priv(dev);
191 priv->membase = (unsigned char *)plat->base;
192 priv->mapbase = plat->base;
193 priv->type = plat->type;
194 priv->clk_mode = plat->clk_mode;
196 sh_serial_init_generic(priv);
201 static const struct dm_serial_ops sh_serial_ops = {
202 .putc = sh_serial_putc,
203 .pending = sh_serial_pending,
204 .getc = sh_serial_getc,
205 .setbrg = sh_serial_setbrg,
208 #if CONFIG_IS_ENABLED(OF_CONTROL)
209 static const struct udevice_id sh_serial_id[] ={
210 {.compatible = "renesas,sci", .data = PORT_SCI},
211 {.compatible = "renesas,scif", .data = PORT_SCIF},
212 {.compatible = "renesas,scifa", .data = PORT_SCIFA},
216 static int sh_serial_ofdata_to_platdata(struct udevice *dev)
218 struct sh_serial_platdata *plat = dev_get_platdata(dev);
219 struct clk sh_serial_clk;
223 addr = devfdt_get_addr(dev);
229 ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
231 ret = clk_enable(&sh_serial_clk);
233 plat->clk = clk_get_rate(&sh_serial_clk);
235 plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
239 plat->type = dev_get_driver_data(dev);
244 U_BOOT_DRIVER(serial_sh) = {
247 .of_match = of_match_ptr(sh_serial_id),
248 .ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata),
249 .platdata_auto_alloc_size = sizeof(struct sh_serial_platdata),
250 .probe = sh_serial_probe,
251 .ops = &sh_serial_ops,
252 #if !CONFIG_IS_ENABLED(OF_CONTROL)
253 .flags = DM_FLAG_PRE_RELOC,
255 .priv_auto_alloc_size = sizeof(struct uart_port),
258 #else /* CONFIG_DM_SERIAL */
260 #if defined(CONFIG_CONS_SCIF0)
261 # define SCIF_BASE SCIF0_BASE
262 #elif defined(CONFIG_CONS_SCIF1)
263 # define SCIF_BASE SCIF1_BASE
264 #elif defined(CONFIG_CONS_SCIF2)
265 # define SCIF_BASE SCIF2_BASE
266 #elif defined(CONFIG_CONS_SCIF3)
267 # define SCIF_BASE SCIF3_BASE
268 #elif defined(CONFIG_CONS_SCIF4)
269 # define SCIF_BASE SCIF4_BASE
270 #elif defined(CONFIG_CONS_SCIF5)
271 # define SCIF_BASE SCIF5_BASE
272 #elif defined(CONFIG_CONS_SCIF6)
273 # define SCIF_BASE SCIF6_BASE
274 #elif defined(CONFIG_CONS_SCIF7)
275 # define SCIF_BASE SCIF7_BASE
276 #elif defined(CONFIG_CONS_SCIFA0)
277 # define SCIF_BASE SCIFA0_BASE
279 # error "Default SCIF doesn't set....."
282 #if defined(CONFIG_SCIF_A)
283 #define SCIF_BASE_PORT PORT_SCIFA
284 #elif defined(CONFIG_SCI)
285 #define SCIF_BASE_PORT PORT_SCI
287 #define SCIF_BASE_PORT PORT_SCIF
290 static struct uart_port sh_sci = {
291 .membase = (unsigned char *)SCIF_BASE,
292 .mapbase = SCIF_BASE,
293 .type = SCIF_BASE_PORT,
294 #ifdef CONFIG_SCIF_USE_EXT_CLK
299 static void sh_serial_setbrg(void)
301 DECLARE_GLOBAL_DATA_PTR;
302 struct uart_port *port = &sh_sci;
304 sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
307 static int sh_serial_init(void)
309 struct uart_port *port = &sh_sci;
311 sh_serial_init_generic(port);
317 static void sh_serial_putc(const char c)
319 struct uart_port *port = &sh_sci;
323 if (serial_raw_putc(port, '\r') != -EAGAIN)
328 if (serial_raw_putc(port, c) != -EAGAIN)
333 static int sh_serial_tstc(void)
335 struct uart_port *port = &sh_sci;
337 return sh_serial_tstc_generic(port);
340 static int sh_serial_getc(void)
342 struct uart_port *port = &sh_sci;
346 ch = sh_serial_getc_generic(port);
354 static struct serial_device sh_serial_drv = {
356 .start = sh_serial_init,
358 .setbrg = sh_serial_setbrg,
359 .putc = sh_serial_putc,
360 .puts = default_serial_puts,
361 .getc = sh_serial_getc,
362 .tstc = sh_serial_tstc,
365 void sh_serial_initialize(void)
367 serial_register(&sh_serial_drv);
370 __weak struct serial_device *default_serial_console(void)
372 return &sh_serial_drv;
374 #endif /* CONFIG_DM_SERIAL */