2 * SuperH SCIF device driver.
3 * Copyright (c) 2007 Nobuhiro Iwamatsu
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <asm/processor.h>
23 #ifdef CFG_SCIF_CONSOLE
25 #if defined (CONFIG_CONS_SCIF0)
26 #define SCIF_BASE SCIF0_BASE
27 #elif defined (CONFIG_CONS_SCIF1)
28 #define SCIF_BASE SCIF1_BASE
30 #error "Default SCIF doesn't set....."
33 #define SCSMR (vu_short *)(SCIF_BASE + 0x0)
34 #define SCBRR (vu_char *)(SCIF_BASE + 0x4)
35 #define SCSCR (vu_short *)(SCIF_BASE + 0x8)
36 #define SCFTDR (vu_char *)(SCIF_BASE + 0xC)
37 #define SCFSR (vu_short *)(SCIF_BASE + 0x10)
38 #define SCFRDR (vu_char *)(SCIF_BASE + 0x14)
39 #define SCFCR (vu_short *)(SCIF_BASE + 0x18)
40 #define SCFDR (vu_short *)(SCIF_BASE + 0x1C)
41 #if defined(CONFIG_SH4A)
42 #define SCRFDR (vu_short *)(SCIF_BASE + 0x20)
43 #define SCSPTR (vu_short *)(SCIF_BASE + 0x24)
44 #define SCLSR (vu_short *)(SCIF_BASE + 0x28)
45 #define SCRER (vu_short *)(SCIF_BASE + 0x2C)
46 #elif defined (CONFIG_SH4)
47 #define SCSPTR (vu_short *)(SCIF_BASE + 0x20)
48 #define SCLSR (vu_short *)(SCIF_BASE + 0x24)
49 #elif defined (CONFIG_SH3)
50 #define SCLSR (vu_short *)(SCIF_BASE + 0x24)
53 #define SCR_RE (1 << 4)
54 #define SCR_TE (1 << 5)
55 #define FCR_RFRST (1 << 1) /* RFCL */
56 #define FCR_TFRST (1 << 2) /* TFCL */
57 #define FSR_DR (1 << 0)
58 #define FSR_RDF (1 << 1)
59 #define FSR_FER (1 << 3)
60 #define FSR_BRK (1 << 4)
61 #define FSR_FER (1 << 3)
62 #define FSR_TEND (1 << 6)
63 #define FSR_ER (1 << 7)
65 /*----------------------------------------------------------------------*/
67 void serial_setbrg (void)
69 DECLARE_GLOBAL_DATA_PTR;
70 int divisor = gd->baudrate * 32;
72 *SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) /
73 (gd->baudrate * 32) - 1;
76 int serial_init (void)
78 *SCSCR = (SCR_RE | SCR_TE);
81 *SCFCR = (FCR_RFRST | FCR_TFRST);
89 static int serial_tx_fifo_level (void)
91 return (*SCFDR >> 8) & 0x1F;
94 static int serial_rx_fifo_level (void)
96 return (*SCFDR >> 0) & 0x1F;
99 void serial_raw_putc (const char c)
101 unsigned int fsr_bits_to_clear;
104 if (*SCFSR & FSR_TEND) { /* Tx fifo is empty */
105 fsr_bits_to_clear = FSR_TEND;
111 if (fsr_bits_to_clear != 0)
112 *SCFSR &= ~fsr_bits_to_clear;
115 void serial_putc (const char c)
118 serial_raw_putc ('\r');
122 void serial_puts (const char *s)
125 while ((c = *s++) != 0)
129 int serial_tstc (void)
131 return serial_rx_fifo_level() ? 1 : 0;
134 #define FSR_ERR_CLEAR 0x0063
135 #define RDRF_CLEAR 0x00fc
137 void handle_error( void ){
140 *SCFSR = FSR_ERR_CLEAR ;
145 int serial_getc_check( void ){
146 unsigned short status;
150 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
152 if( *SCLSR & LSR_ORER )
154 return (status & ( FSR_DR | FSR_RDF ));
157 int serial_getc (void)
159 unsigned short status ;
161 while(!serial_getc_check());
166 *SCFSR = RDRF_CLEAR ;
168 if (status & (FSR_FER | FSR_FER | FSR_ER | FSR_BRK))
171 if( *SCLSR & LSR_ORER )
177 #endif /* CFG_SCIF_CONSOLE */