drivers/serial/serial_pl01x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2000
   4  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
   5  *
   6  * (C) Copyright 2004
   7  * ARM Ltd.
   8  * Philippe Robin, <philippe.robin@arm.com>
   9  */
  10
  11 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
  12
  13 #include <common.h>
  14 /* For get_bus_freq() */
  15 #include <clock_legacy.h>
  16 #include <dm.h>
  17 #include <clk.h>
  18 #include <errno.h>
  19 #include <watchdog.h>
  20 #include <asm/io.h>
  21 #include <serial.h>
  22 #include <dm/device_compat.h>
  23 #include <dm/platform_data/serial_pl01x.h>
  24 #include <linux/compiler.h>
  25 #include "serial_pl01x_internal.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifndef CONFIG_DM_SERIAL
  30
  31 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
  32 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
  33 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
  34 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
  35
  36 #endif
  37
  38 static int pl01x_putc(struct pl01x_regs *regs, char c)
  39 {
  40         /* Wait until there is space in the FIFO */
  41         if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
  42                 return -EAGAIN;
  43
  44         /* Send the character */
  45         writel(c, &regs->dr);
  46
  47         return 0;
  48 }
  49
  50 static int pl01x_getc(struct pl01x_regs *regs)
  51 {
  52         unsigned int data;
  53
  54         /* Wait until there is data in the FIFO */
  55         if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
  56                 return -EAGAIN;
  57
  58         data = readl(&regs->dr);
  59
  60         /* Check for an error flag */
  61         if (data & 0xFFFFFF00) {
  62                 /* Clear the error */
  63                 writel(0xFFFFFFFF, &regs->ecr);
  64                 return -1;
  65         }
  66
  67         return (int) data;
  68 }
  69
  70 static int pl01x_tstc(struct pl01x_regs *regs)
  71 {
  72         WATCHDOG_RESET();
  73         return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
  74 }
  75
  76 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
  77                                      enum pl01x_type type)
  78 {
  79         switch (type) {
  80         case TYPE_PL010:
  81                 /* disable everything */
  82                 writel(0, &regs->pl010_cr);
  83                 break;
  84         case TYPE_PL011:
  85                 /* disable everything */
  86                 writel(0, &regs->pl011_cr);
  87                 break;
  88         default:
  89                 return -EINVAL;
  90         }
  91
  92         return 0;
  93 }
  94
  95 static int pl011_set_line_control(struct pl01x_regs *regs)
  96 {
  97         unsigned int lcr;
  98         /*
  99          * Internal update of baud rate register require line
 100          * control register write
 101          */
 102         lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
 103         writel(lcr, &regs->pl011_lcrh);
 104         return 0;
 105 }
 106
 107 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 108                                 int clock, int baudrate)
 109 {
 110         switch (type) {
 111         case TYPE_PL010: {
 112                 unsigned int divisor;
 113
 114                 /* disable everything */
 115                 writel(0, &regs->pl010_cr);
 116
 117                 switch (baudrate) {
 118                 case 9600:
 119                         divisor = UART_PL010_BAUD_9600;
 120                         break;
 121                 case 19200:
 122                         divisor = UART_PL010_BAUD_19200;
 123                         break;
 124                 case 38400:
 125                         divisor = UART_PL010_BAUD_38400;
 126                         break;
 127                 case 57600:
 128                         divisor = UART_PL010_BAUD_57600;
 129                         break;
 130                 case 115200:
 131                         divisor = UART_PL010_BAUD_115200;
 132                         break;
 133                 default:
 134                         divisor = UART_PL010_BAUD_38400;
 135                 }
 136
 137                 writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
 138                 writel(divisor & 0xff, &regs->pl010_lcrl);
 139
 140                 /*
 141                  * Set line control for the PL010 to be 8 bits, 1 stop bit,
 142                  * no parity, fifo enabled
 143                  */
 144                 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
 145                        &regs->pl010_lcrh);
 146                 /* Finally, enable the UART */
 147                 writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
 148                 break;
 149         }
 150         case TYPE_PL011: {
 151                 unsigned int temp;
 152                 unsigned int divider;
 153                 unsigned int remainder;
 154                 unsigned int fraction;
 155
 156                 /* Without a valid clock rate we cannot set up the baudrate. */
 157                 if (clock) {
 158                         /*
 159                          * Set baud rate
 160                          *
 161                          * IBRD = UART_CLK / (16 * BAUD_RATE)
 162                          * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
 163                          *              / (16 * BAUD_RATE))
 164                          */
 165                         temp = 16 * baudrate;
 166                         divider = clock / temp;
 167                         remainder = clock % temp;
 168                         temp = (8 * remainder) / baudrate;
 169                         fraction = (temp >> 1) + (temp & 1);
 170
 171                         writel(divider, &regs->pl011_ibrd);
 172                         writel(fraction, &regs->pl011_fbrd);
 173                 }
 174
 175                 pl011_set_line_control(regs);
 176                 /* Finally, enable the UART */
 177                 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
 178                        UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
 179                 break;
 180         }
 181         default:
 182                 return -EINVAL;
 183         }
 184
 185         return 0;
 186 }
 187
 188 #ifndef CONFIG_DM_SERIAL
 189 static void pl01x_serial_init_baud(int baudrate)
 190 {
 191         int clock = 0;
 192
 193 #if defined(CONFIG_PL010_SERIAL)
 194         pl01x_type = TYPE_PL010;
 195 #elif defined(CONFIG_PL011_SERIAL)
 196         pl01x_type = TYPE_PL011;
 197         clock = CONFIG_PL011_CLOCK;
 198 #endif
 199         base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
 200
 201         pl01x_generic_serial_init(base_regs, pl01x_type);
 202         pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
 203 }
 204
 205 /*
 206  * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
 207  * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
 208  * Versatile PB has four UARTs.
 209  */
 210 int pl01x_serial_init(void)
 211 {
 212         pl01x_serial_init_baud(CONFIG_BAUDRATE);
 213
 214         return 0;
 215 }
 216
 217 static void pl01x_serial_putc(const char c)
 218 {
 219         if (c == '\n')
 220                 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
 221
 222         while (pl01x_putc(base_regs, c) == -EAGAIN);
 223 }
 224
 225 static int pl01x_serial_getc(void)
 226 {
 227         while (1) {
 228                 int ch = pl01x_getc(base_regs);
 229
 230                 if (ch == -EAGAIN) {
 231                         WATCHDOG_RESET();
 232                         continue;
 233                 }
 234
 235                 return ch;
 236         }
 237 }
 238
 239 static int pl01x_serial_tstc(void)
 240 {
 241         return pl01x_tstc(base_regs);
 242 }
 243
 244 static void pl01x_serial_setbrg(void)
 245 {
 246         /*
 247          * Flush FIFO and wait for non-busy before changing baudrate to avoid
 248          * crap in console
 249          */
 250         while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
 251                 WATCHDOG_RESET();
 252         while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
 253                 WATCHDOG_RESET();
 254         pl01x_serial_init_baud(gd->baudrate);
 255 }
 256
 257 static struct serial_device pl01x_serial_drv = {
 258         .name   = "pl01x_serial",
 259         .start  = pl01x_serial_init,
 260         .stop   = NULL,
 261         .setbrg = pl01x_serial_setbrg,
 262         .putc   = pl01x_serial_putc,
 263         .puts   = default_serial_puts,
 264         .getc   = pl01x_serial_getc,
 265         .tstc   = pl01x_serial_tstc,
 266 };
 267
 268 void pl01x_serial_initialize(void)
 269 {
 270         serial_register(&pl01x_serial_drv);
 271 }
 272
 273 __weak struct serial_device *default_serial_console(void)
 274 {
 275         return &pl01x_serial_drv;
 276 }
 277
 278 #endif /* nCONFIG_DM_SERIAL */
 279
 280 #ifdef CONFIG_DM_SERIAL
 281
 282 int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
 283 {
 284         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 285         struct pl01x_priv *priv = dev_get_priv(dev);
 286
 287         if (!plat->skip_init) {
 288                 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
 289                                      baudrate);
 290         }
 291
 292         return 0;
 293 }
 294
 295 int pl01x_serial_probe(struct udevice *dev)
 296 {
 297         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 298         struct pl01x_priv *priv = dev_get_priv(dev);
 299
 300         priv->regs = (struct pl01x_regs *)plat->base;
 301         priv->type = plat->type;
 302         if (!plat->skip_init)
 303                 return pl01x_generic_serial_init(priv->regs, priv->type);
 304         else
 305                 return 0;
 306 }
 307
 308 int pl01x_serial_getc(struct udevice *dev)
 309 {
 310         struct pl01x_priv *priv = dev_get_priv(dev);
 311
 312         return pl01x_getc(priv->regs);
 313 }
 314
 315 int pl01x_serial_putc(struct udevice *dev, const char ch)
 316 {
 317         struct pl01x_priv *priv = dev_get_priv(dev);
 318
 319         return pl01x_putc(priv->regs, ch);
 320 }
 321
 322 int pl01x_serial_pending(struct udevice *dev, bool input)
 323 {
 324         struct pl01x_priv *priv = dev_get_priv(dev);
 325         unsigned int fr = readl(&priv->regs->fr);
 326
 327         if (input)
 328                 return pl01x_tstc(priv->regs);
 329         else
 330                 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
 331 }
 332
 333 static const struct dm_serial_ops pl01x_serial_ops = {
 334         .putc = pl01x_serial_putc,
 335         .pending = pl01x_serial_pending,
 336         .getc = pl01x_serial_getc,
 337         .setbrg = pl01x_serial_setbrg,
 338 };
 339
 340 #if CONFIG_IS_ENABLED(OF_CONTROL)
 341 static const struct udevice_id pl01x_serial_id[] ={
 342         {.compatible = "arm,pl011", .data = TYPE_PL011},
 343         {.compatible = "arm,pl010", .data = TYPE_PL010},
 344         {}
 345 };
 346
 347 #ifndef CONFIG_PL011_CLOCK
 348 #define CONFIG_PL011_CLOCK 0
 349 #endif
 350
 351 int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
 352 {
 353         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 354         struct clk clk;
 355         fdt_addr_t addr;
 356         int ret;
 357
 358         addr = dev_read_addr(dev);
 359         if (addr == FDT_ADDR_T_NONE)
 360                 return -EINVAL;
 361
 362         plat->base = addr;
 363         plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
 364         ret = clk_get_by_index(dev, 0, &clk);
 365         if (!ret) {
 366                 ret = clk_enable(&clk);
 367                 if (ret && ret != -ENOSYS) {
 368                         dev_err(dev, "failed to enable clock\n");
 369                         return ret;
 370                 }
 371
 372                 plat->clock = clk_get_rate(&clk);
 373                 if (IS_ERR_VALUE(plat->clock)) {
 374                         dev_err(dev, "failed to get rate\n");
 375                         return plat->clock;
 376                 }
 377                 debug("%s: CLK %d\n", __func__, plat->clock);
 378         }
 379         plat->type = dev_get_driver_data(dev);
 380         plat->skip_init = dev_read_bool(dev, "skip-init");
 381
 382         return 0;
 383 }
 384 #endif
 385
 386 U_BOOT_DRIVER(serial_pl01x) = {
 387         .name   = "serial_pl01x",
 388         .id     = UCLASS_SERIAL,
 389         .of_match = of_match_ptr(pl01x_serial_id),
 390         .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
 391         .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
 392         .probe = pl01x_serial_probe,
 393         .ops    = &pl01x_serial_ops,
 394         .flags = DM_FLAG_PRE_RELOC,
 395         .priv_auto_alloc_size = sizeof(struct pl01x_priv),
 396 };
 397
 398 #endif
 399
 400 #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
 401
 402 #include <debug_uart.h>
 403
 404 static void _debug_uart_init(void)
 405 {
 406 #ifndef CONFIG_DEBUG_UART_SKIP_INIT
 407         struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 408         enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
 409                                 TYPE_PL011 : TYPE_PL010;
 410
 411         pl01x_generic_serial_init(regs, type);
 412         pl01x_generic_setbrg(regs, type,
 413                              CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
 414 #endif
 415 }
 416
 417 static inline void _debug_uart_putc(int ch)
 418 {
 419         struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 420
 421         pl01x_putc(regs, ch);
 422 }
 423
 424 DEBUG_UART_FUNCS
 425
 426 #endif