drivers/serial/serial_pl01x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2000
   4  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
   5  *
   6  * (C) Copyright 2004
   7  * ARM Ltd.
   8  * Philippe Robin, <philippe.robin@arm.com>
   9  */
  10
  11 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
  12
  13 #include <common.h>
  14 #include <asm/global_data.h>
  15 /* For get_bus_freq() */
  16 #include <clock_legacy.h>
  17 #include <dm.h>
  18 #include <clk.h>
  19 #include <errno.h>
  20 #include <watchdog.h>
  21 #include <asm/io.h>
  22 #include <serial.h>
  23 #include <dm/device_compat.h>
  24 #include <dm/platform_data/serial_pl01x.h>
  25 #include <linux/compiler.h>
  26 #include "serial_pl01x_internal.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #ifndef CONFIG_DM_SERIAL
  31
  32 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
  33 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
  34 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
  35 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
  36
  37 #endif
  38
  39 static int pl01x_putc(struct pl01x_regs *regs, char c)
  40 {
  41         /* Wait until there is space in the FIFO */
  42         if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
  43                 return -EAGAIN;
  44
  45         /* Send the character */
  46         writel(c, &regs->dr);
  47
  48         return 0;
  49 }
  50
  51 static int pl01x_getc(struct pl01x_regs *regs)
  52 {
  53         unsigned int data;
  54
  55         /* Wait until there is data in the FIFO */
  56         if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
  57                 return -EAGAIN;
  58
  59         data = readl(&regs->dr);
  60
  61         /* Check for an error flag */
  62         if (data & 0xFFFFFF00) {
  63                 /* Clear the error */
  64                 writel(0xFFFFFFFF, &regs->ecr);
  65                 return -1;
  66         }
  67
  68         return (int) data;
  69 }
  70
  71 static int pl01x_tstc(struct pl01x_regs *regs)
  72 {
  73         WATCHDOG_RESET();
  74         return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
  75 }
  76
  77 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
  78                                      enum pl01x_type type)
  79 {
  80         switch (type) {
  81         case TYPE_PL010:
  82                 /* disable everything */
  83                 writel(0, &regs->pl010_cr);
  84                 break;
  85         case TYPE_PL011:
  86                 /* disable everything */
  87                 writel(0, &regs->pl011_cr);
  88                 break;
  89         default:
  90                 return -EINVAL;
  91         }
  92
  93         return 0;
  94 }
  95
  96 static int pl011_set_line_control(struct pl01x_regs *regs)
  97 {
  98         unsigned int lcr;
  99         /*
 100          * Internal update of baud rate register require line
 101          * control register write
 102          */
 103         lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
 104         writel(lcr, &regs->pl011_lcrh);
 105         return 0;
 106 }
 107
 108 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 109                                 int clock, int baudrate)
 110 {
 111         switch (type) {
 112         case TYPE_PL010: {
 113                 unsigned int divisor;
 114
 115                 /* disable everything */
 116                 writel(0, &regs->pl010_cr);
 117
 118                 switch (baudrate) {
 119                 case 9600:
 120                         divisor = UART_PL010_BAUD_9600;
 121                         break;
 122                 case 19200:
 123                         divisor = UART_PL010_BAUD_19200;
 124                         break;
 125                 case 38400:
 126                         divisor = UART_PL010_BAUD_38400;
 127                         break;
 128                 case 57600:
 129                         divisor = UART_PL010_BAUD_57600;
 130                         break;
 131                 case 115200:
 132                         divisor = UART_PL010_BAUD_115200;
 133                         break;
 134                 default:
 135                         divisor = UART_PL010_BAUD_38400;
 136                 }
 137
 138                 writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
 139                 writel(divisor & 0xff, &regs->pl010_lcrl);
 140
 141                 /*
 142                  * Set line control for the PL010 to be 8 bits, 1 stop bit,
 143                  * no parity, fifo enabled
 144                  */
 145                 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
 146                        &regs->pl010_lcrh);
 147                 /* Finally, enable the UART */
 148                 writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
 149                 break;
 150         }
 151         case TYPE_PL011: {
 152                 unsigned int temp;
 153                 unsigned int divider;
 154                 unsigned int remainder;
 155                 unsigned int fraction;
 156
 157                 /* Without a valid clock rate we cannot set up the baudrate. */
 158                 if (clock) {
 159                         /*
 160                          * Set baud rate
 161                          *
 162                          * IBRD = UART_CLK / (16 * BAUD_RATE)
 163                          * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
 164                          *              / (16 * BAUD_RATE))
 165                          */
 166                         temp = 16 * baudrate;
 167                         divider = clock / temp;
 168                         remainder = clock % temp;
 169                         temp = (8 * remainder) / baudrate;
 170                         fraction = (temp >> 1) + (temp & 1);
 171
 172                         writel(divider, &regs->pl011_ibrd);
 173                         writel(fraction, &regs->pl011_fbrd);
 174                 }
 175
 176                 pl011_set_line_control(regs);
 177                 /* Finally, enable the UART */
 178                 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
 179                        UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
 180                 break;
 181         }
 182         default:
 183                 return -EINVAL;
 184         }
 185
 186         return 0;
 187 }
 188
 189 #ifndef CONFIG_DM_SERIAL
 190 static void pl01x_serial_init_baud(int baudrate)
 191 {
 192         int clock = 0;
 193
 194 #if defined(CONFIG_PL010_SERIAL)
 195         pl01x_type = TYPE_PL010;
 196 #elif defined(CONFIG_PL011_SERIAL)
 197         pl01x_type = TYPE_PL011;
 198         clock = CONFIG_PL011_CLOCK;
 199 #endif
 200         base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
 201
 202         pl01x_generic_serial_init(base_regs, pl01x_type);
 203         pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
 204 }
 205
 206 /*
 207  * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
 208  * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
 209  * Versatile PB has four UARTs.
 210  */
 211 int pl01x_serial_init(void)
 212 {
 213         pl01x_serial_init_baud(CONFIG_BAUDRATE);
 214
 215         return 0;
 216 }
 217
 218 static void pl01x_serial_putc(const char c)
 219 {
 220         if (c == '\n')
 221                 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
 222
 223         while (pl01x_putc(base_regs, c) == -EAGAIN);
 224 }
 225
 226 static int pl01x_serial_getc(void)
 227 {
 228         while (1) {
 229                 int ch = pl01x_getc(base_regs);
 230
 231                 if (ch == -EAGAIN) {
 232                         WATCHDOG_RESET();
 233                         continue;
 234                 }
 235
 236                 return ch;
 237         }
 238 }
 239
 240 static int pl01x_serial_tstc(void)
 241 {
 242         return pl01x_tstc(base_regs);
 243 }
 244
 245 static void pl01x_serial_setbrg(void)
 246 {
 247         /*
 248          * Flush FIFO and wait for non-busy before changing baudrate to avoid
 249          * crap in console
 250          */
 251         while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
 252                 WATCHDOG_RESET();
 253         while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
 254                 WATCHDOG_RESET();
 255         pl01x_serial_init_baud(gd->baudrate);
 256 }
 257
 258 static struct serial_device pl01x_serial_drv = {
 259         .name   = "pl01x_serial",
 260         .start  = pl01x_serial_init,
 261         .stop   = NULL,
 262         .setbrg = pl01x_serial_setbrg,
 263         .putc   = pl01x_serial_putc,
 264         .puts   = default_serial_puts,
 265         .getc   = pl01x_serial_getc,
 266         .tstc   = pl01x_serial_tstc,
 267 };
 268
 269 void pl01x_serial_initialize(void)
 270 {
 271         serial_register(&pl01x_serial_drv);
 272 }
 273
 274 __weak struct serial_device *default_serial_console(void)
 275 {
 276         return &pl01x_serial_drv;
 277 }
 278
 279 #endif /* nCONFIG_DM_SERIAL */
 280
 281 #ifdef CONFIG_DM_SERIAL
 282
 283 int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
 284 {
 285         struct pl01x_serial_plat *plat = dev_get_plat(dev);
 286         struct pl01x_priv *priv = dev_get_priv(dev);
 287
 288         if (!plat->skip_init) {
 289                 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
 290                                      baudrate);
 291         }
 292
 293         return 0;
 294 }
 295
 296 int pl01x_serial_probe(struct udevice *dev)
 297 {
 298         struct pl01x_serial_plat *plat = dev_get_plat(dev);
 299         struct pl01x_priv *priv = dev_get_priv(dev);
 300
 301         priv->regs = (struct pl01x_regs *)plat->base;
 302         priv->type = plat->type;
 303         if (!plat->skip_init)
 304                 return pl01x_generic_serial_init(priv->regs, priv->type);
 305         else
 306                 return 0;
 307 }
 308
 309 int pl01x_serial_getc(struct udevice *dev)
 310 {
 311         struct pl01x_priv *priv = dev_get_priv(dev);
 312
 313         return pl01x_getc(priv->regs);
 314 }
 315
 316 int pl01x_serial_putc(struct udevice *dev, const char ch)
 317 {
 318         struct pl01x_priv *priv = dev_get_priv(dev);
 319
 320         return pl01x_putc(priv->regs, ch);
 321 }
 322
 323 int pl01x_serial_pending(struct udevice *dev, bool input)
 324 {
 325         struct pl01x_priv *priv = dev_get_priv(dev);
 326         unsigned int fr = readl(&priv->regs->fr);
 327
 328         if (input)
 329                 return pl01x_tstc(priv->regs);
 330         else
 331                 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
 332 }
 333
 334 static const struct dm_serial_ops pl01x_serial_ops = {
 335         .putc = pl01x_serial_putc,
 336         .pending = pl01x_serial_pending,
 337         .getc = pl01x_serial_getc,
 338         .setbrg = pl01x_serial_setbrg,
 339 };
 340
 341 #if CONFIG_IS_ENABLED(OF_CONTROL)
 342 static const struct udevice_id pl01x_serial_id[] ={
 343         {.compatible = "arm,pl011", .data = TYPE_PL011},
 344         {.compatible = "arm,pl010", .data = TYPE_PL010},
 345         {}
 346 };
 347
 348 #ifndef CONFIG_PL011_CLOCK
 349 #define CONFIG_PL011_CLOCK 0
 350 #endif
 351
 352 int pl01x_serial_of_to_plat(struct udevice *dev)
 353 {
 354         struct pl01x_serial_plat *plat = dev_get_plat(dev);
 355         struct clk clk;
 356         fdt_addr_t addr;
 357         int ret;
 358
 359         addr = dev_read_addr(dev);
 360         if (addr == FDT_ADDR_T_NONE)
 361                 return -EINVAL;
 362
 363         plat->base = addr;
 364         plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
 365         ret = clk_get_by_index(dev, 0, &clk);
 366         if (!ret) {
 367                 ret = clk_enable(&clk);
 368                 if (ret && ret != -ENOSYS) {
 369                         dev_err(dev, "failed to enable clock\n");
 370                         return ret;
 371                 }
 372
 373                 plat->clock = clk_get_rate(&clk);
 374                 if (IS_ERR_VALUE(plat->clock)) {
 375                         dev_err(dev, "failed to get rate\n");
 376                         return plat->clock;
 377                 }
 378                 debug("%s: CLK %d\n", __func__, plat->clock);
 379         }
 380         plat->type = dev_get_driver_data(dev);
 381         plat->skip_init = dev_read_bool(dev, "skip-init");
 382
 383         return 0;
 384 }
 385 #endif
 386
 387 U_BOOT_DRIVER(serial_pl01x) = {
 388         .name   = "serial_pl01x",
 389         .id     = UCLASS_SERIAL,
 390         .of_match = of_match_ptr(pl01x_serial_id),
 391         .of_to_plat = of_match_ptr(pl01x_serial_of_to_plat),
 392         .plat_auto      = sizeof(struct pl01x_serial_plat),
 393         .probe = pl01x_serial_probe,
 394         .ops    = &pl01x_serial_ops,
 395         .flags = DM_FLAG_PRE_RELOC,
 396         .priv_auto      = sizeof(struct pl01x_priv),
 397 };
 398
 399 #endif
 400
 401 #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
 402
 403 #include <debug_uart.h>
 404
 405 static void _debug_uart_init(void)
 406 {
 407 #ifndef CONFIG_DEBUG_UART_SKIP_INIT
 408         struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 409         enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
 410                                 TYPE_PL011 : TYPE_PL010;
 411
 412         pl01x_generic_serial_init(regs, type);
 413         pl01x_generic_setbrg(regs, type,
 414                              CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
 415 #endif
 416 }
 417
 418 static inline void _debug_uart_putc(int ch)
 419 {
 420         struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 421
 422         pl01x_putc(regs, ch);
 423 }
 424
 425 DEBUG_UART_FUNCS
 426
 427 #endif