drivers/serial/serial_pl01x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2000
   4  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
   5  *
   6  * (C) Copyright 2004
   7  * ARM Ltd.
   8  * Philippe Robin, <philippe.robin@arm.com>
   9  */
  10
  11 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
  12
  13 #include <common.h>
  14 #include <asm/global_data.h>
  15 /* For get_bus_freq() */
  16 #include <clock_legacy.h>
  17 #include <dm.h>
  18 #include <clk.h>
  19 #include <errno.h>
  20 #include <watchdog.h>
  21 #include <asm/io.h>
  22 #include <serial.h>
  23 #include <dm/device_compat.h>
  24 #include <dm/platform_data/serial_pl01x.h>
  25 #include <linux/compiler.h>
  26 #include "serial_pl01x_internal.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 #ifndef CONFIG_DM_SERIAL
  31
  32 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
  33 static enum pl01x_type pl01x_type __section(".data");
  34 static struct pl01x_regs *base_regs __section(".data");
  35 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
  36
  37 #endif
  38
  39 static int pl01x_putc(struct pl01x_regs *regs, char c)
  40 {
  41         /* Wait until there is space in the FIFO */
  42         if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
  43                 return -EAGAIN;
  44
  45         /* Send the character */
  46         writel(c, &regs->dr);
  47
  48         return 0;
  49 }
  50
  51 static int pl01x_getc(struct pl01x_regs *regs)
  52 {
  53         unsigned int data;
  54
  55         /* Wait until there is data in the FIFO */
  56         if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
  57                 return -EAGAIN;
  58
  59         data = readl(&regs->dr);
  60
  61         /* Check for an error flag */
  62         if (data & 0xFFFFFF00) {
  63                 /* Clear the error */
  64                 writel(0xFFFFFFFF, &regs->ecr);
  65                 return -1;
  66         }
  67
  68         return (int) data;
  69 }
  70
  71 static int pl01x_tstc(struct pl01x_regs *regs)
  72 {
  73         WATCHDOG_RESET();
  74         return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
  75 }
  76
  77 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
  78                                      enum pl01x_type type)
  79 {
  80         switch (type) {
  81         case TYPE_PL010:
  82                 /* disable everything */
  83                 writel(0, &regs->pl010_cr);
  84                 break;
  85         case TYPE_PL011:
  86                 /* disable everything */
  87                 writel(0, &regs->pl011_cr);
  88                 break;
  89         default:
  90                 return -EINVAL;
  91         }
  92
  93         return 0;
  94 }
  95
  96 static int pl011_set_line_control(struct pl01x_regs *regs)
  97 {
  98         unsigned int lcr;
  99         /*
 100          * Internal update of baud rate register require line
 101          * control register write
 102          */
 103         lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
 104         writel(lcr, &regs->pl011_lcrh);
 105         return 0;
 106 }
 107
 108 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 109                                 int clock, int baudrate)
 110 {
 111         switch (type) {
 112         case TYPE_PL010: {
 113                 unsigned int divisor;
 114
 115                 /* disable everything */
 116                 writel(0, &regs->pl010_cr);
 117
 118                 switch (baudrate) {
 119                 case 9600:
 120                         divisor = UART_PL010_BAUD_9600;
 121                         break;
 122                 case 19200:
 123                         divisor = UART_PL010_BAUD_19200;
 124                         break;
 125                 case 38400:
 126                         divisor = UART_PL010_BAUD_38400;
 127                         break;
 128                 case 57600:
 129                         divisor = UART_PL010_BAUD_57600;
 130                         break;
 131                 case 115200:
 132                         divisor = UART_PL010_BAUD_115200;
 133                         break;
 134                 default:
 135                         divisor = UART_PL010_BAUD_38400;
 136                 }
 137
 138                 writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
 139                 writel(divisor & 0xff, &regs->pl010_lcrl);
 140
 141                 /*
 142                  * Set line control for the PL010 to be 8 bits, 1 stop bit,
 143                  * no parity, fifo enabled
 144                  */
 145                 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
 146                        &regs->pl010_lcrh);
 147                 /* Finally, enable the UART */
 148                 writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
 149                 break;
 150         }
 151         case TYPE_PL011: {
 152                 unsigned int temp;
 153                 unsigned int divider;
 154                 unsigned int remainder;
 155                 unsigned int fraction;
 156
 157                 /* Without a valid clock rate we cannot set up the baudrate. */
 158                 if (clock) {
 159                         /*
 160                          * Set baud rate
 161                          *
 162                          * IBRD = UART_CLK / (16 * BAUD_RATE)
 163                          * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
 164                          *              / (16 * BAUD_RATE))
 165                          */
 166                         temp = 16 * baudrate;
 167                         divider = clock / temp;
 168                         remainder = clock % temp;
 169                         temp = (8 * remainder) / baudrate;
 170                         fraction = (temp >> 1) + (temp & 1);
 171
 172                         writel(divider, &regs->pl011_ibrd);
 173                         writel(fraction, &regs->pl011_fbrd);
 174                 }
 175
 176                 pl011_set_line_control(regs);
 177                 /* Finally, enable the UART */
 178                 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
 179                        UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
 180                 break;
 181         }
 182         default:
 183                 return -EINVAL;
 184         }
 185
 186         return 0;
 187 }
 188
 189 #ifndef CONFIG_DM_SERIAL
 190 static void pl01x_serial_init_baud(int baudrate)
 191 {
 192         int clock = 0;
 193
 194 #if defined(CONFIG_PL011_SERIAL)
 195         pl01x_type = TYPE_PL011;
 196         clock = CONFIG_PL011_CLOCK;
 197 #endif
 198         base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
 199
 200         pl01x_generic_serial_init(base_regs, pl01x_type);
 201         pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
 202 }
 203
 204 /*
 205  * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
 206  * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
 207  * Versatile PB has four UARTs.
 208  */
 209 int pl01x_serial_init(void)
 210 {
 211         pl01x_serial_init_baud(CONFIG_BAUDRATE);
 212
 213         return 0;
 214 }
 215
 216 static void pl01x_serial_putc(const char c)
 217 {
 218         if (c == '\n')
 219                 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
 220
 221         while (pl01x_putc(base_regs, c) == -EAGAIN);
 222 }
 223
 224 static int pl01x_serial_getc(void)
 225 {
 226         while (1) {
 227                 int ch = pl01x_getc(base_regs);
 228
 229                 if (ch == -EAGAIN) {
 230                         WATCHDOG_RESET();
 231                         continue;
 232                 }
 233
 234                 return ch;
 235         }
 236 }
 237
 238 static int pl01x_serial_tstc(void)
 239 {
 240         return pl01x_tstc(base_regs);
 241 }
 242
 243 static void pl01x_serial_setbrg(void)
 244 {
 245         /*
 246          * Flush FIFO and wait for non-busy before changing baudrate to avoid
 247          * crap in console
 248          */
 249         while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
 250                 WATCHDOG_RESET();
 251         while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
 252                 WATCHDOG_RESET();
 253         pl01x_serial_init_baud(gd->baudrate);
 254 }
 255
 256 static struct serial_device pl01x_serial_drv = {
 257         .name   = "pl01x_serial",
 258         .start  = pl01x_serial_init,
 259         .stop   = NULL,
 260         .setbrg = pl01x_serial_setbrg,
 261         .putc   = pl01x_serial_putc,
 262         .puts   = default_serial_puts,
 263         .getc   = pl01x_serial_getc,
 264         .tstc   = pl01x_serial_tstc,
 265 };
 266
 267 void pl01x_serial_initialize(void)
 268 {
 269         serial_register(&pl01x_serial_drv);
 270 }
 271
 272 __weak struct serial_device *default_serial_console(void)
 273 {
 274         return &pl01x_serial_drv;
 275 }
 276
 277 #endif /* nCONFIG_DM_SERIAL */
 278
 279 #ifdef CONFIG_DM_SERIAL
 280
 281 int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
 282 {
 283         struct pl01x_serial_plat *plat = dev_get_plat(dev);
 284         struct pl01x_priv *priv = dev_get_priv(dev);
 285
 286         if (!plat->skip_init) {
 287                 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
 288                                      baudrate);
 289         }
 290
 291         return 0;
 292 }
 293
 294 int pl01x_serial_probe(struct udevice *dev)
 295 {
 296         struct pl01x_serial_plat *plat = dev_get_plat(dev);
 297         struct pl01x_priv *priv = dev_get_priv(dev);
 298
 299         priv->regs = (struct pl01x_regs *)plat->base;
 300         priv->type = plat->type;
 301         if (!plat->skip_init)
 302                 return pl01x_generic_serial_init(priv->regs, priv->type);
 303         else
 304                 return 0;
 305 }
 306
 307 int pl01x_serial_getc(struct udevice *dev)
 308 {
 309         struct pl01x_priv *priv = dev_get_priv(dev);
 310
 311         return pl01x_getc(priv->regs);
 312 }
 313
 314 int pl01x_serial_putc(struct udevice *dev, const char ch)
 315 {
 316         struct pl01x_priv *priv = dev_get_priv(dev);
 317
 318         return pl01x_putc(priv->regs, ch);
 319 }
 320
 321 int pl01x_serial_pending(struct udevice *dev, bool input)
 322 {
 323         struct pl01x_priv *priv = dev_get_priv(dev);
 324         unsigned int fr = readl(&priv->regs->fr);
 325
 326         if (input)
 327                 return pl01x_tstc(priv->regs);
 328         else
 329                 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
 330 }
 331
 332 static const struct dm_serial_ops pl01x_serial_ops = {
 333         .putc = pl01x_serial_putc,
 334         .pending = pl01x_serial_pending,
 335         .getc = pl01x_serial_getc,
 336         .setbrg = pl01x_serial_setbrg,
 337 };
 338
 339 #if CONFIG_IS_ENABLED(OF_CONTROL)
 340 static const struct udevice_id pl01x_serial_id[] ={
 341         {.compatible = "arm,pl011", .data = TYPE_PL011},
 342         {.compatible = "arm,pl010", .data = TYPE_PL010},
 343         {}
 344 };
 345
 346 #ifndef CONFIG_PL011_CLOCK
 347 #define CONFIG_PL011_CLOCK 0
 348 #endif
 349
 350 int pl01x_serial_of_to_plat(struct udevice *dev)
 351 {
 352         struct pl01x_serial_plat *plat = dev_get_plat(dev);
 353         struct clk clk;
 354         fdt_addr_t addr;
 355         int ret;
 356
 357         addr = dev_read_addr(dev);
 358         if (addr == FDT_ADDR_T_NONE)
 359                 return -EINVAL;
 360
 361         plat->base = addr;
 362         plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
 363         ret = clk_get_by_index(dev, 0, &clk);
 364         if (!ret) {
 365                 ret = clk_enable(&clk);
 366                 if (ret && ret != -ENOSYS) {
 367                         dev_err(dev, "failed to enable clock\n");
 368                         return ret;
 369                 }
 370
 371                 plat->clock = clk_get_rate(&clk);
 372                 if (IS_ERR_VALUE(plat->clock)) {
 373                         dev_err(dev, "failed to get rate\n");
 374                         return plat->clock;
 375                 }
 376                 debug("%s: CLK %d\n", __func__, plat->clock);
 377         }
 378         plat->type = dev_get_driver_data(dev);
 379         plat->skip_init = dev_read_bool(dev, "skip-init");
 380
 381         return 0;
 382 }
 383 #endif
 384
 385 U_BOOT_DRIVER(serial_pl01x) = {
 386         .name   = "serial_pl01x",
 387         .id     = UCLASS_SERIAL,
 388         .of_match = of_match_ptr(pl01x_serial_id),
 389         .of_to_plat = of_match_ptr(pl01x_serial_of_to_plat),
 390         .plat_auto      = sizeof(struct pl01x_serial_plat),
 391         .probe = pl01x_serial_probe,
 392         .ops    = &pl01x_serial_ops,
 393         .flags = DM_FLAG_PRE_RELOC,
 394         .priv_auto      = sizeof(struct pl01x_priv),
 395 };
 396
 397 #endif
 398
 399 #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
 400
 401 #include <debug_uart.h>
 402
 403 static void _debug_uart_init(void)
 404 {
 405 #ifndef CONFIG_DEBUG_UART_SKIP_INIT
 406         struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 407         enum pl01x_type type;
 408
 409         if (IS_ENABLED(CONFIG_DEBUG_UART_PL011))
 410                 type = TYPE_PL011;
 411         else
 412                 type = TYPE_PL010;
 413
 414         pl01x_generic_serial_init(regs, type);
 415         pl01x_generic_setbrg(regs, type,
 416                              CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
 417 #endif
 418 }
 419
 420 static inline void _debug_uart_putc(int ch)
 421 {
 422         struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 423
 424         while (pl01x_putc(regs, ch) == -EAGAIN)
 425                 ;
 426 }
 427
 428 DEBUG_UART_FUNCS
 429
 430 #endif