drivers/serial/serial_pl01x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2000
   4  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
   5  *
   6  * (C) Copyright 2004
   7  * ARM Ltd.
   8  * Philippe Robin, <philippe.robin@arm.com>
   9  */
  10
  11 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
  12
  13 #include <common.h>
  14 /* For get_bus_freq() */
  15 #include <clock_legacy.h>
  16 #include <dm.h>
  17 #include <clk.h>
  18 #include <errno.h>
  19 #include <watchdog.h>
  20 #include <asm/io.h>
  21 #include <serial.h>
  22 #include <dm/platform_data/serial_pl01x.h>
  23 #include <linux/compiler.h>
  24 #include "serial_pl01x_internal.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 #ifndef CONFIG_DM_SERIAL
  29
  30 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
  31 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
  32 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
  33 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
  34
  35 #endif
  36
  37 static int pl01x_putc(struct pl01x_regs *regs, char c)
  38 {
  39         /* Wait until there is space in the FIFO */
  40         if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
  41                 return -EAGAIN;
  42
  43         /* Send the character */
  44         writel(c, &regs->dr);
  45
  46         return 0;
  47 }
  48
  49 static int pl01x_getc(struct pl01x_regs *regs)
  50 {
  51         unsigned int data;
  52
  53         /* Wait until there is data in the FIFO */
  54         if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
  55                 return -EAGAIN;
  56
  57         data = readl(&regs->dr);
  58
  59         /* Check for an error flag */
  60         if (data & 0xFFFFFF00) {
  61                 /* Clear the error */
  62                 writel(0xFFFFFFFF, &regs->ecr);
  63                 return -1;
  64         }
  65
  66         return (int) data;
  67 }
  68
  69 static int pl01x_tstc(struct pl01x_regs *regs)
  70 {
  71         WATCHDOG_RESET();
  72         return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
  73 }
  74
  75 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
  76                                      enum pl01x_type type)
  77 {
  78         switch (type) {
  79         case TYPE_PL010:
  80                 /* disable everything */
  81                 writel(0, &regs->pl010_cr);
  82                 break;
  83         case TYPE_PL011:
  84                 /* disable everything */
  85                 writel(0, &regs->pl011_cr);
  86                 break;
  87         default:
  88                 return -EINVAL;
  89         }
  90
  91         return 0;
  92 }
  93
  94 static int pl011_set_line_control(struct pl01x_regs *regs)
  95 {
  96         unsigned int lcr;
  97         /*
  98          * Internal update of baud rate register require line
  99          * control register write
 100          */
 101         lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
 102         writel(lcr, &regs->pl011_lcrh);
 103         return 0;
 104 }
 105
 106 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
 107                                 int clock, int baudrate)
 108 {
 109         switch (type) {
 110         case TYPE_PL010: {
 111                 unsigned int divisor;
 112
 113                 /* disable everything */
 114                 writel(0, &regs->pl010_cr);
 115
 116                 switch (baudrate) {
 117                 case 9600:
 118                         divisor = UART_PL010_BAUD_9600;
 119                         break;
 120                 case 19200:
 121                         divisor = UART_PL010_BAUD_19200;
 122                         break;
 123                 case 38400:
 124                         divisor = UART_PL010_BAUD_38400;
 125                         break;
 126                 case 57600:
 127                         divisor = UART_PL010_BAUD_57600;
 128                         break;
 129                 case 115200:
 130                         divisor = UART_PL010_BAUD_115200;
 131                         break;
 132                 default:
 133                         divisor = UART_PL010_BAUD_38400;
 134                 }
 135
 136                 writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
 137                 writel(divisor & 0xff, &regs->pl010_lcrl);
 138
 139                 /*
 140                  * Set line control for the PL010 to be 8 bits, 1 stop bit,
 141                  * no parity, fifo enabled
 142                  */
 143                 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
 144                        &regs->pl010_lcrh);
 145                 /* Finally, enable the UART */
 146                 writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
 147                 break;
 148         }
 149         case TYPE_PL011: {
 150                 unsigned int temp;
 151                 unsigned int divider;
 152                 unsigned int remainder;
 153                 unsigned int fraction;
 154
 155                 /* Without a valid clock rate we cannot set up the baudrate. */
 156                 if (clock) {
 157                         /*
 158                          * Set baud rate
 159                          *
 160                          * IBRD = UART_CLK / (16 * BAUD_RATE)
 161                          * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
 162                          *              / (16 * BAUD_RATE))
 163                          */
 164                         temp = 16 * baudrate;
 165                         divider = clock / temp;
 166                         remainder = clock % temp;
 167                         temp = (8 * remainder) / baudrate;
 168                         fraction = (temp >> 1) + (temp & 1);
 169
 170                         writel(divider, &regs->pl011_ibrd);
 171                         writel(fraction, &regs->pl011_fbrd);
 172                 }
 173
 174                 pl011_set_line_control(regs);
 175                 /* Finally, enable the UART */
 176                 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
 177                        UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
 178                 break;
 179         }
 180         default:
 181                 return -EINVAL;
 182         }
 183
 184         return 0;
 185 }
 186
 187 #ifndef CONFIG_DM_SERIAL
 188 static void pl01x_serial_init_baud(int baudrate)
 189 {
 190         int clock = 0;
 191
 192 #if defined(CONFIG_PL010_SERIAL)
 193         pl01x_type = TYPE_PL010;
 194 #elif defined(CONFIG_PL011_SERIAL)
 195         pl01x_type = TYPE_PL011;
 196         clock = CONFIG_PL011_CLOCK;
 197 #endif
 198         base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
 199
 200         pl01x_generic_serial_init(base_regs, pl01x_type);
 201         pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
 202 }
 203
 204 /*
 205  * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
 206  * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
 207  * Versatile PB has four UARTs.
 208  */
 209 int pl01x_serial_init(void)
 210 {
 211         pl01x_serial_init_baud(CONFIG_BAUDRATE);
 212
 213         return 0;
 214 }
 215
 216 static void pl01x_serial_putc(const char c)
 217 {
 218         if (c == '\n')
 219                 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
 220
 221         while (pl01x_putc(base_regs, c) == -EAGAIN);
 222 }
 223
 224 static int pl01x_serial_getc(void)
 225 {
 226         while (1) {
 227                 int ch = pl01x_getc(base_regs);
 228
 229                 if (ch == -EAGAIN) {
 230                         WATCHDOG_RESET();
 231                         continue;
 232                 }
 233
 234                 return ch;
 235         }
 236 }
 237
 238 static int pl01x_serial_tstc(void)
 239 {
 240         return pl01x_tstc(base_regs);
 241 }
 242
 243 static void pl01x_serial_setbrg(void)
 244 {
 245         /*
 246          * Flush FIFO and wait for non-busy before changing baudrate to avoid
 247          * crap in console
 248          */
 249         while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
 250                 WATCHDOG_RESET();
 251         while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
 252                 WATCHDOG_RESET();
 253         pl01x_serial_init_baud(gd->baudrate);
 254 }
 255
 256 static struct serial_device pl01x_serial_drv = {
 257         .name   = "pl01x_serial",
 258         .start  = pl01x_serial_init,
 259         .stop   = NULL,
 260         .setbrg = pl01x_serial_setbrg,
 261         .putc   = pl01x_serial_putc,
 262         .puts   = default_serial_puts,
 263         .getc   = pl01x_serial_getc,
 264         .tstc   = pl01x_serial_tstc,
 265 };
 266
 267 void pl01x_serial_initialize(void)
 268 {
 269         serial_register(&pl01x_serial_drv);
 270 }
 271
 272 __weak struct serial_device *default_serial_console(void)
 273 {
 274         return &pl01x_serial_drv;
 275 }
 276
 277 #endif /* nCONFIG_DM_SERIAL */
 278
 279 #ifdef CONFIG_DM_SERIAL
 280
 281 int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
 282 {
 283         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 284         struct pl01x_priv *priv = dev_get_priv(dev);
 285
 286         if (!plat->skip_init) {
 287                 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
 288                                      baudrate);
 289         }
 290
 291         return 0;
 292 }
 293
 294 int pl01x_serial_probe(struct udevice *dev)
 295 {
 296         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 297         struct pl01x_priv *priv = dev_get_priv(dev);
 298
 299         priv->regs = (struct pl01x_regs *)plat->base;
 300         priv->type = plat->type;
 301         if (!plat->skip_init)
 302                 return pl01x_generic_serial_init(priv->regs, priv->type);
 303         else
 304                 return 0;
 305 }
 306
 307 int pl01x_serial_getc(struct udevice *dev)
 308 {
 309         struct pl01x_priv *priv = dev_get_priv(dev);
 310
 311         return pl01x_getc(priv->regs);
 312 }
 313
 314 int pl01x_serial_putc(struct udevice *dev, const char ch)
 315 {
 316         struct pl01x_priv *priv = dev_get_priv(dev);
 317
 318         return pl01x_putc(priv->regs, ch);
 319 }
 320
 321 int pl01x_serial_pending(struct udevice *dev, bool input)
 322 {
 323         struct pl01x_priv *priv = dev_get_priv(dev);
 324         unsigned int fr = readl(&priv->regs->fr);
 325
 326         if (input)
 327                 return pl01x_tstc(priv->regs);
 328         else
 329                 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
 330 }
 331
 332 static const struct dm_serial_ops pl01x_serial_ops = {
 333         .putc = pl01x_serial_putc,
 334         .pending = pl01x_serial_pending,
 335         .getc = pl01x_serial_getc,
 336         .setbrg = pl01x_serial_setbrg,
 337 };
 338
 339 #if CONFIG_IS_ENABLED(OF_CONTROL)
 340 static const struct udevice_id pl01x_serial_id[] ={
 341         {.compatible = "arm,pl011", .data = TYPE_PL011},
 342         {.compatible = "arm,pl010", .data = TYPE_PL010},
 343         {}
 344 };
 345
 346 #ifndef CONFIG_PL011_CLOCK
 347 #define CONFIG_PL011_CLOCK 0
 348 #endif
 349
 350 int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
 351 {
 352         struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
 353         struct clk clk;
 354         fdt_addr_t addr;
 355         int ret;
 356
 357         addr = dev_read_addr(dev);
 358         if (addr == FDT_ADDR_T_NONE)
 359                 return -EINVAL;
 360
 361         plat->base = addr;
 362         plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
 363         ret = clk_get_by_index(dev, 0, &clk);
 364         if (!ret) {
 365                 clk_enable(&clk);
 366                 plat->clock = clk_get_rate(&clk);
 367         }
 368         plat->type = dev_get_driver_data(dev);
 369         plat->skip_init = dev_read_bool(dev, "skip-init");
 370
 371         return 0;
 372 }
 373 #endif
 374
 375 U_BOOT_DRIVER(serial_pl01x) = {
 376         .name   = "serial_pl01x",
 377         .id     = UCLASS_SERIAL,
 378         .of_match = of_match_ptr(pl01x_serial_id),
 379         .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
 380         .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
 381         .probe = pl01x_serial_probe,
 382         .ops    = &pl01x_serial_ops,
 383         .flags = DM_FLAG_PRE_RELOC,
 384         .priv_auto_alloc_size = sizeof(struct pl01x_priv),
 385 };
 386
 387 #endif
 388
 389 #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
 390
 391 #include <debug_uart.h>
 392
 393 static void _debug_uart_init(void)
 394 {
 395 #ifndef CONFIG_DEBUG_UART_SKIP_INIT
 396         struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 397         enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
 398                                 TYPE_PL011 : TYPE_PL010;
 399
 400         pl01x_generic_serial_init(regs, type);
 401         pl01x_generic_setbrg(regs, type,
 402                              CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
 403 #endif
 404 }
 405
 406 static inline void _debug_uart_putc(int ch)
 407 {
 408         struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
 409
 410         pl01x_putc(regs, ch);
 411 }
 412
 413 DEBUG_UART_FUNCS
 414
 415 #endif