1 // SPDX-License-Identifier: GPL-2.0+
4 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
8 * Philippe Robin, <philippe.robin@arm.com>
11 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
19 #include <dm/platform_data/serial_pl01x.h>
20 #include <linux/compiler.h>
21 #include "serial_pl01x_internal.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 #ifndef CONFIG_DM_SERIAL
27 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
28 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
29 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
30 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
34 static int pl01x_putc(struct pl01x_regs *regs, char c)
36 /* Wait until there is space in the FIFO */
37 if (readl(®s->fr) & UART_PL01x_FR_TXFF)
40 /* Send the character */
46 static int pl01x_getc(struct pl01x_regs *regs)
50 /* Wait until there is data in the FIFO */
51 if (readl(®s->fr) & UART_PL01x_FR_RXFE)
54 data = readl(®s->dr);
56 /* Check for an error flag */
57 if (data & 0xFFFFFF00) {
59 writel(0xFFFFFFFF, ®s->ecr);
66 static int pl01x_tstc(struct pl01x_regs *regs)
69 return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
72 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
77 /* disable everything */
78 writel(0, ®s->pl010_cr);
81 /* disable everything */
82 writel(0, ®s->pl011_cr);
91 static int pl011_set_line_control(struct pl01x_regs *regs)
95 * Internal update of baud rate register require line
96 * control register write
98 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
99 writel(lcr, ®s->pl011_lcrh);
103 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
104 int clock, int baudrate)
108 unsigned int divisor;
110 /* disable everything */
111 writel(0, ®s->pl010_cr);
115 divisor = UART_PL010_BAUD_9600;
118 divisor = UART_PL010_BAUD_19200;
121 divisor = UART_PL010_BAUD_38400;
124 divisor = UART_PL010_BAUD_57600;
127 divisor = UART_PL010_BAUD_115200;
130 divisor = UART_PL010_BAUD_38400;
133 writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
134 writel(divisor & 0xff, ®s->pl010_lcrl);
137 * Set line control for the PL010 to be 8 bits, 1 stop bit,
138 * no parity, fifo enabled
140 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
142 /* Finally, enable the UART */
143 writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
148 unsigned int divider;
149 unsigned int remainder;
150 unsigned int fraction;
155 * IBRD = UART_CLK / (16 * BAUD_RATE)
156 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
157 * / (16 * BAUD_RATE))
159 temp = 16 * baudrate;
160 divider = clock / temp;
161 remainder = clock % temp;
162 temp = (8 * remainder) / baudrate;
163 fraction = (temp >> 1) + (temp & 1);
165 writel(divider, ®s->pl011_ibrd);
166 writel(fraction, ®s->pl011_fbrd);
168 pl011_set_line_control(regs);
169 /* Finally, enable the UART */
170 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
171 UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr);
181 #ifndef CONFIG_DM_SERIAL
182 static void pl01x_serial_init_baud(int baudrate)
186 #if defined(CONFIG_PL010_SERIAL)
187 pl01x_type = TYPE_PL010;
188 #elif defined(CONFIG_PL011_SERIAL)
189 pl01x_type = TYPE_PL011;
190 clock = CONFIG_PL011_CLOCK;
192 base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
194 pl01x_generic_serial_init(base_regs, pl01x_type);
195 pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
199 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
200 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
201 * Versatile PB has four UARTs.
203 int pl01x_serial_init(void)
205 pl01x_serial_init_baud(CONFIG_BAUDRATE);
210 static void pl01x_serial_putc(const char c)
213 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
215 while (pl01x_putc(base_regs, c) == -EAGAIN);
218 static int pl01x_serial_getc(void)
221 int ch = pl01x_getc(base_regs);
232 static int pl01x_serial_tstc(void)
234 return pl01x_tstc(base_regs);
237 static void pl01x_serial_setbrg(void)
240 * Flush FIFO and wait for non-busy before changing baudrate to avoid
243 while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
245 while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
247 pl01x_serial_init_baud(gd->baudrate);
250 static struct serial_device pl01x_serial_drv = {
251 .name = "pl01x_serial",
252 .start = pl01x_serial_init,
254 .setbrg = pl01x_serial_setbrg,
255 .putc = pl01x_serial_putc,
256 .puts = default_serial_puts,
257 .getc = pl01x_serial_getc,
258 .tstc = pl01x_serial_tstc,
261 void pl01x_serial_initialize(void)
263 serial_register(&pl01x_serial_drv);
266 __weak struct serial_device *default_serial_console(void)
268 return &pl01x_serial_drv;
271 #endif /* nCONFIG_DM_SERIAL */
273 #ifdef CONFIG_DM_SERIAL
275 int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
277 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
278 struct pl01x_priv *priv = dev_get_priv(dev);
280 if (!plat->skip_init) {
281 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
288 int pl01x_serial_probe(struct udevice *dev)
290 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
291 struct pl01x_priv *priv = dev_get_priv(dev);
293 priv->regs = (struct pl01x_regs *)plat->base;
294 priv->type = plat->type;
295 if (!plat->skip_init)
296 return pl01x_generic_serial_init(priv->regs, priv->type);
301 int pl01x_serial_getc(struct udevice *dev)
303 struct pl01x_priv *priv = dev_get_priv(dev);
305 return pl01x_getc(priv->regs);
308 int pl01x_serial_putc(struct udevice *dev, const char ch)
310 struct pl01x_priv *priv = dev_get_priv(dev);
312 return pl01x_putc(priv->regs, ch);
315 int pl01x_serial_pending(struct udevice *dev, bool input)
317 struct pl01x_priv *priv = dev_get_priv(dev);
318 unsigned int fr = readl(&priv->regs->fr);
321 return pl01x_tstc(priv->regs);
323 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
326 static const struct dm_serial_ops pl01x_serial_ops = {
327 .putc = pl01x_serial_putc,
328 .pending = pl01x_serial_pending,
329 .getc = pl01x_serial_getc,
330 .setbrg = pl01x_serial_setbrg,
333 #if CONFIG_IS_ENABLED(OF_CONTROL)
334 static const struct udevice_id pl01x_serial_id[] ={
335 {.compatible = "arm,pl011", .data = TYPE_PL011},
336 {.compatible = "arm,pl010", .data = TYPE_PL010},
340 int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
342 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
345 addr = devfdt_get_addr(dev);
346 if (addr == FDT_ADDR_T_NONE)
350 plat->clock = dev_read_u32_default(dev, "clock", 1);
351 plat->type = dev_get_driver_data(dev);
352 plat->skip_init = dev_read_bool(dev, "skip-init");
358 U_BOOT_DRIVER(serial_pl01x) = {
359 .name = "serial_pl01x",
361 .of_match = of_match_ptr(pl01x_serial_id),
362 .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
363 .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
364 .probe = pl01x_serial_probe,
365 .ops = &pl01x_serial_ops,
366 #if !CONFIG_IS_ENABLED(OF_CONTROL)
367 .flags = DM_FLAG_PRE_RELOC,
369 .priv_auto_alloc_size = sizeof(struct pl01x_priv),
374 #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
376 #include <debug_uart.h>
378 static void _debug_uart_init(void)
380 #ifndef CONFIG_DEBUG_UART_SKIP_INIT
381 struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
382 enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
383 TYPE_PL011 : TYPE_PL010;
385 pl01x_generic_serial_init(regs, type);
386 pl01x_generic_setbrg(regs, type,
387 CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
391 static inline void _debug_uart_putc(int ch)
393 struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
395 pl01x_putc(regs, ch);