1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2021 Nuvoton Technology Corp.
13 u32 rbr; /* Receive Buffer Register */
14 u32 thr; /* Transmit Holding Register */
15 u32 dll; /* Divisor Latch (Low Byte) Register */
18 u32 ier; /* Interrupt Enable Register */
19 u32 dlm; /* Divisor Latch (Low Byte) Register */
22 u32 iir; /* Interrupt Identification Register */
23 u32 fcr; /* FIFO Control Register */
25 u32 lcr; /* Line Control Register */
26 u32 mcr; /* Modem Control Register */
27 u32 lsr; /* Line Status Control Register */
28 u32 msr; /* Modem Status Register */
29 u32 tor; /* Timeout Register */
32 #define LCR_WLS_8BITS 3 /* 8-bit word length select */
33 #define FCR_TFR BIT(2) /* TxFIFO reset */
34 #define FCR_RFR BIT(1) /* RxFIFO reset */
35 #define FCR_FME BIT(0) /* FIFO mode enable */
36 #define LSR_THRE BIT(5) /* Status of TxFIFO empty */
37 #define LSR_RFDR BIT(0) /* Status of RxFIFO data ready */
38 #define LCR_DLAB BIT(7) /* Divisor latch access bit */
40 struct npcm_serial_plat {
41 struct npcm_uart *reg;
42 u32 uart_clk; /* frequency of uart clock source */
45 static int npcm_serial_pending(struct udevice *dev, bool input)
47 struct npcm_serial_plat *plat = dev_get_plat(dev);
48 struct npcm_uart *uart = plat->reg;
51 return readb(&uart->lsr) & LSR_RFDR ? 1 : 0;
53 return readb(&uart->lsr) & LSR_THRE ? 0 : 1;
56 static int npcm_serial_putc(struct udevice *dev, const char ch)
58 struct npcm_serial_plat *plat = dev_get_plat(dev);
59 struct npcm_uart *uart = plat->reg;
61 if (!(readb(&uart->lsr) & LSR_THRE))
64 writeb(ch, &uart->thr);
69 static int npcm_serial_getc(struct udevice *dev)
71 struct npcm_serial_plat *plat = dev_get_plat(dev);
72 struct npcm_uart *uart = plat->reg;
74 if (!(readb(&uart->lsr) & LSR_RFDR))
77 return readb(&uart->rbr);
80 static int npcm_serial_setbrg(struct udevice *dev, int baudrate)
82 struct npcm_serial_plat *plat = dev_get_plat(dev);
83 struct npcm_uart *uart = plat->reg;
86 /* BaudOut = UART Clock / (16 * [Divisor + 2]) */
87 divisor = DIV_ROUND_CLOSEST(plat->uart_clk, 16 * baudrate + 2) - 2;
89 setbits_8(&uart->lcr, LCR_DLAB);
90 writeb(divisor & 0xff, &uart->dll);
91 writeb(divisor >> 8, &uart->dlm);
92 clrbits_8(&uart->lcr, LCR_DLAB);
97 static int npcm_serial_probe(struct udevice *dev)
99 struct npcm_serial_plat *plat = dev_get_plat(dev);
100 struct npcm_uart *uart = plat->reg;
101 struct clk clk, parent;
105 plat->reg = dev_read_addr_ptr(dev);
106 freq = dev_read_u32_default(dev, "clock-frequency", 0);
108 ret = clk_get_by_index(dev, 0, &clk);
112 ret = clk_get_by_index(dev, 1, &parent);
114 ret = clk_set_parent(&clk, &parent);
119 ret = clk_set_rate(&clk, freq);
122 plat->uart_clk = ret;
124 /* Disable all interrupt */
125 writeb(0, &uart->ier);
127 /* Set 8 bit, 1 stop, no parity */
128 writeb(LCR_WLS_8BITS, &uart->lcr);
130 /* Reset RX/TX FIFO */
131 writeb(FCR_FME | FCR_RFR | FCR_TFR, &uart->fcr);
136 static const struct dm_serial_ops npcm_serial_ops = {
137 .getc = npcm_serial_getc,
138 .setbrg = npcm_serial_setbrg,
139 .putc = npcm_serial_putc,
140 .pending = npcm_serial_pending,
143 static const struct udevice_id npcm_serial_ids[] = {
144 { .compatible = "nuvoton,npcm750-uart" },
145 { .compatible = "nuvoton,npcm845-uart" },
149 U_BOOT_DRIVER(serial_npcm) = {
150 .name = "serial_npcm",
152 .of_match = npcm_serial_ids,
153 .plat_auto = sizeof(struct npcm_serial_plat),
154 .probe = npcm_serial_probe,
155 .ops = &npcm_serial_ops,
156 .flags = DM_FLAG_PRE_RELOC,