1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
11 #include <asm/arch/cpu.h>
22 #define UART_RX_REG 0x00
23 #define UART_TX_REG 0x04
24 #define UART_CTRL_REG 0x08
25 #define UART_STATUS_REG 0x0c
26 #define UART_BAUD_REG 0x10
27 #define UART_POSSR_REG 0x14
29 #define UART_STATUS_RX_RDY 0x10
30 #define UART_STATUS_TX_EMPTY 0x40
31 #define UART_STATUS_TXFIFO_FULL 0x800
33 #define UART_CTRL_RXFIFO_RESET 0x4000
34 #define UART_CTRL_TXFIFO_RESET 0x8000
36 static int mvebu_serial_putc(struct udevice *dev, const char ch)
38 struct mvebu_plat *plat = dev_get_plat(dev);
39 void __iomem *base = plat->base;
41 while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
44 writel(ch, base + UART_TX_REG);
49 static int mvebu_serial_getc(struct udevice *dev)
51 struct mvebu_plat *plat = dev_get_plat(dev);
52 void __iomem *base = plat->base;
54 while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY))
57 return readl(base + UART_RX_REG) & 0xff;
60 static int mvebu_serial_pending(struct udevice *dev, bool input)
62 struct mvebu_plat *plat = dev_get_plat(dev);
63 void __iomem *base = plat->base;
66 if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)
69 if (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY))
76 static int mvebu_serial_setbrg(struct udevice *dev, int baudrate)
78 struct mvebu_plat *plat = dev_get_plat(dev);
79 void __iomem *base = plat->base;
85 * baudrate = clock / 16 / divider
88 divider = DIV_ROUND_CLOSEST(plat->tbg_rate, baudrate * 16 * d1 * d2);
91 * Set Programmable Oversampling Stack to 0,
92 * UART defaults to 16x scheme
98 else if (divider > 1023) {
100 * If divider is too high for selected baudrate then set
101 * divider d1 to the maximal value 6.
104 divider = DIV_ROUND_CLOSEST(plat->tbg_rate,
105 baudrate * 16 * d1 * d2);
108 else if (divider > 1023) {
110 * If divider is still too high then set also divider
111 * d2 to the maximal value 6.
114 divider = DIV_ROUND_CLOSEST(plat->tbg_rate,
115 baudrate * 16 * d1 * d2);
118 else if (divider > 1023) {
120 * And if divider is still to high then
121 * use oversampling with maximal factor 63.
123 oversampling = (63 << 0) | (63 << 8) |
124 (63 << 16) | (63 << 24);
125 divider = DIV_ROUND_CLOSEST(plat->tbg_rate,
126 baudrate * 63 * d1 * d2);
129 else if (divider > 1023)
135 divider |= BIT(19); /* Do not use XTAL as a base clock */
136 divider |= d1 << 15; /* Set d1 divider */
137 divider |= d2 << 12; /* Set d2 divider */
138 divider |= plat->tbg_idx << 10; /* Use selected TBG as a base clock */
140 while (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY))
142 writel(divider, base + UART_BAUD_REG);
143 writel(oversampling, base + UART_POSSR_REG);
148 static int mvebu_serial_probe(struct udevice *dev)
150 struct mvebu_plat *plat = dev_get_plat(dev);
151 void __iomem *base = plat->base;
152 struct udevice *nb_clk;
156 nb_clk_node = ofnode_by_compatible(ofnode_null(),
157 "marvell,armada-3700-periph-clock-nb");
158 if (!ofnode_valid(nb_clk_node)) {
159 printf("%s: NB periph clock node not available\n", __func__);
163 res = device_get_global_by_ofnode(nb_clk_node, &nb_clk);
165 printf("%s: Cannot get NB periph clock\n", __func__);
170 * Choose the TBG clock with lowest frequency which allows to configure
171 * UART also at lower baudrates.
173 for (i = 0; i < 4; i++) {
177 res = clk_get_by_index_nodev(nb_clk_node, i, &clk);
179 printf("%s: Cannot get TBG clock %i: %i\n", __func__,
184 rate = clk_get_rate(&clk);
185 if (!rate || IS_ERR_VALUE(rate)) {
186 printf("%s: Cannot get rate for TBG clock %i\n",
191 if (!i || plat->tbg_rate > rate) {
192 plat->tbg_rate = rate;
198 writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
199 base + UART_CTRL_REG);
201 /* No Parity, 1 Stop */
202 writel(0, base + UART_CTRL_REG);
207 static int mvebu_serial_remove(struct udevice *dev)
209 struct mvebu_plat *plat = dev_get_plat(dev);
210 void __iomem *base = plat->base;
211 ulong new_parent_rate, parent_rate;
212 u32 new_divider, divider;
213 u32 new_oversampling;
218 * Switch UART base clock back to XTAL because older Linux kernel
219 * expects it. Otherwise it does not calculate UART divisor correctly
220 * and therefore UART does not work in kernel.
222 divider = readl(base + UART_BAUD_REG);
223 if (!(divider & BIT(19))) /* UART already uses XTAL */
226 /* Read current divisors settings */
227 d1 = (divider >> 15) & 7;
228 d2 = (divider >> 12) & 7;
229 parent_rate = plat->tbg_rate;
231 oversampling = readl(base + UART_POSSR_REG) & 63;
235 /* Calculate new divisor against XTAL clock without changing baudrate */
236 new_oversampling = 0;
237 new_parent_rate = get_ref_clk() * 1000000;
238 new_divider = DIV_ROUND_CLOSEST(new_parent_rate * divider * d1 * d2 *
239 oversampling, parent_rate * 16);
242 * UART does not work reliably when XTAL divisor is smaller than 4.
243 * In this case we do not switch UART parent to XTAL. User either
244 * configured unsupported settings or has newer kernel with patches
245 * which allow usage of non-XTAL clock as a parent clock.
251 * If new divisor is larger than maximal supported, try to switch
252 * from default x16 scheme to oversampling with maximal factor 63.
254 if (new_divider > 1023) {
255 new_oversampling = 63;
256 new_divider = DIV_ROUND_CLOSEST(new_parent_rate * divider * d1 *
258 parent_rate * new_oversampling);
259 if (new_divider < 4 || new_divider > 1023)
263 while (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY))
266 writel(new_divider, base + UART_BAUD_REG);
267 writel(new_oversampling, base + UART_POSSR_REG);
272 static int mvebu_serial_of_to_plat(struct udevice *dev)
274 struct mvebu_plat *plat = dev_get_plat(dev);
276 plat->base = dev_read_addr_ptr(dev);
281 static const struct dm_serial_ops mvebu_serial_ops = {
282 .putc = mvebu_serial_putc,
283 .pending = mvebu_serial_pending,
284 .getc = mvebu_serial_getc,
285 .setbrg = mvebu_serial_setbrg,
288 static const struct udevice_id mvebu_serial_ids[] = {
289 { .compatible = "marvell,armada-3700-uart" },
293 U_BOOT_DRIVER(serial_mvebu) = {
294 .name = "serial_mvebu",
296 .of_match = mvebu_serial_ids,
297 .of_to_plat = mvebu_serial_of_to_plat,
298 .plat_auto = sizeof(struct mvebu_plat),
299 .probe = mvebu_serial_probe,
300 .remove = mvebu_serial_remove,
301 .flags = DM_FLAG_OS_PREPARE,
302 .ops = &mvebu_serial_ops,
305 #ifdef CONFIG_DEBUG_MVEBU_A3700_UART
307 #include <debug_uart.h>
309 static inline void _debug_uart_init(void)
311 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
312 u32 baudrate, parent_rate, divider;
315 writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
316 base + UART_CTRL_REG);
318 /* No Parity, 1 Stop */
319 writel(0, base + UART_CTRL_REG);
323 * baudrate = clock / 16 / divider
326 parent_rate = get_ref_clk() * 1000000;
327 divider = DIV_ROUND_CLOSEST(parent_rate, baudrate * 16);
328 writel(divider, base + UART_BAUD_REG);
331 * Set Programmable Oversampling Stack to 0,
332 * UART defaults to 16x scheme
334 writel(0, base + UART_POSSR_REG);
337 static inline void _debug_uart_putc(int ch)
339 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
341 while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
344 writel(ch, base + UART_TX_REG);