1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
18 #define UART_RX_REG 0x00
19 #define UART_TX_REG 0x04
20 #define UART_CTRL_REG 0x08
21 #define UART_STATUS_REG 0x0c
22 #define UART_BAUD_REG 0x10
23 #define UART_POSSR_REG 0x14
25 #define UART_STATUS_RX_RDY 0x10
26 #define UART_STATUS_TX_EMPTY 0x40
27 #define UART_STATUS_TXFIFO_FULL 0x800
29 #define UART_CTRL_RXFIFO_RESET 0x4000
30 #define UART_CTRL_TXFIFO_RESET 0x8000
32 #define CONFIG_UART_BASE_CLOCK 25804800
34 static int mvebu_serial_putc(struct udevice *dev, const char ch)
36 struct mvebu_plat *plat = dev_get_plat(dev);
37 void __iomem *base = plat->base;
39 while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
42 writel(ch, base + UART_TX_REG);
47 static int mvebu_serial_getc(struct udevice *dev)
49 struct mvebu_plat *plat = dev_get_plat(dev);
50 void __iomem *base = plat->base;
52 while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY))
55 return readl(base + UART_RX_REG) & 0xff;
58 static int mvebu_serial_pending(struct udevice *dev, bool input)
60 struct mvebu_plat *plat = dev_get_plat(dev);
61 void __iomem *base = plat->base;
64 if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)
67 if (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY))
74 static int mvebu_serial_setbrg(struct udevice *dev, int baudrate)
76 struct mvebu_plat *plat = dev_get_plat(dev);
77 void __iomem *base = plat->base;
81 * baudrate = clock / 16 / divider
83 writel(CONFIG_UART_BASE_CLOCK / baudrate / 16, base + UART_BAUD_REG);
86 * Set Programmable Oversampling Stack to 0,
87 * UART defaults to 16x scheme
89 writel(0, base + UART_POSSR_REG);
94 static int mvebu_serial_probe(struct udevice *dev)
96 struct mvebu_plat *plat = dev_get_plat(dev);
97 void __iomem *base = plat->base;
100 writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
101 base + UART_CTRL_REG);
103 /* No Parity, 1 Stop */
104 writel(0, base + UART_CTRL_REG);
109 static int mvebu_serial_of_to_plat(struct udevice *dev)
111 struct mvebu_plat *plat = dev_get_plat(dev);
113 plat->base = dev_read_addr_ptr(dev);
118 static const struct dm_serial_ops mvebu_serial_ops = {
119 .putc = mvebu_serial_putc,
120 .pending = mvebu_serial_pending,
121 .getc = mvebu_serial_getc,
122 .setbrg = mvebu_serial_setbrg,
125 static const struct udevice_id mvebu_serial_ids[] = {
126 { .compatible = "marvell,armada-3700-uart" },
130 U_BOOT_DRIVER(serial_mvebu) = {
131 .name = "serial_mvebu",
133 .of_match = mvebu_serial_ids,
134 .of_to_plat = mvebu_serial_of_to_plat,
135 .plat_auto = sizeof(struct mvebu_plat),
136 .probe = mvebu_serial_probe,
137 .ops = &mvebu_serial_ops,
140 #ifdef CONFIG_DEBUG_MVEBU_A3700_UART
142 #include <debug_uart.h>
144 static inline void _debug_uart_init(void)
146 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
149 writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
150 base + UART_CTRL_REG);
152 /* No Parity, 1 Stop */
153 writel(0, base + UART_CTRL_REG);
157 * baudrate = clock / 16 / divider
159 writel(CONFIG_UART_BASE_CLOCK / 115200 / 16, base + UART_BAUD_REG);
162 * Set Programmable Oversampling Stack to 0,
163 * UART defaults to 16x scheme
165 writel(0, base + UART_POSSR_REG);
168 static inline void _debug_uart_putc(int ch)
170 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
172 while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
175 writel(ch, base + UART_TX_REG);