1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
7 * UART will work in Data Mover mode.
8 * Based on Linux driver.
18 #include <linux/compiler.h>
20 /* Serial registers - this driver works in uartdm mode*/
22 #define UARTDM_DMRX 0x34 /* Max RX transfer length */
23 #define UARTDM_NCF_TX 0x40 /* Number of chars to TX */
25 #define UARTDM_RXFS 0x50 /* RX channel status register */
26 #define UARTDM_RXFS_BUF_SHIFT 0x7 /* Number of bytes in the packing buffer */
27 #define UARTDM_RXFS_BUF_MASK 0x7
29 #define UARTDM_SR 0xA4 /* Status register */
30 #define UARTDM_SR_RX_READY (1 << 0) /* Word is the receiver FIFO */
31 #define UARTDM_SR_TX_EMPTY (1 << 3) /* Transmitter underrun */
32 #define UARTDM_SR_UART_OVERRUN (1 << 4) /* Receive overrun */
34 #define UARTDM_CR 0xA8 /* Command register */
35 #define UARTDM_CR_CMD_RESET_ERR (3 << 4) /* Clear overrun error */
36 #define UARTDM_CR_CMD_RESET_STALE_INT (8 << 4) /* Clears stale irq */
37 #define UARTDM_CR_CMD_RESET_TX_READY (3 << 8) /* Clears TX Ready irq*/
38 #define UARTDM_CR_CMD_FORCE_STALE (4 << 8) /* Causes stale event */
39 #define UARTDM_CR_CMD_STALE_EVENT_DISABLE (6 << 8) /* Disable stale event */
41 #define UARTDM_IMR 0xB0 /* Interrupt mask register */
42 #define UARTDM_ISR 0xB4 /* Interrupt status register */
43 #define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */
45 #define UARTDM_TF 0x100 /* UART Transmit FIFO register */
46 #define UARTDM_RF 0x140 /* UART Receive FIFO register */
49 DECLARE_GLOBAL_DATA_PTR;
51 struct msm_serial_data {
53 unsigned chars_cnt; /* number of buffered chars */
54 uint32_t chars_buf; /* buffered chars */
57 static int msm_serial_fetch(struct udevice *dev)
59 struct msm_serial_data *priv = dev_get_priv(dev);
63 return priv->chars_cnt;
65 /* Clear error in case of buffer overrun */
66 if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
67 writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
69 /* We need to fetch new character */
70 sr = readl(priv->base + UARTDM_SR);
72 if (sr & UARTDM_SR_RX_READY) {
73 /* There are at least 4 bytes in fifo */
74 priv->chars_buf = readl(priv->base + UARTDM_RF);
77 /* Check if there is anything in fifo */
78 priv->chars_cnt = readl(priv->base + UARTDM_RXFS);
79 /* Extract number of characters in UART packing buffer*/
80 priv->chars_cnt = (priv->chars_cnt >>
81 UARTDM_RXFS_BUF_SHIFT) &
86 /* There is at least one charcter, move it to fifo */
87 writel(UARTDM_CR_CMD_FORCE_STALE,
88 priv->base + UARTDM_CR);
90 priv->chars_buf = readl(priv->base + UARTDM_RF);
91 writel(UARTDM_CR_CMD_RESET_STALE_INT,
92 priv->base + UARTDM_CR);
93 writel(0x7, priv->base + UARTDM_DMRX);
96 return priv->chars_cnt;
99 static int msm_serial_getc(struct udevice *dev)
101 struct msm_serial_data *priv = dev_get_priv(dev);
104 if (!msm_serial_fetch(dev))
107 c = priv->chars_buf & 0xFF;
108 priv->chars_buf >>= 8;
114 static int msm_serial_putc(struct udevice *dev, const char ch)
116 struct msm_serial_data *priv = dev_get_priv(dev);
118 if (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
119 !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
122 writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
124 writel(1, priv->base + UARTDM_NCF_TX);
125 writel(ch, priv->base + UARTDM_TF);
130 static int msm_serial_pending(struct udevice *dev, bool input)
133 if (msm_serial_fetch(dev))
140 static const struct dm_serial_ops msm_serial_ops = {
141 .putc = msm_serial_putc,
142 .pending = msm_serial_pending,
143 .getc = msm_serial_getc,
146 static int msm_uart_clk_init(struct udevice *dev)
148 uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
149 "clock-frequency", 115200);
150 uint clkd[2]; /* clk_id and clk_no */
152 struct udevice *clk_dev;
156 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
161 clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
165 ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
170 ret = clk_request(clk_dev, &clk);
174 ret = clk_set_rate(&clk, clk_rate);
182 static int msm_serial_probe(struct udevice *dev)
184 struct msm_serial_data *priv = dev_get_priv(dev);
186 msm_uart_clk_init(dev); /* Ignore return value and hope clock was
187 properly initialized by earlier loaders */
189 if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN)
190 writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR);
192 writel(0, priv->base + UARTDM_IMR);
193 writel(UARTDM_CR_CMD_STALE_EVENT_DISABLE, priv->base + UARTDM_CR);
194 msm_serial_fetch(dev);
199 static int msm_serial_ofdata_to_platdata(struct udevice *dev)
201 struct msm_serial_data *priv = dev_get_priv(dev);
203 priv->base = devfdt_get_addr(dev);
204 if (priv->base == FDT_ADDR_T_NONE)
210 static const struct udevice_id msm_serial_ids[] = {
211 { .compatible = "qcom,msm-uartdm-v1.4" },
215 U_BOOT_DRIVER(serial_msm) = {
216 .name = "serial_msm",
218 .of_match = msm_serial_ids,
219 .ofdata_to_platdata = msm_serial_ofdata_to_platdata,
220 .priv_auto_alloc_size = sizeof(struct msm_serial_data),
221 .probe = msm_serial_probe,
222 .ops = &msm_serial_ops,