1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2013 Freescale Semiconductor, Inc.
10 #include <fsl_lpuart.h>
14 #include <dm/device_compat.h>
15 #include <linux/compiler.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/clock.h>
19 #define US1_TDRE (1 << 7)
20 #define US1_RDRF (1 << 5)
21 #define US1_OR (1 << 3)
22 #define UC2_TE (1 << 3)
23 #define UC2_RE (1 << 2)
24 #define CFIFO_TXFLUSH (1 << 7)
25 #define CFIFO_RXFLUSH (1 << 6)
26 #define SFIFO_RXOF (1 << 2)
27 #define SFIFO_RXUF (1 << 0)
29 #define STAT_LBKDIF (1 << 31)
30 #define STAT_RXEDGIF (1 << 30)
31 #define STAT_TDRE (1 << 23)
32 #define STAT_RDRF (1 << 21)
33 #define STAT_IDLE (1 << 20)
34 #define STAT_OR (1 << 19)
35 #define STAT_NF (1 << 18)
36 #define STAT_FE (1 << 17)
37 #define STAT_PF (1 << 16)
38 #define STAT_MA1F (1 << 15)
39 #define STAT_MA2F (1 << 14)
40 #define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
41 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
43 #define CTRL_TE (1 << 19)
44 #define CTRL_RE (1 << 18)
46 #define FIFO_RXFLUSH BIT(14)
47 #define FIFO_TXFLUSH BIT(15)
48 #define FIFO_TXSIZE_MASK 0x70
49 #define FIFO_TXSIZE_OFF 4
50 #define FIFO_RXSIZE_MASK 0x7
51 #define FIFO_RXSIZE_OFF 0
52 #define FIFO_TXFE 0x80
53 #if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
54 #define FIFO_RXFE 0x08
56 #define FIFO_RXFE 0x40
59 #define WATER_TXWATER_OFF 0
60 #define WATER_RXWATER_OFF 16
62 DECLARE_GLOBAL_DATA_PTR;
64 #define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
65 #define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
75 struct lpuart_serial_platdata {
77 enum lpuart_devtype devtype;
81 static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
83 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
84 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
85 *(u32 *)val = in_be32(addr);
87 *(u32 *)val = in_le32(addr);
91 static void lpuart_write32(u32 flags, u32 *addr, u32 val)
93 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
94 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
102 #ifndef CONFIG_SYS_CLK_FREQ
103 #define CONFIG_SYS_CLK_FREQ 0
106 u32 __weak get_lpuart_clk(void)
108 return CONFIG_SYS_CLK_FREQ;
111 #if CONFIG_IS_ENABLED(CLK)
112 static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
118 ret = clk_get_by_name(dev, "per", &per_clk);
120 dev_err(dev, "Failed to get per clk: %d\n", ret);
124 rate = clk_get_rate(&per_clk);
125 if ((long)rate <= 0) {
126 dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
133 static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
137 static bool is_lpuart32(struct udevice *dev)
139 struct lpuart_serial_platdata *plat = dev->platdata;
141 return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
144 static void _lpuart_serial_setbrg(struct udevice *dev,
147 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
148 struct lpuart_fsl *base = plat->reg;
153 if (CONFIG_IS_ENABLED(CLK)) {
154 ret = get_lpuart_clk_rate(dev, &clk);
158 clk = get_lpuart_clk();
161 sbr = (u16)(clk / (16 * baudrate));
163 /* place adjustment later - n/32 BRFA */
164 __raw_writeb(sbr >> 8, &base->ubdh);
165 __raw_writeb(sbr & 0xff, &base->ubdl);
168 static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
170 struct lpuart_fsl *base = plat->reg;
171 while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
176 return __raw_readb(&base->ud);
179 static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
182 struct lpuart_fsl *base = plat->reg;
184 while (!(__raw_readb(&base->us1) & US1_TDRE))
187 __raw_writeb(c, &base->ud);
190 /* Test whether a character is in the RX buffer */
191 static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
193 struct lpuart_fsl *base = plat->reg;
195 if (__raw_readb(&base->urcfifo) == 0)
202 * Initialise the serial port with the given baudrate. The settings
203 * are always 8 data bits, no parity, 1 stop bit, no start bits.
205 static int _lpuart_serial_init(struct udevice *dev)
207 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
208 struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
211 ctrl = __raw_readb(&base->uc2);
214 __raw_writeb(ctrl, &base->uc2);
216 __raw_writeb(0, &base->umodem);
217 __raw_writeb(0, &base->uc1);
219 /* Disable FIFO and flush buffer */
220 __raw_writeb(0x0, &base->upfifo);
221 __raw_writeb(0x0, &base->utwfifo);
222 __raw_writeb(0x1, &base->urwfifo);
223 __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
225 /* provide data bits, parity, stop bit, etc */
226 _lpuart_serial_setbrg(dev, gd->baudrate);
228 __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
233 static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
236 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
237 struct lpuart_fsl_reg32 *base = plat->reg;
238 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
242 if (CONFIG_IS_ENABLED(CLK)) {
243 ret = get_lpuart_clk_rate(dev, &clk);
247 clk = get_lpuart_clk();
250 baud_diff = baudrate;
254 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
255 tmp_sbr = (clk / (baudrate * tmp_osr));
260 /*calculate difference in actual buad w/ current values */
261 tmp_diff = (clk / (tmp_osr * tmp_sbr));
262 tmp_diff = tmp_diff - baudrate;
264 /* select best values between sbr and sbr+1 */
265 if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
266 tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
270 if (tmp_diff <= baud_diff) {
271 baud_diff = tmp_diff;
278 * TODO: handle buadrate outside acceptable rate
279 * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
281 * Unacceptable baud rate difference of more than 3%
282 * return kStatus_LPUART_BaudrateNotSupport;
285 tmp = in_le32(&base->baud);
287 if ((osr > 3) && (osr < 8))
288 tmp |= LPUART_BAUD_BOTHEDGE_MASK;
290 tmp &= ~LPUART_BAUD_OSR_MASK;
291 tmp |= LPUART_BAUD_OSR(osr-1);
293 tmp &= ~LPUART_BAUD_SBR_MASK;
294 tmp |= LPUART_BAUD_SBR(sbr);
296 /* explicitly disable 10 bit mode & set 1 stop bit */
297 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
299 out_le32(&base->baud, tmp);
302 static void _lpuart32_serial_setbrg(struct udevice *dev,
305 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
306 struct lpuart_fsl_reg32 *base = plat->reg;
311 if (CONFIG_IS_ENABLED(CLK)) {
312 ret = get_lpuart_clk_rate(dev, &clk);
316 clk = get_lpuart_clk();
319 sbr = (clk / (16 * baudrate));
321 /* place adjustment later - n/32 BRFA */
322 lpuart_write32(plat->flags, &base->baud, sbr);
325 static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
327 struct lpuart_fsl_reg32 *base = plat->reg;
330 lpuart_read32(plat->flags, &base->stat, &stat);
331 while ((stat & STAT_RDRF) == 0) {
332 lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
334 lpuart_read32(plat->flags, &base->stat, &stat);
337 lpuart_read32(plat->flags, &base->data, &val);
339 lpuart_read32(plat->flags, &base->stat, &stat);
341 lpuart_write32(plat->flags, &base->stat, STAT_OR);
346 static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
349 struct lpuart_fsl_reg32 *base = plat->reg;
356 lpuart_read32(plat->flags, &base->stat, &stat);
358 if ((stat & STAT_TDRE))
364 lpuart_write32(plat->flags, &base->data, c);
367 /* Test whether a character is in the RX buffer */
368 static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
370 struct lpuart_fsl_reg32 *base = plat->reg;
373 lpuart_read32(plat->flags, &base->water, &water);
375 if ((water >> 24) == 0)
382 * Initialise the serial port with the given baudrate. The settings
383 * are always 8 data bits, no parity, 1 stop bit, no start bits.
385 static int _lpuart32_serial_init(struct udevice *dev)
387 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
388 struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
389 u32 val, tx_fifo_size;
391 lpuart_read32(plat->flags, &base->ctrl, &val);
394 lpuart_write32(plat->flags, &base->ctrl, val);
396 lpuart_write32(plat->flags, &base->modir, 0);
398 lpuart_read32(plat->flags, &base->fifo, &val);
399 tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
400 /* Set the TX water to half of FIFO size */
401 if (tx_fifo_size > 1)
402 tx_fifo_size = tx_fifo_size >> 1;
404 /* Set RX water to 0, to be triggered by any receive data */
405 lpuart_write32(plat->flags, &base->water,
406 (tx_fifo_size << WATER_TXWATER_OFF));
408 /* Enable TX and RX FIFO */
409 val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
410 lpuart_write32(plat->flags, &base->fifo, val);
412 lpuart_write32(plat->flags, &base->match, 0);
414 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
415 plat->devtype == DEV_IMXRT) {
416 _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
418 /* provide data bits, parity, stop bit, etc */
419 _lpuart32_serial_setbrg(dev, gd->baudrate);
422 lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
427 static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
429 struct lpuart_serial_platdata *plat = dev_get_platdata(dev);
431 if (is_lpuart32(dev)) {
432 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
433 plat->devtype == DEV_IMXRT)
434 _lpuart32_serial_setbrg_7ulp(dev, baudrate);
436 _lpuart32_serial_setbrg(dev, baudrate);
438 _lpuart_serial_setbrg(dev, baudrate);
444 static int lpuart_serial_getc(struct udevice *dev)
446 struct lpuart_serial_platdata *plat = dev->platdata;
448 if (is_lpuart32(dev))
449 return _lpuart32_serial_getc(plat);
451 return _lpuart_serial_getc(plat);
454 static int lpuart_serial_putc(struct udevice *dev, const char c)
456 struct lpuart_serial_platdata *plat = dev->platdata;
458 if (is_lpuart32(dev))
459 _lpuart32_serial_putc(plat, c);
461 _lpuart_serial_putc(plat, c);
466 static int lpuart_serial_pending(struct udevice *dev, bool input)
468 struct lpuart_serial_platdata *plat = dev->platdata;
469 struct lpuart_fsl *reg = plat->reg;
470 struct lpuart_fsl_reg32 *reg32 = plat->reg;
473 if (is_lpuart32(dev)) {
475 return _lpuart32_serial_tstc(plat);
477 lpuart_read32(plat->flags, ®32->stat, &stat);
478 return stat & STAT_TDRE ? 0 : 1;
483 return _lpuart_serial_tstc(plat);
485 return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
488 static int lpuart_serial_probe(struct udevice *dev)
490 #if CONFIG_IS_ENABLED(CLK)
494 ret = clk_get_by_name(dev, "per", &per_clk);
496 ret = clk_enable(&per_clk);
498 dev_err(dev, "Failed to get per clk: %d\n", ret);
502 debug("%s: Failed to get per clk: %d\n", __func__, ret);
506 if (is_lpuart32(dev))
507 return _lpuart32_serial_init(dev);
509 return _lpuart_serial_init(dev);
512 static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
514 struct lpuart_serial_platdata *plat = dev->platdata;
515 const void *blob = gd->fdt_blob;
516 int node = dev_of_offset(dev);
519 addr = devfdt_get_addr(dev);
520 if (addr == FDT_ADDR_T_NONE)
523 plat->reg = (void *)addr;
524 plat->flags = dev_get_driver_data(dev);
526 if (fdtdec_get_bool(blob, node, "little-endian"))
527 plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
529 if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
530 plat->devtype = DEV_LS1021A;
531 else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
532 plat->devtype = DEV_MX7ULP;
533 else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
534 plat->devtype = DEV_VF610;
535 else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
536 plat->devtype = DEV_IMX8;
537 else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
538 plat->devtype = DEV_IMXRT;
543 static const struct dm_serial_ops lpuart_serial_ops = {
544 .putc = lpuart_serial_putc,
545 .pending = lpuart_serial_pending,
546 .getc = lpuart_serial_getc,
547 .setbrg = lpuart_serial_setbrg,
550 static const struct udevice_id lpuart_serial_ids[] = {
551 { .compatible = "fsl,ls1021a-lpuart", .data =
552 LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
553 { .compatible = "fsl,imx7ulp-lpuart",
554 .data = LPUART_FLAG_REGMAP_32BIT_REG },
555 { .compatible = "fsl,vf610-lpuart"},
556 { .compatible = "fsl,imx8qm-lpuart",
557 .data = LPUART_FLAG_REGMAP_32BIT_REG },
558 { .compatible = "fsl,imxrt-lpuart",
559 .data = LPUART_FLAG_REGMAP_32BIT_REG },
563 U_BOOT_DRIVER(serial_lpuart) = {
564 .name = "serial_lpuart",
566 .of_match = lpuart_serial_ids,
567 .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
568 .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
569 .probe = lpuart_serial_probe,
570 .ops = &lpuart_serial_ops,