3 * originally from linux source (arch/powerpc/boot/ns16550.c)
4 * modified to use CONFIG_SYS_ISA_MEM and new defines
7 #include <clock_legacy.h>
16 #include <linux/types.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
22 #define UART_MCRVAL (UART_MCR_DTR | \
23 UART_MCR_RTS) /* RTS/DTR */
25 #if !CONFIG_IS_ENABLED(DM_SERIAL)
26 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
27 #define serial_out(x, y) outb(x, (ulong)y)
28 #define serial_in(y) inb((ulong)y)
29 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0)
30 #define serial_out(x, y) out_be32(y, x)
31 #define serial_in(y) in_be32(y)
32 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0)
33 #define serial_out(x, y) out_le32(y, x)
34 #define serial_in(y) in_le32(y)
36 #define serial_out(x, y) writeb(x, y)
37 #define serial_in(y) readb(y)
39 #endif /* !CONFIG_DM_SERIAL */
41 #if defined(CONFIG_SOC_KEYSTONE)
42 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0
43 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
45 #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL
46 #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE)
48 #define UART_MCRVAL (UART_MCR_RTS)
52 #ifndef CONFIG_SYS_NS16550_IER
53 #define CONFIG_SYS_NS16550_IER 0x00
54 #endif /* CONFIG_SYS_NS16550_IER */
56 static inline void serial_out_shift(void *addr, int shift, int value)
58 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
59 outb(value, (ulong)addr);
60 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
61 out_le32(addr, value);
62 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
63 out_be32(addr, value);
64 #elif defined(CONFIG_SYS_NS16550_MEM32)
66 #elif defined(CONFIG_SYS_BIG_ENDIAN)
67 writeb(value, addr + (1 << shift) - 1);
73 static inline int serial_in_shift(void *addr, int shift)
75 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
76 return inb((ulong)addr);
77 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
79 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
81 #elif defined(CONFIG_SYS_NS16550_MEM32)
83 #elif defined(CONFIG_SYS_BIG_ENDIAN)
84 return readb(addr + (1 << shift) - 1);
90 #if CONFIG_IS_ENABLED(DM_SERIAL)
92 #ifndef CONFIG_SYS_NS16550_CLK
93 #define CONFIG_SYS_NS16550_CLK 0
97 * Use this #ifdef for now since many platforms don't define in(), out(),
98 * out_le32(), etc. but we don't have #defines to indicate this.
100 * TODO(sjg@chromium.org): Add CONFIG options to indicate what I/O is available
103 #ifdef CONFIG_NS16550_DYNAMIC
104 static void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
107 if (plat->flags & NS16550_FLAG_IO) {
109 } else if (plat->reg_width == 4) {
110 if (plat->flags & NS16550_FLAG_ENDIAN) {
111 if (plat->flags & NS16550_FLAG_BE)
112 out_be32(addr, value);
114 out_le32(addr, value);
118 } else if (plat->flags & NS16550_FLAG_BE) {
119 writeb(value, addr + (1 << plat->reg_shift) - 1);
125 static int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
127 if (plat->flags & NS16550_FLAG_IO) {
129 } else if (plat->reg_width == 4) {
130 if (plat->flags & NS16550_FLAG_ENDIAN) {
131 if (plat->flags & NS16550_FLAG_BE)
132 return in_be32(addr);
134 return in_le32(addr);
138 } else if (plat->flags & NS16550_FLAG_BE) {
139 return readb(addr + (1 << plat->reg_shift) - 1);
145 static inline void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
150 static inline int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
155 #endif /* CONFIG_NS16550_DYNAMIC */
157 static void ns16550_writeb(NS16550_t port, int offset, int value)
159 struct ns16550_platdata *plat = port->plat;
162 offset *= 1 << plat->reg_shift;
163 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
165 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
166 serial_out_dynamic(plat, addr, value);
168 serial_out_shift(addr, plat->reg_shift, value);
171 static int ns16550_readb(NS16550_t port, int offset)
173 struct ns16550_platdata *plat = port->plat;
176 offset *= 1 << plat->reg_shift;
177 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
179 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
180 return serial_in_dynamic(plat, addr);
182 return serial_in_shift(addr, plat->reg_shift);
185 static u32 ns16550_getfcr(NS16550_t port)
187 struct ns16550_platdata *plat = port->plat;
192 /* We can clean these up once everything is moved to driver model */
193 #define serial_out(value, addr) \
194 ns16550_writeb(com_port, \
195 (unsigned char *)addr - (unsigned char *)com_port, value)
196 #define serial_in(addr) \
197 ns16550_readb(com_port, \
198 (unsigned char *)addr - (unsigned char *)com_port)
200 static u32 ns16550_getfcr(NS16550_t port)
202 return UART_FCR_DEFVAL;
206 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
208 const unsigned int mode_x_div = 16;
210 return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
213 static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
215 /* to keep serial format, read lcr before writing BKSE */
216 int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE;
218 serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr);
219 serial_out(baud_divisor & 0xff, &com_port->dll);
220 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
221 serial_out(lcr_val, &com_port->lcr);
224 void NS16550_init(NS16550_t com_port, int baud_divisor)
226 #if (defined(CONFIG_SPL_BUILD) && \
227 (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX)))
229 * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
230 * before SPL starts only THRE bit is set. We have to empty the
231 * transmitter before initialization starts.
233 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
235 if (baud_divisor != -1)
236 NS16550_setbrg(com_port, baud_divisor);
238 // Re-use old baud rate divisor to flush transmit reg.
239 const int dll = serial_in(&com_port->dll);
240 const int dlm = serial_in(&com_port->dlm);
241 const int divisor = dll | (dlm << 8);
242 NS16550_setbrg(com_port, divisor);
244 serial_out(0, &com_port->mdr1);
248 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
251 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
252 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL)
253 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
256 serial_out(UART_MCRVAL, &com_port->mcr);
257 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
258 /* initialize serial config to 8N1 before writing baudrate */
259 serial_out(UART_LCRVAL, &com_port->lcr);
260 if (baud_divisor != -1)
261 NS16550_setbrg(com_port, baud_divisor);
262 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \
263 defined(CONFIG_OMAP_SERIAL)
264 /* /16 is proper to hit 115200 with 48MHz */
265 serial_out(0, &com_port->mdr1);
267 #if defined(CONFIG_SOC_KEYSTONE)
268 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
272 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
273 void NS16550_reinit(NS16550_t com_port, int baud_divisor)
275 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
276 NS16550_setbrg(com_port, 0);
277 serial_out(UART_MCRVAL, &com_port->mcr);
278 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
279 NS16550_setbrg(com_port, baud_divisor);
281 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
283 void NS16550_putc(NS16550_t com_port, char c)
285 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0)
287 serial_out(c, &com_port->thr);
290 * Call watchdog_reset() upon newline. This is done here in putc
291 * since the environment code uses a single puts() to print the complete
292 * environment upon "printenv". So we can't put this watchdog call
299 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
300 char NS16550_getc(NS16550_t com_port)
302 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
303 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY)
304 extern void usbtty_poll(void);
309 return serial_in(&com_port->rbr);
312 int NS16550_tstc(NS16550_t com_port)
314 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
317 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
319 #ifdef CONFIG_DEBUG_UART_NS16550
321 #include <debug_uart.h>
323 static inline void _debug_uart_init(void)
325 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
329 * We copy the code from above because it is already horribly messy.
330 * Trying to refactor to nicely remove the duplication doesn't seem
331 * feasible. The better fix is to move all users of this driver to
334 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
336 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
337 serial_dout(&com_port->mcr, UART_MCRVAL);
338 serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
340 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
341 serial_dout(&com_port->dll, baud_divisor & 0xff);
342 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
343 serial_dout(&com_port->lcr, UART_LCRVAL);
346 static inline int NS16550_read_baud_divisor(struct NS16550 *com_port)
350 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
351 ret = serial_din(&com_port->dll) & 0xff;
352 ret |= (serial_din(&com_port->dlm) & 0xff) << 8;
353 serial_dout(&com_port->lcr, UART_LCRVAL);
358 static inline void _debug_uart_putc(int ch)
360 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
362 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) {
363 #ifdef CONFIG_DEBUG_UART_NS16550_CHECK_ENABLED
364 if (!NS16550_read_baud_divisor(com_port))
368 serial_dout(&com_port->thr, ch);
375 #if CONFIG_IS_ENABLED(DM_SERIAL)
376 static int ns16550_serial_putc(struct udevice *dev, const char ch)
378 struct NS16550 *const com_port = dev_get_priv(dev);
380 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE))
382 serial_out(ch, &com_port->thr);
385 * Call watchdog_reset() upon newline. This is done here in putc
386 * since the environment code uses a single puts() to print the complete
387 * environment upon "printenv". So we can't put this watchdog call
396 static int ns16550_serial_pending(struct udevice *dev, bool input)
398 struct NS16550 *const com_port = dev_get_priv(dev);
401 return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0;
403 return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1;
406 static int ns16550_serial_getc(struct udevice *dev)
408 struct NS16550 *const com_port = dev_get_priv(dev);
410 if (!(serial_in(&com_port->lsr) & UART_LSR_DR))
413 return serial_in(&com_port->rbr);
416 static int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
418 struct NS16550 *const com_port = dev_get_priv(dev);
419 struct ns16550_platdata *plat = com_port->plat;
422 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate);
424 NS16550_setbrg(com_port, clock_divisor);
429 static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config)
431 struct NS16550 *const com_port = dev_get_priv(dev);
432 int lcr_val = UART_LCR_WLS_8;
433 uint parity = SERIAL_GET_PARITY(serial_config);
434 uint bits = SERIAL_GET_BITS(serial_config);
435 uint stop = SERIAL_GET_STOP(serial_config);
438 * only parity config is implemented, check if other serial settings
439 * are the default one.
441 if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP)
442 return -ENOTSUPP; /* not supported in driver*/
445 case SERIAL_PAR_NONE:
449 lcr_val |= UART_LCR_PEN;
451 case SERIAL_PAR_EVEN:
452 lcr_val |= UART_LCR_PEN | UART_LCR_EPS;
455 return -ENOTSUPP; /* not supported in driver*/
458 serial_out(lcr_val, &com_port->lcr);
462 static int ns16550_serial_getinfo(struct udevice *dev,
463 struct serial_device_info *info)
465 struct NS16550 *const com_port = dev_get_priv(dev);
466 struct ns16550_platdata *plat = com_port->plat;
468 info->type = SERIAL_CHIP_16550_COMPATIBLE;
469 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
470 info->addr_space = SERIAL_ADDRESS_SPACE_IO;
472 info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY;
474 info->addr = plat->base;
475 info->reg_width = plat->reg_width;
476 info->reg_shift = plat->reg_shift;
477 info->reg_offset = plat->reg_offset;
481 int ns16550_serial_probe(struct udevice *dev)
483 struct NS16550 *const com_port = dev_get_priv(dev);
484 struct reset_ctl_bulk reset_bulk;
487 ret = reset_get_bulk(dev, &reset_bulk);
489 reset_deassert_bulk(&reset_bulk);
491 com_port->plat = dev_get_platdata(dev);
492 NS16550_init(com_port, -1);
497 #if CONFIG_IS_ENABLED(OF_CONTROL)
504 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
505 int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
507 struct ns16550_platdata *plat = dev->platdata;
508 const u32 port_type = dev_get_driver_data(dev);
513 /* try Processor Local Bus device first */
514 addr = dev_read_addr_pci(dev);
515 if (addr == FDT_ADDR_T_NONE)
518 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
521 plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
524 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
525 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
526 plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
528 err = clk_get_by_index(dev, 0, &clk);
530 err = clk_get_rate(&clk);
531 if (!IS_ERR_VALUE(err))
533 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
534 debug("ns16550 failed to get clock\n");
539 plat->clock = dev_read_u32_default(dev, "clock-frequency",
540 CONFIG_SYS_NS16550_CLK);
542 debug("ns16550 clock not defined\n");
546 plat->fcr = UART_FCR_DEFVAL;
547 if (port_type == PORT_JZ4780)
548 plat->fcr |= UART_FCR_UME;
554 const struct dm_serial_ops ns16550_serial_ops = {
555 .putc = ns16550_serial_putc,
556 .pending = ns16550_serial_pending,
557 .getc = ns16550_serial_getc,
558 .setbrg = ns16550_serial_setbrg,
559 .setconfig = ns16550_serial_setconfig,
560 .getinfo = ns16550_serial_getinfo,
563 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
565 * Please consider existing compatible strings before adding a new
566 * one to keep this table compact. Or you may add a generic "ns16550"
567 * compatible string to your dts.
569 static const struct udevice_id ns16550_serial_ids[] = {
570 { .compatible = "ns16550", .data = PORT_NS16550 },
571 { .compatible = "ns16550a", .data = PORT_NS16550 },
572 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
573 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
574 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
577 #endif /* OF_CONTROL && !OF_PLATDATA */
579 #if CONFIG_IS_ENABLED(SERIAL_PRESENT)
581 /* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */
582 #if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL)
583 U_BOOT_DRIVER(ns16550_serial) = {
584 .name = "ns16550_serial",
586 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
587 .of_match = ns16550_serial_ids,
588 .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
589 .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
591 .priv_auto_alloc_size = sizeof(struct NS16550),
592 .probe = ns16550_serial_probe,
593 .ops = &ns16550_serial_ops,
594 #if !CONFIG_IS_ENABLED(OF_CONTROL)
595 .flags = DM_FLAG_PRE_RELOC,
599 #endif /* SERIAL_PRESENT */
601 #endif /* CONFIG_DM_SERIAL */