3 * originally from linux source (arch/powerpc/boot/ns16550.c)
4 * modified to use CONFIG_SYS_ISA_MEM and new defines
7 #include <clock_legacy.h>
17 #include <asm/global_data.h>
18 #include <linux/err.h>
19 #include <linux/types.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
25 #define UART_MCRVAL (UART_MCR_DTR | \
26 UART_MCR_RTS) /* RTS/DTR */
28 #if !CONFIG_IS_ENABLED(DM_SERIAL)
29 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
30 #define serial_out(x, y) outb(x, (ulong)y)
31 #define serial_in(y) inb((ulong)y)
32 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0)
33 #define serial_out(x, y) out_be32(y, x)
34 #define serial_in(y) in_be32(y)
35 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0)
36 #define serial_out(x, y) out_le32(y, x)
37 #define serial_in(y) in_le32(y)
39 #define serial_out(x, y) writeb(x, y)
40 #define serial_in(y) readb(y)
42 #endif /* !CONFIG_DM_SERIAL */
44 #if defined(CONFIG_ARCH_KEYSTONE)
45 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0
46 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
48 #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL
49 #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE)
51 #define UART_MCRVAL (UART_MCR_RTS)
55 #ifndef CFG_SYS_NS16550_IER
56 #define CFG_SYS_NS16550_IER 0x00
57 #endif /* CFG_SYS_NS16550_IER */
59 static inline void serial_out_shift(void *addr, int shift, int value)
61 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
62 outb(value, (ulong)addr);
63 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
64 out_le32(addr, value);
65 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
66 out_be32(addr, value);
67 #elif defined(CONFIG_SYS_NS16550_MEM32)
69 #elif defined(CONFIG_SYS_BIG_ENDIAN)
70 writeb(value, addr + (1 << shift) - 1);
76 static inline int serial_in_shift(void *addr, int shift)
78 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
79 return inb((ulong)addr);
80 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
82 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
84 #elif defined(CONFIG_SYS_NS16550_MEM32)
86 #elif defined(CONFIG_SYS_BIG_ENDIAN)
87 return readb(addr + (1 << shift) - 1);
93 #if CONFIG_IS_ENABLED(DM_SERIAL)
95 #ifndef CFG_SYS_NS16550_CLK
96 #define CFG_SYS_NS16550_CLK 0
100 * Use this #ifdef for now since many platforms don't define in(), out(),
101 * out_le32(), etc. but we don't have #defines to indicate this.
103 * TODO(sjg@chromium.org): Add CONFIG options to indicate what I/O is available
106 #ifdef CONFIG_NS16550_DYNAMIC
107 static void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
110 if (plat->flags & NS16550_FLAG_IO) {
112 } else if (plat->reg_width == 4) {
113 if (plat->flags & NS16550_FLAG_ENDIAN) {
114 if (plat->flags & NS16550_FLAG_BE)
115 out_be32(addr, value);
117 out_le32(addr, value);
121 } else if (plat->flags & NS16550_FLAG_BE) {
122 writeb(value, addr + (1 << plat->reg_shift) - 1);
128 static int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
130 if (plat->flags & NS16550_FLAG_IO) {
132 } else if (plat->reg_width == 4) {
133 if (plat->flags & NS16550_FLAG_ENDIAN) {
134 if (plat->flags & NS16550_FLAG_BE)
135 return in_be32(addr);
137 return in_le32(addr);
141 } else if (plat->flags & NS16550_FLAG_BE) {
142 return readb(addr + (1 << plat->reg_shift) - 1);
148 static inline void serial_out_dynamic(struct ns16550_plat *plat, u8 *addr,
153 static inline int serial_in_dynamic(struct ns16550_plat *plat, u8 *addr)
158 #endif /* CONFIG_NS16550_DYNAMIC */
160 static void ns16550_writeb(struct ns16550 *port, int offset, int value)
162 struct ns16550_plat *plat = port->plat;
165 offset *= 1 << plat->reg_shift;
166 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
168 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
169 serial_out_dynamic(plat, addr, value);
171 serial_out_shift(addr, plat->reg_shift, value);
174 static int ns16550_readb(struct ns16550 *port, int offset)
176 struct ns16550_plat *plat = port->plat;
179 offset *= 1 << plat->reg_shift;
180 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
182 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
183 return serial_in_dynamic(plat, addr);
185 return serial_in_shift(addr, plat->reg_shift);
188 static u32 ns16550_getfcr(struct ns16550 *port)
190 struct ns16550_plat *plat = port->plat;
195 /* We can clean these up once everything is moved to driver model */
196 #define serial_out(value, addr) \
197 ns16550_writeb(com_port, \
198 (unsigned char *)addr - (unsigned char *)com_port, value)
199 #define serial_in(addr) \
200 ns16550_readb(com_port, \
201 (unsigned char *)addr - (unsigned char *)com_port)
203 static u32 ns16550_getfcr(struct ns16550 *port)
205 return UART_FCR_DEFVAL;
209 int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate)
211 const unsigned int mode_x_div = 16;
213 return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
216 static void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor)
218 /* to keep serial format, read lcr before writing BKSE */
219 int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE;
221 serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr);
222 serial_out(baud_divisor & 0xff, &com_port->dll);
223 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
224 serial_out(lcr_val, &com_port->lcr);
227 void ns16550_init(struct ns16550 *com_port, int baud_divisor)
229 #if (defined(CONFIG_SPL_BUILD) && \
230 (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX)))
232 * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
233 * before SPL starts only THRE bit is set. We have to empty the
234 * transmitter before initialization starts.
236 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
238 if (baud_divisor != -1)
239 ns16550_setbrg(com_port, baud_divisor);
241 // Re-use old baud rate divisor to flush transmit reg.
242 const int dll = serial_in(&com_port->dll);
243 const int dlm = serial_in(&com_port->dlm);
244 const int divisor = dll | (dlm << 8);
245 ns16550_setbrg(com_port, divisor);
247 serial_out(0, &com_port->mdr1);
251 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
254 serial_out(CFG_SYS_NS16550_IER, &com_port->ier);
255 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL)
256 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
259 serial_out(UART_MCRVAL, &com_port->mcr);
260 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
261 /* initialize serial config to 8N1 before writing baudrate */
262 serial_out(UART_LCRVAL, &com_port->lcr);
263 if (baud_divisor != -1)
264 ns16550_setbrg(com_port, baud_divisor);
265 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \
266 defined(CONFIG_OMAP_SERIAL)
267 /* /16 is proper to hit 115200 with 48MHz */
268 serial_out(0, &com_port->mdr1);
270 #if defined(CONFIG_ARCH_KEYSTONE)
271 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
275 #if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
276 void ns16550_reinit(struct ns16550 *com_port, int baud_divisor)
278 serial_out(CFG_SYS_NS16550_IER, &com_port->ier);
279 ns16550_setbrg(com_port, 0);
280 serial_out(UART_MCRVAL, &com_port->mcr);
281 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
282 ns16550_setbrg(com_port, baud_divisor);
284 #endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */
286 void ns16550_putc(struct ns16550 *com_port, char c)
288 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0)
290 serial_out(c, &com_port->thr);
293 * Call watchdog_reset() upon newline. This is done here in putc
294 * since the environment code uses a single puts() to print the complete
295 * environment upon "printenv". So we can't put this watchdog call
302 #if !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS)
303 char ns16550_getc(struct ns16550 *com_port)
305 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
306 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY)
307 extern void usbtty_poll(void);
312 return serial_in(&com_port->rbr);
315 int ns16550_tstc(struct ns16550 *com_port)
317 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
320 #endif /* !CONFIG_IS_ENABLED(NS16550_MIN_FUNCTIONS) */
322 #ifdef CONFIG_DEBUG_UART_NS16550
324 #include <debug_uart.h>
326 static inline void _debug_uart_init(void)
328 struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
331 /* Wait until tx buffer is empty */
332 while (!(serial_din(&com_port->lsr) & UART_LSR_TEMT))
336 * We copy the code from above because it is already horribly messy.
337 * Trying to refactor to nicely remove the duplication doesn't seem
338 * feasible. The better fix is to move all users of this driver to
341 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
343 serial_dout(&com_port->ier, CFG_SYS_NS16550_IER);
344 serial_dout(&com_port->mcr, UART_MCRVAL);
345 serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
347 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
348 serial_dout(&com_port->dll, baud_divisor & 0xff);
349 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
350 serial_dout(&com_port->lcr, UART_LCRVAL);
353 static inline int NS16550_read_baud_divisor(struct ns16550 *com_port)
357 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
358 ret = serial_din(&com_port->dll) & 0xff;
359 ret |= (serial_din(&com_port->dlm) & 0xff) << 8;
360 serial_dout(&com_port->lcr, UART_LCRVAL);
365 static inline void _debug_uart_putc(int ch)
367 struct ns16550 *com_port = (struct ns16550 *)CONFIG_VAL(DEBUG_UART_BASE);
369 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) {
370 #ifdef CONFIG_DEBUG_UART_NS16550_CHECK_ENABLED
371 if (!NS16550_read_baud_divisor(com_port))
375 serial_dout(&com_port->thr, ch);
382 #if CONFIG_IS_ENABLED(DM_SERIAL)
383 static int ns16550_serial_putc(struct udevice *dev, const char ch)
385 struct ns16550 *const com_port = dev_get_priv(dev);
387 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE))
389 serial_out(ch, &com_port->thr);
392 * Call watchdog_reset() upon newline. This is done here in putc
393 * since the environment code uses a single puts() to print the complete
394 * environment upon "printenv". So we can't put this watchdog call
403 static int ns16550_serial_pending(struct udevice *dev, bool input)
405 struct ns16550 *const com_port = dev_get_priv(dev);
408 return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0;
410 return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1;
413 static int ns16550_serial_getc(struct udevice *dev)
415 struct ns16550 *const com_port = dev_get_priv(dev);
417 if (!(serial_in(&com_port->lsr) & UART_LSR_DR))
420 return serial_in(&com_port->rbr);
423 static int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
425 struct ns16550 *const com_port = dev_get_priv(dev);
426 struct ns16550_plat *plat = com_port->plat;
429 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate);
431 ns16550_setbrg(com_port, clock_divisor);
436 static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config)
438 struct ns16550 *const com_port = dev_get_priv(dev);
439 int lcr_val = UART_LCR_WLS_8;
440 uint parity = SERIAL_GET_PARITY(serial_config);
441 uint bits = SERIAL_GET_BITS(serial_config);
442 uint stop = SERIAL_GET_STOP(serial_config);
445 * only parity config is implemented, check if other serial settings
446 * are the default one.
448 if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP)
449 return -ENOTSUPP; /* not supported in driver*/
452 case SERIAL_PAR_NONE:
456 lcr_val |= UART_LCR_PEN;
458 case SERIAL_PAR_EVEN:
459 lcr_val |= UART_LCR_PEN | UART_LCR_EPS;
462 return -ENOTSUPP; /* not supported in driver*/
465 serial_out(lcr_val, &com_port->lcr);
469 static int ns16550_serial_getinfo(struct udevice *dev,
470 struct serial_device_info *info)
472 struct ns16550 *const com_port = dev_get_priv(dev);
473 struct ns16550_plat *plat = com_port->plat;
475 info->type = SERIAL_CHIP_16550_COMPATIBLE;
476 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
477 info->addr_space = SERIAL_ADDRESS_SPACE_IO;
479 info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY;
481 info->addr = plat->base;
482 info->reg_width = plat->reg_width;
483 info->reg_shift = plat->reg_shift;
484 info->reg_offset = plat->reg_offset;
485 info->clock = plat->clock;
490 static int ns16550_serial_assign_base(struct ns16550_plat *plat, fdt_addr_t base)
492 if (base == FDT_ADDR_T_NONE)
495 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
498 plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE);
504 int ns16550_serial_probe(struct udevice *dev)
506 struct ns16550_plat *plat = dev_get_plat(dev);
507 struct ns16550 *const com_port = dev_get_priv(dev);
508 struct reset_ctl_bulk reset_bulk;
513 * If we are on PCI bus, either directly attached to a PCI root port,
514 * or via a PCI bridge, assign plat->base before probing hardware.
516 if (device_is_on_pci_bus(dev)) {
517 addr = devfdt_get_addr_pci(dev);
518 ret = ns16550_serial_assign_base(plat, addr);
523 ret = reset_get_bulk(dev, &reset_bulk);
525 reset_deassert_bulk(&reset_bulk);
527 com_port->plat = dev_get_plat(dev);
528 ns16550_init(com_port, -1);
533 #if CONFIG_IS_ENABLED(OF_CONTROL)
540 #if CONFIG_IS_ENABLED(OF_REAL)
541 int ns16550_serial_of_to_plat(struct udevice *dev)
543 struct ns16550_plat *plat = dev_get_plat(dev);
544 const u32 port_type = dev_get_driver_data(dev);
549 addr = dev_read_addr(dev);
550 err = ns16550_serial_assign_base(plat, addr);
551 if (err && !device_is_on_pci_bus(dev))
554 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
555 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
556 plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
558 err = clk_get_by_index(dev, 0, &clk);
560 err = clk_get_rate(&clk);
561 if (!IS_ERR_VALUE(err))
563 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
564 debug("ns16550 failed to get clock\n");
569 plat->clock = dev_read_u32_default(dev, "clock-frequency",
570 CFG_SYS_NS16550_CLK);
572 plat->clock = CFG_SYS_NS16550_CLK;
574 debug("ns16550 clock not defined\n");
578 plat->fcr = UART_FCR_DEFVAL;
579 if (port_type == PORT_JZ4780)
580 plat->fcr |= UART_FCR_UME;
586 const struct dm_serial_ops ns16550_serial_ops = {
587 .putc = ns16550_serial_putc,
588 .pending = ns16550_serial_pending,
589 .getc = ns16550_serial_getc,
590 .setbrg = ns16550_serial_setbrg,
591 .setconfig = ns16550_serial_setconfig,
592 .getinfo = ns16550_serial_getinfo,
595 #if CONFIG_IS_ENABLED(OF_REAL)
597 * Please consider existing compatible strings before adding a new
598 * one to keep this table compact. Or you may add a generic "ns16550"
599 * compatible string to your dts.
601 static const struct udevice_id ns16550_serial_ids[] = {
602 { .compatible = "ns16550", .data = PORT_NS16550 },
603 { .compatible = "ns16550a", .data = PORT_NS16550 },
604 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
605 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
606 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
611 #if CONFIG_IS_ENABLED(SERIAL_PRESENT)
613 /* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */
614 #if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL)
615 U_BOOT_DRIVER(ns16550_serial) = {
616 .name = "ns16550_serial",
618 #if CONFIG_IS_ENABLED(OF_REAL)
619 .of_match = ns16550_serial_ids,
620 .of_to_plat = ns16550_serial_of_to_plat,
621 .plat_auto = sizeof(struct ns16550_plat),
623 .priv_auto = sizeof(struct ns16550),
624 .probe = ns16550_serial_probe,
625 .ops = &ns16550_serial_ops,
626 #if !CONFIG_IS_ENABLED(OF_CONTROL)
627 .flags = DM_FLAG_PRE_RELOC,
631 DM_DRIVER_ALIAS(ns16550_serial, ti_da830_uart)
633 #endif /* SERIAL_PRESENT */
635 #endif /* CONFIG_DM_SERIAL */