3 * originally from linux source (arch/powerpc/boot/ns16550.c)
4 * modified to use CONFIG_SYS_ISA_MEM and new defines
7 #include <clock_legacy.h>
16 #include <linux/err.h>
17 #include <linux/types.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
23 #define UART_MCRVAL (UART_MCR_DTR | \
24 UART_MCR_RTS) /* RTS/DTR */
26 #if !CONFIG_IS_ENABLED(DM_SERIAL)
27 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
28 #define serial_out(x, y) outb(x, (ulong)y)
29 #define serial_in(y) inb((ulong)y)
30 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0)
31 #define serial_out(x, y) out_be32(y, x)
32 #define serial_in(y) in_be32(y)
33 #elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0)
34 #define serial_out(x, y) out_le32(y, x)
35 #define serial_in(y) in_le32(y)
37 #define serial_out(x, y) writeb(x, y)
38 #define serial_in(y) readb(y)
40 #endif /* !CONFIG_DM_SERIAL */
42 #if defined(CONFIG_SOC_KEYSTONE)
43 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0
44 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
46 #ifdef CONFIG_SERIAL_HW_FLOW_CONTROL
47 #define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE)
49 #define UART_MCRVAL (UART_MCR_RTS)
53 #ifndef CONFIG_SYS_NS16550_IER
54 #define CONFIG_SYS_NS16550_IER 0x00
55 #endif /* CONFIG_SYS_NS16550_IER */
57 static inline void serial_out_shift(void *addr, int shift, int value)
59 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
60 outb(value, (ulong)addr);
61 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
62 out_le32(addr, value);
63 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
64 out_be32(addr, value);
65 #elif defined(CONFIG_SYS_NS16550_MEM32)
67 #elif defined(CONFIG_SYS_BIG_ENDIAN)
68 writeb(value, addr + (1 << shift) - 1);
74 static inline int serial_in_shift(void *addr, int shift)
76 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
77 return inb((ulong)addr);
78 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
80 #elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
82 #elif defined(CONFIG_SYS_NS16550_MEM32)
84 #elif defined(CONFIG_SYS_BIG_ENDIAN)
85 return readb(addr + (1 << shift) - 1);
91 #if CONFIG_IS_ENABLED(DM_SERIAL)
93 #ifndef CONFIG_SYS_NS16550_CLK
94 #define CONFIG_SYS_NS16550_CLK 0
98 * Use this #ifdef for now since many platforms don't define in(), out(),
99 * out_le32(), etc. but we don't have #defines to indicate this.
101 * TODO(sjg@chromium.org): Add CONFIG options to indicate what I/O is available
104 #ifdef CONFIG_NS16550_DYNAMIC
105 static void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
108 if (plat->flags & NS16550_FLAG_IO) {
110 } else if (plat->reg_width == 4) {
111 if (plat->flags & NS16550_FLAG_ENDIAN) {
112 if (plat->flags & NS16550_FLAG_BE)
113 out_be32(addr, value);
115 out_le32(addr, value);
119 } else if (plat->flags & NS16550_FLAG_BE) {
120 writeb(value, addr + (1 << plat->reg_shift) - 1);
126 static int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
128 if (plat->flags & NS16550_FLAG_IO) {
130 } else if (plat->reg_width == 4) {
131 if (plat->flags & NS16550_FLAG_ENDIAN) {
132 if (plat->flags & NS16550_FLAG_BE)
133 return in_be32(addr);
135 return in_le32(addr);
139 } else if (plat->flags & NS16550_FLAG_BE) {
140 return readb(addr + (1 << plat->reg_shift) - 1);
146 static inline void serial_out_dynamic(struct ns16550_platdata *plat, u8 *addr,
151 static inline int serial_in_dynamic(struct ns16550_platdata *plat, u8 *addr)
156 #endif /* CONFIG_NS16550_DYNAMIC */
158 static void ns16550_writeb(NS16550_t port, int offset, int value)
160 struct ns16550_platdata *plat = port->plat;
163 offset *= 1 << plat->reg_shift;
164 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
166 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
167 serial_out_dynamic(plat, addr, value);
169 serial_out_shift(addr, plat->reg_shift, value);
172 static int ns16550_readb(NS16550_t port, int offset)
174 struct ns16550_platdata *plat = port->plat;
177 offset *= 1 << plat->reg_shift;
178 addr = (unsigned char *)plat->base + offset + plat->reg_offset;
180 if (IS_ENABLED(CONFIG_NS16550_DYNAMIC))
181 return serial_in_dynamic(plat, addr);
183 return serial_in_shift(addr, plat->reg_shift);
186 static u32 ns16550_getfcr(NS16550_t port)
188 struct ns16550_platdata *plat = port->plat;
193 /* We can clean these up once everything is moved to driver model */
194 #define serial_out(value, addr) \
195 ns16550_writeb(com_port, \
196 (unsigned char *)addr - (unsigned char *)com_port, value)
197 #define serial_in(addr) \
198 ns16550_readb(com_port, \
199 (unsigned char *)addr - (unsigned char *)com_port)
201 static u32 ns16550_getfcr(NS16550_t port)
203 return UART_FCR_DEFVAL;
207 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate)
209 const unsigned int mode_x_div = 16;
211 return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
214 static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
216 /* to keep serial format, read lcr before writing BKSE */
217 int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE;
219 serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr);
220 serial_out(baud_divisor & 0xff, &com_port->dll);
221 serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
222 serial_out(lcr_val, &com_port->lcr);
225 void NS16550_init(NS16550_t com_port, int baud_divisor)
227 #if (defined(CONFIG_SPL_BUILD) && \
228 (defined(CONFIG_OMAP34XX) || defined(CONFIG_OMAP44XX)))
230 * On some OMAP3/OMAP4 devices when UART3 is configured for boot mode
231 * before SPL starts only THRE bit is set. We have to empty the
232 * transmitter before initialization starts.
234 if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE))
236 if (baud_divisor != -1)
237 NS16550_setbrg(com_port, baud_divisor);
239 // Re-use old baud rate divisor to flush transmit reg.
240 const int dll = serial_in(&com_port->dll);
241 const int dlm = serial_in(&com_port->dlm);
242 const int divisor = dll | (dlm << 8);
243 NS16550_setbrg(com_port, divisor);
245 serial_out(0, &com_port->mdr1);
249 while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
252 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
253 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_OMAP_SERIAL)
254 serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
257 serial_out(UART_MCRVAL, &com_port->mcr);
258 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
259 /* initialize serial config to 8N1 before writing baudrate */
260 serial_out(UART_LCRVAL, &com_port->lcr);
261 if (baud_divisor != -1)
262 NS16550_setbrg(com_port, baud_divisor);
263 #if defined(CONFIG_ARCH_OMAP2PLUS) || defined(CONFIG_SOC_DA8XX) || \
264 defined(CONFIG_OMAP_SERIAL)
265 /* /16 is proper to hit 115200 with 48MHz */
266 serial_out(0, &com_port->mdr1);
268 #if defined(CONFIG_SOC_KEYSTONE)
269 serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC);
273 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
274 void NS16550_reinit(NS16550_t com_port, int baud_divisor)
276 serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
277 NS16550_setbrg(com_port, 0);
278 serial_out(UART_MCRVAL, &com_port->mcr);
279 serial_out(ns16550_getfcr(com_port), &com_port->fcr);
280 NS16550_setbrg(com_port, baud_divisor);
282 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
284 void NS16550_putc(NS16550_t com_port, char c)
286 while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0)
288 serial_out(c, &com_port->thr);
291 * Call watchdog_reset() upon newline. This is done here in putc
292 * since the environment code uses a single puts() to print the complete
293 * environment upon "printenv". So we can't put this watchdog call
300 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
301 char NS16550_getc(NS16550_t com_port)
303 while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
304 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY)
305 extern void usbtty_poll(void);
310 return serial_in(&com_port->rbr);
313 int NS16550_tstc(NS16550_t com_port)
315 return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
318 #endif /* CONFIG_NS16550_MIN_FUNCTIONS */
320 #ifdef CONFIG_DEBUG_UART_NS16550
322 #include <debug_uart.h>
324 static inline void _debug_uart_init(void)
326 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
330 * We copy the code from above because it is already horribly messy.
331 * Trying to refactor to nicely remove the duplication doesn't seem
332 * feasible. The better fix is to move all users of this driver to
335 baud_divisor = ns16550_calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
337 serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
338 serial_dout(&com_port->mcr, UART_MCRVAL);
339 serial_dout(&com_port->fcr, UART_FCR_DEFVAL);
341 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
342 serial_dout(&com_port->dll, baud_divisor & 0xff);
343 serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
344 serial_dout(&com_port->lcr, UART_LCRVAL);
347 static inline int NS16550_read_baud_divisor(struct NS16550 *com_port)
351 serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
352 ret = serial_din(&com_port->dll) & 0xff;
353 ret |= (serial_din(&com_port->dlm) & 0xff) << 8;
354 serial_dout(&com_port->lcr, UART_LCRVAL);
359 static inline void _debug_uart_putc(int ch)
361 struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
363 while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) {
364 #ifdef CONFIG_DEBUG_UART_NS16550_CHECK_ENABLED
365 if (!NS16550_read_baud_divisor(com_port))
369 serial_dout(&com_port->thr, ch);
376 #if CONFIG_IS_ENABLED(DM_SERIAL)
377 static int ns16550_serial_putc(struct udevice *dev, const char ch)
379 struct NS16550 *const com_port = dev_get_priv(dev);
381 if (!(serial_in(&com_port->lsr) & UART_LSR_THRE))
383 serial_out(ch, &com_port->thr);
386 * Call watchdog_reset() upon newline. This is done here in putc
387 * since the environment code uses a single puts() to print the complete
388 * environment upon "printenv". So we can't put this watchdog call
397 static int ns16550_serial_pending(struct udevice *dev, bool input)
399 struct NS16550 *const com_port = dev_get_priv(dev);
402 return (serial_in(&com_port->lsr) & UART_LSR_DR) ? 1 : 0;
404 return (serial_in(&com_port->lsr) & UART_LSR_THRE) ? 0 : 1;
407 static int ns16550_serial_getc(struct udevice *dev)
409 struct NS16550 *const com_port = dev_get_priv(dev);
411 if (!(serial_in(&com_port->lsr) & UART_LSR_DR))
414 return serial_in(&com_port->rbr);
417 static int ns16550_serial_setbrg(struct udevice *dev, int baudrate)
419 struct NS16550 *const com_port = dev_get_priv(dev);
420 struct ns16550_platdata *plat = com_port->plat;
423 clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate);
425 NS16550_setbrg(com_port, clock_divisor);
430 static int ns16550_serial_setconfig(struct udevice *dev, uint serial_config)
432 struct NS16550 *const com_port = dev_get_priv(dev);
433 int lcr_val = UART_LCR_WLS_8;
434 uint parity = SERIAL_GET_PARITY(serial_config);
435 uint bits = SERIAL_GET_BITS(serial_config);
436 uint stop = SERIAL_GET_STOP(serial_config);
439 * only parity config is implemented, check if other serial settings
440 * are the default one.
442 if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP)
443 return -ENOTSUPP; /* not supported in driver*/
446 case SERIAL_PAR_NONE:
450 lcr_val |= UART_LCR_PEN;
452 case SERIAL_PAR_EVEN:
453 lcr_val |= UART_LCR_PEN | UART_LCR_EPS;
456 return -ENOTSUPP; /* not supported in driver*/
459 serial_out(lcr_val, &com_port->lcr);
463 static int ns16550_serial_getinfo(struct udevice *dev,
464 struct serial_device_info *info)
466 struct NS16550 *const com_port = dev_get_priv(dev);
467 struct ns16550_platdata *plat = com_port->plat;
469 info->type = SERIAL_CHIP_16550_COMPATIBLE;
470 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
471 info->addr_space = SERIAL_ADDRESS_SPACE_IO;
473 info->addr_space = SERIAL_ADDRESS_SPACE_MEMORY;
475 info->addr = plat->base;
476 info->reg_width = plat->reg_width;
477 info->reg_shift = plat->reg_shift;
478 info->reg_offset = plat->reg_offset;
482 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
483 static int ns1655_serial_set_base_addr(struct udevice *dev)
486 struct ns16550_platdata *plat;
488 plat = dev_get_platdata(dev);
490 addr = dev_read_addr_pci(dev);
491 if (addr == FDT_ADDR_T_NONE)
494 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
497 plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
504 int ns16550_serial_probe(struct udevice *dev)
506 struct NS16550 *const com_port = dev_get_priv(dev);
507 struct reset_ctl_bulk reset_bulk;
510 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
511 ret = ns1655_serial_set_base_addr(dev);
516 ret = reset_get_bulk(dev, &reset_bulk);
518 reset_deassert_bulk(&reset_bulk);
520 com_port->plat = dev_get_platdata(dev);
521 NS16550_init(com_port, -1);
526 #if CONFIG_IS_ENABLED(OF_CONTROL)
533 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
534 int ns16550_serial_ofdata_to_platdata(struct udevice *dev)
536 struct ns16550_platdata *plat = dev->platdata;
537 const u32 port_type = dev_get_driver_data(dev);
541 plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0);
542 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0);
543 plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1);
545 err = clk_get_by_index(dev, 0, &clk);
547 err = clk_get_rate(&clk);
548 if (!IS_ERR_VALUE(err))
550 } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
551 debug("ns16550 failed to get clock\n");
556 plat->clock = dev_read_u32_default(dev, "clock-frequency",
557 CONFIG_SYS_NS16550_CLK);
559 debug("ns16550 clock not defined\n");
563 plat->fcr = UART_FCR_DEFVAL;
564 if (port_type == PORT_JZ4780)
565 plat->fcr |= UART_FCR_UME;
571 const struct dm_serial_ops ns16550_serial_ops = {
572 .putc = ns16550_serial_putc,
573 .pending = ns16550_serial_pending,
574 .getc = ns16550_serial_getc,
575 .setbrg = ns16550_serial_setbrg,
576 .setconfig = ns16550_serial_setconfig,
577 .getinfo = ns16550_serial_getinfo,
580 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
582 * Please consider existing compatible strings before adding a new
583 * one to keep this table compact. Or you may add a generic "ns16550"
584 * compatible string to your dts.
586 static const struct udevice_id ns16550_serial_ids[] = {
587 { .compatible = "ns16550", .data = PORT_NS16550 },
588 { .compatible = "ns16550a", .data = PORT_NS16550 },
589 { .compatible = "ingenic,jz4780-uart", .data = PORT_JZ4780 },
590 { .compatible = "nvidia,tegra20-uart", .data = PORT_NS16550 },
591 { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 },
594 #endif /* OF_CONTROL && !OF_PLATDATA */
596 #if CONFIG_IS_ENABLED(SERIAL_PRESENT)
598 /* TODO(sjg@chromium.org): Integrate this into a macro like CONFIG_IS_ENABLED */
599 #if !defined(CONFIG_TPL_BUILD) || defined(CONFIG_TPL_DM_SERIAL)
600 U_BOOT_DRIVER(ns16550_serial) = {
601 .name = "ns16550_serial",
603 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
604 .of_match = ns16550_serial_ids,
605 .ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
606 .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
608 .priv_auto_alloc_size = sizeof(struct NS16550),
609 .probe = ns16550_serial_probe,
610 .ops = &ns16550_serial_ops,
611 #if !CONFIG_IS_ENABLED(OF_CONTROL)
612 .flags = DM_FLAG_PRE_RELOC,
616 #endif /* SERIAL_PRESENT */
618 #endif /* CONFIG_DM_SERIAL */