2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial_core.h>
26 #include <linux/8250_pci.h>
27 #include <linux/bitops.h>
29 #include <asm/byteorder.h>
34 #undef SERIAL_DEBUG_PCI
37 * init function returns:
38 * > 0 - number of ports
39 * = 0 - use board->num_ports
42 struct pci_serial_quirk {
47 int (*init)(struct pci_dev *dev);
48 int (*setup)(struct serial_private *, struct pciserial_board *,
49 struct uart_port *, int);
50 void (*exit)(struct pci_dev *dev);
53 #define PCI_NUM_BAR_RESOURCES 6
55 struct serial_private {
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
63 static void moan_device(const char *str, struct pci_dev *dev)
65 printk(KERN_WARNING "%s: %s\n"
66 KERN_WARNING "Please send the output of lspci -vv, this\n"
67 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 KERN_WARNING "manufacturer and name of serial board or\n"
69 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
75 setup_port(struct serial_private *priv, struct uart_port *port,
76 int bar, int offset, int regshift)
78 struct pci_dev *dev = priv->dev;
79 unsigned long base, len;
81 if (bar >= PCI_NUM_BAR_RESOURCES)
84 base = pci_resource_start(dev, bar);
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 len = pci_resource_len(dev, bar);
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap(base, len);
91 if (!priv->remapped_bar[bar])
94 port->iotype = UPIO_MEM;
96 port->mapbase = base + offset;
97 port->membase = priv->remapped_bar[bar] + offset;
98 port->regshift = regshift;
100 port->iotype = UPIO_PORT;
101 port->iobase = base + offset;
103 port->membase = NULL;
110 * AFAVLAB uses a different mixture of BARs and offsets
111 * Not that ugly ;) -- HW
114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
115 struct uart_port *port, int idx)
117 unsigned int bar, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
124 offset += (idx - 4) * board->uart_offset;
127 return setup_port(priv, port, bar, offset, board->reg_shift);
131 * HP's Remote Management Console. The Diva chip came in several
132 * different versions. N-class, L2000 and A500 have two Diva chips, each
133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
135 * one Diva chip, but it has been expanded to 5 UARTs.
137 static int pci_hp_diva_init(struct pci_dev *dev)
141 switch (dev->subsystem_device) {
142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
145 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
155 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
164 * HP's Diva chip puts the 4th/5th serial port further out, and
165 * some serial ports are supposed to be hidden on certain models.
168 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
169 struct uart_port *port, int idx)
171 unsigned int offset = board->first_offset;
172 unsigned int bar = FL_GET_BASE(board->flags);
174 switch (priv->dev->subsystem_device) {
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
189 offset += idx * board->uart_offset;
191 return setup_port(priv, port, bar, offset, board->reg_shift);
195 * Added for EKF Intel i960 serial boards
197 static int pci_inteli960ni_init(struct pci_dev *dev)
199 unsigned long oldval;
201 if (!(dev->subsystem_device & 0x1000))
204 /* is firmware started? */
205 pci_read_config_dword(dev, 0x44, (void*) &oldval);
206 if (oldval == 0x00001000L) { /* RESET value */
207 printk(KERN_DEBUG "Local i960 firmware missing");
214 * Some PCI serial cards using the PLX 9050 PCI interface chip require
215 * that the card interrupt be explicitly enabled or disabled. This
216 * seems to be mainly needed on card using the PLX which also use I/O
219 static int pci_plx9050_init(struct pci_dev *dev)
224 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
225 moan_device("no memory in bar 0", dev);
230 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
231 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
234 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
235 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
237 * As the megawolf cards have the int pins active
238 * high, and have 2 UART chips, both ints must be
239 * enabled on the 9050. Also, the UARTS are set in
240 * 16450 mode by default, so we have to enable the
241 * 16C950 'enhanced' mode so that we can use the
248 * enable/disable interrupts
250 p = ioremap(pci_resource_start(dev, 0), 0x80);
253 writel(irq_config, p + 0x4c);
256 * Read the register back to ensure that it took effect.
264 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
268 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
274 p = ioremap(pci_resource_start(dev, 0), 0x80);
279 * Read the register back to ensure that it took effect.
286 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
288 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
289 struct uart_port *port, int idx)
291 unsigned int bar, offset = board->first_offset;
296 /* first four channels map to 0, 0x100, 0x200, 0x300 */
297 offset += idx * board->uart_offset;
298 } else if (idx < 8) {
299 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
300 offset += idx * board->uart_offset + 0xC00;
301 } else /* we have only 8 ports on PMC-OCTALPRO */
304 return setup_port(priv, port, bar, offset, board->reg_shift);
308 * This does initialization for PMC OCTALPRO cards:
309 * maps the device memory, resets the UARTs (needed, bc
310 * if the module is removed and inserted again, the card
311 * is in the sleep mode) and enables global interrupt.
314 /* global control register offset for SBS PMC-OctalPro */
315 #define OCT_REG_CR_OFF 0x500
317 static int sbs_init(struct pci_dev *dev)
321 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
325 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
326 writeb(0x10,p + OCT_REG_CR_OFF);
328 writeb(0x0,p + OCT_REG_CR_OFF);
330 /* Set bit-2 (INTENABLE) of Control Register */
331 writeb(0x4, p + OCT_REG_CR_OFF);
338 * Disables the global interrupt of PMC-OctalPro
341 static void __devexit sbs_exit(struct pci_dev *dev)
345 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
347 writeb(0, p + OCT_REG_CR_OFF);
353 * SIIG serial cards have an PCI interface chip which also controls
354 * the UART clocking frequency. Each UART can be clocked independently
355 * (except cards equiped with 4 UARTs) and initial clocking settings
356 * are stored in the EEPROM chip. It can cause problems because this
357 * version of serial driver doesn't support differently clocked UART's
358 * on single PCI card. To prevent this, initialization functions set
359 * high frequency clocking for all UART's on given card. It is safe (I
360 * hope) because it doesn't touch EEPROM settings to prevent conflicts
361 * with other OSes (like M$ DOS).
363 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
365 * There is two family of SIIG serial cards with different PCI
366 * interface chip and different configuration methods:
367 * - 10x cards have control registers in IO and/or memory space;
368 * - 20x cards have control registers in standard PCI configuration space.
370 * Note: all 10x cards have PCI device ids 0x10..
371 * all 20x cards have PCI device ids 0x20..
373 * There are also Quartet Serial cards which use Oxford Semiconductor
374 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
376 * Note: some SIIG cards are probed by the parport_serial object.
379 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
380 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
382 static int pci_siig10x_init(struct pci_dev *dev)
387 switch (dev->device & 0xfff8) {
388 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
391 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
394 default: /* 1S1P, 4S */
399 p = ioremap(pci_resource_start(dev, 0), 0x80);
403 writew(readw(p + 0x28) & data, p + 0x28);
409 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
410 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
412 static int pci_siig20x_init(struct pci_dev *dev)
416 /* Change clock frequency for the first UART. */
417 pci_read_config_byte(dev, 0x6f, &data);
418 pci_write_config_byte(dev, 0x6f, data & 0xef);
420 /* If this card has 2 UART, we have to do the same with second UART. */
421 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
422 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
423 pci_read_config_byte(dev, 0x73, &data);
424 pci_write_config_byte(dev, 0x73, data & 0xef);
429 static int pci_siig_init(struct pci_dev *dev)
431 unsigned int type = dev->device & 0xff00;
434 return pci_siig10x_init(dev);
435 else if (type == 0x2000)
436 return pci_siig20x_init(dev);
438 moan_device("Unknown SIIG card", dev);
442 static int pci_siig_setup(struct serial_private *priv,
443 struct pciserial_board *board,
444 struct uart_port *port, int idx)
446 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
450 offset = (idx - 4) * 8;
453 return setup_port(priv, port, bar, offset, 0);
457 * Timedia has an explosion of boards, and to avoid the PCI table from
458 * growing *huge*, we use this function to collapse some 70 entries
459 * in the PCI table into one, for sanity's and compactness's sake.
461 static const unsigned short timedia_single_port[] = {
462 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
465 static const unsigned short timedia_dual_port[] = {
466 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
467 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
468 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
469 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
473 static const unsigned short timedia_quad_port[] = {
474 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
475 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
476 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
480 static const unsigned short timedia_eight_port[] = {
481 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
482 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
485 static const struct timedia_struct {
487 const unsigned short *ids;
489 { 1, timedia_single_port },
490 { 2, timedia_dual_port },
491 { 4, timedia_quad_port },
492 { 8, timedia_eight_port }
495 static int pci_timedia_init(struct pci_dev *dev)
497 const unsigned short *ids;
500 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
501 ids = timedia_data[i].ids;
502 for (j = 0; ids[j]; j++)
503 if (dev->subsystem_device == ids[j])
504 return timedia_data[i].num;
510 * Timedia/SUNIX uses a mixture of BARs and offsets
511 * Ugh, this is ugly as all hell --- TYT
514 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
515 struct uart_port *port, int idx)
517 unsigned int bar = 0, offset = board->first_offset;
524 offset = board->uart_offset;
531 offset = board->uart_offset;
540 return setup_port(priv, port, bar, offset, board->reg_shift);
544 * Some Titan cards are also a little weird
547 titan_400l_800l_setup(struct serial_private *priv,
548 struct pciserial_board *board,
549 struct uart_port *port, int idx)
551 unsigned int bar, offset = board->first_offset;
562 offset = (idx - 2) * board->uart_offset;
565 return setup_port(priv, port, bar, offset, board->reg_shift);
568 static int pci_xircom_init(struct pci_dev *dev)
574 static int pci_netmos_init(struct pci_dev *dev)
576 /* subdevice 0x00PS means <P> parallel, <S> serial */
577 unsigned int num_serial = dev->subsystem_device & 0xf;
585 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
586 struct uart_port *port, int idx)
588 unsigned int bar, offset = board->first_offset, maxnr;
590 bar = FL_GET_BASE(board->flags);
591 if (board->flags & FL_BASE_BARS)
594 offset += idx * board->uart_offset;
596 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
597 (board->reg_shift + 3);
599 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
602 return setup_port(priv, port, bar, offset, board->reg_shift);
605 /* This should be in linux/pci_ids.h */
606 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
607 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
608 #define PCI_DEVICE_ID_OCTPRO 0x0001
609 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
610 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
611 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
612 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
615 * Master list of serial port init/setup/exit quirks.
616 * This does not describe the general nature of the port.
617 * (ie, baud base, number and location of ports, etc)
619 * This list is ordered alphabetically by vendor then device.
620 * Specific entries must come before more generic entries.
622 static struct pci_serial_quirk pci_serial_quirks[] = {
624 * AFAVLAB cards - these may be called via parport_serial
625 * It is not clear whether this applies to all products.
628 .vendor = PCI_VENDOR_ID_AFAVLAB,
629 .device = PCI_ANY_ID,
630 .subvendor = PCI_ANY_ID,
631 .subdevice = PCI_ANY_ID,
632 .setup = afavlab_setup,
638 .vendor = PCI_VENDOR_ID_HP,
639 .device = PCI_DEVICE_ID_HP_DIVA,
640 .subvendor = PCI_ANY_ID,
641 .subdevice = PCI_ANY_ID,
642 .init = pci_hp_diva_init,
643 .setup = pci_hp_diva_setup,
649 .vendor = PCI_VENDOR_ID_INTEL,
650 .device = PCI_DEVICE_ID_INTEL_80960_RP,
652 .subdevice = PCI_ANY_ID,
653 .init = pci_inteli960ni_init,
654 .setup = pci_default_setup,
660 .vendor = PCI_VENDOR_ID_PANACOM,
661 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
662 .subvendor = PCI_ANY_ID,
663 .subdevice = PCI_ANY_ID,
664 .init = pci_plx9050_init,
665 .setup = pci_default_setup,
666 .exit = __devexit_p(pci_plx9050_exit),
669 .vendor = PCI_VENDOR_ID_PANACOM,
670 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
671 .subvendor = PCI_ANY_ID,
672 .subdevice = PCI_ANY_ID,
673 .init = pci_plx9050_init,
674 .setup = pci_default_setup,
675 .exit = __devexit_p(pci_plx9050_exit),
681 .vendor = PCI_VENDOR_ID_PLX,
682 .device = PCI_DEVICE_ID_PLX_9030,
683 .subvendor = PCI_SUBVENDOR_ID_PERLE,
684 .subdevice = PCI_ANY_ID,
685 .setup = pci_default_setup,
688 .vendor = PCI_VENDOR_ID_PLX,
689 .device = PCI_DEVICE_ID_PLX_9050,
690 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
691 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
692 .init = pci_plx9050_init,
693 .setup = pci_default_setup,
694 .exit = __devexit_p(pci_plx9050_exit),
697 .vendor = PCI_VENDOR_ID_PLX,
698 .device = PCI_DEVICE_ID_PLX_9050,
699 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
700 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
701 .init = pci_plx9050_init,
702 .setup = pci_default_setup,
703 .exit = __devexit_p(pci_plx9050_exit),
706 .vendor = PCI_VENDOR_ID_PLX,
707 .device = PCI_DEVICE_ID_PLX_ROMULUS,
708 .subvendor = PCI_VENDOR_ID_PLX,
709 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
710 .init = pci_plx9050_init,
711 .setup = pci_default_setup,
712 .exit = __devexit_p(pci_plx9050_exit),
715 * SBS Technologies, Inc., PMC-OCTALPRO 232
718 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
719 .device = PCI_DEVICE_ID_OCTPRO,
720 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
721 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
724 .exit = __devexit_p(sbs_exit),
727 * SBS Technologies, Inc., PMC-OCTALPRO 422
730 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
731 .device = PCI_DEVICE_ID_OCTPRO,
732 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
733 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
736 .exit = __devexit_p(sbs_exit),
739 * SBS Technologies, Inc., P-Octal 232
742 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
743 .device = PCI_DEVICE_ID_OCTPRO,
744 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
745 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
748 .exit = __devexit_p(sbs_exit),
751 * SBS Technologies, Inc., P-Octal 422
754 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
755 .device = PCI_DEVICE_ID_OCTPRO,
756 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
757 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
760 .exit = __devexit_p(sbs_exit),
763 * SIIG cards - these may be called via parport_serial
766 .vendor = PCI_VENDOR_ID_SIIG,
767 .device = PCI_ANY_ID,
768 .subvendor = PCI_ANY_ID,
769 .subdevice = PCI_ANY_ID,
770 .init = pci_siig_init,
771 .setup = pci_siig_setup,
777 .vendor = PCI_VENDOR_ID_TITAN,
778 .device = PCI_DEVICE_ID_TITAN_400L,
779 .subvendor = PCI_ANY_ID,
780 .subdevice = PCI_ANY_ID,
781 .setup = titan_400l_800l_setup,
784 .vendor = PCI_VENDOR_ID_TITAN,
785 .device = PCI_DEVICE_ID_TITAN_800L,
786 .subvendor = PCI_ANY_ID,
787 .subdevice = PCI_ANY_ID,
788 .setup = titan_400l_800l_setup,
794 .vendor = PCI_VENDOR_ID_TIMEDIA,
795 .device = PCI_DEVICE_ID_TIMEDIA_1889,
796 .subvendor = PCI_VENDOR_ID_TIMEDIA,
797 .subdevice = PCI_ANY_ID,
798 .init = pci_timedia_init,
799 .setup = pci_timedia_setup,
802 .vendor = PCI_VENDOR_ID_TIMEDIA,
803 .device = PCI_ANY_ID,
804 .subvendor = PCI_ANY_ID,
805 .subdevice = PCI_ANY_ID,
806 .setup = pci_timedia_setup,
812 .vendor = PCI_VENDOR_ID_XIRCOM,
813 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
814 .subvendor = PCI_ANY_ID,
815 .subdevice = PCI_ANY_ID,
816 .init = pci_xircom_init,
817 .setup = pci_default_setup,
820 * Netmos cards - these may be called via parport_serial
823 .vendor = PCI_VENDOR_ID_NETMOS,
824 .device = PCI_ANY_ID,
825 .subvendor = PCI_ANY_ID,
826 .subdevice = PCI_ANY_ID,
827 .init = pci_netmos_init,
828 .setup = pci_default_setup,
831 * Default "match everything" terminator entry
834 .vendor = PCI_ANY_ID,
835 .device = PCI_ANY_ID,
836 .subvendor = PCI_ANY_ID,
837 .subdevice = PCI_ANY_ID,
838 .setup = pci_default_setup,
842 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
844 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
847 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
849 struct pci_serial_quirk *quirk;
851 for (quirk = pci_serial_quirks; ; quirk++)
852 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
853 quirk_id_matches(quirk->device, dev->device) &&
854 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
855 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
860 static inline int get_pci_irq(struct pci_dev *dev,
861 struct pciserial_board *board)
863 if (board->flags & FL_NOIRQ)
870 * This is the configuration table for all of the PCI serial boards
871 * which we support. It is directly indexed by the pci_board_num_t enum
872 * value, which is encoded in the pci_device_id PCI probe table's
873 * driver_data member.
875 * The makeup of these names are:
876 * pbn_bn{_bt}_n_baud{_offsetinhex}
878 * bn = PCI BAR number
879 * bt = Index using PCI BARs
880 * n = number of serial ports
882 * offsetinhex = offset for each sequential port (in hex)
884 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
886 * Please note: in theory if n = 1, _bt infix should make no difference.
887 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
889 enum pci_board_num_t {
908 pbn_b0_2_1843200_200,
909 pbn_b0_4_1843200_200,
910 pbn_b0_8_1843200_200,
970 * Board-specific versions.
991 * uart_offset - the space between channels
992 * reg_shift - describes how the UART registers are mapped
993 * to PCI memory by the card.
994 * For example IER register on SBS, Inc. PMC-OctPro is located at
995 * offset 0x10 from the UART base, while UART_IER is defined as 1
996 * in include/linux/serial_reg.h,
997 * see first lines of serial_in() and serial_out() in 8250.c
1000 static struct pciserial_board pci_boards[] __devinitdata = {
1004 .base_baud = 115200,
1007 [pbn_b0_1_115200] = {
1010 .base_baud = 115200,
1013 [pbn_b0_2_115200] = {
1016 .base_baud = 115200,
1019 [pbn_b0_4_115200] = {
1022 .base_baud = 115200,
1025 [pbn_b0_5_115200] = {
1028 .base_baud = 115200,
1032 [pbn_b0_1_921600] = {
1035 .base_baud = 921600,
1038 [pbn_b0_2_921600] = {
1041 .base_baud = 921600,
1044 [pbn_b0_4_921600] = {
1047 .base_baud = 921600,
1051 [pbn_b0_2_1130000] = {
1054 .base_baud = 1130000,
1058 [pbn_b0_4_1152000] = {
1061 .base_baud = 1152000,
1065 [pbn_b0_2_1843200] = {
1068 .base_baud = 1843200,
1071 [pbn_b0_4_1843200] = {
1074 .base_baud = 1843200,
1078 [pbn_b0_2_1843200_200] = {
1081 .base_baud = 1843200,
1082 .uart_offset = 0x200,
1084 [pbn_b0_4_1843200_200] = {
1087 .base_baud = 1843200,
1088 .uart_offset = 0x200,
1090 [pbn_b0_8_1843200_200] = {
1093 .base_baud = 1843200,
1094 .uart_offset = 0x200,
1097 [pbn_b0_bt_1_115200] = {
1098 .flags = FL_BASE0|FL_BASE_BARS,
1100 .base_baud = 115200,
1103 [pbn_b0_bt_2_115200] = {
1104 .flags = FL_BASE0|FL_BASE_BARS,
1106 .base_baud = 115200,
1109 [pbn_b0_bt_8_115200] = {
1110 .flags = FL_BASE0|FL_BASE_BARS,
1112 .base_baud = 115200,
1116 [pbn_b0_bt_1_460800] = {
1117 .flags = FL_BASE0|FL_BASE_BARS,
1119 .base_baud = 460800,
1122 [pbn_b0_bt_2_460800] = {
1123 .flags = FL_BASE0|FL_BASE_BARS,
1125 .base_baud = 460800,
1128 [pbn_b0_bt_4_460800] = {
1129 .flags = FL_BASE0|FL_BASE_BARS,
1131 .base_baud = 460800,
1135 [pbn_b0_bt_1_921600] = {
1136 .flags = FL_BASE0|FL_BASE_BARS,
1138 .base_baud = 921600,
1141 [pbn_b0_bt_2_921600] = {
1142 .flags = FL_BASE0|FL_BASE_BARS,
1144 .base_baud = 921600,
1147 [pbn_b0_bt_4_921600] = {
1148 .flags = FL_BASE0|FL_BASE_BARS,
1150 .base_baud = 921600,
1153 [pbn_b0_bt_8_921600] = {
1154 .flags = FL_BASE0|FL_BASE_BARS,
1156 .base_baud = 921600,
1160 [pbn_b1_1_115200] = {
1163 .base_baud = 115200,
1166 [pbn_b1_2_115200] = {
1169 .base_baud = 115200,
1172 [pbn_b1_4_115200] = {
1175 .base_baud = 115200,
1178 [pbn_b1_8_115200] = {
1181 .base_baud = 115200,
1185 [pbn_b1_1_921600] = {
1188 .base_baud = 921600,
1191 [pbn_b1_2_921600] = {
1194 .base_baud = 921600,
1197 [pbn_b1_4_921600] = {
1200 .base_baud = 921600,
1203 [pbn_b1_8_921600] = {
1206 .base_baud = 921600,
1209 [pbn_b1_2_1250000] = {
1212 .base_baud = 1250000,
1216 [pbn_b1_bt_2_921600] = {
1217 .flags = FL_BASE1|FL_BASE_BARS,
1219 .base_baud = 921600,
1223 [pbn_b1_1_1382400] = {
1226 .base_baud = 1382400,
1229 [pbn_b1_2_1382400] = {
1232 .base_baud = 1382400,
1235 [pbn_b1_4_1382400] = {
1238 .base_baud = 1382400,
1241 [pbn_b1_8_1382400] = {
1244 .base_baud = 1382400,
1248 [pbn_b2_1_115200] = {
1251 .base_baud = 115200,
1254 [pbn_b2_2_115200] = {
1257 .base_baud = 115200,
1260 [pbn_b2_4_115200] = {
1263 .base_baud = 115200,
1266 [pbn_b2_8_115200] = {
1269 .base_baud = 115200,
1273 [pbn_b2_1_460800] = {
1276 .base_baud = 460800,
1279 [pbn_b2_4_460800] = {
1282 .base_baud = 460800,
1285 [pbn_b2_8_460800] = {
1288 .base_baud = 460800,
1291 [pbn_b2_16_460800] = {
1294 .base_baud = 460800,
1298 [pbn_b2_1_921600] = {
1301 .base_baud = 921600,
1304 [pbn_b2_4_921600] = {
1307 .base_baud = 921600,
1310 [pbn_b2_8_921600] = {
1313 .base_baud = 921600,
1317 [pbn_b2_bt_1_115200] = {
1318 .flags = FL_BASE2|FL_BASE_BARS,
1320 .base_baud = 115200,
1323 [pbn_b2_bt_2_115200] = {
1324 .flags = FL_BASE2|FL_BASE_BARS,
1326 .base_baud = 115200,
1329 [pbn_b2_bt_4_115200] = {
1330 .flags = FL_BASE2|FL_BASE_BARS,
1332 .base_baud = 115200,
1336 [pbn_b2_bt_2_921600] = {
1337 .flags = FL_BASE2|FL_BASE_BARS,
1339 .base_baud = 921600,
1342 [pbn_b2_bt_4_921600] = {
1343 .flags = FL_BASE2|FL_BASE_BARS,
1345 .base_baud = 921600,
1349 [pbn_b3_2_115200] = {
1352 .base_baud = 115200,
1355 [pbn_b3_4_115200] = {
1358 .base_baud = 115200,
1361 [pbn_b3_8_115200] = {
1364 .base_baud = 115200,
1369 * Entries following this are board-specific.
1378 .base_baud = 921600,
1379 .uart_offset = 0x400,
1383 .flags = FL_BASE2|FL_BASE_BARS,
1385 .base_baud = 921600,
1386 .uart_offset = 0x400,
1390 .flags = FL_BASE2|FL_BASE_BARS,
1392 .base_baud = 921600,
1393 .uart_offset = 0x400,
1397 [pbn_exsys_4055] = {
1400 .base_baud = 115200,
1404 /* I think this entry is broken - the first_offset looks wrong --rmk */
1405 [pbn_plx_romulus] = {
1408 .base_baud = 921600,
1409 .uart_offset = 8 << 2,
1411 .first_offset = 0x03,
1415 * This board uses the size of PCI Base region 0 to
1416 * signal now many ports are available
1419 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1421 .base_baud = 115200,
1426 * EKF addition for i960 Boards form EKF with serial port.
1429 [pbn_intel_i960] = {
1432 .base_baud = 921600,
1433 .uart_offset = 8 << 2,
1435 .first_offset = 0x10000,
1438 .flags = FL_BASE0|FL_NOIRQ,
1440 .base_baud = 458333,
1443 .first_offset = 0x20178,
1447 * NEC Vrc-5074 (Nile 4) builtin UART.
1452 .base_baud = 520833,
1453 .uart_offset = 8 << 3,
1455 .first_offset = 0x300,
1459 * Computone - uses IOMEM.
1461 [pbn_computone_4] = {
1464 .base_baud = 921600,
1465 .uart_offset = 0x40,
1467 .first_offset = 0x200,
1469 [pbn_computone_6] = {
1472 .base_baud = 921600,
1473 .uart_offset = 0x40,
1475 .first_offset = 0x200,
1477 [pbn_computone_8] = {
1480 .base_baud = 921600,
1481 .uart_offset = 0x40,
1483 .first_offset = 0x200,
1488 .base_baud = 460800,
1493 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1494 * Only basic 16550A support.
1495 * XR17C15[24] are not tested, but they should work.
1497 [pbn_exar_XR17C152] = {
1500 .base_baud = 921600,
1501 .uart_offset = 0x200,
1503 [pbn_exar_XR17C154] = {
1506 .base_baud = 921600,
1507 .uart_offset = 0x200,
1509 [pbn_exar_XR17C158] = {
1512 .base_baud = 921600,
1513 .uart_offset = 0x200,
1518 * Given a complete unknown PCI device, try to use some heuristics to
1519 * guess what the configuration might be, based on the pitiful PCI
1520 * serial specs. Returns 0 on success, 1 on failure.
1522 static int __devinit
1523 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1525 int num_iomem, num_port, first_port = -1, i;
1528 * If it is not a communications device or the programming
1529 * interface is greater than 6, give up.
1531 * (Should we try to make guesses for multiport serial devices
1534 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1535 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1536 (dev->class & 0xff) > 6)
1539 num_iomem = num_port = 0;
1540 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1541 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1543 if (first_port == -1)
1546 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1551 * If there is 1 or 0 iomem regions, and exactly one port,
1552 * use it. We guess the number of ports based on the IO
1555 if (num_iomem <= 1 && num_port == 1) {
1556 board->flags = first_port;
1557 board->num_ports = pci_resource_len(dev, first_port) / 8;
1562 * Now guess if we've got a board which indexes by BARs.
1563 * Each IO BAR should be 8 bytes, and they should follow
1568 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1569 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1570 pci_resource_len(dev, i) == 8 &&
1571 (first_port == -1 || (first_port + num_port) == i)) {
1573 if (first_port == -1)
1579 board->flags = first_port | FL_BASE_BARS;
1580 board->num_ports = num_port;
1588 serial_pci_matches(struct pciserial_board *board,
1589 struct pciserial_board *guessed)
1592 board->num_ports == guessed->num_ports &&
1593 board->base_baud == guessed->base_baud &&
1594 board->uart_offset == guessed->uart_offset &&
1595 board->reg_shift == guessed->reg_shift &&
1596 board->first_offset == guessed->first_offset;
1599 struct serial_private *
1600 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1602 struct uart_port serial_port;
1603 struct serial_private *priv;
1604 struct pci_serial_quirk *quirk;
1605 int rc, nr_ports, i;
1607 nr_ports = board->num_ports;
1610 * Find an init and setup quirks.
1612 quirk = find_quirk(dev);
1615 * Run the new-style initialization function.
1616 * The initialization function returns:
1618 * 0 - use board->num_ports
1619 * >0 - number of ports
1622 rc = quirk->init(dev);
1631 priv = kzalloc(sizeof(struct serial_private) +
1632 sizeof(unsigned int) * nr_ports,
1635 priv = ERR_PTR(-ENOMEM);
1640 priv->quirk = quirk;
1642 memset(&serial_port, 0, sizeof(struct uart_port));
1643 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1644 serial_port.uartclk = board->base_baud * 16;
1645 serial_port.irq = get_pci_irq(dev, board);
1646 serial_port.dev = &dev->dev;
1648 for (i = 0; i < nr_ports; i++) {
1649 if (quirk->setup(priv, board, &serial_port, i))
1652 #ifdef SERIAL_DEBUG_PCI
1653 printk("Setup PCI port: port %x, irq %d, type %d\n",
1654 serial_port.iobase, serial_port.irq, serial_port.iotype);
1657 priv->line[i] = serial8250_register_port(&serial_port);
1658 if (priv->line[i] < 0) {
1659 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1674 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1676 void pciserial_remove_ports(struct serial_private *priv)
1678 struct pci_serial_quirk *quirk;
1681 for (i = 0; i < priv->nr; i++)
1682 serial8250_unregister_port(priv->line[i]);
1684 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1685 if (priv->remapped_bar[i])
1686 iounmap(priv->remapped_bar[i]);
1687 priv->remapped_bar[i] = NULL;
1691 * Find the exit quirks.
1693 quirk = find_quirk(priv->dev);
1695 quirk->exit(priv->dev);
1699 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1701 void pciserial_suspend_ports(struct serial_private *priv)
1705 for (i = 0; i < priv->nr; i++)
1706 if (priv->line[i] >= 0)
1707 serial8250_suspend_port(priv->line[i]);
1709 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1711 void pciserial_resume_ports(struct serial_private *priv)
1716 * Ensure that the board is correctly configured.
1718 if (priv->quirk->init)
1719 priv->quirk->init(priv->dev);
1721 for (i = 0; i < priv->nr; i++)
1722 if (priv->line[i] >= 0)
1723 serial8250_resume_port(priv->line[i]);
1725 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1728 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1729 * to the arrangement of serial ports on a PCI card.
1731 static int __devinit
1732 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1734 struct serial_private *priv;
1735 struct pciserial_board *board, tmp;
1738 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1739 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1744 board = &pci_boards[ent->driver_data];
1746 rc = pci_enable_device(dev);
1750 if (ent->driver_data == pbn_default) {
1752 * Use a copy of the pci_board entry for this;
1753 * avoid changing entries in the table.
1755 memcpy(&tmp, board, sizeof(struct pciserial_board));
1759 * We matched one of our class entries. Try to
1760 * determine the parameters of this board.
1762 rc = serial_pci_guess_board(dev, board);
1767 * We matched an explicit entry. If we are able to
1768 * detect this boards settings with our heuristic,
1769 * then we no longer need this entry.
1771 memcpy(&tmp, &pci_boards[pbn_default],
1772 sizeof(struct pciserial_board));
1773 rc = serial_pci_guess_board(dev, &tmp);
1774 if (rc == 0 && serial_pci_matches(board, &tmp))
1775 moan_device("Redundant entry in serial pci_table.",
1779 priv = pciserial_init_ports(dev, board);
1780 if (!IS_ERR(priv)) {
1781 pci_set_drvdata(dev, priv);
1788 pci_disable_device(dev);
1792 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1794 struct serial_private *priv = pci_get_drvdata(dev);
1796 pci_set_drvdata(dev, NULL);
1798 pciserial_remove_ports(priv);
1800 pci_disable_device(dev);
1804 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1806 struct serial_private *priv = pci_get_drvdata(dev);
1809 pciserial_suspend_ports(priv);
1811 pci_save_state(dev);
1812 pci_set_power_state(dev, pci_choose_state(dev, state));
1816 static int pciserial_resume_one(struct pci_dev *dev)
1818 struct serial_private *priv = pci_get_drvdata(dev);
1820 pci_set_power_state(dev, PCI_D0);
1821 pci_restore_state(dev);
1825 * The device may have been disabled. Re-enable it.
1827 pci_enable_device(dev);
1829 pciserial_resume_ports(priv);
1835 static struct pci_device_id serial_pci_tbl[] = {
1836 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1837 PCI_SUBVENDOR_ID_CONNECT_TECH,
1838 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1840 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1841 PCI_SUBVENDOR_ID_CONNECT_TECH,
1842 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1844 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1845 PCI_SUBVENDOR_ID_CONNECT_TECH,
1846 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1848 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1849 PCI_SUBVENDOR_ID_CONNECT_TECH,
1850 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1852 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1853 PCI_SUBVENDOR_ID_CONNECT_TECH,
1854 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1856 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1857 PCI_SUBVENDOR_ID_CONNECT_TECH,
1858 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1860 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1861 PCI_SUBVENDOR_ID_CONNECT_TECH,
1862 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1864 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1865 PCI_SUBVENDOR_ID_CONNECT_TECH,
1866 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1868 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1869 PCI_SUBVENDOR_ID_CONNECT_TECH,
1870 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1872 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1873 PCI_SUBVENDOR_ID_CONNECT_TECH,
1874 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1876 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1877 PCI_SUBVENDOR_ID_CONNECT_TECH,
1878 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1880 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1881 PCI_SUBVENDOR_ID_CONNECT_TECH,
1882 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1884 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1885 PCI_SUBVENDOR_ID_CONNECT_TECH,
1886 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1888 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1889 PCI_SUBVENDOR_ID_CONNECT_TECH,
1890 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1892 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1893 PCI_SUBVENDOR_ID_CONNECT_TECH,
1894 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
1896 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1897 PCI_SUBVENDOR_ID_CONNECT_TECH,
1898 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
1900 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1901 PCI_SUBVENDOR_ID_CONNECT_TECH,
1902 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
1904 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1905 PCI_VENDOR_ID_AFAVLAB,
1906 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
1908 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1909 PCI_SUBVENDOR_ID_CONNECT_TECH,
1910 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
1911 pbn_b0_2_1843200_200 },
1912 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1913 PCI_SUBVENDOR_ID_CONNECT_TECH,
1914 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
1915 pbn_b0_4_1843200_200 },
1916 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1917 PCI_SUBVENDOR_ID_CONNECT_TECH,
1918 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
1919 pbn_b0_8_1843200_200 },
1920 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1921 PCI_SUBVENDOR_ID_CONNECT_TECH,
1922 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
1923 pbn_b0_2_1843200_200 },
1924 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1925 PCI_SUBVENDOR_ID_CONNECT_TECH,
1926 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
1927 pbn_b0_4_1843200_200 },
1928 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1929 PCI_SUBVENDOR_ID_CONNECT_TECH,
1930 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
1931 pbn_b0_8_1843200_200 },
1932 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1933 PCI_SUBVENDOR_ID_CONNECT_TECH,
1934 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
1935 pbn_b0_2_1843200_200 },
1936 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1937 PCI_SUBVENDOR_ID_CONNECT_TECH,
1938 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
1939 pbn_b0_4_1843200_200 },
1940 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1941 PCI_SUBVENDOR_ID_CONNECT_TECH,
1942 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
1943 pbn_b0_8_1843200_200 },
1944 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
1945 PCI_SUBVENDOR_ID_CONNECT_TECH,
1946 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
1947 pbn_b0_2_1843200_200 },
1948 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
1949 PCI_SUBVENDOR_ID_CONNECT_TECH,
1950 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
1951 pbn_b0_4_1843200_200 },
1952 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
1953 PCI_SUBVENDOR_ID_CONNECT_TECH,
1954 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
1955 pbn_b0_8_1843200_200 },
1957 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1959 pbn_b2_bt_1_115200 },
1960 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1962 pbn_b2_bt_2_115200 },
1963 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1965 pbn_b2_bt_4_115200 },
1966 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1968 pbn_b2_bt_2_115200 },
1969 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1971 pbn_b2_bt_4_115200 },
1972 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1975 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1979 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1981 pbn_b2_bt_2_115200 },
1982 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1984 pbn_b2_bt_2_921600 },
1986 * VScom SPCOM800, from sl@s.pl
1988 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1991 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1994 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1995 PCI_SUBVENDOR_ID_KEYSPAN,
1996 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1998 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2001 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2004 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2005 PCI_VENDOR_ID_ESDGMBH,
2006 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2008 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2009 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2010 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
2012 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2013 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2014 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
2016 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2017 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2018 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
2020 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2021 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
2022 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
2024 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2025 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2026 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
2028 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2029 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
2030 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
2032 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2033 PCI_SUBVENDOR_ID_EXSYS,
2034 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2037 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2040 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2041 0x10b5, 0x106a, 0, 0,
2043 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2046 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2047 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2049 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2052 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2055 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
2056 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
2058 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2059 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
2063 * The below card is a little controversial since it is the
2064 * subject of a PCI vendor/device ID clash. (See
2065 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2066 * For now just used the hex ID 0x950a.
2068 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2071 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2074 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2076 pbn_b0_bt_2_921600 },
2079 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2080 * from skokodyn@yahoo.com
2082 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2083 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
2085 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2086 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
2088 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2089 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
2091 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
2092 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
2096 * Digitan DS560-558, from jimd@esoft.com
2098 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
2099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2103 * Titan Electronic cards
2104 * The 400L and 800L have a custom setup quirk.
2106 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
2107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2109 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
2110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2112 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
2113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2115 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
2116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2118 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
2119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2121 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
2122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2123 pbn_b1_bt_2_921600 },
2124 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
2125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2126 pbn_b0_bt_4_921600 },
2127 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
2128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2129 pbn_b0_bt_8_921600 },
2131 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
2132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2134 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
2135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2137 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
2138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2140 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
2141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2142 pbn_b2_bt_2_921600 },
2143 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
2144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2145 pbn_b2_bt_2_921600 },
2146 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
2147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2148 pbn_b2_bt_2_921600 },
2149 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
2150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2151 pbn_b2_bt_4_921600 },
2152 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
2153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2154 pbn_b2_bt_4_921600 },
2155 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
2156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2157 pbn_b2_bt_4_921600 },
2158 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
2159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2161 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
2162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2164 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
2165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2167 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
2168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2169 pbn_b0_bt_2_921600 },
2170 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
2171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2172 pbn_b0_bt_2_921600 },
2173 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
2174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2175 pbn_b0_bt_2_921600 },
2176 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
2177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2178 pbn_b0_bt_4_921600 },
2179 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2181 pbn_b0_bt_4_921600 },
2182 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2184 pbn_b0_bt_4_921600 },
2185 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
2186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2187 pbn_b0_bt_8_921600 },
2188 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
2189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2190 pbn_b0_bt_8_921600 },
2191 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
2192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2193 pbn_b0_bt_8_921600 },
2196 * Computone devices submitted by Doug McNash dmcnash@computone.com
2198 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2199 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2200 0, 0, pbn_computone_4 },
2201 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2202 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2203 0, 0, pbn_computone_8 },
2204 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2205 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2206 0, 0, pbn_computone_6 },
2208 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2211 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2212 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2213 pbn_b0_bt_1_921600 },
2216 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2218 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2220 pbn_b0_bt_8_115200 },
2221 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2223 pbn_b0_bt_8_115200 },
2225 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2227 pbn_b0_bt_2_115200 },
2228 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2229 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2230 pbn_b0_bt_2_115200 },
2231 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2232 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2233 pbn_b0_bt_2_115200 },
2234 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2236 pbn_b0_bt_4_460800 },
2237 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2239 pbn_b0_bt_4_460800 },
2240 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2241 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2242 pbn_b0_bt_2_460800 },
2243 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2245 pbn_b0_bt_2_460800 },
2246 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2248 pbn_b0_bt_2_460800 },
2249 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2251 pbn_b0_bt_1_115200 },
2252 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2254 pbn_b0_bt_1_460800 },
2257 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2258 * Cards are identified by their subsystem vendor IDs, which
2259 * (in hex) match the model number.
2261 * Note that JC140x are RS422/485 cards which require ox950
2262 * ACR = 0x10, and as such are not currently fully supported.
2264 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2265 0x1204, 0x0004, 0, 0,
2267 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2268 0x1208, 0x0004, 0, 0,
2270 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2271 0x1402, 0x0002, 0, 0,
2272 pbn_b0_2_921600 }, */
2273 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2274 0x1404, 0x0004, 0, 0,
2275 pbn_b0_4_921600 }, */
2276 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
2277 0x1208, 0x0004, 0, 0,
2281 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2283 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2288 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2290 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2295 * RAStel 2 port modem, gerg@moreton.com.au
2297 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2299 pbn_b2_bt_2_115200 },
2302 * EKF addition for i960 Boards form EKF with serial port
2304 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2305 0xE4BF, PCI_ANY_ID, 0, 0,
2309 * Xircom Cardbus/Ethernet combos
2311 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2315 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2317 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2322 * Untested PCI modems, sent in from various folks...
2326 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2328 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2329 0x1048, 0x1500, 0, 0,
2332 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2339 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2340 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2342 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2345 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2350 * NEC Vrc-5074 (Nile 4) builtin UART.
2352 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2356 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
2357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2359 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2362 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2367 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2369 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2370 PCI_ANY_ID, PCI_ANY_ID,
2372 0, pbn_exar_XR17C152 },
2373 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2374 PCI_ANY_ID, PCI_ANY_ID,
2376 0, pbn_exar_XR17C154 },
2377 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2378 PCI_ANY_ID, PCI_ANY_ID,
2380 0, pbn_exar_XR17C158 },
2383 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2385 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2392 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
2393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
2397 * Perle PCI-RAS cards
2399 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2400 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
2401 0, 0, pbn_b2_4_921600 },
2402 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2403 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
2404 0, 0, pbn_b2_8_921600 },
2406 * These entries match devices with class COMMUNICATION_SERIAL,
2407 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2409 { PCI_ANY_ID, PCI_ANY_ID,
2410 PCI_ANY_ID, PCI_ANY_ID,
2411 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2412 0xffff00, pbn_default },
2413 { PCI_ANY_ID, PCI_ANY_ID,
2414 PCI_ANY_ID, PCI_ANY_ID,
2415 PCI_CLASS_COMMUNICATION_MODEM << 8,
2416 0xffff00, pbn_default },
2417 { PCI_ANY_ID, PCI_ANY_ID,
2418 PCI_ANY_ID, PCI_ANY_ID,
2419 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2420 0xffff00, pbn_default },
2424 static struct pci_driver serial_pci_driver = {
2426 .probe = pciserial_init_one,
2427 .remove = __devexit_p(pciserial_remove_one),
2429 .suspend = pciserial_suspend_one,
2430 .resume = pciserial_resume_one,
2432 .id_table = serial_pci_tbl,
2435 static int __init serial8250_pci_init(void)
2437 return pci_register_driver(&serial_pci_driver);
2440 static void __exit serial8250_pci_exit(void)
2442 pci_unregister_driver(&serial_pci_driver);
2445 module_init(serial8250_pci_init);
2446 module_exit(serial8250_pci_exit);
2448 MODULE_LICENSE("GPL");
2449 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2450 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);