drivers/scsi/qla4xxx/ql4_nx.c

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2010 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7 #include <linux/delay.h>
   8 #include <linux/io.h>
   9 #include <linux/pci.h>
  10 #include <linux/ratelimit.h>
  11 #include "ql4_def.h"
  12 #include "ql4_glbl.h"
  13
  14 #include <asm-generic/io-64-nonatomic-lo-hi.h>
  15
  16 #define MASK(n)         DMA_BIT_MASK(n)
  17 #define MN_WIN(addr)    (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
  18 #define OCM_WIN(addr)   (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
  19 #define MS_WIN(addr)    (addr & 0x0ffc0000)
  20 #define QLA82XX_PCI_MN_2M       (0)
  21 #define QLA82XX_PCI_MS_2M       (0x80000)
  22 #define QLA82XX_PCI_OCM0_2M     (0xc0000)
  23 #define VALID_OCM_ADDR(addr)    (((addr) & 0x3f800) != 0x3f800)
  24 #define GET_MEM_OFFS_2M(addr)   (addr & MASK(18))
  25
  26 /* CRB window related */
  27 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  28 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  29 #define CRB_WINDOW_2M   (0x130060)
  30 #define CRB_HI(off)     ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \
  31                         ((off) & 0xf0000))
  32 #define QLA82XX_PCI_CAMQM_2M_END        (0x04800800UL)
  33 #define QLA82XX_PCI_CAMQM_2M_BASE       (0x000ff800UL)
  34 #define CRB_INDIRECT_2M                 (0x1e0000UL)
  35
  36 static inline void __iomem *
  37 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off)
  38 {
  39         if ((off < ha->first_page_group_end) &&
  40             (off >= ha->first_page_group_start))
  41                 return (void __iomem *)(ha->nx_pcibase + off);
  42
  43         return NULL;
  44 }
  45
  46 #define MAX_CRB_XFORM 60
  47 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
  48 static int qla4_8xxx_crb_table_initialized;
  49
  50 #define qla4_8xxx_crb_addr_transform(name) \
  51         (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
  52          QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
  53 static void
  54 qla4_8xxx_crb_addr_transform_setup(void)
  55 {
  56         qla4_8xxx_crb_addr_transform(XDMA);
  57         qla4_8xxx_crb_addr_transform(TIMR);
  58         qla4_8xxx_crb_addr_transform(SRE);
  59         qla4_8xxx_crb_addr_transform(SQN3);
  60         qla4_8xxx_crb_addr_transform(SQN2);
  61         qla4_8xxx_crb_addr_transform(SQN1);
  62         qla4_8xxx_crb_addr_transform(SQN0);
  63         qla4_8xxx_crb_addr_transform(SQS3);
  64         qla4_8xxx_crb_addr_transform(SQS2);
  65         qla4_8xxx_crb_addr_transform(SQS1);
  66         qla4_8xxx_crb_addr_transform(SQS0);
  67         qla4_8xxx_crb_addr_transform(RPMX7);
  68         qla4_8xxx_crb_addr_transform(RPMX6);
  69         qla4_8xxx_crb_addr_transform(RPMX5);
  70         qla4_8xxx_crb_addr_transform(RPMX4);
  71         qla4_8xxx_crb_addr_transform(RPMX3);
  72         qla4_8xxx_crb_addr_transform(RPMX2);
  73         qla4_8xxx_crb_addr_transform(RPMX1);
  74         qla4_8xxx_crb_addr_transform(RPMX0);
  75         qla4_8xxx_crb_addr_transform(ROMUSB);
  76         qla4_8xxx_crb_addr_transform(SN);
  77         qla4_8xxx_crb_addr_transform(QMN);
  78         qla4_8xxx_crb_addr_transform(QMS);
  79         qla4_8xxx_crb_addr_transform(PGNI);
  80         qla4_8xxx_crb_addr_transform(PGND);
  81         qla4_8xxx_crb_addr_transform(PGN3);
  82         qla4_8xxx_crb_addr_transform(PGN2);
  83         qla4_8xxx_crb_addr_transform(PGN1);
  84         qla4_8xxx_crb_addr_transform(PGN0);
  85         qla4_8xxx_crb_addr_transform(PGSI);
  86         qla4_8xxx_crb_addr_transform(PGSD);
  87         qla4_8xxx_crb_addr_transform(PGS3);
  88         qla4_8xxx_crb_addr_transform(PGS2);
  89         qla4_8xxx_crb_addr_transform(PGS1);
  90         qla4_8xxx_crb_addr_transform(PGS0);
  91         qla4_8xxx_crb_addr_transform(PS);
  92         qla4_8xxx_crb_addr_transform(PH);
  93         qla4_8xxx_crb_addr_transform(NIU);
  94         qla4_8xxx_crb_addr_transform(I2Q);
  95         qla4_8xxx_crb_addr_transform(EG);
  96         qla4_8xxx_crb_addr_transform(MN);
  97         qla4_8xxx_crb_addr_transform(MS);
  98         qla4_8xxx_crb_addr_transform(CAS2);
  99         qla4_8xxx_crb_addr_transform(CAS1);
 100         qla4_8xxx_crb_addr_transform(CAS0);
 101         qla4_8xxx_crb_addr_transform(CAM);
 102         qla4_8xxx_crb_addr_transform(C2C1);
 103         qla4_8xxx_crb_addr_transform(C2C0);
 104         qla4_8xxx_crb_addr_transform(SMB);
 105         qla4_8xxx_crb_addr_transform(OCM0);
 106         qla4_8xxx_crb_addr_transform(I2C0);
 107
 108         qla4_8xxx_crb_table_initialized = 1;
 109 }
 110
 111 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
 112         {{{0, 0,         0,         0} } },             /* 0: PCI */
 113         {{{1, 0x0100000, 0x0102000, 0x120000},  /* 1: PCIE */
 114                 {1, 0x0110000, 0x0120000, 0x130000},
 115                 {1, 0x0120000, 0x0122000, 0x124000},
 116                 {1, 0x0130000, 0x0132000, 0x126000},
 117                 {1, 0x0140000, 0x0142000, 0x128000},
 118                 {1, 0x0150000, 0x0152000, 0x12a000},
 119                 {1, 0x0160000, 0x0170000, 0x110000},
 120                 {1, 0x0170000, 0x0172000, 0x12e000},
 121                 {0, 0x0000000, 0x0000000, 0x000000},
 122                 {0, 0x0000000, 0x0000000, 0x000000},
 123                 {0, 0x0000000, 0x0000000, 0x000000},
 124                 {0, 0x0000000, 0x0000000, 0x000000},
 125                 {0, 0x0000000, 0x0000000, 0x000000},
 126                 {0, 0x0000000, 0x0000000, 0x000000},
 127                 {1, 0x01e0000, 0x01e0800, 0x122000},
 128                 {0, 0x0000000, 0x0000000, 0x000000} } },
 129         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
 130         {{{0, 0,         0,         0} } },         /* 3: */
 131         {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
 132         {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
 133         {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
 134         {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
 135         {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
 136                 {0, 0x0000000, 0x0000000, 0x000000},
 137                 {0, 0x0000000, 0x0000000, 0x000000},
 138                 {0, 0x0000000, 0x0000000, 0x000000},
 139                 {0, 0x0000000, 0x0000000, 0x000000},
 140                 {0, 0x0000000, 0x0000000, 0x000000},
 141                 {0, 0x0000000, 0x0000000, 0x000000},
 142                 {0, 0x0000000, 0x0000000, 0x000000},
 143                 {0, 0x0000000, 0x0000000, 0x000000},
 144                 {0, 0x0000000, 0x0000000, 0x000000},
 145                 {0, 0x0000000, 0x0000000, 0x000000},
 146                 {0, 0x0000000, 0x0000000, 0x000000},
 147                 {0, 0x0000000, 0x0000000, 0x000000},
 148                 {0, 0x0000000, 0x0000000, 0x000000},
 149                 {0, 0x0000000, 0x0000000, 0x000000},
 150                 {1, 0x08f0000, 0x08f2000, 0x172000} } },
 151         {{{1, 0x0900000, 0x0902000, 0x174000},  /* 9: SQM1*/
 152                 {0, 0x0000000, 0x0000000, 0x000000},
 153                 {0, 0x0000000, 0x0000000, 0x000000},
 154                 {0, 0x0000000, 0x0000000, 0x000000},
 155                 {0, 0x0000000, 0x0000000, 0x000000},
 156                 {0, 0x0000000, 0x0000000, 0x000000},
 157                 {0, 0x0000000, 0x0000000, 0x000000},
 158                 {0, 0x0000000, 0x0000000, 0x000000},
 159                 {0, 0x0000000, 0x0000000, 0x000000},
 160                 {0, 0x0000000, 0x0000000, 0x000000},
 161                 {0, 0x0000000, 0x0000000, 0x000000},
 162                 {0, 0x0000000, 0x0000000, 0x000000},
 163                 {0, 0x0000000, 0x0000000, 0x000000},
 164                 {0, 0x0000000, 0x0000000, 0x000000},
 165                 {0, 0x0000000, 0x0000000, 0x000000},
 166                 {1, 0x09f0000, 0x09f2000, 0x176000} } },
 167         {{{0, 0x0a00000, 0x0a02000, 0x178000},  /* 10: SQM2*/
 168                 {0, 0x0000000, 0x0000000, 0x000000},
 169                 {0, 0x0000000, 0x0000000, 0x000000},
 170                 {0, 0x0000000, 0x0000000, 0x000000},
 171                 {0, 0x0000000, 0x0000000, 0x000000},
 172                 {0, 0x0000000, 0x0000000, 0x000000},
 173                 {0, 0x0000000, 0x0000000, 0x000000},
 174                 {0, 0x0000000, 0x0000000, 0x000000},
 175                 {0, 0x0000000, 0x0000000, 0x000000},
 176                 {0, 0x0000000, 0x0000000, 0x000000},
 177                 {0, 0x0000000, 0x0000000, 0x000000},
 178                 {0, 0x0000000, 0x0000000, 0x000000},
 179                 {0, 0x0000000, 0x0000000, 0x000000},
 180                 {0, 0x0000000, 0x0000000, 0x000000},
 181                 {0, 0x0000000, 0x0000000, 0x000000},
 182                 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 183         {{{0, 0x0b00000, 0x0b02000, 0x17c000},  /* 11: SQM3*/
 184                 {0, 0x0000000, 0x0000000, 0x000000},
 185                 {0, 0x0000000, 0x0000000, 0x000000},
 186                 {0, 0x0000000, 0x0000000, 0x000000},
 187                 {0, 0x0000000, 0x0000000, 0x000000},
 188                 {0, 0x0000000, 0x0000000, 0x000000},
 189                 {0, 0x0000000, 0x0000000, 0x000000},
 190                 {0, 0x0000000, 0x0000000, 0x000000},
 191                 {0, 0x0000000, 0x0000000, 0x000000},
 192                 {0, 0x0000000, 0x0000000, 0x000000},
 193                 {0, 0x0000000, 0x0000000, 0x000000},
 194                 {0, 0x0000000, 0x0000000, 0x000000},
 195                 {0, 0x0000000, 0x0000000, 0x000000},
 196                 {0, 0x0000000, 0x0000000, 0x000000},
 197                 {0, 0x0000000, 0x0000000, 0x000000},
 198                 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 199         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 200         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 201         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 202         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 203         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 204         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 205         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 206         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 207         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 208         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 209         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 210         {{{0, 0,         0,         0} } },     /* 23: */
 211         {{{0, 0,         0,         0} } },     /* 24: */
 212         {{{0, 0,         0,         0} } },     /* 25: */
 213         {{{0, 0,         0,         0} } },     /* 26: */
 214         {{{0, 0,         0,         0} } },     /* 27: */
 215         {{{0, 0,         0,         0} } },     /* 28: */
 216         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 217         {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 218         {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 219         {{{0} } },                              /* 32: PCI */
 220         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 221                 {1, 0x2110000, 0x2120000, 0x130000},
 222                 {1, 0x2120000, 0x2122000, 0x124000},
 223                 {1, 0x2130000, 0x2132000, 0x126000},
 224                 {1, 0x2140000, 0x2142000, 0x128000},
 225                 {1, 0x2150000, 0x2152000, 0x12a000},
 226                 {1, 0x2160000, 0x2170000, 0x110000},
 227                 {1, 0x2170000, 0x2172000, 0x12e000},
 228                 {0, 0x0000000, 0x0000000, 0x000000},
 229                 {0, 0x0000000, 0x0000000, 0x000000},
 230                 {0, 0x0000000, 0x0000000, 0x000000},
 231                 {0, 0x0000000, 0x0000000, 0x000000},
 232                 {0, 0x0000000, 0x0000000, 0x000000},
 233                 {0, 0x0000000, 0x0000000, 0x000000},
 234                 {0, 0x0000000, 0x0000000, 0x000000},
 235                 {0, 0x0000000, 0x0000000, 0x000000} } },
 236         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 237         {{{0} } },                              /* 35: */
 238         {{{0} } },                              /* 36: */
 239         {{{0} } },                              /* 37: */
 240         {{{0} } },                              /* 38: */
 241         {{{0} } },                              /* 39: */
 242         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 243         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 244         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 245         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 246         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 247         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 248         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 249         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 250         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 251         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 252         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 253         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 254         {{{0} } },                              /* 52: */
 255         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 256         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 257         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 258         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 259         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 260         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 261         {{{0} } },                              /* 59: I2C0 */
 262         {{{0} } },                              /* 60: I2C1 */
 263         {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */
 264         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 265         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 266 };
 267
 268 /*
 269  * top 12 bits of crb internal address (hub, agent)
 270  */
 271 static unsigned qla4_8xxx_crb_hub_agt[64] = {
 272         0,
 273         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 274         QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
 275         QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
 276         0,
 277         QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
 278         QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
 279         QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
 280         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
 281         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
 282         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
 283         QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
 284         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 285         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 286         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 287         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
 288         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 289         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
 290         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
 291         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
 292         QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
 293         QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
 294         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
 295         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
 296         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
 297         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
 298         QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
 299         0,
 300         QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
 301         QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
 302         0,
 303         QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
 304         0,
 305         QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
 306         QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
 307         0,
 308         0,
 309         0,
 310         0,
 311         0,
 312         QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
 313         0,
 314         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
 315         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
 316         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
 317         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
 318         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
 319         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
 320         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
 321         QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
 322         QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
 323         QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
 324         0,
 325         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
 326         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
 327         QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
 328         QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
 329         0,
 330         QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
 331         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
 332         QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
 333         0,
 334         QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
 335         0,
 336 };
 337
 338 /* Device states */
 339 static char *qdev_state[] = {
 340         "Unknown",
 341         "Cold",
 342         "Initializing",
 343         "Ready",
 344         "Need Reset",
 345         "Need Quiescent",
 346         "Failed",
 347         "Quiescent",
 348 };
 349
 350 /*
 351  * In: 'off' is offset from CRB space in 128M pci map
 352  * Out: 'off' is 2M pci map addr
 353  * side effect: lock crb window
 354  */
 355 static void
 356 qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
 357 {
 358         u32 win_read;
 359
 360         ha->crb_win = CRB_HI(*off);
 361         writel(ha->crb_win,
 362                 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 363
 364         /* Read back value to make sure write has gone through before trying
 365         * to use it. */
 366         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 367         if (win_read != ha->crb_win) {
 368                 DEBUG2(ql4_printk(KERN_INFO, ha,
 369                     "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
 370                     " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
 371         }
 372         *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
 373 }
 374
 375 void
 376 qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
 377 {
 378         unsigned long flags = 0;
 379         int rv;
 380
 381         rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
 382
 383         BUG_ON(rv == -1);
 384
 385         if (rv == 1) {
 386                 write_lock_irqsave(&ha->hw_lock, flags);
 387                 qla4_8xxx_crb_win_lock(ha);
 388                 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
 389         }
 390
 391         writel(data, (void __iomem *)off);
 392
 393         if (rv == 1) {
 394                 qla4_8xxx_crb_win_unlock(ha);
 395                 write_unlock_irqrestore(&ha->hw_lock, flags);
 396         }
 397 }
 398
 399 int
 400 qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off)
 401 {
 402         unsigned long flags = 0;
 403         int rv;
 404         u32 data;
 405
 406         rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
 407
 408         BUG_ON(rv == -1);
 409
 410         if (rv == 1) {
 411                 write_lock_irqsave(&ha->hw_lock, flags);
 412                 qla4_8xxx_crb_win_lock(ha);
 413                 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
 414         }
 415         data = readl((void __iomem *)off);
 416
 417         if (rv == 1) {
 418                 qla4_8xxx_crb_win_unlock(ha);
 419                 write_unlock_irqrestore(&ha->hw_lock, flags);
 420         }
 421         return data;
 422 }
 423
 424 /* Minidump related functions */
 425 static int qla4_8xxx_md_rw_32(struct scsi_qla_host *ha, uint32_t off,
 426                               u32 data, uint8_t flag)
 427 {
 428         uint32_t win_read, off_value, rval = QLA_SUCCESS;
 429
 430         off_value  = off & 0xFFFF0000;
 431         writel(off_value, (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 432
 433         /* Read back value to make sure write has gone through before trying
 434          * to use it.
 435          */
 436         win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
 437         if (win_read != off_value) {
 438                 DEBUG2(ql4_printk(KERN_INFO, ha,
 439                                   "%s: Written (0x%x) != Read (0x%x), off=0x%x\n",
 440                                    __func__, off_value, win_read, off));
 441                 return QLA_ERROR;
 442         }
 443
 444         off_value  = off & 0x0000FFFF;
 445
 446         if (flag)
 447                 writel(data, (void __iomem *)(off_value + CRB_INDIRECT_2M +
 448                                               ha->nx_pcibase));
 449         else
 450                 rval = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
 451                                               ha->nx_pcibase));
 452
 453         return rval;
 454 }
 455
 456 #define CRB_WIN_LOCK_TIMEOUT 100000000
 457
 458 int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha)
 459 {
 460         int i;
 461         int done = 0, timeout = 0;
 462
 463         while (!done) {
 464                 /* acquire semaphore3 from PCI HW block */
 465                 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
 466                 if (done == 1)
 467                         break;
 468                 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
 469                         return -1;
 470
 471                 timeout++;
 472
 473                 /* Yield CPU */
 474                 if (!in_interrupt())
 475                         schedule();
 476                 else {
 477                         for (i = 0; i < 20; i++)
 478                                 cpu_relax();    /*This a nop instr on i386*/
 479                 }
 480         }
 481         qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
 482         return 0;
 483 }
 484
 485 void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha)
 486 {
 487         qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
 488 }
 489
 490 #define IDC_LOCK_TIMEOUT 100000000
 491
 492 /**
 493  * qla4_8xxx_idc_lock - hw_lock
 494  * @ha: pointer to adapter structure
 495  *
 496  * General purpose lock used to synchronize access to
 497  * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
 498  **/
 499 int qla4_8xxx_idc_lock(struct scsi_qla_host *ha)
 500 {
 501         int i;
 502         int done = 0, timeout = 0;
 503
 504         while (!done) {
 505                 /* acquire semaphore5 from PCI HW block */
 506                 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
 507                 if (done == 1)
 508                         break;
 509                 if (timeout >= IDC_LOCK_TIMEOUT)
 510                         return -1;
 511
 512                 timeout++;
 513
 514                 /* Yield CPU */
 515                 if (!in_interrupt())
 516                         schedule();
 517                 else {
 518                         for (i = 0; i < 20; i++)
 519                                 cpu_relax();    /*This a nop instr on i386*/
 520                 }
 521         }
 522         return 0;
 523 }
 524
 525 void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha)
 526 {
 527         qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
 528 }
 529
 530 int
 531 qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
 532 {
 533         struct crb_128M_2M_sub_block_map *m;
 534
 535         if (*off >= QLA82XX_CRB_MAX)
 536                 return -1;
 537
 538         if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
 539                 *off = (*off - QLA82XX_PCI_CAMQM) +
 540                     QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
 541                 return 0;
 542         }
 543
 544         if (*off < QLA82XX_PCI_CRBSPACE)
 545                 return -1;
 546
 547         *off -= QLA82XX_PCI_CRBSPACE;
 548         /*
 549          * Try direct map
 550          */
 551
 552         m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
 553
 554         if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
 555                 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase;
 556                 return 0;
 557         }
 558
 559         /*
 560          * Not in direct map, use crb window
 561          */
 562         return 1;
 563 }
 564
 565 /*  PCI Windowing for DDR regions.  */
 566 #define QLA82XX_ADDR_IN_RANGE(addr, low, high)            \
 567         (((addr) <= (high)) && ((addr) >= (low)))
 568
 569 /*
 570 * check memory access boundary.
 571 * used by test agent. support ddr access only for now
 572 */
 573 static unsigned long
 574 qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha,
 575                 unsigned long long addr, int size)
 576 {
 577         if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 578             QLA82XX_ADDR_DDR_NET_MAX) ||
 579             !QLA82XX_ADDR_IN_RANGE(addr + size - 1,
 580             QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) ||
 581             ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
 582                 return 0;
 583         }
 584         return 1;
 585 }
 586
 587 static int qla4_8xxx_pci_set_window_warning_count;
 588
 589 static unsigned long
 590 qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
 591 {
 592         int window;
 593         u32 win_read;
 594
 595         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 596             QLA82XX_ADDR_DDR_NET_MAX)) {
 597                 /* DDR network side */
 598                 window = MN_WIN(addr);
 599                 ha->ddr_mn_window = window;
 600                 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
 601                     QLA82XX_PCI_CRBSPACE, window);
 602                 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
 603                     QLA82XX_PCI_CRBSPACE);
 604                 if ((win_read << 17) != window) {
 605                         ql4_printk(KERN_WARNING, ha,
 606                         "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
 607                         __func__, window, win_read);
 608                 }
 609                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
 610         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 611                                 QLA82XX_ADDR_OCM0_MAX)) {
 612                 unsigned int temp1;
 613                 /* if bits 19:18&17:11 are on */
 614                 if ((addr & 0x00ff800) == 0xff800) {
 615                         printk("%s: QM access not handled.\n", __func__);
 616                         addr = -1UL;
 617                 }
 618
 619                 window = OCM_WIN(addr);
 620                 ha->ddr_mn_window = window;
 621                 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
 622                     QLA82XX_PCI_CRBSPACE, window);
 623                 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
 624                     QLA82XX_PCI_CRBSPACE);
 625                 temp1 = ((window & 0x1FF) << 7) |
 626                     ((window & 0x0FFFE0000) >> 17);
 627                 if (win_read != temp1) {
 628                         printk("%s: Written OCMwin (0x%x) != Read"
 629                             " OCMwin (0x%x)\n", __func__, temp1, win_read);
 630                 }
 631                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
 632
 633         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
 634                                 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
 635                 /* QDR network side */
 636                 window = MS_WIN(addr);
 637                 ha->qdr_sn_window = window;
 638                 qla4_8xxx_wr_32(ha, ha->ms_win_crb |
 639                     QLA82XX_PCI_CRBSPACE, window);
 640                 win_read = qla4_8xxx_rd_32(ha,
 641                      ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
 642                 if (win_read != window) {
 643                         printk("%s: Written MSwin (0x%x) != Read "
 644                             "MSwin (0x%x)\n", __func__, window, win_read);
 645                 }
 646                 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
 647
 648         } else {
 649                 /*
 650                  * peg gdb frequently accesses memory that doesn't exist,
 651                  * this limits the chit chat so debugging isn't slowed down.
 652                  */
 653                 if ((qla4_8xxx_pci_set_window_warning_count++ < 8) ||
 654                     (qla4_8xxx_pci_set_window_warning_count%64 == 0)) {
 655                         printk("%s: Warning:%s Unknown address range!\n",
 656                             __func__, DRIVER_NAME);
 657                 }
 658                 addr = -1UL;
 659         }
 660         return addr;
 661 }
 662
 663 /* check if address is in the same windows as the previous access */
 664 static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha,
 665                 unsigned long long addr)
 666 {
 667         int window;
 668         unsigned long long qdr_max;
 669
 670         qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
 671
 672         if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
 673             QLA82XX_ADDR_DDR_NET_MAX)) {
 674                 /* DDR network side */
 675                 BUG();  /* MN access can not come here */
 676         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
 677              QLA82XX_ADDR_OCM0_MAX)) {
 678                 return 1;
 679         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1,
 680              QLA82XX_ADDR_OCM1_MAX)) {
 681                 return 1;
 682         } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
 683             qdr_max)) {
 684                 /* QDR network side */
 685                 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
 686                 if (ha->qdr_sn_window == window)
 687                         return 1;
 688         }
 689
 690         return 0;
 691 }
 692
 693 static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha,
 694                 u64 off, void *data, int size)
 695 {
 696         unsigned long flags;
 697         void __iomem *addr;
 698         int ret = 0;
 699         u64 start;
 700         void __iomem *mem_ptr = NULL;
 701         unsigned long mem_base;
 702         unsigned long mem_page;
 703
 704         write_lock_irqsave(&ha->hw_lock, flags);
 705
 706         /*
 707          * If attempting to access unknown address or straddle hw windows,
 708          * do not access.
 709          */
 710         start = qla4_8xxx_pci_set_window(ha, off);
 711         if ((start == -1UL) ||
 712             (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
 713                 write_unlock_irqrestore(&ha->hw_lock, flags);
 714                 printk(KERN_ERR"%s out of bound pci memory access. "
 715                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 716                 return -1;
 717         }
 718
 719         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 720         if (!addr) {
 721                 write_unlock_irqrestore(&ha->hw_lock, flags);
 722                 mem_base = pci_resource_start(ha->pdev, 0);
 723                 mem_page = start & PAGE_MASK;
 724                 /* Map two pages whenever user tries to access addresses in two
 725                    consecutive pages.
 726                  */
 727                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 728                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
 729                 else
 730                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 731
 732                 if (mem_ptr == NULL) {
 733                         *(u8 *)data = 0;
 734                         return -1;
 735                 }
 736                 addr = mem_ptr;
 737                 addr += start & (PAGE_SIZE - 1);
 738                 write_lock_irqsave(&ha->hw_lock, flags);
 739         }
 740
 741         switch (size) {
 742         case 1:
 743                 *(u8  *)data = readb(addr);
 744                 break;
 745         case 2:
 746                 *(u16 *)data = readw(addr);
 747                 break;
 748         case 4:
 749                 *(u32 *)data = readl(addr);
 750                 break;
 751         case 8:
 752                 *(u64 *)data = readq(addr);
 753                 break;
 754         default:
 755                 ret = -1;
 756                 break;
 757         }
 758         write_unlock_irqrestore(&ha->hw_lock, flags);
 759
 760         if (mem_ptr)
 761                 iounmap(mem_ptr);
 762         return ret;
 763 }
 764
 765 static int
 766 qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
 767                 void *data, int size)
 768 {
 769         unsigned long flags;
 770         void __iomem *addr;
 771         int ret = 0;
 772         u64 start;
 773         void __iomem *mem_ptr = NULL;
 774         unsigned long mem_base;
 775         unsigned long mem_page;
 776
 777         write_lock_irqsave(&ha->hw_lock, flags);
 778
 779         /*
 780          * If attempting to access unknown address or straddle hw windows,
 781          * do not access.
 782          */
 783         start = qla4_8xxx_pci_set_window(ha, off);
 784         if ((start == -1UL) ||
 785             (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
 786                 write_unlock_irqrestore(&ha->hw_lock, flags);
 787                 printk(KERN_ERR"%s out of bound pci memory access. "
 788                                 "offset is 0x%llx\n", DRIVER_NAME, off);
 789                 return -1;
 790         }
 791
 792         addr = qla4_8xxx_pci_base_offsetfset(ha, start);
 793         if (!addr) {
 794                 write_unlock_irqrestore(&ha->hw_lock, flags);
 795                 mem_base = pci_resource_start(ha->pdev, 0);
 796                 mem_page = start & PAGE_MASK;
 797                 /* Map two pages whenever user tries to access addresses in two
 798                    consecutive pages.
 799                  */
 800                 if (mem_page != ((start + size - 1) & PAGE_MASK))
 801                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
 802                 else
 803                         mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
 804                 if (mem_ptr == NULL)
 805                         return -1;
 806
 807                 addr = mem_ptr;
 808                 addr += start & (PAGE_SIZE - 1);
 809                 write_lock_irqsave(&ha->hw_lock, flags);
 810         }
 811
 812         switch (size) {
 813         case 1:
 814                 writeb(*(u8 *)data, addr);
 815                 break;
 816         case 2:
 817                 writew(*(u16 *)data, addr);
 818                 break;
 819         case 4:
 820                 writel(*(u32 *)data, addr);
 821                 break;
 822         case 8:
 823                 writeq(*(u64 *)data, addr);
 824                 break;
 825         default:
 826                 ret = -1;
 827                 break;
 828         }
 829         write_unlock_irqrestore(&ha->hw_lock, flags);
 830         if (mem_ptr)
 831                 iounmap(mem_ptr);
 832         return ret;
 833 }
 834
 835 #define MTU_FUDGE_FACTOR 100
 836
 837 static unsigned long
 838 qla4_8xxx_decode_crb_addr(unsigned long addr)
 839 {
 840         int i;
 841         unsigned long base_addr, offset, pci_base;
 842
 843         if (!qla4_8xxx_crb_table_initialized)
 844                 qla4_8xxx_crb_addr_transform_setup();
 845
 846         pci_base = ADDR_ERROR;
 847         base_addr = addr & 0xfff00000;
 848         offset = addr & 0x000fffff;
 849
 850         for (i = 0; i < MAX_CRB_XFORM; i++) {
 851                 if (crb_addr_xform[i] == base_addr) {
 852                         pci_base = i << 20;
 853                         break;
 854                 }
 855         }
 856         if (pci_base == ADDR_ERROR)
 857                 return pci_base;
 858         else
 859                 return pci_base + offset;
 860 }
 861
 862 static long rom_max_timeout = 100;
 863 static long qla4_8xxx_rom_lock_timeout = 100;
 864
 865 static int
 866 qla4_8xxx_rom_lock(struct scsi_qla_host *ha)
 867 {
 868         int i;
 869         int done = 0, timeout = 0;
 870
 871         while (!done) {
 872                 /* acquire semaphore2 from PCI HW block */
 873
 874                 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
 875                 if (done == 1)
 876                         break;
 877                 if (timeout >= qla4_8xxx_rom_lock_timeout)
 878                         return -1;
 879
 880                 timeout++;
 881
 882                 /* Yield CPU */
 883                 if (!in_interrupt())
 884                         schedule();
 885                 else {
 886                         for (i = 0; i < 20; i++)
 887                                 cpu_relax();    /*This a nop instr on i386*/
 888                 }
 889         }
 890         qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
 891         return 0;
 892 }
 893
 894 static void
 895 qla4_8xxx_rom_unlock(struct scsi_qla_host *ha)
 896 {
 897         qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
 898 }
 899
 900 static int
 901 qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha)
 902 {
 903         long timeout = 0;
 904         long done = 0 ;
 905
 906         while (done == 0) {
 907                 done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
 908                 done &= 2;
 909                 timeout++;
 910                 if (timeout >= rom_max_timeout) {
 911                         printk("%s: Timeout reached  waiting for rom done",
 912                                         DRIVER_NAME);
 913                         return -1;
 914                 }
 915         }
 916         return 0;
 917 }
 918
 919 static int
 920 qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 921 {
 922         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
 923         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 924         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
 925         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
 926         if (qla4_8xxx_wait_rom_done(ha)) {
 927                 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
 928                 return -1;
 929         }
 930         /* reset abyte_cnt and dummy_byte_cnt */
 931         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
 932         udelay(10);
 933         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
 934
 935         *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
 936         return 0;
 937 }
 938
 939 static int
 940 qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
 941 {
 942         int ret, loops = 0;
 943
 944         while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
 945                 udelay(100);
 946                 loops++;
 947         }
 948         if (loops >= 50000) {
 949                 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME);
 950                 return -1;
 951         }
 952         ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp);
 953         qla4_8xxx_rom_unlock(ha);
 954         return ret;
 955 }
 956
 957 /**
 958  * This routine does CRB initialize sequence
 959  * to put the ISP into operational state
 960  **/
 961 static int
 962 qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
 963 {
 964         int addr, val;
 965         int i ;
 966         struct crb_addr_pair *buf;
 967         unsigned long off;
 968         unsigned offset, n;
 969
 970         struct crb_addr_pair {
 971                 long addr;
 972                 long data;
 973         };
 974
 975         /* Halt all the indiviual PEGs and other blocks of the ISP */
 976         qla4_8xxx_rom_lock(ha);
 977
 978         /* disable all I2Q */
 979         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
 980         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
 981         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
 982         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
 983         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
 984         qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
 985
 986         /* disable all niu interrupts */
 987         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
 988         /* disable xge rx/tx */
 989         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
 990         /* disable xg1 rx/tx */
 991         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
 992         /* disable sideband mac */
 993         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
 994         /* disable ap0 mac */
 995         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
 996         /* disable ap1 mac */
 997         qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
 998
 999         /* halt sre */
1000         val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1001         qla4_8xxx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1002
1003         /* halt epg */
1004         qla4_8xxx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1005
1006         /* halt timers */
1007         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1008         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1009         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1010         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1011         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1012         qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1013
1014         /* halt pegs */
1015         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1016         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1017         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1018         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1019         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1020         msleep(5);
1021
1022         /* big hammer */
1023         if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1024                 /* don't reset CAM block on reset */
1025                 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1026         else
1027                 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1028
1029         qla4_8xxx_rom_unlock(ha);
1030
1031         /* Read the signature value from the flash.
1032          * Offset 0: Contain signature (0xcafecafe)
1033          * Offset 4: Offset and number of addr/value pairs
1034          * that present in CRB initialize sequence
1035          */
1036         if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1037             qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) {
1038                 ql4_printk(KERN_WARNING, ha,
1039                         "[ERROR] Reading crb_init area: n: %08x\n", n);
1040                 return -1;
1041         }
1042
1043         /* Offset in flash = lower 16 bits
1044          * Number of enteries = upper 16 bits
1045          */
1046         offset = n & 0xffffU;
1047         n = (n >> 16) & 0xffffU;
1048
1049         /* number of addr/value pair should not exceed 1024 enteries */
1050         if (n  >= 1024) {
1051                 ql4_printk(KERN_WARNING, ha,
1052                     "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n",
1053                     DRIVER_NAME, __func__, n);
1054                 return -1;
1055         }
1056
1057         ql4_printk(KERN_INFO, ha,
1058                 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n);
1059
1060         buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1061         if (buf == NULL) {
1062                 ql4_printk(KERN_WARNING, ha,
1063                     "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1064                 return -1;
1065         }
1066
1067         for (i = 0; i < n; i++) {
1068                 if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1069                     qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1070                     0) {
1071                         kfree(buf);
1072                         return -1;
1073                 }
1074
1075                 buf[i].addr = addr;
1076                 buf[i].data = val;
1077         }
1078
1079         for (i = 0; i < n; i++) {
1080                 /* Translate internal CRB initialization
1081                  * address to PCI bus address
1082                  */
1083                 off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) +
1084                     QLA82XX_PCI_CRBSPACE;
1085                 /* Not all CRB  addr/value pair to be written,
1086                  * some of them are skipped
1087                  */
1088
1089                 /* skip if LS bit is set*/
1090                 if (off & 0x1) {
1091                         DEBUG2(ql4_printk(KERN_WARNING, ha,
1092                             "Skip CRB init replay for offset = 0x%lx\n", off));
1093                         continue;
1094                 }
1095
1096                 /* skipping cold reboot MAGIC */
1097                 if (off == QLA82XX_CAM_RAM(0x1fc))
1098                         continue;
1099
1100                 /* do not reset PCI */
1101                 if (off == (ROMUSB_GLB + 0xbc))
1102                         continue;
1103
1104                 /* skip core clock, so that firmware can increase the clock */
1105                 if (off == (ROMUSB_GLB + 0xc8))
1106                         continue;
1107
1108                 /* skip the function enable register */
1109                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1110                         continue;
1111
1112                 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1113                         continue;
1114
1115                 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1116                         continue;
1117
1118                 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1119                         continue;
1120
1121                 if (off == ADDR_ERROR) {
1122                         ql4_printk(KERN_WARNING, ha,
1123                             "%s: [ERROR] Unknown addr: 0x%08lx\n",
1124                             DRIVER_NAME, buf[i].addr);
1125                         continue;
1126                 }
1127
1128                 qla4_8xxx_wr_32(ha, off, buf[i].data);
1129
1130                 /* ISP requires much bigger delay to settle down,
1131                  * else crb_window returns 0xffffffff
1132                  */
1133                 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1134                         msleep(1000);
1135
1136                 /* ISP requires millisec delay between
1137                  * successive CRB register updation
1138                  */
1139                 msleep(1);
1140         }
1141
1142         kfree(buf);
1143
1144         /* Resetting the data and instruction cache */
1145         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1146         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1147         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1148
1149         /* Clear all protocol processing engines */
1150         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1151         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1152         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1153         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1154         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1155         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1156         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1157         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1158
1159         return 0;
1160 }
1161
1162 static int
1163 qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1164 {
1165         int  i, rval = 0;
1166         long size = 0;
1167         long flashaddr, memaddr;
1168         u64 data;
1169         u32 high, low;
1170
1171         flashaddr = memaddr = ha->hw.flt_region_bootload;
1172         size = (image_start - flashaddr) / 8;
1173
1174         DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1175             ha->host_no, __func__, flashaddr, image_start));
1176
1177         for (i = 0; i < size; i++) {
1178                 if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1179                     (qla4_8xxx_rom_fast_read(ha, flashaddr + 4,
1180                     (int *)&high))) {
1181                         rval = -1;
1182                         goto exit_load_from_flash;
1183                 }
1184                 data = ((u64)high << 32) | low ;
1185                 rval = qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8);
1186                 if (rval)
1187                         goto exit_load_from_flash;
1188
1189                 flashaddr += 8;
1190                 memaddr   += 8;
1191
1192                 if (i % 0x1000 == 0)
1193                         msleep(1);
1194
1195         }
1196
1197         udelay(100);
1198
1199         read_lock(&ha->hw_lock);
1200         qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1201         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1202         read_unlock(&ha->hw_lock);
1203
1204 exit_load_from_flash:
1205         return rval;
1206 }
1207
1208 static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1209 {
1210         u32 rst;
1211
1212         qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1213         if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1214                 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1215                     __func__);
1216                 return QLA_ERROR;
1217         }
1218
1219         udelay(500);
1220
1221         /* at this point, QM is in reset. This could be a problem if there are
1222          * incoming d* transition queue messages. QM/PCIE could wedge.
1223          * To get around this, QM is brought out of reset.
1224          */
1225
1226         rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1227         /* unreset qm */
1228         rst &= ~(1 << 28);
1229         qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1230
1231         if (qla4_8xxx_load_from_flash(ha, image_start)) {
1232                 printk("%s: Error trying to load fw from flash!\n", __func__);
1233                 return QLA_ERROR;
1234         }
1235
1236         return QLA_SUCCESS;
1237 }
1238
1239 int
1240 qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha,
1241                 u64 off, void *data, int size)
1242 {
1243         int i, j = 0, k, start, end, loop, sz[2], off0[2];
1244         int shift_amount;
1245         uint32_t temp;
1246         uint64_t off8, val, mem_crb, word[2] = {0, 0};
1247
1248         /*
1249          * If not MN, go check for MS or invalid.
1250          */
1251
1252         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1253                 mem_crb = QLA82XX_CRB_QDR_NET;
1254         else {
1255                 mem_crb = QLA82XX_CRB_DDR_NET;
1256                 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1257                         return qla4_8xxx_pci_mem_read_direct(ha,
1258                                         off, data, size);
1259         }
1260
1261
1262         off8 = off & 0xfffffff0;
1263         off0[0] = off & 0xf;
1264         sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1265         shift_amount = 4;
1266
1267         loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1268         off0[1] = 0;
1269         sz[1] = size - sz[0];
1270
1271         for (i = 0; i < loop; i++) {
1272                 temp = off8 + (i << shift_amount);
1273                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1274                 temp = 0;
1275                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1276                 temp = MIU_TA_CTL_ENABLE;
1277                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1278                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1279                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1280
1281                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1282                         temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1283                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1284                                 break;
1285                 }
1286
1287                 if (j >= MAX_CTL_CHECK) {
1288                         printk_ratelimited(KERN_ERR
1289                                            "%s: failed to read through agent\n",
1290                                            __func__);
1291                         break;
1292                 }
1293
1294                 start = off0[i] >> 2;
1295                 end   = (off0[i] + sz[i] - 1) >> 2;
1296                 for (k = start; k <= end; k++) {
1297                         temp = qla4_8xxx_rd_32(ha,
1298                                 mem_crb + MIU_TEST_AGT_RDDATA(k));
1299                         word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1300                 }
1301         }
1302
1303         if (j >= MAX_CTL_CHECK)
1304                 return -1;
1305
1306         if ((off0[0] & 7) == 0) {
1307                 val = word[0];
1308         } else {
1309                 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1310                 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1311         }
1312
1313         switch (size) {
1314         case 1:
1315                 *(uint8_t  *)data = val;
1316                 break;
1317         case 2:
1318                 *(uint16_t *)data = val;
1319                 break;
1320         case 4:
1321                 *(uint32_t *)data = val;
1322                 break;
1323         case 8:
1324                 *(uint64_t *)data = val;
1325                 break;
1326         }
1327         return 0;
1328 }
1329
1330 int
1331 qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha,
1332                 u64 off, void *data, int size)
1333 {
1334         int i, j, ret = 0, loop, sz[2], off0;
1335         int scale, shift_amount, startword;
1336         uint32_t temp;
1337         uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1338
1339         /*
1340          * If not MN, go check for MS or invalid.
1341          */
1342         if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1343                 mem_crb = QLA82XX_CRB_QDR_NET;
1344         else {
1345                 mem_crb = QLA82XX_CRB_DDR_NET;
1346                 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1347                         return qla4_8xxx_pci_mem_write_direct(ha,
1348                                         off, data, size);
1349         }
1350
1351         off0 = off & 0x7;
1352         sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1353         sz[1] = size - sz[0];
1354
1355         off8 = off & 0xfffffff0;
1356         loop = (((off & 0xf) + size - 1) >> 4) + 1;
1357         shift_amount = 4;
1358         scale = 2;
1359         startword = (off & 0xf)/8;
1360
1361         for (i = 0; i < loop; i++) {
1362                 if (qla4_8xxx_pci_mem_read_2M(ha, off8 +
1363                     (i << shift_amount), &word[i * scale], 8))
1364                         return -1;
1365         }
1366
1367         switch (size) {
1368         case 1:
1369                 tmpw = *((uint8_t *)data);
1370                 break;
1371         case 2:
1372                 tmpw = *((uint16_t *)data);
1373                 break;
1374         case 4:
1375                 tmpw = *((uint32_t *)data);
1376                 break;
1377         case 8:
1378         default:
1379                 tmpw = *((uint64_t *)data);
1380                 break;
1381         }
1382
1383         if (sz[0] == 8)
1384                 word[startword] = tmpw;
1385         else {
1386                 word[startword] &=
1387                     ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1388                 word[startword] |= tmpw << (off0 * 8);
1389         }
1390
1391         if (sz[1] != 0) {
1392                 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1393                 word[startword+1] |= tmpw >> (sz[0] * 8);
1394         }
1395
1396         for (i = 0; i < loop; i++) {
1397                 temp = off8 + (i << shift_amount);
1398                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1399                 temp = 0;
1400                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1401                 temp = word[i * scale] & 0xffffffff;
1402                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1403                 temp = (word[i * scale] >> 32) & 0xffffffff;
1404                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1405                 temp = word[i*scale + 1] & 0xffffffff;
1406                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1407                     temp);
1408                 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1409                 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1410                     temp);
1411
1412                 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1413                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1414                 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1415                 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1416
1417                 for (j = 0; j < MAX_CTL_CHECK; j++) {
1418                         temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1419                         if ((temp & MIU_TA_CTL_BUSY) == 0)
1420                                 break;
1421                 }
1422
1423                 if (j >= MAX_CTL_CHECK) {
1424                         if (printk_ratelimit())
1425                                 ql4_printk(KERN_ERR, ha,
1426                                            "%s: failed to read through agent\n",
1427                                            __func__);
1428                         ret = -1;
1429                         break;
1430                 }
1431         }
1432
1433         return ret;
1434 }
1435
1436 static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1437 {
1438         u32 val = 0;
1439         int retries = 60;
1440
1441         if (!pegtune_val) {
1442                 do {
1443                         val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE);
1444                         if ((val == PHAN_INITIALIZE_COMPLETE) ||
1445                             (val == PHAN_INITIALIZE_ACK))
1446                                 return 0;
1447                         set_current_state(TASK_UNINTERRUPTIBLE);
1448                         schedule_timeout(500);
1449
1450                 } while (--retries);
1451
1452                 if (!retries) {
1453                         pegtune_val = qla4_8xxx_rd_32(ha,
1454                                 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1455                         printk(KERN_WARNING "%s: init failed, "
1456                                 "pegtune_val = %x\n", __func__, pegtune_val);
1457                         return -1;
1458                 }
1459         }
1460         return 0;
1461 }
1462
1463 static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha)
1464 {
1465         uint32_t state = 0;
1466         int loops = 0;
1467
1468         /* Window 1 call */
1469         read_lock(&ha->hw_lock);
1470         state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1471         read_unlock(&ha->hw_lock);
1472
1473         while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1474                 udelay(100);
1475                 /* Window 1 call */
1476                 read_lock(&ha->hw_lock);
1477                 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1478                 read_unlock(&ha->hw_lock);
1479
1480                 loops++;
1481         }
1482
1483         if (loops >= 30000) {
1484                 DEBUG2(ql4_printk(KERN_INFO, ha,
1485                     "Receive Peg initialization not complete: 0x%x.\n", state));
1486                 return QLA_ERROR;
1487         }
1488
1489         return QLA_SUCCESS;
1490 }
1491
1492 void
1493 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1494 {
1495         uint32_t drv_active;
1496
1497         drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1498         drv_active |= (1 << (ha->func_num * 4));
1499         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1500                    __func__, ha->host_no, drv_active);
1501         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1502 }
1503
1504 void
1505 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1506 {
1507         uint32_t drv_active;
1508
1509         drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1510         drv_active &= ~(1 << (ha->func_num * 4));
1511         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1512                    __func__, ha->host_no, drv_active);
1513         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1514 }
1515
1516 static inline int
1517 qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1518 {
1519         uint32_t drv_state, drv_active;
1520         int rval;
1521
1522         drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1523         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1524         rval = drv_state & (1 << (ha->func_num * 4));
1525         if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1526                 rval = 1;
1527
1528         return rval;
1529 }
1530
1531 static inline void
1532 qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1533 {
1534         uint32_t drv_state;
1535
1536         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1537         drv_state |= (1 << (ha->func_num * 4));
1538         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1539                    __func__, ha->host_no, drv_state);
1540         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1541 }
1542
1543 static inline void
1544 qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1545 {
1546         uint32_t drv_state;
1547
1548         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1549         drv_state &= ~(1 << (ha->func_num * 4));
1550         ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1551                    __func__, ha->host_no, drv_state);
1552         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1553 }
1554
1555 static inline void
1556 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1557 {
1558         uint32_t qsnt_state;
1559
1560         qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1561         qsnt_state |= (2 << (ha->func_num * 4));
1562         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
1563 }
1564
1565
1566 static int
1567 qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1568 {
1569         uint16_t lnk;
1570
1571         /* scrub dma mask expansion register */
1572         qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1573
1574         /* Overwrite stale initialization register values */
1575         qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1576         qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1577         qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1578         qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1579
1580         if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) {
1581                 printk("%s: Error trying to start fw!\n", __func__);
1582                 return QLA_ERROR;
1583         }
1584
1585         /* Handshake with the card before we register the devices. */
1586         if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1587                 printk("%s: Error during card handshake!\n", __func__);
1588                 return QLA_ERROR;
1589         }
1590
1591         /* Negotiated Link width */
1592         pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
1593         ha->link_width = (lnk >> 4) & 0x3f;
1594
1595         /* Synchronize with Receive peg */
1596         return qla4_8xxx_rcvpeg_ready(ha);
1597 }
1598
1599 static int
1600 qla4_8xxx_try_start_fw(struct scsi_qla_host *ha)
1601 {
1602         int rval = QLA_ERROR;
1603
1604         /*
1605          * FW Load priority:
1606          * 1) Operational firmware residing in flash.
1607          * 2) Fail
1608          */
1609
1610         ql4_printk(KERN_INFO, ha,
1611             "FW: Retrieving flash offsets from FLT/FDT ...\n");
1612         rval = qla4_8xxx_get_flash_info(ha);
1613         if (rval != QLA_SUCCESS)
1614                 return rval;
1615
1616         ql4_printk(KERN_INFO, ha,
1617             "FW: Attempting to load firmware from flash...\n");
1618         rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw);
1619
1620         if (rval != QLA_SUCCESS) {
1621                 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1622                     " FAILED...\n");
1623                 return rval;
1624         }
1625
1626         return rval;
1627 }
1628
1629 static void qla4_8xxx_rom_lock_recovery(struct scsi_qla_host *ha)
1630 {
1631         if (qla4_8xxx_rom_lock(ha)) {
1632                 /* Someone else is holding the lock. */
1633                 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1634         }
1635
1636         /*
1637          * Either we got the lock, or someone
1638          * else died while holding it.
1639          * In either case, unlock.
1640          */
1641         qla4_8xxx_rom_unlock(ha);
1642 }
1643
1644 static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1645                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1646                                 uint32_t **d_ptr)
1647 {
1648         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1649         struct qla82xx_minidump_entry_crb *crb_hdr;
1650         uint32_t *data_ptr = *d_ptr;
1651
1652         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1653         crb_hdr = (struct qla82xx_minidump_entry_crb *)entry_hdr;
1654         r_addr = crb_hdr->addr;
1655         r_stride = crb_hdr->crb_strd.addr_stride;
1656         loop_cnt = crb_hdr->op_count;
1657
1658         for (i = 0; i < loop_cnt; i++) {
1659                 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0);
1660                 *data_ptr++ = cpu_to_le32(r_addr);
1661                 *data_ptr++ = cpu_to_le32(r_value);
1662                 r_addr += r_stride;
1663         }
1664         *d_ptr = data_ptr;
1665 }
1666
1667 static int qla4_8xxx_minidump_process_l2tag(struct scsi_qla_host *ha,
1668                                  struct qla82xx_minidump_entry_hdr *entry_hdr,
1669                                  uint32_t **d_ptr)
1670 {
1671         uint32_t addr, r_addr, c_addr, t_r_addr;
1672         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1673         unsigned long p_wait, w_time, p_mask;
1674         uint32_t c_value_w, c_value_r;
1675         struct qla82xx_minidump_entry_cache *cache_hdr;
1676         int rval = QLA_ERROR;
1677         uint32_t *data_ptr = *d_ptr;
1678
1679         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1680         cache_hdr = (struct qla82xx_minidump_entry_cache *)entry_hdr;
1681
1682         loop_count = cache_hdr->op_count;
1683         r_addr = cache_hdr->read_addr;
1684         c_addr = cache_hdr->control_addr;
1685         c_value_w = cache_hdr->cache_ctrl.write_value;
1686
1687         t_r_addr = cache_hdr->tag_reg_addr;
1688         t_value = cache_hdr->addr_ctrl.init_tag_value;
1689         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1690         p_wait = cache_hdr->cache_ctrl.poll_wait;
1691         p_mask = cache_hdr->cache_ctrl.poll_mask;
1692
1693         for (i = 0; i < loop_count; i++) {
1694                 qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1);
1695
1696                 if (c_value_w)
1697                         qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1);
1698
1699                 if (p_mask) {
1700                         w_time = jiffies + p_wait;
1701                         do {
1702                                 c_value_r = qla4_8xxx_md_rw_32(ha, c_addr,
1703                                                                 0, 0);
1704                                 if ((c_value_r & p_mask) == 0) {
1705                                         break;
1706                                 } else if (time_after_eq(jiffies, w_time)) {
1707                                         /* capturing dump failed */
1708                                         return rval;
1709                                 }
1710                         } while (1);
1711                 }
1712
1713                 addr = r_addr;
1714                 for (k = 0; k < r_cnt; k++) {
1715                         r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0);
1716                         *data_ptr++ = cpu_to_le32(r_value);
1717                         addr += cache_hdr->read_ctrl.read_addr_stride;
1718                 }
1719
1720                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
1721         }
1722         *d_ptr = data_ptr;
1723         return QLA_SUCCESS;
1724 }
1725
1726 static int qla4_8xxx_minidump_process_control(struct scsi_qla_host *ha,
1727                                 struct qla82xx_minidump_entry_hdr *entry_hdr)
1728 {
1729         struct qla82xx_minidump_entry_crb *crb_entry;
1730         uint32_t read_value, opcode, poll_time, addr, index, rval = QLA_SUCCESS;
1731         uint32_t crb_addr;
1732         unsigned long wtime;
1733         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
1734         int i;
1735
1736         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1737         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
1738                                                 ha->fw_dump_tmplt_hdr;
1739         crb_entry = (struct qla82xx_minidump_entry_crb *)entry_hdr;
1740
1741         crb_addr = crb_entry->addr;
1742         for (i = 0; i < crb_entry->op_count; i++) {
1743                 opcode = crb_entry->crb_ctrl.opcode;
1744                 if (opcode & QLA82XX_DBG_OPCODE_WR) {
1745                         qla4_8xxx_md_rw_32(ha, crb_addr,
1746                                            crb_entry->value_1, 1);
1747                         opcode &= ~QLA82XX_DBG_OPCODE_WR;
1748                 }
1749                 if (opcode & QLA82XX_DBG_OPCODE_RW) {
1750                         read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
1751                         qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1);
1752                         opcode &= ~QLA82XX_DBG_OPCODE_RW;
1753                 }
1754                 if (opcode & QLA82XX_DBG_OPCODE_AND) {
1755                         read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
1756                         read_value &= crb_entry->value_2;
1757                         opcode &= ~QLA82XX_DBG_OPCODE_AND;
1758                         if (opcode & QLA82XX_DBG_OPCODE_OR) {
1759                                 read_value |= crb_entry->value_3;
1760                                 opcode &= ~QLA82XX_DBG_OPCODE_OR;
1761                         }
1762                         qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1);
1763                 }
1764                 if (opcode & QLA82XX_DBG_OPCODE_OR) {
1765                         read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
1766                         read_value |= crb_entry->value_3;
1767                         qla4_8xxx_md_rw_32(ha, crb_addr, read_value, 1);
1768                         opcode &= ~QLA82XX_DBG_OPCODE_OR;
1769                 }
1770                 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
1771                         poll_time = crb_entry->crb_strd.poll_timeout;
1772                         wtime = jiffies + poll_time;
1773                         read_value = qla4_8xxx_md_rw_32(ha, crb_addr, 0, 0);
1774
1775                         do {
1776                                 if ((read_value & crb_entry->value_2) ==
1777                                     crb_entry->value_1)
1778                                         break;
1779                                 else if (time_after_eq(jiffies, wtime)) {
1780                                         /* capturing dump failed */
1781                                         rval = QLA_ERROR;
1782                                         break;
1783                                 } else
1784                                         read_value = qla4_8xxx_md_rw_32(ha,
1785                                                                 crb_addr, 0, 0);
1786                         } while (1);
1787                         opcode &= ~QLA82XX_DBG_OPCODE_POLL;
1788                 }
1789
1790                 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
1791                         if (crb_entry->crb_strd.state_index_a) {
1792                                 index = crb_entry->crb_strd.state_index_a;
1793                                 addr = tmplt_hdr->saved_state_array[index];
1794                         } else {
1795                                 addr = crb_addr;
1796                         }
1797
1798                         read_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0);
1799                         index = crb_entry->crb_ctrl.state_index_v;
1800                         tmplt_hdr->saved_state_array[index] = read_value;
1801                         opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
1802                 }
1803
1804                 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
1805                         if (crb_entry->crb_strd.state_index_a) {
1806                                 index = crb_entry->crb_strd.state_index_a;
1807                                 addr = tmplt_hdr->saved_state_array[index];
1808                         } else {
1809                                 addr = crb_addr;
1810                         }
1811
1812                         if (crb_entry->crb_ctrl.state_index_v) {
1813                                 index = crb_entry->crb_ctrl.state_index_v;
1814                                 read_value =
1815                                         tmplt_hdr->saved_state_array[index];
1816                         } else {
1817                                 read_value = crb_entry->value_1;
1818                         }
1819
1820                         qla4_8xxx_md_rw_32(ha, addr, read_value, 1);
1821                         opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
1822                 }
1823
1824                 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
1825                         index = crb_entry->crb_ctrl.state_index_v;
1826                         read_value = tmplt_hdr->saved_state_array[index];
1827                         read_value <<= crb_entry->crb_ctrl.shl;
1828                         read_value >>= crb_entry->crb_ctrl.shr;
1829                         if (crb_entry->value_2)
1830                                 read_value &= crb_entry->value_2;
1831                         read_value |= crb_entry->value_3;
1832                         read_value += crb_entry->value_1;
1833                         tmplt_hdr->saved_state_array[index] = read_value;
1834                         opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
1835                 }
1836                 crb_addr += crb_entry->crb_strd.addr_stride;
1837         }
1838         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s\n", __func__));
1839         return rval;
1840 }
1841
1842 static void qla4_8xxx_minidump_process_rdocm(struct scsi_qla_host *ha,
1843                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1844                                 uint32_t **d_ptr)
1845 {
1846         uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1847         struct qla82xx_minidump_entry_rdocm *ocm_hdr;
1848         uint32_t *data_ptr = *d_ptr;
1849
1850         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1851         ocm_hdr = (struct qla82xx_minidump_entry_rdocm *)entry_hdr;
1852         r_addr = ocm_hdr->read_addr;
1853         r_stride = ocm_hdr->read_addr_stride;
1854         loop_cnt = ocm_hdr->op_count;
1855
1856         DEBUG2(ql4_printk(KERN_INFO, ha,
1857                           "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
1858                           __func__, r_addr, r_stride, loop_cnt));
1859
1860         for (i = 0; i < loop_cnt; i++) {
1861                 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
1862                 *data_ptr++ = cpu_to_le32(r_value);
1863                 r_addr += r_stride;
1864         }
1865         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
1866                           __func__, (loop_cnt * sizeof(uint32_t))));
1867         *d_ptr = data_ptr;
1868 }
1869
1870 static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
1871                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1872                                 uint32_t **d_ptr)
1873 {
1874         uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
1875         struct qla82xx_minidump_entry_mux *mux_hdr;
1876         uint32_t *data_ptr = *d_ptr;
1877
1878         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1879         mux_hdr = (struct qla82xx_minidump_entry_mux *)entry_hdr;
1880         r_addr = mux_hdr->read_addr;
1881         s_addr = mux_hdr->select_addr;
1882         s_stride = mux_hdr->select_value_stride;
1883         s_value = mux_hdr->select_value;
1884         loop_cnt = mux_hdr->op_count;
1885
1886         for (i = 0; i < loop_cnt; i++) {
1887                 qla4_8xxx_md_rw_32(ha, s_addr, s_value, 1);
1888                 r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0);
1889                 *data_ptr++ = cpu_to_le32(s_value);
1890                 *data_ptr++ = cpu_to_le32(r_value);
1891                 s_value += s_stride;
1892         }
1893         *d_ptr = data_ptr;
1894 }
1895
1896 static void qla4_8xxx_minidump_process_l1cache(struct scsi_qla_host *ha,
1897                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1898                                 uint32_t **d_ptr)
1899 {
1900         uint32_t addr, r_addr, c_addr, t_r_addr;
1901         uint32_t i, k, loop_count, t_value, r_cnt, r_value;
1902         uint32_t c_value_w;
1903         struct qla82xx_minidump_entry_cache *cache_hdr;
1904         uint32_t *data_ptr = *d_ptr;
1905
1906         cache_hdr = (struct qla82xx_minidump_entry_cache *)entry_hdr;
1907         loop_count = cache_hdr->op_count;
1908         r_addr = cache_hdr->read_addr;
1909         c_addr = cache_hdr->control_addr;
1910         c_value_w = cache_hdr->cache_ctrl.write_value;
1911
1912         t_r_addr = cache_hdr->tag_reg_addr;
1913         t_value = cache_hdr->addr_ctrl.init_tag_value;
1914         r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
1915
1916         for (i = 0; i < loop_count; i++) {
1917                 qla4_8xxx_md_rw_32(ha, t_r_addr, t_value, 1);
1918                 qla4_8xxx_md_rw_32(ha, c_addr, c_value_w, 1);
1919                 addr = r_addr;
1920                 for (k = 0; k < r_cnt; k++) {
1921                         r_value = qla4_8xxx_md_rw_32(ha, addr, 0, 0);
1922                         *data_ptr++ = cpu_to_le32(r_value);
1923                         addr += cache_hdr->read_ctrl.read_addr_stride;
1924                 }
1925                 t_value += cache_hdr->addr_ctrl.tag_value_stride;
1926         }
1927         *d_ptr = data_ptr;
1928 }
1929
1930 static void qla4_8xxx_minidump_process_queue(struct scsi_qla_host *ha,
1931                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1932                                 uint32_t **d_ptr)
1933 {
1934         uint32_t s_addr, r_addr;
1935         uint32_t r_stride, r_value, r_cnt, qid = 0;
1936         uint32_t i, k, loop_cnt;
1937         struct qla82xx_minidump_entry_queue *q_hdr;
1938         uint32_t *data_ptr = *d_ptr;
1939
1940         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1941         q_hdr = (struct qla82xx_minidump_entry_queue *)entry_hdr;
1942         s_addr = q_hdr->select_addr;
1943         r_cnt = q_hdr->rd_strd.read_addr_cnt;
1944         r_stride = q_hdr->rd_strd.read_addr_stride;
1945         loop_cnt = q_hdr->op_count;
1946
1947         for (i = 0; i < loop_cnt; i++) {
1948                 qla4_8xxx_md_rw_32(ha, s_addr, qid, 1);
1949                 r_addr = q_hdr->read_addr;
1950                 for (k = 0; k < r_cnt; k++) {
1951                         r_value = qla4_8xxx_md_rw_32(ha, r_addr, 0, 0);
1952                         *data_ptr++ = cpu_to_le32(r_value);
1953                         r_addr += r_stride;
1954                 }
1955                 qid += q_hdr->q_strd.queue_id_stride;
1956         }
1957         *d_ptr = data_ptr;
1958 }
1959
1960 #define MD_DIRECT_ROM_WINDOW            0x42110030
1961 #define MD_DIRECT_ROM_READ_BASE         0x42150000
1962
1963 static void qla4_8xxx_minidump_process_rdrom(struct scsi_qla_host *ha,
1964                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1965                                 uint32_t **d_ptr)
1966 {
1967         uint32_t r_addr, r_value;
1968         uint32_t i, loop_cnt;
1969         struct qla82xx_minidump_entry_rdrom *rom_hdr;
1970         uint32_t *data_ptr = *d_ptr;
1971
1972         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
1973         rom_hdr = (struct qla82xx_minidump_entry_rdrom *)entry_hdr;
1974         r_addr = rom_hdr->read_addr;
1975         loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
1976
1977         DEBUG2(ql4_printk(KERN_INFO, ha,
1978                           "[%s]: flash_addr: 0x%x, read_data_size: 0x%x\n",
1979                            __func__, r_addr, loop_cnt));
1980
1981         for (i = 0; i < loop_cnt; i++) {
1982                 qla4_8xxx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
1983                                    (r_addr & 0xFFFF0000), 1);
1984                 r_value = qla4_8xxx_md_rw_32(ha,
1985                                              MD_DIRECT_ROM_READ_BASE +
1986                                              (r_addr & 0x0000FFFF), 0, 0);
1987                 *data_ptr++ = cpu_to_le32(r_value);
1988                 r_addr += sizeof(uint32_t);
1989         }
1990         *d_ptr = data_ptr;
1991 }
1992
1993 #define MD_MIU_TEST_AGT_CTRL            0x41000090
1994 #define MD_MIU_TEST_AGT_ADDR_LO         0x41000094
1995 #define MD_MIU_TEST_AGT_ADDR_HI         0x41000098
1996
1997 static int qla4_8xxx_minidump_process_rdmem(struct scsi_qla_host *ha,
1998                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
1999                                 uint32_t **d_ptr)
2000 {
2001         uint32_t r_addr, r_value, r_data;
2002         uint32_t i, j, loop_cnt;
2003         struct qla82xx_minidump_entry_rdmem *m_hdr;
2004         unsigned long flags;
2005         uint32_t *data_ptr = *d_ptr;
2006
2007         DEBUG2(ql4_printk(KERN_INFO, ha, "Entering fn: %s\n", __func__));
2008         m_hdr = (struct qla82xx_minidump_entry_rdmem *)entry_hdr;
2009         r_addr = m_hdr->read_addr;
2010         loop_cnt = m_hdr->read_data_size/16;
2011
2012         DEBUG2(ql4_printk(KERN_INFO, ha,
2013                           "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
2014                           __func__, r_addr, m_hdr->read_data_size));
2015
2016         if (r_addr & 0xf) {
2017                 DEBUG2(ql4_printk(KERN_INFO, ha,
2018                                   "[%s]: Read addr 0x%x not 16 bytes alligned\n",
2019                                   __func__, r_addr));
2020                 return QLA_ERROR;
2021         }
2022
2023         if (m_hdr->read_data_size % 16) {
2024                 DEBUG2(ql4_printk(KERN_INFO, ha,
2025                                   "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
2026                                   __func__, m_hdr->read_data_size));
2027                 return QLA_ERROR;
2028         }
2029
2030         DEBUG2(ql4_printk(KERN_INFO, ha,
2031                           "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
2032                           __func__, r_addr, m_hdr->read_data_size, loop_cnt));
2033
2034         write_lock_irqsave(&ha->hw_lock, flags);
2035         for (i = 0; i < loop_cnt; i++) {
2036                 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
2037                 r_value = 0;
2038                 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
2039                 r_value = MIU_TA_CTL_ENABLE;
2040                 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
2041                 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
2042                 qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
2043
2044                 for (j = 0; j < MAX_CTL_CHECK; j++) {
2045                         r_value = qla4_8xxx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL,
2046                                                      0, 0);
2047                         if ((r_value & MIU_TA_CTL_BUSY) == 0)
2048                                 break;
2049                 }
2050
2051                 if (j >= MAX_CTL_CHECK) {
2052                         printk_ratelimited(KERN_ERR
2053                                            "%s: failed to read through agent\n",
2054                                             __func__);
2055                         write_unlock_irqrestore(&ha->hw_lock, flags);
2056                         return QLA_SUCCESS;
2057                 }
2058
2059                 for (j = 0; j < 4; j++) {
2060                         r_data = qla4_8xxx_md_rw_32(ha,
2061                                                     MD_MIU_TEST_AGT_RDDATA[j],
2062                                                     0, 0);
2063                         *data_ptr++ = cpu_to_le32(r_data);
2064                 }
2065
2066                 r_addr += 16;
2067         }
2068         write_unlock_irqrestore(&ha->hw_lock, flags);
2069
2070         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%x\n",
2071                           __func__, (loop_cnt * 16)));
2072
2073         *d_ptr = data_ptr;
2074         return QLA_SUCCESS;
2075 }
2076
2077 static void ql4_8xxx_mark_entry_skipped(struct scsi_qla_host *ha,
2078                                 struct qla82xx_minidump_entry_hdr *entry_hdr,
2079                                 int index)
2080 {
2081         entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
2082         DEBUG2(ql4_printk(KERN_INFO, ha,
2083                           "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2084                           ha->host_no, index, entry_hdr->entry_type,
2085                           entry_hdr->d_ctrl.entry_capture_mask));
2086 }
2087
2088 /**
2089  * qla82xx_collect_md_data - Retrieve firmware minidump data.
2090  * @ha: pointer to adapter structure
2091  **/
2092 static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2093 {
2094         int num_entry_hdr = 0;
2095         struct qla82xx_minidump_entry_hdr *entry_hdr;
2096         struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2097         uint32_t *data_ptr;
2098         uint32_t data_collected = 0;
2099         int i, rval = QLA_ERROR;
2100         uint64_t now;
2101         uint32_t timestamp;
2102
2103         if (!ha->fw_dump) {
2104                 ql4_printk(KERN_INFO, ha, "%s(%ld) No buffer to dump\n",
2105                            __func__, ha->host_no);
2106                 return rval;
2107         }
2108
2109         tmplt_hdr = (struct qla4_8xxx_minidump_template_hdr *)
2110                                                 ha->fw_dump_tmplt_hdr;
2111         data_ptr = (uint32_t *)((uint8_t *)ha->fw_dump +
2112                                                 ha->fw_dump_tmplt_size);
2113         data_collected += ha->fw_dump_tmplt_size;
2114
2115         num_entry_hdr = tmplt_hdr->num_of_entries;
2116         ql4_printk(KERN_INFO, ha, "[%s]: starting data ptr: %p\n",
2117                    __func__, data_ptr);
2118         ql4_printk(KERN_INFO, ha,
2119                    "[%s]: no of entry headers in Template: 0x%x\n",
2120                    __func__, num_entry_hdr);
2121         ql4_printk(KERN_INFO, ha, "[%s]: Capture Mask obtained: 0x%x\n",
2122                    __func__, ha->fw_dump_capture_mask);
2123         ql4_printk(KERN_INFO, ha, "[%s]: Total_data_size 0x%x, %d obtained\n",
2124                    __func__, ha->fw_dump_size, ha->fw_dump_size);
2125
2126         /* Update current timestamp before taking dump */
2127         now = get_jiffies_64();
2128         timestamp = (u32)(jiffies_to_msecs(now) / 1000);
2129         tmplt_hdr->driver_timestamp = timestamp;
2130
2131         entry_hdr = (struct qla82xx_minidump_entry_hdr *)
2132                                         (((uint8_t *)ha->fw_dump_tmplt_hdr) +
2133                                          tmplt_hdr->first_entry_offset);
2134
2135         /* Walk through the entry headers - validate/perform required action */
2136         for (i = 0; i < num_entry_hdr; i++) {
2137                 if (data_collected >= ha->fw_dump_size) {
2138                         ql4_printk(KERN_INFO, ha,
2139                                    "Data collected: [0x%x], Total Dump size: [0x%x]\n",
2140                                    data_collected, ha->fw_dump_size);
2141                         return rval;
2142                 }
2143
2144                 if (!(entry_hdr->d_ctrl.entry_capture_mask &
2145                       ha->fw_dump_capture_mask)) {
2146                         entry_hdr->d_ctrl.driver_flags |=
2147                                                 QLA82XX_DBG_SKIPPED_FLAG;
2148                         goto skip_nxt_entry;
2149                 }
2150
2151                 DEBUG2(ql4_printk(KERN_INFO, ha,
2152                                   "Data collected: [0x%x], Dump size left:[0x%x]\n",
2153                                   data_collected,
2154                                   (ha->fw_dump_size - data_collected)));
2155
2156                 /* Decode the entry type and take required action to capture
2157                  * debug data
2158                  */
2159                 switch (entry_hdr->entry_type) {
2160                 case QLA82XX_RDEND:
2161                         ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2162                         break;
2163                 case QLA82XX_CNTRL:
2164                         rval = qla4_8xxx_minidump_process_control(ha,
2165                                                                   entry_hdr);
2166                         if (rval != QLA_SUCCESS) {
2167                                 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2168                                 goto md_failed;
2169                         }
2170                         break;
2171                 case QLA82XX_RDCRB:
2172                         qla4_8xxx_minidump_process_rdcrb(ha, entry_hdr,
2173                                                          &data_ptr);
2174                         break;
2175                 case QLA82XX_RDMEM:
2176                         rval = qla4_8xxx_minidump_process_rdmem(ha, entry_hdr,
2177                                                                 &data_ptr);
2178                         if (rval != QLA_SUCCESS) {
2179                                 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2180                                 goto md_failed;
2181                         }
2182                         break;
2183                 case QLA82XX_BOARD:
2184                 case QLA82XX_RDROM:
2185                         qla4_8xxx_minidump_process_rdrom(ha, entry_hdr,
2186                                                          &data_ptr);
2187                         break;
2188                 case QLA82XX_L2DTG:
2189                 case QLA82XX_L2ITG:
2190                 case QLA82XX_L2DAT:
2191                 case QLA82XX_L2INS:
2192                         rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
2193                                                                 &data_ptr);
2194                         if (rval != QLA_SUCCESS) {
2195                                 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2196                                 goto md_failed;
2197                         }
2198                         break;
2199                 case QLA82XX_L1DAT:
2200                 case QLA82XX_L1INS:
2201                         qla4_8xxx_minidump_process_l1cache(ha, entry_hdr,
2202                                                            &data_ptr);
2203                         break;
2204                 case QLA82XX_RDOCM:
2205                         qla4_8xxx_minidump_process_rdocm(ha, entry_hdr,
2206                                                          &data_ptr);
2207                         break;
2208                 case QLA82XX_RDMUX:
2209                         qla4_8xxx_minidump_process_rdmux(ha, entry_hdr,
2210                                                          &data_ptr);
2211                         break;
2212                 case QLA82XX_QUEUE:
2213                         qla4_8xxx_minidump_process_queue(ha, entry_hdr,
2214                                                          &data_ptr);
2215                         break;
2216                 case QLA82XX_RDNOP:
2217                 default:
2218                         ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2219                         break;
2220                 }
2221
2222                 data_collected = (uint8_t *)data_ptr -
2223                                  ((uint8_t *)((uint8_t *)ha->fw_dump +
2224                                                 ha->fw_dump_tmplt_size));
2225 skip_nxt_entry:
2226                 /*  next entry in the template */
2227                 entry_hdr = (struct qla82xx_minidump_entry_hdr *)
2228                                 (((uint8_t *)entry_hdr) +
2229                                  entry_hdr->entry_size);
2230         }
2231
2232         if ((data_collected + ha->fw_dump_tmplt_size) != ha->fw_dump_size) {
2233                 ql4_printk(KERN_INFO, ha,
2234                            "Dump data mismatch: Data collected: [0x%x], total_data_size:[0x%x]\n",
2235                            data_collected, ha->fw_dump_size);
2236                 goto md_failed;
2237         }
2238
2239         DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s Last entry: 0x%x\n",
2240                           __func__, i));
2241 md_failed:
2242         return rval;
2243 }
2244
2245 /**
2246  * qla4_8xxx_uevent_emit - Send uevent when the firmware dump is ready.
2247  * @ha: pointer to adapter structure
2248  **/
2249 static void qla4_8xxx_uevent_emit(struct scsi_qla_host *ha, u32 code)
2250 {
2251         char event_string[40];
2252         char *envp[] = { event_string, NULL };
2253
2254         switch (code) {
2255         case QL4_UEVENT_CODE_FW_DUMP:
2256                 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
2257                          ha->host_no);
2258                 break;
2259         default:
2260                 /*do nothing*/
2261                 break;
2262         }
2263
2264         kobject_uevent_env(&(&ha->pdev->dev)->kobj, KOBJ_CHANGE, envp);
2265 }
2266
2267 /**
2268  * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw
2269  * @ha: pointer to adapter structure
2270  *
2271  * Note: IDC lock must be held upon entry
2272  **/
2273 static int
2274 qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha)
2275 {
2276         int rval = QLA_ERROR;
2277         int i, timeout;
2278         uint32_t old_count, count;
2279         int need_reset = 0, peg_stuck = 1;
2280
2281         need_reset = qla4_8xxx_need_reset(ha);
2282
2283         old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2284
2285         for (i = 0; i < 10; i++) {
2286                 timeout = msleep_interruptible(200);
2287                 if (timeout) {
2288                         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2289                            QLA82XX_DEV_FAILED);
2290                         return rval;
2291                 }
2292
2293                 count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2294                 if (count != old_count)
2295                         peg_stuck = 0;
2296         }
2297
2298         if (need_reset) {
2299                 /* We are trying to perform a recovery here. */
2300                 if (peg_stuck)
2301                         qla4_8xxx_rom_lock_recovery(ha);
2302                 goto dev_initialize;
2303         } else  {
2304                 /* Start of day for this ha context. */
2305                 if (peg_stuck) {
2306                         /* Either we are the first or recovery in progress. */
2307                         qla4_8xxx_rom_lock_recovery(ha);
2308                         goto dev_initialize;
2309                 } else {
2310                         /* Firmware already running. */
2311                         rval = QLA_SUCCESS;
2312                         goto dev_ready;
2313                 }
2314         }
2315
2316 dev_initialize:
2317         /* set to DEV_INITIALIZING */
2318         ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
2319         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
2320
2321         /* Driver that sets device state to initializating sets IDC version */
2322         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
2323
2324         qla4_8xxx_idc_unlock(ha);
2325         if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
2326             !test_and_set_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
2327                 if (!qla4_8xxx_collect_md_data(ha)) {
2328                         qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
2329                 } else {
2330                         ql4_printk(KERN_INFO, ha, "Unable to collect minidump\n");
2331                         clear_bit(AF_82XX_FW_DUMPED, &ha->flags);
2332                 }
2333         }
2334         rval = qla4_8xxx_try_start_fw(ha);
2335         qla4_8xxx_idc_lock(ha);
2336
2337         if (rval != QLA_SUCCESS) {
2338                 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
2339                 qla4_8xxx_clear_drv_active(ha);
2340                 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
2341                 return rval;
2342         }
2343
2344 dev_ready:
2345         ql4_printk(KERN_INFO, ha, "HW State: READY\n");
2346         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
2347
2348         return rval;
2349 }
2350
2351 /**
2352  * qla4_8xxx_need_reset_handler - Code to start reset sequence
2353  * @ha: pointer to adapter structure
2354  *
2355  * Note: IDC lock must be held upon entry
2356  **/
2357 static void
2358 qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha)
2359 {
2360         uint32_t dev_state, drv_state, drv_active;
2361         uint32_t active_mask = 0xFFFFFFFF;
2362         unsigned long reset_timeout;
2363
2364         ql4_printk(KERN_INFO, ha,
2365                 "Performing ISP error recovery\n");
2366
2367         if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
2368                 qla4_8xxx_idc_unlock(ha);
2369                 ha->isp_ops->disable_intrs(ha);
2370                 qla4_8xxx_idc_lock(ha);
2371         }
2372
2373         if (!test_bit(AF_82XX_RST_OWNER, &ha->flags)) {
2374                 DEBUG2(ql4_printk(KERN_INFO, ha,
2375                                   "%s(%ld): reset acknowledged\n",
2376                                   __func__, ha->host_no));
2377                 qla4_8xxx_set_rst_ready(ha);
2378         } else {
2379                 active_mask = (~(1 << (ha->func_num * 4)));
2380         }
2381
2382         /* wait for 10 seconds for reset ack from all functions */
2383         reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
2384
2385         drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2386         drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2387
2388         ql4_printk(KERN_INFO, ha,
2389                 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2390                 __func__, ha->host_no, drv_state, drv_active);
2391
2392         while (drv_state != (drv_active & active_mask)) {
2393                 if (time_after_eq(jiffies, reset_timeout)) {
2394                         ql4_printk(KERN_INFO, ha,
2395                                    "%s: RESET TIMEOUT! drv_state: 0x%08x, drv_active: 0x%08x\n",
2396                                    DRIVER_NAME, drv_state, drv_active);
2397                         break;
2398                 }
2399
2400                 /*
2401                  * When reset_owner times out, check which functions
2402                  * acked/did not ack
2403                  */
2404                 if (test_bit(AF_82XX_RST_OWNER, &ha->flags)) {
2405                         ql4_printk(KERN_INFO, ha,
2406                                    "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2407                                    __func__, ha->host_no, drv_state,
2408                                    drv_active);
2409                 }
2410                 qla4_8xxx_idc_unlock(ha);
2411                 msleep(1000);
2412                 qla4_8xxx_idc_lock(ha);
2413
2414                 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2415                 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2416         }
2417
2418         /* Clear RESET OWNER as we are not going to use it any further */
2419         clear_bit(AF_82XX_RST_OWNER, &ha->flags);
2420
2421         dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2422         ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
2423                    dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
2424
2425         /* Force to DEV_COLD unless someone else is starting a reset */
2426         if (dev_state != QLA82XX_DEV_INITIALIZING) {
2427                 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
2428                 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
2429                 qla4_8xxx_set_rst_ready(ha);
2430         }
2431 }
2432
2433 /**
2434  * qla4_8xxx_need_qsnt_handler - Code to start qsnt
2435  * @ha: pointer to adapter structure
2436  **/
2437 void
2438 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
2439 {
2440         qla4_8xxx_idc_lock(ha);
2441         qla4_8xxx_set_qsnt_ready(ha);
2442         qla4_8xxx_idc_unlock(ha);
2443 }
2444
2445 /**
2446  * qla4_8xxx_device_state_handler - Adapter state machine
2447  * @ha: pointer to host adapter structure.
2448  *
2449  * Note: IDC lock must be UNLOCKED upon entry
2450  **/
2451 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2452 {
2453         uint32_t dev_state;
2454         int rval = QLA_SUCCESS;
2455         unsigned long dev_init_timeout;
2456
2457         if (!test_bit(AF_INIT_DONE, &ha->flags)) {
2458                 qla4_8xxx_idc_lock(ha);
2459                 qla4_8xxx_set_drv_active(ha);
2460                 qla4_8xxx_idc_unlock(ha);
2461         }
2462
2463         dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2464         DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2465                           dev_state, dev_state < MAX_STATES ?
2466                           qdev_state[dev_state] : "Unknown"));
2467
2468         /* wait for 30 seconds for device to go ready */
2469         dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
2470
2471         qla4_8xxx_idc_lock(ha);
2472         while (1) {
2473
2474                 if (time_after_eq(jiffies, dev_init_timeout)) {
2475                         ql4_printk(KERN_WARNING, ha,
2476                                    "%s: Device Init Failed 0x%x = %s\n",
2477                                    DRIVER_NAME,
2478                                    dev_state, dev_state < MAX_STATES ?
2479                                    qdev_state[dev_state] : "Unknown");
2480                         qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2481                                 QLA82XX_DEV_FAILED);
2482                 }
2483
2484                 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2485                 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2486                            dev_state, dev_state < MAX_STATES ?
2487                            qdev_state[dev_state] : "Unknown");
2488
2489                 /* NOTE: Make sure idc unlocked upon exit of switch statement */
2490                 switch (dev_state) {
2491                 case QLA82XX_DEV_READY:
2492                         goto exit;
2493                 case QLA82XX_DEV_COLD:
2494                         rval = qla4_8xxx_device_bootstrap(ha);
2495                         goto exit;
2496                 case QLA82XX_DEV_INITIALIZING:
2497                         qla4_8xxx_idc_unlock(ha);
2498                         msleep(1000);
2499                         qla4_8xxx_idc_lock(ha);
2500                         break;
2501                 case QLA82XX_DEV_NEED_RESET:
2502                         if (!ql4xdontresethba) {
2503                                 qla4_8xxx_need_reset_handler(ha);
2504                                 /* Update timeout value after need
2505                                  * reset handler */
2506                                 dev_init_timeout = jiffies +
2507                                         (ha->nx_dev_init_timeout * HZ);
2508                         } else {
2509                                 qla4_8xxx_idc_unlock(ha);
2510                                 msleep(1000);
2511                                 qla4_8xxx_idc_lock(ha);
2512                         }
2513                         break;
2514                 case QLA82XX_DEV_NEED_QUIESCENT:
2515                         /* idc locked/unlocked in handler */
2516                         qla4_8xxx_need_qsnt_handler(ha);
2517                         break;
2518                 case QLA82XX_DEV_QUIESCENT:
2519                         qla4_8xxx_idc_unlock(ha);
2520                         msleep(1000);
2521                         qla4_8xxx_idc_lock(ha);
2522                         break;
2523                 case QLA82XX_DEV_FAILED:
2524                         qla4_8xxx_idc_unlock(ha);
2525                         qla4xxx_dead_adapter_cleanup(ha);
2526                         rval = QLA_ERROR;
2527                         qla4_8xxx_idc_lock(ha);
2528                         goto exit;
2529                 default:
2530                         qla4_8xxx_idc_unlock(ha);
2531                         qla4xxx_dead_adapter_cleanup(ha);
2532                         rval = QLA_ERROR;
2533                         qla4_8xxx_idc_lock(ha);
2534                         goto exit;
2535                 }
2536         }
2537 exit:
2538         qla4_8xxx_idc_unlock(ha);
2539         return rval;
2540 }
2541
2542 int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
2543 {
2544         int retval;
2545
2546         /* clear the interrupt */
2547         writel(0, &ha->qla4_8xxx_reg->host_int);
2548         readl(&ha->qla4_8xxx_reg->host_int);
2549
2550         retval = qla4_8xxx_device_state_handler(ha);
2551
2552         if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags))
2553                 retval = qla4xxx_request_irqs(ha);
2554
2555         return retval;
2556 }
2557
2558 /*****************************************************************************/
2559 /* Flash Manipulation Routines                                               */
2560 /*****************************************************************************/
2561
2562 #define OPTROM_BURST_SIZE       0x1000
2563 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
2564
2565 #define FARX_DATA_FLAG  BIT_31
2566 #define FARX_ACCESS_FLASH_CONF  0x7FFD0000
2567 #define FARX_ACCESS_FLASH_DATA  0x7FF00000
2568
2569 static inline uint32_t
2570 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
2571 {
2572         return hw->flash_conf_off | faddr;
2573 }
2574
2575 static inline uint32_t
2576 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
2577 {
2578         return hw->flash_data_off | faddr;
2579 }
2580
2581 static uint32_t *
2582 qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
2583     uint32_t faddr, uint32_t length)
2584 {
2585         uint32_t i;
2586         uint32_t val;
2587         int loops = 0;
2588         while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
2589                 udelay(100);
2590                 cond_resched();
2591                 loops++;
2592         }
2593         if (loops >= 50000) {
2594                 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
2595                 return dwptr;
2596         }
2597
2598         /* Dword reads to flash. */
2599         for (i = 0; i < length/4; i++, faddr += 4) {
2600                 if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) {
2601                         ql4_printk(KERN_WARNING, ha,
2602                             "Do ROM fast read failed\n");
2603                         goto done_read;
2604                 }
2605                 dwptr[i] = __constant_cpu_to_le32(val);
2606         }
2607
2608 done_read:
2609         qla4_8xxx_rom_unlock(ha);
2610         return dwptr;
2611 }
2612
2613 /**
2614  * Address and length are byte address
2615  **/
2616 static uint8_t *
2617 qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
2618                 uint32_t offset, uint32_t length)
2619 {
2620         qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length);
2621         return buf;
2622 }
2623
2624 static int
2625 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
2626 {
2627         const char *loc, *locations[] = { "DEF", "PCI" };
2628
2629         /*
2630          * FLT-location structure resides after the last PCI region.
2631          */
2632
2633         /* Begin with sane defaults. */
2634         loc = locations[0];
2635         *start = FA_FLASH_LAYOUT_ADDR_82;
2636
2637         DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
2638         return QLA_SUCCESS;
2639 }
2640
2641 static void
2642 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr)
2643 {
2644         const char *loc, *locations[] = { "DEF", "FLT" };
2645         uint16_t *wptr;
2646         uint16_t cnt, chksum;
2647         uint32_t start;
2648         struct qla_flt_header *flt;
2649         struct qla_flt_region *region;
2650         struct ql82xx_hw_data *hw = &ha->hw;
2651
2652         hw->flt_region_flt = flt_addr;
2653         wptr = (uint16_t *)ha->request_ring;
2654         flt = (struct qla_flt_header *)ha->request_ring;
2655         region = (struct qla_flt_region *)&flt[1];
2656         qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2657                         flt_addr << 2, OPTROM_BURST_SIZE);
2658         if (*wptr == __constant_cpu_to_le16(0xffff))
2659                 goto no_flash_data;
2660         if (flt->version != __constant_cpu_to_le16(1)) {
2661                 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
2662                         "version=0x%x length=0x%x checksum=0x%x.\n",
2663                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
2664                         le16_to_cpu(flt->checksum)));
2665                 goto no_flash_data;
2666         }
2667
2668         cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
2669         for (chksum = 0; cnt; cnt--)
2670                 chksum += le16_to_cpu(*wptr++);
2671         if (chksum) {
2672                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
2673                         "version=0x%x length=0x%x checksum=0x%x.\n",
2674                         le16_to_cpu(flt->version), le16_to_cpu(flt->length),
2675                         chksum));
2676                 goto no_flash_data;
2677         }
2678
2679         loc = locations[1];
2680         cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
2681         for ( ; cnt; cnt--, region++) {
2682                 /* Store addresses as DWORD offsets. */
2683                 start = le32_to_cpu(region->start) >> 2;
2684
2685                 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
2686                     "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
2687                     le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
2688
2689                 switch (le32_to_cpu(region->code) & 0xff) {
2690                 case FLT_REG_FDT:
2691                         hw->flt_region_fdt = start;
2692                         break;
2693                 case FLT_REG_BOOT_CODE_82:
2694                         hw->flt_region_boot = start;
2695                         break;
2696                 case FLT_REG_FW_82:
2697                 case FLT_REG_FW_82_1:
2698                         hw->flt_region_fw = start;
2699                         break;
2700                 case FLT_REG_BOOTLOAD_82:
2701                         hw->flt_region_bootload = start;
2702                         break;
2703                 case FLT_REG_ISCSI_PARAM:
2704                         hw->flt_iscsi_param =  start;
2705                         break;
2706                 case FLT_REG_ISCSI_CHAP:
2707                         hw->flt_region_chap =  start;
2708                         hw->flt_chap_size =  le32_to_cpu(region->size);
2709                         break;
2710                 }
2711         }
2712         goto done;
2713
2714 no_flash_data:
2715         /* Use hardcoded defaults. */
2716         loc = locations[0];
2717
2718         hw->flt_region_fdt      = FA_FLASH_DESCR_ADDR_82;
2719         hw->flt_region_boot     = FA_BOOT_CODE_ADDR_82;
2720         hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82;
2721         hw->flt_region_fw       = FA_RISC_CODE_ADDR_82;
2722         hw->flt_region_chap     = FA_FLASH_ISCSI_CHAP;
2723         hw->flt_chap_size       = FA_FLASH_CHAP_SIZE;
2724
2725 done:
2726         DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x "
2727             "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt,
2728             hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload,
2729             hw->flt_region_fw));
2730 }
2731
2732 static void
2733 qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha)
2734 {
2735 #define FLASH_BLK_SIZE_4K       0x1000
2736 #define FLASH_BLK_SIZE_32K      0x8000
2737 #define FLASH_BLK_SIZE_64K      0x10000
2738         const char *loc, *locations[] = { "MID", "FDT" };
2739         uint16_t cnt, chksum;
2740         uint16_t *wptr;
2741         struct qla_fdt_layout *fdt;
2742         uint16_t mid = 0;
2743         uint16_t fid = 0;
2744         struct ql82xx_hw_data *hw = &ha->hw;
2745
2746         hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2747         hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
2748
2749         wptr = (uint16_t *)ha->request_ring;
2750         fdt = (struct qla_fdt_layout *)ha->request_ring;
2751         qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2752             hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
2753
2754         if (*wptr == __constant_cpu_to_le16(0xffff))
2755                 goto no_flash_data;
2756
2757         if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
2758             fdt->sig[3] != 'D')
2759                 goto no_flash_data;
2760
2761         for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
2762             cnt++)
2763                 chksum += le16_to_cpu(*wptr++);
2764
2765         if (chksum) {
2766                 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
2767                     "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
2768                     le16_to_cpu(fdt->version)));
2769                 goto no_flash_data;
2770         }
2771
2772         loc = locations[1];
2773         mid = le16_to_cpu(fdt->man_id);
2774         fid = le16_to_cpu(fdt->id);
2775         hw->fdt_wrt_disable = fdt->wrt_disable_bits;
2776         hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd);
2777         hw->fdt_block_size = le32_to_cpu(fdt->block_size);
2778
2779         if (fdt->unprotect_sec_cmd) {
2780                 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 |
2781                     fdt->unprotect_sec_cmd);
2782                 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
2783                     flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) :
2784                     flash_conf_addr(hw, 0x0336);
2785         }
2786         goto done;
2787
2788 no_flash_data:
2789         loc = locations[0];
2790         hw->fdt_block_size = FLASH_BLK_SIZE_64K;
2791 done:
2792         DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
2793                 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
2794                 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
2795                 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
2796                 hw->fdt_block_size));
2797 }
2798
2799 static void
2800 qla4_8xxx_get_idc_param(struct scsi_qla_host *ha)
2801 {
2802 #define QLA82XX_IDC_PARAM_ADDR      0x003e885c
2803         uint32_t *wptr;
2804
2805         if (!is_qla8022(ha))
2806                 return;
2807         wptr = (uint32_t *)ha->request_ring;
2808         qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2809                         QLA82XX_IDC_PARAM_ADDR , 8);
2810
2811         if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
2812                 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
2813                 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
2814         } else {
2815                 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
2816                 ha->nx_reset_timeout = le32_to_cpu(*wptr);
2817         }
2818
2819         DEBUG2(ql4_printk(KERN_DEBUG, ha,
2820                 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout));
2821         DEBUG2(ql4_printk(KERN_DEBUG, ha,
2822                 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout));
2823         return;
2824 }
2825
2826 int
2827 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha)
2828 {
2829         int ret;
2830         uint32_t flt_addr;
2831
2832         ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
2833         if (ret != QLA_SUCCESS)
2834                 return ret;
2835
2836         qla4_8xxx_get_flt_info(ha, flt_addr);
2837         qla4_8xxx_get_fdt_info(ha);
2838         qla4_8xxx_get_idc_param(ha);
2839
2840         return QLA_SUCCESS;
2841 }
2842
2843 /**
2844  * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
2845  * @ha: pointer to host adapter structure.
2846  *
2847  * Remarks:
2848  * For iSCSI, throws away all I/O and AENs into bit bucket, so they will
2849  * not be available after successful return.  Driver must cleanup potential
2850  * outstanding I/O's after calling this funcion.
2851  **/
2852 int
2853 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha)
2854 {
2855         int status;
2856         uint32_t mbox_cmd[MBOX_REG_COUNT];
2857         uint32_t mbox_sts[MBOX_REG_COUNT];
2858
2859         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2860         memset(&mbox_sts, 0, sizeof(mbox_sts));
2861
2862         mbox_cmd[0] = MBOX_CMD_STOP_FW;
2863         status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1,
2864             &mbox_cmd[0], &mbox_sts[0]);
2865
2866         DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
2867             __func__, status));
2868         return status;
2869 }
2870
2871 /**
2872  * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands.
2873  * @ha: pointer to host adapter structure.
2874  **/
2875 int
2876 qla4_8xxx_isp_reset(struct scsi_qla_host *ha)
2877 {
2878         int rval;
2879         uint32_t dev_state;
2880
2881         qla4_8xxx_idc_lock(ha);
2882         dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2883
2884         if (dev_state == QLA82XX_DEV_READY) {
2885                 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
2886                 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2887                     QLA82XX_DEV_NEED_RESET);
2888                 set_bit(AF_82XX_RST_OWNER, &ha->flags);
2889         } else
2890                 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
2891
2892         qla4_8xxx_idc_unlock(ha);
2893
2894         rval = qla4_8xxx_device_state_handler(ha);
2895
2896         qla4_8xxx_idc_lock(ha);
2897         qla4_8xxx_clear_rst_ready(ha);
2898         qla4_8xxx_idc_unlock(ha);
2899
2900         if (rval == QLA_SUCCESS) {
2901                 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_8xxx_isp_reset\n");
2902                 clear_bit(AF_FW_RECOVERY, &ha->flags);
2903         }
2904
2905         return rval;
2906 }
2907
2908 /**
2909  * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number
2910  * @ha: pointer to host adapter structure.
2911  *
2912  **/
2913 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
2914 {
2915         uint32_t mbox_cmd[MBOX_REG_COUNT];
2916         uint32_t mbox_sts[MBOX_REG_COUNT];
2917         struct mbx_sys_info *sys_info;
2918         dma_addr_t sys_info_dma;
2919         int status = QLA_ERROR;
2920
2921         sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info),
2922                                       &sys_info_dma, GFP_KERNEL);
2923         if (sys_info == NULL) {
2924                 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n",
2925                     ha->host_no, __func__));
2926                 return status;
2927         }
2928
2929         memset(sys_info, 0, sizeof(*sys_info));
2930         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2931         memset(&mbox_sts, 0, sizeof(mbox_sts));
2932
2933         mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO;
2934         mbox_cmd[1] = LSDW(sys_info_dma);
2935         mbox_cmd[2] = MSDW(sys_info_dma);
2936         mbox_cmd[4] = sizeof(*sys_info);
2937
2938         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0],
2939             &mbox_sts[0]) != QLA_SUCCESS) {
2940                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n",
2941                     ha->host_no, __func__));
2942                 goto exit_validate_mac82;
2943         }
2944
2945         /* Make sure we receive the minimum required data to cache internally */
2946         if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) {
2947                 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive"
2948                     " error (%x)\n", ha->host_no, __func__, mbox_sts[4]));
2949                 goto exit_validate_mac82;
2950
2951         }
2952
2953         /* Save M.A.C. address & serial_number */
2954         ha->port_num = sys_info->port_num;
2955         memcpy(ha->my_mac, &sys_info->mac_addr[0],
2956             min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr)));
2957         memcpy(ha->serial_number, &sys_info->serial_number,
2958             min(sizeof(ha->serial_number), sizeof(sys_info->serial_number)));
2959         memcpy(ha->model_name, &sys_info->board_id_str,
2960                min(sizeof(ha->model_name), sizeof(sys_info->board_id_str)));
2961         ha->phy_port_cnt = sys_info->phys_port_cnt;
2962         ha->phy_port_num = sys_info->port_num;
2963         ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt;
2964
2965         DEBUG2(printk("scsi%ld: %s: "
2966             "mac %02x:%02x:%02x:%02x:%02x:%02x "
2967             "serial %s\n", ha->host_no, __func__,
2968             ha->my_mac[0], ha->my_mac[1], ha->my_mac[2],
2969             ha->my_mac[3], ha->my_mac[4], ha->my_mac[5],
2970             ha->serial_number));
2971
2972         status = QLA_SUCCESS;
2973
2974 exit_validate_mac82:
2975         dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info,
2976                           sys_info_dma);
2977         return status;
2978 }
2979
2980 /* Interrupt handling helpers. */
2981
2982 static int
2983 qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
2984 {
2985         uint32_t mbox_cmd[MBOX_REG_COUNT];
2986         uint32_t mbox_sts[MBOX_REG_COUNT];
2987
2988         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
2989
2990         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2991         memset(&mbox_sts, 0, sizeof(mbox_sts));
2992         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
2993         mbox_cmd[1] = INTR_ENABLE;
2994         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2995                 &mbox_sts[0]) != QLA_SUCCESS) {
2996                 DEBUG2(ql4_printk(KERN_INFO, ha,
2997                     "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
2998                     __func__, mbox_sts[0]));
2999                 return QLA_ERROR;
3000         }
3001         return QLA_SUCCESS;
3002 }
3003
3004 static int
3005 qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
3006 {
3007         uint32_t mbox_cmd[MBOX_REG_COUNT];
3008         uint32_t mbox_sts[MBOX_REG_COUNT];
3009
3010         DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__));
3011
3012         memset(&mbox_cmd, 0, sizeof(mbox_cmd));
3013         memset(&mbox_sts, 0, sizeof(mbox_sts));
3014         mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS;
3015         mbox_cmd[1] = INTR_DISABLE;
3016         if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
3017             &mbox_sts[0]) != QLA_SUCCESS) {
3018                 DEBUG2(ql4_printk(KERN_INFO, ha,
3019                         "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n",
3020                         __func__, mbox_sts[0]));
3021                 return QLA_ERROR;
3022         }
3023
3024         return QLA_SUCCESS;
3025 }
3026
3027 void
3028 qla4_8xxx_enable_intrs(struct scsi_qla_host *ha)
3029 {
3030         qla4_8xxx_mbx_intr_enable(ha);
3031
3032         spin_lock_irq(&ha->hardware_lock);
3033         /* BIT 10 - reset */
3034         qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
3035         spin_unlock_irq(&ha->hardware_lock);
3036         set_bit(AF_INTERRUPTS_ON, &ha->flags);
3037 }
3038
3039 void
3040 qla4_8xxx_disable_intrs(struct scsi_qla_host *ha)
3041 {
3042         if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
3043                 qla4_8xxx_mbx_intr_disable(ha);
3044
3045         spin_lock_irq(&ha->hardware_lock);
3046         /* BIT 10 - set */
3047         qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
3048         spin_unlock_irq(&ha->hardware_lock);
3049 }
3050
3051 struct ql4_init_msix_entry {
3052         uint16_t entry;
3053         uint16_t index;
3054         const char *name;
3055         irq_handler_t handler;
3056 };
3057
3058 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = {
3059         { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT,
3060             "qla4xxx (default)",
3061             (irq_handler_t)qla4_8xxx_default_intr_handler },
3062         { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q,
3063             "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q },
3064 };
3065
3066 void
3067 qla4_8xxx_disable_msix(struct scsi_qla_host *ha)
3068 {
3069         int i;
3070         struct ql4_msix_entry *qentry;
3071
3072         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3073                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3074                 if (qentry->have_irq) {
3075                         free_irq(qentry->msix_vector, ha);
3076                         DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3077                                 __func__, qla4_8xxx_msix_entries[i].name));
3078                 }
3079         }
3080         pci_disable_msix(ha->pdev);
3081         clear_bit(AF_MSIX_ENABLED, &ha->flags);
3082 }
3083
3084 int
3085 qla4_8xxx_enable_msix(struct scsi_qla_host *ha)
3086 {
3087         int i, ret;
3088         struct msix_entry entries[QLA_MSIX_ENTRIES];
3089         struct ql4_msix_entry *qentry;
3090
3091         for (i = 0; i < QLA_MSIX_ENTRIES; i++)
3092                 entries[i].entry = qla4_8xxx_msix_entries[i].entry;
3093
3094         ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries));
3095         if (ret) {
3096                 ql4_printk(KERN_WARNING, ha,
3097                     "MSI-X: Failed to enable support -- %d/%d\n",
3098                     QLA_MSIX_ENTRIES, ret);
3099                 goto msix_out;
3100         }
3101         set_bit(AF_MSIX_ENABLED, &ha->flags);
3102
3103         for (i = 0; i < QLA_MSIX_ENTRIES; i++) {
3104                 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index];
3105                 qentry->msix_vector = entries[i].vector;
3106                 qentry->msix_entry = entries[i].entry;
3107                 qentry->have_irq = 0;
3108                 ret = request_irq(qentry->msix_vector,
3109                     qla4_8xxx_msix_entries[i].handler, 0,
3110                     qla4_8xxx_msix_entries[i].name, ha);
3111                 if (ret) {
3112                         ql4_printk(KERN_WARNING, ha,
3113                             "MSI-X: Unable to register handler -- %x/%d.\n",
3114                             qla4_8xxx_msix_entries[i].index, ret);
3115                         qla4_8xxx_disable_msix(ha);
3116                         goto msix_out;
3117                 }
3118                 qentry->have_irq = 1;
3119                 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n",
3120                         __func__, qla4_8xxx_msix_entries[i].name));
3121         }
3122 msix_out:
3123         return ret;
3124 }