2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <linux/blk-mq-pci.h>
17 #include <linux/refcount.h>
19 #include <scsi/scsi_tcq.h>
20 #include <scsi/scsicam.h>
21 #include <scsi/scsi_transport.h>
22 #include <scsi/scsi_transport_fc.h>
24 #include "qla_target.h"
29 char qla2x00_version_str[40];
31 static int apidev_major;
34 * SRB allocation cache
36 struct kmem_cache *srb_cachep;
39 * CT6 CTX allocation cache
41 static struct kmem_cache *ctx_cachep;
43 * error level for logging
45 uint ql_errlev = 0x8001;
47 static int ql2xenableclass2;
48 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
49 MODULE_PARM_DESC(ql2xenableclass2,
50 "Specify if Class 2 operations are supported from the very "
51 "beginning. Default is 0 - class 2 not supported.");
54 int ql2xlogintimeout = 20;
55 module_param(ql2xlogintimeout, int, S_IRUGO);
56 MODULE_PARM_DESC(ql2xlogintimeout,
57 "Login timeout value in seconds.");
59 int qlport_down_retry;
60 module_param(qlport_down_retry, int, S_IRUGO);
61 MODULE_PARM_DESC(qlport_down_retry,
62 "Maximum number of command retries to a port that returns "
63 "a PORT-DOWN status.");
65 int ql2xplogiabsentdevice;
66 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
67 MODULE_PARM_DESC(ql2xplogiabsentdevice,
68 "Option to enable PLOGI to devices that are not present after "
69 "a Fabric scan. This is needed for several broken switches. "
70 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
72 int ql2xloginretrycount;
73 module_param(ql2xloginretrycount, int, S_IRUGO);
74 MODULE_PARM_DESC(ql2xloginretrycount,
75 "Specify an alternate value for the NVRAM login retry count.");
77 int ql2xallocfwdump = 1;
78 module_param(ql2xallocfwdump, int, S_IRUGO);
79 MODULE_PARM_DESC(ql2xallocfwdump,
80 "Option to enable allocation of memory for a firmware dump "
81 "during HBA initialization. Memory allocation requirements "
82 "vary by ISP type. Default is 1 - allocate memory.");
84 int ql2xextended_error_logging;
85 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
86 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
87 MODULE_PARM_DESC(ql2xextended_error_logging,
88 "Option to enable extended error logging,\n"
89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
100 "\t\t0x1e400000 - Preferred value for capturing essential "
101 "debug information (equivalent to old "
102 "ql2xextended_error_logging=1).\n"
103 "\t\tDo LOGICAL OR of the value to enable more than one level");
105 int ql2xshiftctondsd = 6;
106 module_param(ql2xshiftctondsd, int, S_IRUGO);
107 MODULE_PARM_DESC(ql2xshiftctondsd,
108 "Set to control shifting of command type processing "
109 "based on total number of SG elements.");
111 int ql2xfdmienable = 1;
112 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
113 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
114 MODULE_PARM_DESC(ql2xfdmienable,
115 "Enables FDMI registrations. "
116 "0 - no FDMI. Default is 1 - perform FDMI.");
118 #define MAX_Q_DEPTH 64
119 static int ql2xmaxqdepth = MAX_Q_DEPTH;
120 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
121 MODULE_PARM_DESC(ql2xmaxqdepth,
122 "Maximum queue depth to set for each LUN. "
125 #if (IS_ENABLED(CONFIG_NVME_FC))
128 int ql2xenabledif = 2;
130 module_param(ql2xenabledif, int, S_IRUGO);
131 MODULE_PARM_DESC(ql2xenabledif,
132 " Enable T10-CRC-DIF:\n"
134 " 0 -- No DIF Support\n"
135 " 1 -- Enable DIF for all types\n"
136 " 2 -- Enable DIF for all types, except Type 0.\n");
138 #if (IS_ENABLED(CONFIG_NVME_FC))
139 int ql2xnvmeenable = 1;
143 module_param(ql2xnvmeenable, int, 0644);
144 MODULE_PARM_DESC(ql2xnvmeenable,
145 "Enables NVME support. "
146 "0 - no NVMe. Default is Y");
148 int ql2xenablehba_err_chk = 2;
149 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
150 MODULE_PARM_DESC(ql2xenablehba_err_chk,
151 " Enable T10-CRC-DIF Error isolation by HBA:\n"
153 " 0 -- Error isolation disabled\n"
154 " 1 -- Error isolation enabled only for DIX Type 0\n"
155 " 2 -- Error isolation enabled for all Types\n");
157 int ql2xiidmaenable = 1;
158 module_param(ql2xiidmaenable, int, S_IRUGO);
159 MODULE_PARM_DESC(ql2xiidmaenable,
160 "Enables iIDMA settings "
161 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
163 int ql2xmqsupport = 1;
164 module_param(ql2xmqsupport, int, S_IRUGO);
165 MODULE_PARM_DESC(ql2xmqsupport,
166 "Enable on demand multiple queue pairs support "
167 "Default is 1 for supported. "
168 "Set it to 0 to turn off mq qpair support.");
171 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
172 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
173 MODULE_PARM_DESC(ql2xfwloadbin,
174 "Option to specify location from which to load ISP firmware:.\n"
175 " 2 -- load firmware via the request_firmware() (hotplug).\n"
177 " 1 -- load firmware from flash.\n"
178 " 0 -- use default semantics.\n");
181 module_param(ql2xetsenable, int, S_IRUGO);
182 MODULE_PARM_DESC(ql2xetsenable,
183 "Enables firmware ETS burst."
184 "Default is 0 - skip ETS enablement.");
187 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
188 MODULE_PARM_DESC(ql2xdbwr,
189 "Option to specify scheme for request queue posting.\n"
190 " 0 -- Regular doorbell.\n"
191 " 1 -- CAMRAM doorbell (faster).\n");
193 int ql2xtargetreset = 1;
194 module_param(ql2xtargetreset, int, S_IRUGO);
195 MODULE_PARM_DESC(ql2xtargetreset,
196 "Enable target reset."
197 "Default is 1 - use hw defaults.");
200 module_param(ql2xgffidenable, int, S_IRUGO);
201 MODULE_PARM_DESC(ql2xgffidenable,
202 "Enables GFF_ID checks of port type. "
203 "Default is 0 - Do not use GFF_ID information.");
205 int ql2xasynctmfenable = 1;
206 module_param(ql2xasynctmfenable, int, S_IRUGO);
207 MODULE_PARM_DESC(ql2xasynctmfenable,
208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
209 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
211 int ql2xdontresethba;
212 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
213 MODULE_PARM_DESC(ql2xdontresethba,
214 "Option to specify reset behaviour.\n"
215 " 0 (Default) -- Reset on failure.\n"
216 " 1 -- Do not reset on failure.\n");
218 uint64_t ql2xmaxlun = MAX_LUNS;
219 module_param(ql2xmaxlun, ullong, S_IRUGO);
220 MODULE_PARM_DESC(ql2xmaxlun,
221 "Defines the maximum LU number to register with the SCSI "
222 "midlayer. Default is 65535.");
224 int ql2xmdcapmask = 0x1F;
225 module_param(ql2xmdcapmask, int, S_IRUGO);
226 MODULE_PARM_DESC(ql2xmdcapmask,
227 "Set the Minidump driver capture mask level. "
228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
230 int ql2xmdenable = 1;
231 module_param(ql2xmdenable, int, S_IRUGO);
232 MODULE_PARM_DESC(ql2xmdenable,
233 "Enable/disable MiniDump. "
234 "0 - MiniDump disabled. "
235 "1 (Default) - MiniDump enabled.");
238 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
239 MODULE_PARM_DESC(ql2xexlogins,
240 "Number of extended Logins. "
241 "0 (Default)- Disabled.");
243 int ql2xexchoffld = 1024;
244 module_param(ql2xexchoffld, uint, 0644);
245 MODULE_PARM_DESC(ql2xexchoffld,
246 "Number of target exchanges.");
248 int ql2xiniexchg = 1024;
249 module_param(ql2xiniexchg, uint, 0644);
250 MODULE_PARM_DESC(ql2xiniexchg,
251 "Number of initiator exchanges.");
254 module_param(ql2xfwholdabts, int, S_IRUGO);
255 MODULE_PARM_DESC(ql2xfwholdabts,
256 "Allow FW to hold status IOCB until ABTS rsp received. "
257 "0 (Default) Do not set fw option. "
258 "1 - Set fw option to hold ABTS.");
260 int ql2xmvasynctoatio = 1;
261 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
262 MODULE_PARM_DESC(ql2xmvasynctoatio,
263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
264 "0 (Default). Do not move IOCBs"
267 int ql2xautodetectsfp = 1;
268 module_param(ql2xautodetectsfp, int, 0444);
269 MODULE_PARM_DESC(ql2xautodetectsfp,
270 "Detect SFP range and set appropriate distance.\n"
271 "1 (Default): Enable\n");
273 int ql2xenablemsix = 1;
274 module_param(ql2xenablemsix, int, 0444);
275 MODULE_PARM_DESC(ql2xenablemsix,
276 "Set to enable MSI or MSI-X interrupt mechanism.\n"
277 " Default is 1, enable MSI-X interrupt mechanism.\n"
278 " 0 -- enable traditional pin-based mechanism.\n"
279 " 1 -- enable MSI-X interrupt mechanism.\n"
280 " 2 -- enable MSI interrupt mechanism.\n");
282 int qla2xuseresexchforels;
283 module_param(qla2xuseresexchforels, int, 0444);
284 MODULE_PARM_DESC(qla2xuseresexchforels,
285 "Reserve 1/2 of emergency exchanges for ELS.\n"
286 " 0 (default): disabled");
288 static int ql2xprotmask;
289 module_param(ql2xprotmask, int, 0644);
290 MODULE_PARM_DESC(ql2xprotmask,
291 "Override DIF/DIX protection capabilities mask\n"
292 "Default is 0 which sets protection mask based on "
293 "capabilities reported by HBA firmware.\n");
295 static int ql2xprotguard;
296 module_param(ql2xprotguard, int, 0644);
297 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
298 " 0 -- Let HBA firmware decide\n"
299 " 1 -- Force T10 CRC\n"
300 " 2 -- Force IP checksum\n");
302 int ql2xdifbundlinginternalbuffers;
303 module_param(ql2xdifbundlinginternalbuffers, int, 0644);
304 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
305 "Force using internal buffers for DIF information\n"
306 "0 (Default). Based on check.\n"
307 "1 Force using internal buffers\n");
309 static void qla2x00_clear_drv_active(struct qla_hw_data *);
310 static void qla2x00_free_device(scsi_qla_host_t *);
311 static int qla2xxx_map_queues(struct Scsi_Host *shost);
312 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
315 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
316 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
318 /* TODO Convert to inlines
324 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
326 timer_setup(&vha->timer, qla2x00_timer, 0);
327 vha->timer.expires = jiffies + interval * HZ;
328 add_timer(&vha->timer);
329 vha->timer_active = 1;
333 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
335 /* Currently used for 82XX only. */
336 if (vha->device_flags & DFLG_DEV_FAILED) {
337 ql_dbg(ql_dbg_timer, vha, 0x600d,
338 "Device in a failed state, returning.\n");
342 mod_timer(&vha->timer, jiffies + interval * HZ);
345 static __inline__ void
346 qla2x00_stop_timer(scsi_qla_host_t *vha)
348 del_timer_sync(&vha->timer);
349 vha->timer_active = 0;
352 static int qla2x00_do_dpc(void *data);
354 static void qla2x00_rst_aen(scsi_qla_host_t *);
356 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
357 struct req_que **, struct rsp_que **);
358 static void qla2x00_free_fw_dump(struct qla_hw_data *);
359 static void qla2x00_mem_free(struct qla_hw_data *);
360 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
361 struct qla_qpair *qpair);
363 /* -------------------------------------------------------------------------- */
364 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
367 struct qla_hw_data *ha = vha->hw;
369 rsp->qpair = ha->base_qpair;
371 ha->base_qpair->hw = ha;
372 ha->base_qpair->req = req;
373 ha->base_qpair->rsp = rsp;
374 ha->base_qpair->vha = vha;
375 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
376 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
377 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
378 ha->base_qpair->srb_mempool = ha->srb_mempool;
379 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
380 ha->base_qpair->enable_class_2 = ql2xenableclass2;
381 /* init qpair to this cpu. Will adjust at run time. */
382 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
383 ha->base_qpair->pdev = ha->pdev;
385 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
386 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
389 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
392 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
394 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
396 if (!ha->req_q_map) {
397 ql_log(ql_log_fatal, vha, 0x003b,
398 "Unable to allocate memory for request queue ptrs.\n");
402 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
404 if (!ha->rsp_q_map) {
405 ql_log(ql_log_fatal, vha, 0x003c,
406 "Unable to allocate memory for response queue ptrs.\n");
410 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
411 if (ha->base_qpair == NULL) {
412 ql_log(ql_log_warn, vha, 0x00e0,
413 "Failed to allocate base queue pair memory.\n");
414 goto fail_base_qpair;
417 qla_init_base_qpair(vha, req, rsp);
419 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
420 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
422 if (!ha->queue_pair_map) {
423 ql_log(ql_log_fatal, vha, 0x0180,
424 "Unable to allocate memory for queue pair ptrs.\n");
430 * Make sure we record at least the request and response queue zero in
431 * case we need to free them if part of the probe fails.
433 ha->rsp_q_map[0] = rsp;
434 ha->req_q_map[0] = req;
435 set_bit(0, ha->rsp_qid_map);
436 set_bit(0, ha->req_qid_map);
440 kfree(ha->base_qpair);
441 ha->base_qpair = NULL;
443 kfree(ha->rsp_q_map);
444 ha->rsp_q_map = NULL;
446 kfree(ha->req_q_map);
447 ha->req_q_map = NULL;
452 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
454 if (IS_QLAFX00(ha)) {
455 if (req && req->ring_fx00)
456 dma_free_coherent(&ha->pdev->dev,
457 (req->length_fx00 + 1) * sizeof(request_t),
458 req->ring_fx00, req->dma_fx00);
459 } else if (req && req->ring)
460 dma_free_coherent(&ha->pdev->dev,
461 (req->length + 1) * sizeof(request_t),
462 req->ring, req->dma);
465 kfree(req->outstanding_cmds);
470 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
472 if (IS_QLAFX00(ha)) {
473 if (rsp && rsp->ring_fx00)
474 dma_free_coherent(&ha->pdev->dev,
475 (rsp->length_fx00 + 1) * sizeof(request_t),
476 rsp->ring_fx00, rsp->dma_fx00);
477 } else if (rsp && rsp->ring) {
478 dma_free_coherent(&ha->pdev->dev,
479 (rsp->length + 1) * sizeof(response_t),
480 rsp->ring, rsp->dma);
485 static void qla2x00_free_queues(struct qla_hw_data *ha)
492 if (ha->queue_pair_map) {
493 kfree(ha->queue_pair_map);
494 ha->queue_pair_map = NULL;
496 if (ha->base_qpair) {
497 kfree(ha->base_qpair);
498 ha->base_qpair = NULL;
501 spin_lock_irqsave(&ha->hardware_lock, flags);
502 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
503 if (!test_bit(cnt, ha->req_qid_map))
506 req = ha->req_q_map[cnt];
507 clear_bit(cnt, ha->req_qid_map);
508 ha->req_q_map[cnt] = NULL;
510 spin_unlock_irqrestore(&ha->hardware_lock, flags);
511 qla2x00_free_req_que(ha, req);
512 spin_lock_irqsave(&ha->hardware_lock, flags);
514 spin_unlock_irqrestore(&ha->hardware_lock, flags);
516 kfree(ha->req_q_map);
517 ha->req_q_map = NULL;
520 spin_lock_irqsave(&ha->hardware_lock, flags);
521 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
522 if (!test_bit(cnt, ha->rsp_qid_map))
525 rsp = ha->rsp_q_map[cnt];
526 clear_bit(cnt, ha->rsp_qid_map);
527 ha->rsp_q_map[cnt] = NULL;
528 spin_unlock_irqrestore(&ha->hardware_lock, flags);
529 qla2x00_free_rsp_que(ha, rsp);
530 spin_lock_irqsave(&ha->hardware_lock, flags);
532 spin_unlock_irqrestore(&ha->hardware_lock, flags);
534 kfree(ha->rsp_q_map);
535 ha->rsp_q_map = NULL;
539 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
541 struct qla_hw_data *ha = vha->hw;
542 static const char *const pci_bus_modes[] = {
543 "33", "66", "100", "133",
547 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
549 snprintf(str, str_len, "PCI-X (%s MHz)",
550 pci_bus_modes[pci_bus]);
552 pci_bus = (ha->pci_attr & BIT_8) >> 8;
553 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
560 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
562 static const char *const pci_bus_modes[] = {
563 "33", "66", "100", "133",
565 struct qla_hw_data *ha = vha->hw;
568 if (pci_is_pcie(ha->pdev)) {
569 uint32_t lstat, lspeed, lwidth;
570 const char *speed_str;
572 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
573 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
574 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
578 speed_str = "2.5GT/s";
581 speed_str = "5.0GT/s";
584 speed_str = "8.0GT/s";
587 speed_str = "<unknown>";
590 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
595 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
596 if (pci_bus == 0 || pci_bus == 8)
597 snprintf(str, str_len, "PCI (%s MHz)",
598 pci_bus_modes[pci_bus >> 3]);
600 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
602 pci_bus_modes[pci_bus & 3]);
608 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
611 struct qla_hw_data *ha = vha->hw;
613 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
614 ha->fw_minor_version, ha->fw_subminor_version);
616 if (ha->fw_attributes & BIT_9) {
621 switch (ha->fw_attributes & 0xFF) {
635 sprintf(un_str, "(%x)", ha->fw_attributes);
639 if (ha->fw_attributes & 0x100)
646 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
648 struct qla_hw_data *ha = vha->hw;
650 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
651 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
655 void qla2x00_sp_free_dma(srb_t *sp)
657 struct qla_hw_data *ha = sp->vha->hw;
658 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
660 if (sp->flags & SRB_DMA_VALID) {
662 sp->flags &= ~SRB_DMA_VALID;
665 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
666 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
667 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
668 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
671 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
672 /* List assured to be having elements */
673 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
674 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
677 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
678 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
680 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
681 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
684 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
685 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
687 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
689 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
690 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
691 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
692 mempool_free(ctx1, ha->ctx_mempool);
696 void qla2x00_sp_compl(srb_t *sp, int res)
698 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
699 struct completion *comp = sp->comp;
701 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
704 atomic_dec(&sp->ref_count);
714 void qla2xxx_qpair_sp_free_dma(srb_t *sp)
716 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
717 struct qla_hw_data *ha = sp->fcport->vha->hw;
719 if (sp->flags & SRB_DMA_VALID) {
721 sp->flags &= ~SRB_DMA_VALID;
724 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
725 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
726 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
727 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
730 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
731 /* List assured to be having elements */
732 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
733 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
736 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
737 struct crc_context *difctx = sp->u.scmd.crc_ctx;
738 struct dsd_dma *dif_dsd, *nxt_dsd;
740 list_for_each_entry_safe(dif_dsd, nxt_dsd,
741 &difctx->ldif_dma_hndl_list, list) {
742 list_del(&dif_dsd->list);
743 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
744 dif_dsd->dsd_list_dma);
746 difctx->no_dif_bundl--;
749 list_for_each_entry_safe(dif_dsd, nxt_dsd,
750 &difctx->ldif_dsd_list, list) {
751 list_del(&dif_dsd->list);
752 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
753 dif_dsd->dsd_list_dma);
755 difctx->no_ldif_dsd--;
758 if (difctx->no_ldif_dsd) {
759 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
760 "%s: difctx->no_ldif_dsd=%x\n",
761 __func__, difctx->no_ldif_dsd);
764 if (difctx->no_dif_bundl) {
765 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
766 "%s: difctx->no_dif_bundl=%x\n",
767 __func__, difctx->no_dif_bundl);
769 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
772 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
773 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
775 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
777 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
778 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
779 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
780 mempool_free(ctx1, ha->ctx_mempool);
781 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
784 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
785 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
787 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
788 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
792 void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
794 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
795 struct completion *comp = sp->comp;
797 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
800 atomic_dec(&sp->ref_count);
811 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
813 scsi_qla_host_t *vha = shost_priv(host);
814 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
815 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
816 struct qla_hw_data *ha = vha->hw;
817 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
821 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
822 WARN_ON_ONCE(!rport)) {
823 cmd->result = DID_NO_CONNECT << 16;
824 goto qc24_fail_command;
830 struct qla_qpair *qpair = NULL;
832 tag = blk_mq_unique_tag(cmd->request);
833 hwq = blk_mq_unique_tag_to_hwq(tag);
834 qpair = ha->queue_pair_map[hwq];
837 return qla2xxx_mqueuecommand(host, cmd, qpair);
840 if (ha->flags.eeh_busy) {
841 if (ha->flags.pci_channel_io_perm_failure) {
842 ql_dbg(ql_dbg_aer, vha, 0x9010,
843 "PCI Channel IO permanent failure, exiting "
845 cmd->result = DID_NO_CONNECT << 16;
847 ql_dbg(ql_dbg_aer, vha, 0x9011,
848 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
849 cmd->result = DID_REQUEUE << 16;
851 goto qc24_fail_command;
854 rval = fc_remote_port_chkready(rport);
857 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
858 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
860 goto qc24_fail_command;
863 if (!vha->flags.difdix_supported &&
864 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
865 ql_dbg(ql_dbg_io, vha, 0x3004,
866 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
868 cmd->result = DID_NO_CONNECT << 16;
869 goto qc24_fail_command;
873 cmd->result = DID_NO_CONNECT << 16;
874 goto qc24_fail_command;
877 if (atomic_read(&fcport->state) != FCS_ONLINE) {
878 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
879 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
880 ql_dbg(ql_dbg_io, vha, 0x3005,
881 "Returning DNC, fcport_state=%d loop_state=%d.\n",
882 atomic_read(&fcport->state),
883 atomic_read(&base_vha->loop_state));
884 cmd->result = DID_NO_CONNECT << 16;
885 goto qc24_fail_command;
887 goto qc24_target_busy;
891 * Return target busy if we've received a non-zero retry_delay_timer
894 if (fcport->retry_delay_timestamp == 0) {
895 /* retry delay not set */
896 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
897 fcport->retry_delay_timestamp = 0;
899 goto qc24_target_busy;
901 sp = scsi_cmd_priv(cmd);
902 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
904 sp->u.scmd.cmd = cmd;
905 sp->type = SRB_SCSI_CMD;
906 atomic_set(&sp->ref_count, 1);
907 CMD_SP(cmd) = (void *)sp;
908 sp->free = qla2x00_sp_free_dma;
909 sp->done = qla2x00_sp_compl;
911 rval = ha->isp_ops->start_scsi(sp);
912 if (rval != QLA_SUCCESS) {
913 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
914 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
915 goto qc24_host_busy_free_sp;
920 qc24_host_busy_free_sp:
924 return SCSI_MLQUEUE_TARGET_BUSY;
932 /* For MQ supported I/O */
934 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
935 struct qla_qpair *qpair)
937 scsi_qla_host_t *vha = shost_priv(host);
938 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
939 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
940 struct qla_hw_data *ha = vha->hw;
941 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
945 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE;
948 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
949 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
951 goto qc24_fail_command;
955 cmd->result = DID_NO_CONNECT << 16;
956 goto qc24_fail_command;
959 if (atomic_read(&fcport->state) != FCS_ONLINE) {
960 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
961 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
962 ql_dbg(ql_dbg_io, vha, 0x3077,
963 "Returning DNC, fcport_state=%d loop_state=%d.\n",
964 atomic_read(&fcport->state),
965 atomic_read(&base_vha->loop_state));
966 cmd->result = DID_NO_CONNECT << 16;
967 goto qc24_fail_command;
969 goto qc24_target_busy;
973 * Return target busy if we've received a non-zero retry_delay_timer
976 if (fcport->retry_delay_timestamp == 0) {
977 /* retry delay not set */
978 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
979 fcport->retry_delay_timestamp = 0;
981 goto qc24_target_busy;
983 sp = scsi_cmd_priv(cmd);
984 qla2xxx_init_sp(sp, vha, qpair, fcport);
986 sp->u.scmd.cmd = cmd;
987 sp->type = SRB_SCSI_CMD;
988 atomic_set(&sp->ref_count, 1);
989 CMD_SP(cmd) = (void *)sp;
990 sp->free = qla2xxx_qpair_sp_free_dma;
991 sp->done = qla2xxx_qpair_sp_compl;
994 rval = ha->isp_ops->start_scsi_mq(sp);
995 if (rval != QLA_SUCCESS) {
996 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
997 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
998 if (rval == QLA_INTERFACE_ERROR)
999 goto qc24_fail_command;
1000 goto qc24_host_busy_free_sp;
1005 qc24_host_busy_free_sp:
1009 return SCSI_MLQUEUE_TARGET_BUSY;
1012 cmd->scsi_done(cmd);
1018 * qla2x00_eh_wait_on_command
1019 * Waits for the command to be returned by the Firmware for some
1023 * cmd = Scsi Command to wait on.
1026 * Completed in time : QLA_SUCCESS
1027 * Did not complete in time : QLA_FUNCTION_FAILED
1030 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1032 #define ABORT_POLLING_PERIOD 1000
1033 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1034 unsigned long wait_iter = ABORT_WAIT_ITER;
1035 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1036 struct qla_hw_data *ha = vha->hw;
1037 int ret = QLA_SUCCESS;
1039 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
1040 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1041 "Return:eh_wait.\n");
1045 while (CMD_SP(cmd) && wait_iter--) {
1046 msleep(ABORT_POLLING_PERIOD);
1049 ret = QLA_FUNCTION_FAILED;
1055 * qla2x00_wait_for_hba_online
1056 * Wait till the HBA is online after going through
1057 * <= MAX_RETRIES_OF_ISP_ABORT or
1058 * finally HBA is disabled ie marked offline
1061 * ha - pointer to host adapter structure
1064 * Does context switching-Release SPIN_LOCK
1065 * (if any) before calling this routine.
1068 * Success (Adapter is online) : 0
1069 * Failed (Adapter is offline/disabled) : 1
1072 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1075 unsigned long wait_online;
1076 struct qla_hw_data *ha = vha->hw;
1077 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1079 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1080 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1081 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1082 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1083 ha->dpc_active) && time_before(jiffies, wait_online)) {
1087 if (base_vha->flags.online)
1088 return_status = QLA_SUCCESS;
1090 return_status = QLA_FUNCTION_FAILED;
1092 return (return_status);
1095 static inline int test_fcport_count(scsi_qla_host_t *vha)
1097 struct qla_hw_data *ha = vha->hw;
1098 unsigned long flags;
1101 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1102 ql_dbg(ql_dbg_init, vha, 0x00ec,
1103 "tgt %p, fcport_count=%d\n",
1104 vha, vha->fcport_count);
1105 res = (vha->fcport_count == 0);
1106 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1112 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1113 * it has dependency on UNLOADING flag to stop device discovery
1116 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1120 qla2x00_mark_all_devices_lost(vha, 0);
1122 for (i = 0; i < 10; i++)
1123 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha),
1126 flush_workqueue(vha->hw->wq);
1130 * qla2x00_wait_for_hba_ready
1131 * Wait till the HBA is ready before doing driver unload
1134 * ha - pointer to host adapter structure
1137 * Does context switching-Release SPIN_LOCK
1138 * (if any) before calling this routine.
1142 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1144 struct qla_hw_data *ha = vha->hw;
1145 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1147 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1148 ha->flags.mbox_busy) ||
1149 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1150 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1151 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1158 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1161 unsigned long wait_reset;
1162 struct qla_hw_data *ha = vha->hw;
1163 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1165 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1166 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1167 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1168 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1169 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1173 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1174 ha->flags.chip_reset_done)
1177 if (ha->flags.chip_reset_done)
1178 return_status = QLA_SUCCESS;
1180 return_status = QLA_FUNCTION_FAILED;
1182 return return_status;
1186 sp_get(struct srb *sp)
1188 if (!refcount_inc_not_zero((refcount_t *)&sp->ref_count))
1195 #define ISP_REG_DISCONNECT 0xffffffffU
1196 /**************************************************************************
1197 * qla2x00_isp_reg_stat
1200 * Read the host status register of ISP before aborting the command.
1203 * ha = pointer to host adapter structure.
1207 * Either true or false.
1209 * Note: Return true if there is register disconnect.
1210 **************************************************************************/
1212 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1214 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1215 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
1217 if (IS_P3P_TYPE(ha))
1218 return ((RD_REG_DWORD(®82->host_int)) == ISP_REG_DISCONNECT);
1220 return ((RD_REG_DWORD(®->host_status)) ==
1221 ISP_REG_DISCONNECT);
1224 /**************************************************************************
1228 * The abort function will abort the specified command.
1231 * cmd = Linux SCSI command packet to be aborted.
1234 * Either SUCCESS or FAILED.
1237 * Only return FAILED if command not returned by firmware.
1238 **************************************************************************/
1240 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1242 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1243 DECLARE_COMPLETION_ONSTACK(comp);
1249 struct qla_hw_data *ha = vha->hw;
1251 if (qla2x00_isp_reg_stat(ha)) {
1252 ql_log(ql_log_info, vha, 0x8042,
1253 "PCI/Register disconnect, exiting.\n");
1257 ret = fc_block_scsi_eh(cmd);
1261 sp = scsi_cmd_priv(cmd);
1263 if (sp->fcport && sp->fcport->deleted)
1266 /* Return if the command has already finished. */
1270 id = cmd->device->id;
1271 lun = cmd->device->lun;
1273 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1274 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1275 vha->host_no, id, lun, sp, cmd, sp->handle);
1277 rval = ha->isp_ops->abort_command(sp);
1278 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1279 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
1284 * The command has been aborted. That means that the firmware
1285 * won't report a completion.
1287 sp->done(sp, DID_ABORT << 16);
1290 case QLA_FUNCTION_PARAMETER_ERROR: {
1291 /* Wait for the command completion. */
1292 uint32_t ratov = ha->r_a_tov/10;
1293 uint32_t ratov_j = msecs_to_jiffies(4 * ratov * 1000);
1295 WARN_ON_ONCE(sp->comp);
1297 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1298 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1299 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1300 __func__, ha->r_a_tov);
1309 * Either abort failed or abort and completion raced. Let
1310 * the SCSI core retry the abort in the former case.
1317 atomic_dec(&sp->ref_count);
1318 ql_log(ql_log_info, vha, 0x801c,
1319 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1320 vha->host_no, id, lun, ret);
1326 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1329 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1330 uint64_t l, enum nexus_wait_type type)
1332 int cnt, match, status;
1333 unsigned long flags;
1334 struct qla_hw_data *ha = vha->hw;
1335 struct req_que *req;
1337 struct scsi_cmnd *cmd;
1339 status = QLA_SUCCESS;
1341 spin_lock_irqsave(&ha->hardware_lock, flags);
1343 for (cnt = 1; status == QLA_SUCCESS &&
1344 cnt < req->num_outstanding_cmds; cnt++) {
1345 sp = req->outstanding_cmds[cnt];
1348 if (sp->type != SRB_SCSI_CMD)
1350 if (vha->vp_idx != sp->vha->vp_idx)
1353 cmd = GET_CMD_SP(sp);
1359 match = cmd->device->id == t;
1362 match = (cmd->device->id == t &&
1363 cmd->device->lun == l);
1369 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1370 status = qla2x00_eh_wait_on_command(cmd);
1371 spin_lock_irqsave(&ha->hardware_lock, flags);
1373 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1378 static char *reset_errors[] = {
1381 "Task management failed",
1382 "Waiting for command completions",
1386 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1387 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1389 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1390 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1397 err = fc_block_scsi_eh(cmd);
1401 if (fcport->deleted)
1404 ql_log(ql_log_info, vha, 0x8009,
1405 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1406 cmd->device->id, cmd->device->lun, cmd);
1409 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1410 ql_log(ql_log_warn, vha, 0x800a,
1411 "Wait for hba online failed for cmd=%p.\n", cmd);
1412 goto eh_reset_failed;
1415 if (do_reset(fcport, cmd->device->lun, 1)
1417 ql_log(ql_log_warn, vha, 0x800c,
1418 "do_reset failed for cmd=%p.\n", cmd);
1419 goto eh_reset_failed;
1422 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1423 cmd->device->lun, type) != QLA_SUCCESS) {
1424 ql_log(ql_log_warn, vha, 0x800d,
1425 "wait for pending cmds failed for cmd=%p.\n", cmd);
1426 goto eh_reset_failed;
1429 ql_log(ql_log_info, vha, 0x800e,
1430 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1431 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1436 ql_log(ql_log_info, vha, 0x800f,
1437 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1438 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1444 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1446 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1447 struct qla_hw_data *ha = vha->hw;
1449 if (qla2x00_isp_reg_stat(ha)) {
1450 ql_log(ql_log_info, vha, 0x803e,
1451 "PCI/Register disconnect, exiting.\n");
1455 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1456 ha->isp_ops->lun_reset);
1460 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1462 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1463 struct qla_hw_data *ha = vha->hw;
1465 if (qla2x00_isp_reg_stat(ha)) {
1466 ql_log(ql_log_info, vha, 0x803f,
1467 "PCI/Register disconnect, exiting.\n");
1471 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1472 ha->isp_ops->target_reset);
1475 /**************************************************************************
1476 * qla2xxx_eh_bus_reset
1479 * The bus reset function will reset the bus and abort any executing
1483 * cmd = Linux SCSI command packet of the command that cause the
1487 * SUCCESS/FAILURE (defined as macro in scsi.h).
1489 **************************************************************************/
1491 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1493 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1494 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1498 struct qla_hw_data *ha = vha->hw;
1500 if (qla2x00_isp_reg_stat(ha)) {
1501 ql_log(ql_log_info, vha, 0x8040,
1502 "PCI/Register disconnect, exiting.\n");
1506 id = cmd->device->id;
1507 lun = cmd->device->lun;
1513 ret = fc_block_scsi_eh(cmd);
1518 if (qla2x00_chip_is_down(vha))
1521 ql_log(ql_log_info, vha, 0x8012,
1522 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1524 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1525 ql_log(ql_log_fatal, vha, 0x8013,
1526 "Wait for hba online failed board disabled.\n");
1527 goto eh_bus_reset_done;
1530 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1534 goto eh_bus_reset_done;
1536 /* Flush outstanding commands. */
1537 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1539 ql_log(ql_log_warn, vha, 0x8014,
1540 "Wait for pending commands failed.\n");
1545 ql_log(ql_log_warn, vha, 0x802b,
1546 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1547 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1552 /**************************************************************************
1553 * qla2xxx_eh_host_reset
1556 * The reset function will reset the Adapter.
1559 * cmd = Linux SCSI command packet of the command that cause the
1563 * Either SUCCESS or FAILED.
1566 **************************************************************************/
1568 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1570 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1571 struct qla_hw_data *ha = vha->hw;
1575 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1577 if (qla2x00_isp_reg_stat(ha)) {
1578 ql_log(ql_log_info, vha, 0x8041,
1579 "PCI/Register disconnect, exiting.\n");
1580 schedule_work(&ha->board_disable);
1584 id = cmd->device->id;
1585 lun = cmd->device->lun;
1587 ql_log(ql_log_info, vha, 0x8018,
1588 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1591 * No point in issuing another reset if one is active. Also do not
1592 * attempt a reset if we are updating flash.
1594 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1595 goto eh_host_reset_lock;
1597 if (vha != base_vha) {
1598 if (qla2x00_vp_abort_isp(vha))
1599 goto eh_host_reset_lock;
1601 if (IS_P3P_TYPE(vha->hw)) {
1602 if (!qla82xx_fcoe_ctx_reset(vha)) {
1603 /* Ctx reset success */
1605 goto eh_host_reset_lock;
1607 /* fall thru if ctx reset failed */
1610 flush_workqueue(ha->wq);
1612 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1613 if (ha->isp_ops->abort_isp(base_vha)) {
1614 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1615 /* failed. schedule dpc to try */
1616 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1618 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1619 ql_log(ql_log_warn, vha, 0x802a,
1620 "wait for hba online failed.\n");
1621 goto eh_host_reset_lock;
1624 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1627 /* Waiting for command to be returned to OS.*/
1628 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1633 ql_log(ql_log_info, vha, 0x8017,
1634 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1635 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1641 * qla2x00_loop_reset
1645 * ha = adapter block pointer.
1651 qla2x00_loop_reset(scsi_qla_host_t *vha)
1654 struct fc_port *fcport;
1655 struct qla_hw_data *ha = vha->hw;
1657 if (IS_QLAFX00(ha)) {
1658 return qlafx00_loop_reset(vha);
1661 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1662 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1663 if (fcport->port_type != FCT_TARGET)
1666 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1667 if (ret != QLA_SUCCESS) {
1668 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1669 "Bus Reset failed: Reset=%d "
1670 "d_id=%x.\n", ret, fcport->d_id.b24);
1676 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1677 atomic_set(&vha->loop_state, LOOP_DOWN);
1678 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1679 qla2x00_mark_all_devices_lost(vha, 0);
1680 ret = qla2x00_full_login_lip(vha);
1681 if (ret != QLA_SUCCESS) {
1682 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1683 "full_login_lip=%d.\n", ret);
1687 if (ha->flags.enable_lip_reset) {
1688 ret = qla2x00_lip_reset(vha);
1689 if (ret != QLA_SUCCESS)
1690 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1691 "lip_reset failed (%d).\n", ret);
1694 /* Issue marker command only when we are going to start the I/O */
1695 vha->marker_needed = 1;
1700 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1701 unsigned long *flags)
1702 __releases(qp->qp_lock_ptr)
1703 __acquires(qp->qp_lock_ptr)
1705 DECLARE_COMPLETION_ONSTACK(comp);
1706 scsi_qla_host_t *vha = qp->vha;
1707 struct qla_hw_data *ha = vha->hw;
1713 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1714 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1715 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1716 !qla2x00_isp_reg_stat(ha))) {
1718 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1719 rval = ha->isp_ops->abort_command(sp);
1725 case QLA_FUNCTION_PARAMETER_ERROR:
1726 wait_for_completion(&comp);
1730 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1734 atomic_dec(&sp->ref_count);
1738 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1741 unsigned long flags;
1743 scsi_qla_host_t *vha = qp->vha;
1744 struct qla_hw_data *ha = vha->hw;
1745 struct req_que *req;
1746 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1747 struct qla_tgt_cmd *cmd;
1751 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1753 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1754 sp = req->outstanding_cmds[cnt];
1756 req->outstanding_cmds[cnt] = NULL;
1757 switch (sp->cmd_type) {
1759 qla2x00_abort_srb(qp, sp, res, &flags);
1762 if (!vha->hw->tgt.tgt_ops || !tgt ||
1763 qla_ini_mode_enabled(vha)) {
1764 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1765 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1769 cmd = (struct qla_tgt_cmd *)sp;
1772 case TYPE_TGT_TMCMD:
1773 /* Skip task management functions. */
1780 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1784 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1787 struct qla_hw_data *ha = vha->hw;
1789 /* Continue only if initialization complete. */
1790 if (!ha->base_qpair)
1792 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1794 if (!ha->queue_pair_map)
1796 for (que = 0; que < ha->max_qpairs; que++) {
1797 if (!ha->queue_pair_map[que])
1800 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1805 qla2xxx_slave_alloc(struct scsi_device *sdev)
1807 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1809 if (!rport || fc_remote_port_chkready(rport))
1812 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1818 qla2xxx_slave_configure(struct scsi_device *sdev)
1820 scsi_qla_host_t *vha = shost_priv(sdev->host);
1821 struct req_que *req = vha->req;
1823 if (IS_T10_PI_CAPABLE(vha->hw))
1824 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1826 scsi_change_queue_depth(sdev, req->max_q_depth);
1831 qla2xxx_slave_destroy(struct scsi_device *sdev)
1833 sdev->hostdata = NULL;
1837 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1840 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1841 * supported addressing method.
1844 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1846 /* Assume a 32bit DMA mask. */
1847 ha->flags.enable_64bit_addressing = 0;
1849 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1850 /* Any upper-dword bits set? */
1851 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1852 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1853 /* Ok, a 64bit DMA mask is applicable. */
1854 ha->flags.enable_64bit_addressing = 1;
1855 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1856 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1861 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1862 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1866 qla2x00_enable_intrs(struct qla_hw_data *ha)
1868 unsigned long flags = 0;
1869 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1871 spin_lock_irqsave(&ha->hardware_lock, flags);
1872 ha->interrupts_on = 1;
1873 /* enable risc and host interrupts */
1874 WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC);
1875 RD_REG_WORD(®->ictrl);
1876 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1881 qla2x00_disable_intrs(struct qla_hw_data *ha)
1883 unsigned long flags = 0;
1884 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1886 spin_lock_irqsave(&ha->hardware_lock, flags);
1887 ha->interrupts_on = 0;
1888 /* disable risc and host interrupts */
1889 WRT_REG_WORD(®->ictrl, 0);
1890 RD_REG_WORD(®->ictrl);
1891 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1895 qla24xx_enable_intrs(struct qla_hw_data *ha)
1897 unsigned long flags = 0;
1898 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1900 spin_lock_irqsave(&ha->hardware_lock, flags);
1901 ha->interrupts_on = 1;
1902 WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT);
1903 RD_REG_DWORD(®->ictrl);
1904 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1908 qla24xx_disable_intrs(struct qla_hw_data *ha)
1910 unsigned long flags = 0;
1911 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1913 if (IS_NOPOLLING_TYPE(ha))
1915 spin_lock_irqsave(&ha->hardware_lock, flags);
1916 ha->interrupts_on = 0;
1917 WRT_REG_DWORD(®->ictrl, 0);
1918 RD_REG_DWORD(®->ictrl);
1919 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1923 qla2x00_iospace_config(struct qla_hw_data *ha)
1925 resource_size_t pio;
1928 if (pci_request_selected_regions(ha->pdev, ha->bars,
1929 QLA2XXX_DRIVER_NAME)) {
1930 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1931 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1932 pci_name(ha->pdev));
1933 goto iospace_error_exit;
1935 if (!(ha->bars & 1))
1938 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1939 pio = pci_resource_start(ha->pdev, 0);
1940 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1941 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1942 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1943 "Invalid pci I/O region size (%s).\n",
1944 pci_name(ha->pdev));
1948 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1949 "Region #0 no a PIO resource (%s).\n",
1950 pci_name(ha->pdev));
1953 ha->pio_address = pio;
1954 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1955 "PIO address=%llu.\n",
1956 (unsigned long long)ha->pio_address);
1959 /* Use MMIO operations for all accesses. */
1960 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1961 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1962 "Region #1 not an MMIO resource (%s), aborting.\n",
1963 pci_name(ha->pdev));
1964 goto iospace_error_exit;
1966 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1967 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1968 "Invalid PCI mem region size (%s), aborting.\n",
1969 pci_name(ha->pdev));
1970 goto iospace_error_exit;
1973 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1975 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1976 "Cannot remap MMIO (%s), aborting.\n",
1977 pci_name(ha->pdev));
1978 goto iospace_error_exit;
1981 /* Determine queue resources */
1982 ha->max_req_queues = ha->max_rsp_queues = 1;
1983 ha->msix_count = QLA_BASE_VECTORS;
1984 if (!ql2xmqsupport || !ql2xnvmeenable ||
1985 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1988 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1989 pci_resource_len(ha->pdev, 3));
1991 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1992 "MQIO Base=%p.\n", ha->mqiobase);
1993 /* Read MSIX vector size of the board */
1994 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1995 ha->msix_count = msix + 1;
1996 /* Max queues are bounded by available msix vectors */
1997 /* MB interrupt uses 1 vector */
1998 ha->max_req_queues = ha->msix_count - 1;
1999 ha->max_rsp_queues = ha->max_req_queues;
2000 /* Queue pairs is the max value minus the base queue pair */
2001 ha->max_qpairs = ha->max_rsp_queues - 1;
2002 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2003 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2005 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2006 "MSI-X vector count: %d.\n", ha->msix_count);
2008 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2009 "BAR 3 not enabled.\n");
2012 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2013 "MSIX Count: %d.\n", ha->msix_count);
2022 qla83xx_iospace_config(struct qla_hw_data *ha)
2026 if (pci_request_selected_regions(ha->pdev, ha->bars,
2027 QLA2XXX_DRIVER_NAME)) {
2028 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2029 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2030 pci_name(ha->pdev));
2032 goto iospace_error_exit;
2035 /* Use MMIO operations for all accesses. */
2036 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2037 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2038 "Invalid pci I/O region size (%s).\n",
2039 pci_name(ha->pdev));
2040 goto iospace_error_exit;
2042 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2043 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2044 "Invalid PCI mem region size (%s), aborting\n",
2045 pci_name(ha->pdev));
2046 goto iospace_error_exit;
2049 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2051 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2052 "Cannot remap MMIO (%s), aborting.\n",
2053 pci_name(ha->pdev));
2054 goto iospace_error_exit;
2057 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2058 /* 83XX 26XX always use MQ type access for queues
2059 * - mbar 2, a.k.a region 4 */
2060 ha->max_req_queues = ha->max_rsp_queues = 1;
2061 ha->msix_count = QLA_BASE_VECTORS;
2062 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2063 pci_resource_len(ha->pdev, 4));
2065 if (!ha->mqiobase) {
2066 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2067 "BAR2/region4 not enabled\n");
2071 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2072 pci_resource_len(ha->pdev, 2));
2074 /* Read MSIX vector size of the board */
2075 pci_read_config_word(ha->pdev,
2076 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2077 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2079 * By default, driver uses at least two msix vectors
2082 if (ql2xmqsupport || ql2xnvmeenable) {
2083 /* MB interrupt uses 1 vector */
2084 ha->max_req_queues = ha->msix_count - 1;
2086 /* ATIOQ needs 1 vector. That's 1 less QPair */
2087 if (QLA_TGT_MODE_ENABLED())
2088 ha->max_req_queues--;
2090 ha->max_rsp_queues = ha->max_req_queues;
2092 /* Queue pairs is the max value minus
2093 * the base queue pair */
2094 ha->max_qpairs = ha->max_req_queues - 1;
2095 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2096 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2098 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2099 "MSI-X vector count: %d.\n", ha->msix_count);
2101 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2102 "BAR 1 not enabled.\n");
2105 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2106 "MSIX Count: %d.\n", ha->msix_count);
2113 static struct isp_operations qla2100_isp_ops = {
2114 .pci_config = qla2100_pci_config,
2115 .reset_chip = qla2x00_reset_chip,
2116 .chip_diag = qla2x00_chip_diag,
2117 .config_rings = qla2x00_config_rings,
2118 .reset_adapter = qla2x00_reset_adapter,
2119 .nvram_config = qla2x00_nvram_config,
2120 .update_fw_options = qla2x00_update_fw_options,
2121 .load_risc = qla2x00_load_risc,
2122 .pci_info_str = qla2x00_pci_info_str,
2123 .fw_version_str = qla2x00_fw_version_str,
2124 .intr_handler = qla2100_intr_handler,
2125 .enable_intrs = qla2x00_enable_intrs,
2126 .disable_intrs = qla2x00_disable_intrs,
2127 .abort_command = qla2x00_abort_command,
2128 .target_reset = qla2x00_abort_target,
2129 .lun_reset = qla2x00_lun_reset,
2130 .fabric_login = qla2x00_login_fabric,
2131 .fabric_logout = qla2x00_fabric_logout,
2132 .calc_req_entries = qla2x00_calc_iocbs_32,
2133 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2134 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2135 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2136 .read_nvram = qla2x00_read_nvram_data,
2137 .write_nvram = qla2x00_write_nvram_data,
2138 .fw_dump = qla2100_fw_dump,
2141 .beacon_blink = NULL,
2142 .read_optrom = qla2x00_read_optrom_data,
2143 .write_optrom = qla2x00_write_optrom_data,
2144 .get_flash_version = qla2x00_get_flash_version,
2145 .start_scsi = qla2x00_start_scsi,
2146 .start_scsi_mq = NULL,
2147 .abort_isp = qla2x00_abort_isp,
2148 .iospace_config = qla2x00_iospace_config,
2149 .initialize_adapter = qla2x00_initialize_adapter,
2152 static struct isp_operations qla2300_isp_ops = {
2153 .pci_config = qla2300_pci_config,
2154 .reset_chip = qla2x00_reset_chip,
2155 .chip_diag = qla2x00_chip_diag,
2156 .config_rings = qla2x00_config_rings,
2157 .reset_adapter = qla2x00_reset_adapter,
2158 .nvram_config = qla2x00_nvram_config,
2159 .update_fw_options = qla2x00_update_fw_options,
2160 .load_risc = qla2x00_load_risc,
2161 .pci_info_str = qla2x00_pci_info_str,
2162 .fw_version_str = qla2x00_fw_version_str,
2163 .intr_handler = qla2300_intr_handler,
2164 .enable_intrs = qla2x00_enable_intrs,
2165 .disable_intrs = qla2x00_disable_intrs,
2166 .abort_command = qla2x00_abort_command,
2167 .target_reset = qla2x00_abort_target,
2168 .lun_reset = qla2x00_lun_reset,
2169 .fabric_login = qla2x00_login_fabric,
2170 .fabric_logout = qla2x00_fabric_logout,
2171 .calc_req_entries = qla2x00_calc_iocbs_32,
2172 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2173 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2174 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2175 .read_nvram = qla2x00_read_nvram_data,
2176 .write_nvram = qla2x00_write_nvram_data,
2177 .fw_dump = qla2300_fw_dump,
2178 .beacon_on = qla2x00_beacon_on,
2179 .beacon_off = qla2x00_beacon_off,
2180 .beacon_blink = qla2x00_beacon_blink,
2181 .read_optrom = qla2x00_read_optrom_data,
2182 .write_optrom = qla2x00_write_optrom_data,
2183 .get_flash_version = qla2x00_get_flash_version,
2184 .start_scsi = qla2x00_start_scsi,
2185 .start_scsi_mq = NULL,
2186 .abort_isp = qla2x00_abort_isp,
2187 .iospace_config = qla2x00_iospace_config,
2188 .initialize_adapter = qla2x00_initialize_adapter,
2191 static struct isp_operations qla24xx_isp_ops = {
2192 .pci_config = qla24xx_pci_config,
2193 .reset_chip = qla24xx_reset_chip,
2194 .chip_diag = qla24xx_chip_diag,
2195 .config_rings = qla24xx_config_rings,
2196 .reset_adapter = qla24xx_reset_adapter,
2197 .nvram_config = qla24xx_nvram_config,
2198 .update_fw_options = qla24xx_update_fw_options,
2199 .load_risc = qla24xx_load_risc,
2200 .pci_info_str = qla24xx_pci_info_str,
2201 .fw_version_str = qla24xx_fw_version_str,
2202 .intr_handler = qla24xx_intr_handler,
2203 .enable_intrs = qla24xx_enable_intrs,
2204 .disable_intrs = qla24xx_disable_intrs,
2205 .abort_command = qla24xx_abort_command,
2206 .target_reset = qla24xx_abort_target,
2207 .lun_reset = qla24xx_lun_reset,
2208 .fabric_login = qla24xx_login_fabric,
2209 .fabric_logout = qla24xx_fabric_logout,
2210 .calc_req_entries = NULL,
2211 .build_iocbs = NULL,
2212 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2213 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2214 .read_nvram = qla24xx_read_nvram_data,
2215 .write_nvram = qla24xx_write_nvram_data,
2216 .fw_dump = qla24xx_fw_dump,
2217 .beacon_on = qla24xx_beacon_on,
2218 .beacon_off = qla24xx_beacon_off,
2219 .beacon_blink = qla24xx_beacon_blink,
2220 .read_optrom = qla24xx_read_optrom_data,
2221 .write_optrom = qla24xx_write_optrom_data,
2222 .get_flash_version = qla24xx_get_flash_version,
2223 .start_scsi = qla24xx_start_scsi,
2224 .start_scsi_mq = NULL,
2225 .abort_isp = qla2x00_abort_isp,
2226 .iospace_config = qla2x00_iospace_config,
2227 .initialize_adapter = qla2x00_initialize_adapter,
2230 static struct isp_operations qla25xx_isp_ops = {
2231 .pci_config = qla25xx_pci_config,
2232 .reset_chip = qla24xx_reset_chip,
2233 .chip_diag = qla24xx_chip_diag,
2234 .config_rings = qla24xx_config_rings,
2235 .reset_adapter = qla24xx_reset_adapter,
2236 .nvram_config = qla24xx_nvram_config,
2237 .update_fw_options = qla24xx_update_fw_options,
2238 .load_risc = qla24xx_load_risc,
2239 .pci_info_str = qla24xx_pci_info_str,
2240 .fw_version_str = qla24xx_fw_version_str,
2241 .intr_handler = qla24xx_intr_handler,
2242 .enable_intrs = qla24xx_enable_intrs,
2243 .disable_intrs = qla24xx_disable_intrs,
2244 .abort_command = qla24xx_abort_command,
2245 .target_reset = qla24xx_abort_target,
2246 .lun_reset = qla24xx_lun_reset,
2247 .fabric_login = qla24xx_login_fabric,
2248 .fabric_logout = qla24xx_fabric_logout,
2249 .calc_req_entries = NULL,
2250 .build_iocbs = NULL,
2251 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2252 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2253 .read_nvram = qla25xx_read_nvram_data,
2254 .write_nvram = qla25xx_write_nvram_data,
2255 .fw_dump = qla25xx_fw_dump,
2256 .beacon_on = qla24xx_beacon_on,
2257 .beacon_off = qla24xx_beacon_off,
2258 .beacon_blink = qla24xx_beacon_blink,
2259 .read_optrom = qla25xx_read_optrom_data,
2260 .write_optrom = qla24xx_write_optrom_data,
2261 .get_flash_version = qla24xx_get_flash_version,
2262 .start_scsi = qla24xx_dif_start_scsi,
2263 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2264 .abort_isp = qla2x00_abort_isp,
2265 .iospace_config = qla2x00_iospace_config,
2266 .initialize_adapter = qla2x00_initialize_adapter,
2269 static struct isp_operations qla81xx_isp_ops = {
2270 .pci_config = qla25xx_pci_config,
2271 .reset_chip = qla24xx_reset_chip,
2272 .chip_diag = qla24xx_chip_diag,
2273 .config_rings = qla24xx_config_rings,
2274 .reset_adapter = qla24xx_reset_adapter,
2275 .nvram_config = qla81xx_nvram_config,
2276 .update_fw_options = qla81xx_update_fw_options,
2277 .load_risc = qla81xx_load_risc,
2278 .pci_info_str = qla24xx_pci_info_str,
2279 .fw_version_str = qla24xx_fw_version_str,
2280 .intr_handler = qla24xx_intr_handler,
2281 .enable_intrs = qla24xx_enable_intrs,
2282 .disable_intrs = qla24xx_disable_intrs,
2283 .abort_command = qla24xx_abort_command,
2284 .target_reset = qla24xx_abort_target,
2285 .lun_reset = qla24xx_lun_reset,
2286 .fabric_login = qla24xx_login_fabric,
2287 .fabric_logout = qla24xx_fabric_logout,
2288 .calc_req_entries = NULL,
2289 .build_iocbs = NULL,
2290 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2291 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2293 .write_nvram = NULL,
2294 .fw_dump = qla81xx_fw_dump,
2295 .beacon_on = qla24xx_beacon_on,
2296 .beacon_off = qla24xx_beacon_off,
2297 .beacon_blink = qla83xx_beacon_blink,
2298 .read_optrom = qla25xx_read_optrom_data,
2299 .write_optrom = qla24xx_write_optrom_data,
2300 .get_flash_version = qla24xx_get_flash_version,
2301 .start_scsi = qla24xx_dif_start_scsi,
2302 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2303 .abort_isp = qla2x00_abort_isp,
2304 .iospace_config = qla2x00_iospace_config,
2305 .initialize_adapter = qla2x00_initialize_adapter,
2308 static struct isp_operations qla82xx_isp_ops = {
2309 .pci_config = qla82xx_pci_config,
2310 .reset_chip = qla82xx_reset_chip,
2311 .chip_diag = qla24xx_chip_diag,
2312 .config_rings = qla82xx_config_rings,
2313 .reset_adapter = qla24xx_reset_adapter,
2314 .nvram_config = qla81xx_nvram_config,
2315 .update_fw_options = qla24xx_update_fw_options,
2316 .load_risc = qla82xx_load_risc,
2317 .pci_info_str = qla24xx_pci_info_str,
2318 .fw_version_str = qla24xx_fw_version_str,
2319 .intr_handler = qla82xx_intr_handler,
2320 .enable_intrs = qla82xx_enable_intrs,
2321 .disable_intrs = qla82xx_disable_intrs,
2322 .abort_command = qla24xx_abort_command,
2323 .target_reset = qla24xx_abort_target,
2324 .lun_reset = qla24xx_lun_reset,
2325 .fabric_login = qla24xx_login_fabric,
2326 .fabric_logout = qla24xx_fabric_logout,
2327 .calc_req_entries = NULL,
2328 .build_iocbs = NULL,
2329 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2330 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2331 .read_nvram = qla24xx_read_nvram_data,
2332 .write_nvram = qla24xx_write_nvram_data,
2333 .fw_dump = qla82xx_fw_dump,
2334 .beacon_on = qla82xx_beacon_on,
2335 .beacon_off = qla82xx_beacon_off,
2336 .beacon_blink = NULL,
2337 .read_optrom = qla82xx_read_optrom_data,
2338 .write_optrom = qla82xx_write_optrom_data,
2339 .get_flash_version = qla82xx_get_flash_version,
2340 .start_scsi = qla82xx_start_scsi,
2341 .start_scsi_mq = NULL,
2342 .abort_isp = qla82xx_abort_isp,
2343 .iospace_config = qla82xx_iospace_config,
2344 .initialize_adapter = qla2x00_initialize_adapter,
2347 static struct isp_operations qla8044_isp_ops = {
2348 .pci_config = qla82xx_pci_config,
2349 .reset_chip = qla82xx_reset_chip,
2350 .chip_diag = qla24xx_chip_diag,
2351 .config_rings = qla82xx_config_rings,
2352 .reset_adapter = qla24xx_reset_adapter,
2353 .nvram_config = qla81xx_nvram_config,
2354 .update_fw_options = qla24xx_update_fw_options,
2355 .load_risc = qla82xx_load_risc,
2356 .pci_info_str = qla24xx_pci_info_str,
2357 .fw_version_str = qla24xx_fw_version_str,
2358 .intr_handler = qla8044_intr_handler,
2359 .enable_intrs = qla82xx_enable_intrs,
2360 .disable_intrs = qla82xx_disable_intrs,
2361 .abort_command = qla24xx_abort_command,
2362 .target_reset = qla24xx_abort_target,
2363 .lun_reset = qla24xx_lun_reset,
2364 .fabric_login = qla24xx_login_fabric,
2365 .fabric_logout = qla24xx_fabric_logout,
2366 .calc_req_entries = NULL,
2367 .build_iocbs = NULL,
2368 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2369 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2371 .write_nvram = NULL,
2372 .fw_dump = qla8044_fw_dump,
2373 .beacon_on = qla82xx_beacon_on,
2374 .beacon_off = qla82xx_beacon_off,
2375 .beacon_blink = NULL,
2376 .read_optrom = qla8044_read_optrom_data,
2377 .write_optrom = qla8044_write_optrom_data,
2378 .get_flash_version = qla82xx_get_flash_version,
2379 .start_scsi = qla82xx_start_scsi,
2380 .start_scsi_mq = NULL,
2381 .abort_isp = qla8044_abort_isp,
2382 .iospace_config = qla82xx_iospace_config,
2383 .initialize_adapter = qla2x00_initialize_adapter,
2386 static struct isp_operations qla83xx_isp_ops = {
2387 .pci_config = qla25xx_pci_config,
2388 .reset_chip = qla24xx_reset_chip,
2389 .chip_diag = qla24xx_chip_diag,
2390 .config_rings = qla24xx_config_rings,
2391 .reset_adapter = qla24xx_reset_adapter,
2392 .nvram_config = qla81xx_nvram_config,
2393 .update_fw_options = qla81xx_update_fw_options,
2394 .load_risc = qla81xx_load_risc,
2395 .pci_info_str = qla24xx_pci_info_str,
2396 .fw_version_str = qla24xx_fw_version_str,
2397 .intr_handler = qla24xx_intr_handler,
2398 .enable_intrs = qla24xx_enable_intrs,
2399 .disable_intrs = qla24xx_disable_intrs,
2400 .abort_command = qla24xx_abort_command,
2401 .target_reset = qla24xx_abort_target,
2402 .lun_reset = qla24xx_lun_reset,
2403 .fabric_login = qla24xx_login_fabric,
2404 .fabric_logout = qla24xx_fabric_logout,
2405 .calc_req_entries = NULL,
2406 .build_iocbs = NULL,
2407 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2408 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2410 .write_nvram = NULL,
2411 .fw_dump = qla83xx_fw_dump,
2412 .beacon_on = qla24xx_beacon_on,
2413 .beacon_off = qla24xx_beacon_off,
2414 .beacon_blink = qla83xx_beacon_blink,
2415 .read_optrom = qla25xx_read_optrom_data,
2416 .write_optrom = qla24xx_write_optrom_data,
2417 .get_flash_version = qla24xx_get_flash_version,
2418 .start_scsi = qla24xx_dif_start_scsi,
2419 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2420 .abort_isp = qla2x00_abort_isp,
2421 .iospace_config = qla83xx_iospace_config,
2422 .initialize_adapter = qla2x00_initialize_adapter,
2425 static struct isp_operations qlafx00_isp_ops = {
2426 .pci_config = qlafx00_pci_config,
2427 .reset_chip = qlafx00_soft_reset,
2428 .chip_diag = qlafx00_chip_diag,
2429 .config_rings = qlafx00_config_rings,
2430 .reset_adapter = qlafx00_soft_reset,
2431 .nvram_config = NULL,
2432 .update_fw_options = NULL,
2434 .pci_info_str = qlafx00_pci_info_str,
2435 .fw_version_str = qlafx00_fw_version_str,
2436 .intr_handler = qlafx00_intr_handler,
2437 .enable_intrs = qlafx00_enable_intrs,
2438 .disable_intrs = qlafx00_disable_intrs,
2439 .abort_command = qla24xx_async_abort_command,
2440 .target_reset = qlafx00_abort_target,
2441 .lun_reset = qlafx00_lun_reset,
2442 .fabric_login = NULL,
2443 .fabric_logout = NULL,
2444 .calc_req_entries = NULL,
2445 .build_iocbs = NULL,
2446 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2447 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2448 .read_nvram = qla24xx_read_nvram_data,
2449 .write_nvram = qla24xx_write_nvram_data,
2451 .beacon_on = qla24xx_beacon_on,
2452 .beacon_off = qla24xx_beacon_off,
2453 .beacon_blink = NULL,
2454 .read_optrom = qla24xx_read_optrom_data,
2455 .write_optrom = qla24xx_write_optrom_data,
2456 .get_flash_version = qla24xx_get_flash_version,
2457 .start_scsi = qlafx00_start_scsi,
2458 .start_scsi_mq = NULL,
2459 .abort_isp = qlafx00_abort_isp,
2460 .iospace_config = qlafx00_iospace_config,
2461 .initialize_adapter = qlafx00_initialize_adapter,
2464 static struct isp_operations qla27xx_isp_ops = {
2465 .pci_config = qla25xx_pci_config,
2466 .reset_chip = qla24xx_reset_chip,
2467 .chip_diag = qla24xx_chip_diag,
2468 .config_rings = qla24xx_config_rings,
2469 .reset_adapter = qla24xx_reset_adapter,
2470 .nvram_config = qla81xx_nvram_config,
2471 .update_fw_options = qla24xx_update_fw_options,
2472 .load_risc = qla81xx_load_risc,
2473 .pci_info_str = qla24xx_pci_info_str,
2474 .fw_version_str = qla24xx_fw_version_str,
2475 .intr_handler = qla24xx_intr_handler,
2476 .enable_intrs = qla24xx_enable_intrs,
2477 .disable_intrs = qla24xx_disable_intrs,
2478 .abort_command = qla24xx_abort_command,
2479 .target_reset = qla24xx_abort_target,
2480 .lun_reset = qla24xx_lun_reset,
2481 .fabric_login = qla24xx_login_fabric,
2482 .fabric_logout = qla24xx_fabric_logout,
2483 .calc_req_entries = NULL,
2484 .build_iocbs = NULL,
2485 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2486 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2488 .write_nvram = NULL,
2489 .fw_dump = qla27xx_fwdump,
2490 .beacon_on = qla24xx_beacon_on,
2491 .beacon_off = qla24xx_beacon_off,
2492 .beacon_blink = qla83xx_beacon_blink,
2493 .read_optrom = qla25xx_read_optrom_data,
2494 .write_optrom = qla24xx_write_optrom_data,
2495 .get_flash_version = qla24xx_get_flash_version,
2496 .start_scsi = qla24xx_dif_start_scsi,
2497 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2498 .abort_isp = qla2x00_abort_isp,
2499 .iospace_config = qla83xx_iospace_config,
2500 .initialize_adapter = qla2x00_initialize_adapter,
2504 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2506 ha->device_type = DT_EXTENDED_IDS;
2507 switch (ha->pdev->device) {
2508 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2509 ha->isp_type |= DT_ISP2100;
2510 ha->device_type &= ~DT_EXTENDED_IDS;
2511 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2513 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2514 ha->isp_type |= DT_ISP2200;
2515 ha->device_type &= ~DT_EXTENDED_IDS;
2516 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2518 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2519 ha->isp_type |= DT_ISP2300;
2520 ha->device_type |= DT_ZIO_SUPPORTED;
2521 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2523 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2524 ha->isp_type |= DT_ISP2312;
2525 ha->device_type |= DT_ZIO_SUPPORTED;
2526 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2528 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2529 ha->isp_type |= DT_ISP2322;
2530 ha->device_type |= DT_ZIO_SUPPORTED;
2531 if (ha->pdev->subsystem_vendor == 0x1028 &&
2532 ha->pdev->subsystem_device == 0x0170)
2533 ha->device_type |= DT_OEM_001;
2534 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2536 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2537 ha->isp_type |= DT_ISP6312;
2538 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2540 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2541 ha->isp_type |= DT_ISP6322;
2542 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2544 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2545 ha->isp_type |= DT_ISP2422;
2546 ha->device_type |= DT_ZIO_SUPPORTED;
2547 ha->device_type |= DT_FWI2;
2548 ha->device_type |= DT_IIDMA;
2549 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2551 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2552 ha->isp_type |= DT_ISP2432;
2553 ha->device_type |= DT_ZIO_SUPPORTED;
2554 ha->device_type |= DT_FWI2;
2555 ha->device_type |= DT_IIDMA;
2556 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2558 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2559 ha->isp_type |= DT_ISP8432;
2560 ha->device_type |= DT_ZIO_SUPPORTED;
2561 ha->device_type |= DT_FWI2;
2562 ha->device_type |= DT_IIDMA;
2563 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2565 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2566 ha->isp_type |= DT_ISP5422;
2567 ha->device_type |= DT_FWI2;
2568 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2570 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2571 ha->isp_type |= DT_ISP5432;
2572 ha->device_type |= DT_FWI2;
2573 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2575 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2576 ha->isp_type |= DT_ISP2532;
2577 ha->device_type |= DT_ZIO_SUPPORTED;
2578 ha->device_type |= DT_FWI2;
2579 ha->device_type |= DT_IIDMA;
2580 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2582 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2583 ha->isp_type |= DT_ISP8001;
2584 ha->device_type |= DT_ZIO_SUPPORTED;
2585 ha->device_type |= DT_FWI2;
2586 ha->device_type |= DT_IIDMA;
2587 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2589 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2590 ha->isp_type |= DT_ISP8021;
2591 ha->device_type |= DT_ZIO_SUPPORTED;
2592 ha->device_type |= DT_FWI2;
2593 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2594 /* Initialize 82XX ISP flags */
2595 qla82xx_init_flags(ha);
2597 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2598 ha->isp_type |= DT_ISP8044;
2599 ha->device_type |= DT_ZIO_SUPPORTED;
2600 ha->device_type |= DT_FWI2;
2601 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2602 /* Initialize 82XX ISP flags */
2603 qla82xx_init_flags(ha);
2605 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2606 ha->isp_type |= DT_ISP2031;
2607 ha->device_type |= DT_ZIO_SUPPORTED;
2608 ha->device_type |= DT_FWI2;
2609 ha->device_type |= DT_IIDMA;
2610 ha->device_type |= DT_T10_PI;
2611 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2613 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2614 ha->isp_type |= DT_ISP8031;
2615 ha->device_type |= DT_ZIO_SUPPORTED;
2616 ha->device_type |= DT_FWI2;
2617 ha->device_type |= DT_IIDMA;
2618 ha->device_type |= DT_T10_PI;
2619 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2621 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2622 ha->isp_type |= DT_ISPFX00;
2624 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2625 ha->isp_type |= DT_ISP2071;
2626 ha->device_type |= DT_ZIO_SUPPORTED;
2627 ha->device_type |= DT_FWI2;
2628 ha->device_type |= DT_IIDMA;
2629 ha->device_type |= DT_T10_PI;
2630 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2632 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2633 ha->isp_type |= DT_ISP2271;
2634 ha->device_type |= DT_ZIO_SUPPORTED;
2635 ha->device_type |= DT_FWI2;
2636 ha->device_type |= DT_IIDMA;
2637 ha->device_type |= DT_T10_PI;
2638 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2640 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2641 ha->isp_type |= DT_ISP2261;
2642 ha->device_type |= DT_ZIO_SUPPORTED;
2643 ha->device_type |= DT_FWI2;
2644 ha->device_type |= DT_IIDMA;
2645 ha->device_type |= DT_T10_PI;
2646 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2648 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2649 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2650 ha->isp_type |= DT_ISP2081;
2651 ha->device_type |= DT_ZIO_SUPPORTED;
2652 ha->device_type |= DT_FWI2;
2653 ha->device_type |= DT_IIDMA;
2654 ha->device_type |= DT_T10_PI;
2655 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2657 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2658 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2659 ha->isp_type |= DT_ISP2281;
2660 ha->device_type |= DT_ZIO_SUPPORTED;
2661 ha->device_type |= DT_FWI2;
2662 ha->device_type |= DT_IIDMA;
2663 ha->device_type |= DT_T10_PI;
2664 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2669 ha->port_no = ha->portnum & 1;
2671 /* Get adapter physical port no from interrupt pin register. */
2672 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2673 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2674 IS_QLA27XX(ha) || IS_QLA28XX(ha))
2677 ha->port_no = !(ha->port_no & 1);
2680 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2681 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2682 ha->device_type, ha->port_no, ha->fw_srisc_address);
2686 qla2xxx_scan_start(struct Scsi_Host *shost)
2688 scsi_qla_host_t *vha = shost_priv(shost);
2690 if (vha->hw->flags.running_gold_fw)
2693 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2694 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2695 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2696 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2700 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2702 scsi_qla_host_t *vha = shost_priv(shost);
2704 if (test_bit(UNLOADING, &vha->dpc_flags))
2708 if (time > vha->hw->loop_reset_delay * HZ)
2711 return atomic_read(&vha->loop_state) == LOOP_READY;
2714 static void qla2x00_iocb_work_fn(struct work_struct *work)
2716 struct scsi_qla_host *vha = container_of(work,
2717 struct scsi_qla_host, iocb_work);
2718 struct qla_hw_data *ha = vha->hw;
2719 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2721 unsigned long flags;
2723 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2726 while (!list_empty(&vha->work_list) && i > 0) {
2727 qla2x00_do_work(vha);
2731 spin_lock_irqsave(&vha->work_lock, flags);
2732 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2733 spin_unlock_irqrestore(&vha->work_lock, flags);
2737 * PCI driver interface
2740 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2743 struct Scsi_Host *host;
2744 scsi_qla_host_t *base_vha = NULL;
2745 struct qla_hw_data *ha;
2747 char fw_str[30], wq_name[30];
2748 struct scsi_host_template *sht;
2749 int bars, mem_only = 0;
2750 uint16_t req_length = 0, rsp_length = 0;
2751 struct req_que *req = NULL;
2752 struct rsp_que *rsp = NULL;
2755 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2756 sht = &qla2xxx_driver_template;
2757 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2758 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2759 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2760 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2761 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2762 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2763 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2764 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2765 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2766 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2767 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2768 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2769 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2770 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2771 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2772 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2773 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2774 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2775 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
2776 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2778 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2779 "Mem only adapter.\n");
2781 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2782 "Bars=%d.\n", bars);
2785 if (pci_enable_device_mem(pdev))
2788 if (pci_enable_device(pdev))
2792 /* This may fail but that's ok */
2793 pci_enable_pcie_error_reporting(pdev);
2795 /* Turn off T10-DIF when FC-NVMe is enabled */
2799 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2801 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2802 "Unable to allocate memory for ha.\n");
2803 goto disable_device;
2805 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2806 "Memory allocated for ha=%p.\n", ha);
2808 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2809 spin_lock_init(&ha->tgt.q_full_lock);
2810 spin_lock_init(&ha->tgt.sess_lock);
2811 spin_lock_init(&ha->tgt.atio_lock);
2813 atomic_set(&ha->nvme_active_aen_cnt, 0);
2815 /* Clear our data area */
2817 ha->mem_only = mem_only;
2818 spin_lock_init(&ha->hardware_lock);
2819 spin_lock_init(&ha->vport_slock);
2820 mutex_init(&ha->selflogin_lock);
2821 mutex_init(&ha->optrom_mutex);
2823 /* Set ISP-type information. */
2824 qla2x00_set_isp_flags(ha);
2826 /* Set EEH reset type to fundamental if required by hba */
2827 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2828 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
2829 pdev->needs_freset = 1;
2831 ha->prev_topology = 0;
2832 ha->init_cb_size = sizeof(init_cb_t);
2833 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2834 ha->optrom_size = OPTROM_SIZE_2300;
2835 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
2836 atomic_set(&ha->num_pend_mbx_stage1, 0);
2837 atomic_set(&ha->num_pend_mbx_stage2, 0);
2838 atomic_set(&ha->num_pend_mbx_stage3, 0);
2839 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2840 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
2842 /* Assign ISP specific operations. */
2843 if (IS_QLA2100(ha)) {
2844 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2845 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2846 req_length = REQUEST_ENTRY_CNT_2100;
2847 rsp_length = RESPONSE_ENTRY_CNT_2100;
2848 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2849 ha->gid_list_info_size = 4;
2850 ha->flash_conf_off = ~0;
2851 ha->flash_data_off = ~0;
2852 ha->nvram_conf_off = ~0;
2853 ha->nvram_data_off = ~0;
2854 ha->isp_ops = &qla2100_isp_ops;
2855 } else if (IS_QLA2200(ha)) {
2856 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2857 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2858 req_length = REQUEST_ENTRY_CNT_2200;
2859 rsp_length = RESPONSE_ENTRY_CNT_2100;
2860 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2861 ha->gid_list_info_size = 4;
2862 ha->flash_conf_off = ~0;
2863 ha->flash_data_off = ~0;
2864 ha->nvram_conf_off = ~0;
2865 ha->nvram_data_off = ~0;
2866 ha->isp_ops = &qla2100_isp_ops;
2867 } else if (IS_QLA23XX(ha)) {
2868 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2869 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2870 req_length = REQUEST_ENTRY_CNT_2200;
2871 rsp_length = RESPONSE_ENTRY_CNT_2300;
2872 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2873 ha->gid_list_info_size = 6;
2874 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2875 ha->optrom_size = OPTROM_SIZE_2322;
2876 ha->flash_conf_off = ~0;
2877 ha->flash_data_off = ~0;
2878 ha->nvram_conf_off = ~0;
2879 ha->nvram_data_off = ~0;
2880 ha->isp_ops = &qla2300_isp_ops;
2881 } else if (IS_QLA24XX_TYPE(ha)) {
2882 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2883 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2884 req_length = REQUEST_ENTRY_CNT_24XX;
2885 rsp_length = RESPONSE_ENTRY_CNT_2300;
2886 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2887 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2888 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2889 ha->gid_list_info_size = 8;
2890 ha->optrom_size = OPTROM_SIZE_24XX;
2891 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2892 ha->isp_ops = &qla24xx_isp_ops;
2893 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2894 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2895 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2896 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2897 } else if (IS_QLA25XX(ha)) {
2898 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2899 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2900 req_length = REQUEST_ENTRY_CNT_24XX;
2901 rsp_length = RESPONSE_ENTRY_CNT_2300;
2902 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2903 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2904 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2905 ha->gid_list_info_size = 8;
2906 ha->optrom_size = OPTROM_SIZE_25XX;
2907 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2908 ha->isp_ops = &qla25xx_isp_ops;
2909 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2910 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2911 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2912 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2913 } else if (IS_QLA81XX(ha)) {
2914 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2915 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2916 req_length = REQUEST_ENTRY_CNT_24XX;
2917 rsp_length = RESPONSE_ENTRY_CNT_2300;
2918 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2919 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2920 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2921 ha->gid_list_info_size = 8;
2922 ha->optrom_size = OPTROM_SIZE_81XX;
2923 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2924 ha->isp_ops = &qla81xx_isp_ops;
2925 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2926 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2927 ha->nvram_conf_off = ~0;
2928 ha->nvram_data_off = ~0;
2929 } else if (IS_QLA82XX(ha)) {
2930 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2931 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2932 req_length = REQUEST_ENTRY_CNT_82XX;
2933 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2934 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2935 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2936 ha->gid_list_info_size = 8;
2937 ha->optrom_size = OPTROM_SIZE_82XX;
2938 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2939 ha->isp_ops = &qla82xx_isp_ops;
2940 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2941 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2942 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2943 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2944 } else if (IS_QLA8044(ha)) {
2945 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2946 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2947 req_length = REQUEST_ENTRY_CNT_82XX;
2948 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2949 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2950 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2951 ha->gid_list_info_size = 8;
2952 ha->optrom_size = OPTROM_SIZE_83XX;
2953 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2954 ha->isp_ops = &qla8044_isp_ops;
2955 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2956 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2957 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2958 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2959 } else if (IS_QLA83XX(ha)) {
2960 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2961 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2962 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2963 req_length = REQUEST_ENTRY_CNT_83XX;
2964 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2965 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2966 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2967 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2968 ha->gid_list_info_size = 8;
2969 ha->optrom_size = OPTROM_SIZE_83XX;
2970 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2971 ha->isp_ops = &qla83xx_isp_ops;
2972 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2973 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2974 ha->nvram_conf_off = ~0;
2975 ha->nvram_data_off = ~0;
2976 } else if (IS_QLAFX00(ha)) {
2977 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2978 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2979 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2980 req_length = REQUEST_ENTRY_CNT_FX00;
2981 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2982 ha->isp_ops = &qlafx00_isp_ops;
2983 ha->port_down_retry_count = 30; /* default value */
2984 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2985 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2986 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
2987 ha->mr.fw_hbt_en = 1;
2988 ha->mr.host_info_resend = false;
2989 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
2990 } else if (IS_QLA27XX(ha)) {
2991 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2992 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2993 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2994 req_length = REQUEST_ENTRY_CNT_83XX;
2995 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2996 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2997 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2998 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2999 ha->gid_list_info_size = 8;
3000 ha->optrom_size = OPTROM_SIZE_83XX;
3001 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3002 ha->isp_ops = &qla27xx_isp_ops;
3003 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3004 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3005 ha->nvram_conf_off = ~0;
3006 ha->nvram_data_off = ~0;
3007 } else if (IS_QLA28XX(ha)) {
3008 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3009 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3010 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3011 req_length = REQUEST_ENTRY_CNT_24XX;
3012 rsp_length = RESPONSE_ENTRY_CNT_2300;
3013 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3014 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3015 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3016 ha->gid_list_info_size = 8;
3017 ha->optrom_size = OPTROM_SIZE_28XX;
3018 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3019 ha->isp_ops = &qla27xx_isp_ops;
3020 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3021 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3022 ha->nvram_conf_off = ~0;
3023 ha->nvram_data_off = ~0;
3026 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3027 "mbx_count=%d, req_length=%d, "
3028 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3029 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3030 "max_fibre_devices=%d.\n",
3031 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3032 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3033 ha->nvram_npiv_size, ha->max_fibre_devices);
3034 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3035 "isp_ops=%p, flash_conf_off=%d, "
3036 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3037 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3038 ha->nvram_conf_off, ha->nvram_data_off);
3040 /* Configure PCI I/O space */
3041 ret = ha->isp_ops->iospace_config(ha);
3043 goto iospace_config_failed;
3045 ql_log_pci(ql_log_info, pdev, 0x001d,
3046 "Found an ISP%04X irq %d iobase 0x%p.\n",
3047 pdev->device, pdev->irq, ha->iobase);
3048 mutex_init(&ha->vport_lock);
3049 mutex_init(&ha->mq_lock);
3050 init_completion(&ha->mbx_cmd_comp);
3051 complete(&ha->mbx_cmd_comp);
3052 init_completion(&ha->mbx_intr_comp);
3053 init_completion(&ha->dcbx_comp);
3054 init_completion(&ha->lb_portup_comp);
3056 set_bit(0, (unsigned long *) ha->vp_idx_map);
3058 qla2x00_config_dma_addressing(ha);
3059 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3060 "64 Bit addressing is %s.\n",
3061 ha->flags.enable_64bit_addressing ? "enable" :
3063 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3065 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3066 "Failed to allocate memory for adapter, aborting.\n");
3068 goto probe_hw_failed;
3071 req->max_q_depth = MAX_Q_DEPTH;
3072 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3073 req->max_q_depth = ql2xmaxqdepth;
3076 base_vha = qla2x00_create_host(sht, ha);
3079 goto probe_hw_failed;
3082 pci_set_drvdata(pdev, base_vha);
3083 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3085 host = base_vha->host;
3086 base_vha->req = req;
3087 if (IS_QLA2XXX_MIDTYPE(ha))
3088 base_vha->mgmt_svr_loop_id =
3089 qla2x00_reserve_mgmt_server_loop_id(base_vha);
3091 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3094 /* Setup fcport template structure. */
3095 ha->mr.fcport.vha = base_vha;
3096 ha->mr.fcport.port_type = FCT_UNKNOWN;
3097 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3098 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3099 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3100 ha->mr.fcport.scan_state = 1;
3102 /* Set the SG table size based on ISP type */
3103 if (!IS_FWI2_CAPABLE(ha)) {
3105 host->sg_tablesize = 32;
3107 if (!IS_QLA82XX(ha))
3108 host->sg_tablesize = QLA_SG_ALL;
3110 host->max_id = ha->max_fibre_devices;
3111 host->cmd_per_lun = 3;
3112 host->unique_id = host->host_no;
3113 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3114 host->max_cmd_len = 32;
3116 host->max_cmd_len = MAX_CMDSZ;
3117 host->max_channel = MAX_BUSES - 1;
3118 /* Older HBAs support only 16-bit LUNs */
3119 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3120 ql2xmaxlun > 0xffff)
3121 host->max_lun = 0xffff;
3123 host->max_lun = ql2xmaxlun;
3124 host->transportt = qla2xxx_transport_template;
3125 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3127 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3128 "max_id=%d this_id=%d "
3129 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3130 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3131 host->this_id, host->cmd_per_lun, host->unique_id,
3132 host->max_cmd_len, host->max_channel, host->max_lun,
3133 host->transportt, sht->vendor_id);
3135 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3137 /* Set up the irqs */
3138 ret = qla2x00_request_irqs(ha, rsp);
3142 /* Alloc arrays of request and response ring ptrs */
3143 ret = qla2x00_alloc_queues(ha, req, rsp);
3145 ql_log(ql_log_fatal, base_vha, 0x003d,
3146 "Failed to allocate memory for queue pointers..."
3153 /* number of hardware queues supported by blk/scsi-mq*/
3154 host->nr_hw_queues = ha->max_qpairs;
3156 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3157 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3159 if (ql2xnvmeenable) {
3160 host->nr_hw_queues = ha->max_qpairs;
3161 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3162 "FC-NVMe support is enabled, HW queues=%d\n",
3163 host->nr_hw_queues);
3165 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3166 "blk/scsi-mq disabled.\n");
3170 qlt_probe_one_stage1(base_vha, ha);
3172 pci_save_state(pdev);
3174 /* Assign back pointers */
3178 if (IS_QLAFX00(ha)) {
3179 ha->rsp_q_map[0] = rsp;
3180 ha->req_q_map[0] = req;
3181 set_bit(0, ha->req_qid_map);
3182 set_bit(0, ha->rsp_qid_map);
3185 /* FWI2-capable only. */
3186 req->req_q_in = &ha->iobase->isp24.req_q_in;
3187 req->req_q_out = &ha->iobase->isp24.req_q_out;
3188 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3189 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3190 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3192 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3193 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3194 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3195 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3198 if (IS_QLAFX00(ha)) {
3199 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3200 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3201 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3202 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3205 if (IS_P3P_TYPE(ha)) {
3206 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3207 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3208 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3211 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3212 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3213 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3214 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3215 "req->req_q_in=%p req->req_q_out=%p "
3216 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3217 req->req_q_in, req->req_q_out,
3218 rsp->rsp_q_in, rsp->rsp_q_out);
3219 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3220 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3221 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3222 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3223 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3224 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3226 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3227 if (unlikely(!ha->wq)) {
3232 if (ha->isp_ops->initialize_adapter(base_vha)) {
3233 ql_log(ql_log_fatal, base_vha, 0x00d6,
3234 "Failed to initialize adapter - Adapter flags %x.\n",
3235 base_vha->device_flags);
3237 if (IS_QLA82XX(ha)) {
3238 qla82xx_idc_lock(ha);
3239 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3240 QLA8XXX_DEV_FAILED);
3241 qla82xx_idc_unlock(ha);
3242 ql_log(ql_log_fatal, base_vha, 0x00d7,
3243 "HW State: FAILED.\n");
3244 } else if (IS_QLA8044(ha)) {
3245 qla8044_idc_lock(ha);
3246 qla8044_wr_direct(base_vha,
3247 QLA8044_CRB_DEV_STATE_INDEX,
3248 QLA8XXX_DEV_FAILED);
3249 qla8044_idc_unlock(ha);
3250 ql_log(ql_log_fatal, base_vha, 0x0150,
3251 "HW State: FAILED.\n");
3259 host->can_queue = QLAFX00_MAX_CANQUEUE;
3261 host->can_queue = req->num_outstanding_cmds - 10;
3263 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3264 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3265 host->can_queue, base_vha->req,
3266 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3269 bool startit = false;
3271 if (QLA_TGT_MODE_ENABLED())
3274 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
3277 /* Create start of day qpairs for Block MQ */
3278 for (i = 0; i < ha->max_qpairs; i++)
3279 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3282 if (ha->flags.running_gold_fw)
3286 * Startup the kernel thread for this host adapter
3288 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3289 "%s_dpc", base_vha->host_str);
3290 if (IS_ERR(ha->dpc_thread)) {
3291 ql_log(ql_log_fatal, base_vha, 0x00ed,
3292 "Failed to start DPC thread.\n");
3293 ret = PTR_ERR(ha->dpc_thread);
3294 ha->dpc_thread = NULL;
3297 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3298 "DPC thread started successfully.\n");
3301 * If we're not coming up in initiator mode, we might sit for
3302 * a while without waking up the dpc thread, which leads to a
3303 * stuck process warning. So just kick the dpc once here and
3304 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3306 qla2xxx_wake_dpc(base_vha);
3308 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3310 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3311 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3312 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3313 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3315 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3316 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3317 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3318 INIT_WORK(&ha->idc_state_handler,
3319 qla83xx_idc_state_handler_work);
3320 INIT_WORK(&ha->nic_core_unrecoverable,
3321 qla83xx_nic_core_unrecoverable_work);
3325 list_add_tail(&base_vha->list, &ha->vp_list);
3326 base_vha->host->irq = ha->pdev->irq;
3328 /* Initialized the timer */
3329 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3330 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3331 "Started qla2x00_timer with "
3332 "interval=%d.\n", WATCH_INTERVAL);
3333 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3334 "Detected hba at address=%p.\n",
3337 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3338 if (ha->fw_attributes & BIT_4) {
3339 int prot = 0, guard;
3341 base_vha->flags.difdix_supported = 1;
3342 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3343 "Registering for DIF/DIX type 1 and 3 protection.\n");
3344 if (ql2xenabledif == 1)
3345 prot = SHOST_DIX_TYPE0_PROTECTION;
3347 scsi_host_set_prot(host, ql2xprotmask);
3349 scsi_host_set_prot(host,
3350 prot | SHOST_DIF_TYPE1_PROTECTION
3351 | SHOST_DIF_TYPE2_PROTECTION
3352 | SHOST_DIF_TYPE3_PROTECTION
3353 | SHOST_DIX_TYPE1_PROTECTION
3354 | SHOST_DIX_TYPE2_PROTECTION
3355 | SHOST_DIX_TYPE3_PROTECTION);
3357 guard = SHOST_DIX_GUARD_CRC;
3359 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3360 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3361 guard |= SHOST_DIX_GUARD_IP;
3364 scsi_host_set_guard(host, ql2xprotguard);
3366 scsi_host_set_guard(host, guard);
3368 base_vha->flags.difdix_supported = 0;
3371 ha->isp_ops->enable_intrs(ha);
3373 if (IS_QLAFX00(ha)) {
3374 ret = qlafx00_fx_disc(base_vha,
3375 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3376 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3380 ret = scsi_add_host(host, &pdev->dev);
3384 base_vha->flags.init_done = 1;
3385 base_vha->flags.online = 1;
3386 ha->prev_minidump_failed = 0;
3388 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3389 "Init done and hba is online.\n");
3391 if (qla_ini_mode_enabled(base_vha) ||
3392 qla_dual_mode_enabled(base_vha))
3393 scsi_scan_host(host);
3395 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3396 "skipping scsi_scan_host() for non-initiator port\n");
3398 qla2x00_alloc_sysfs_attr(base_vha);
3400 if (IS_QLAFX00(ha)) {
3401 ret = qlafx00_fx_disc(base_vha,
3402 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3404 /* Register system information */
3405 ret = qlafx00_fx_disc(base_vha,
3406 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3409 qla2x00_init_host_attr(base_vha);
3411 qla2x00_dfs_setup(base_vha);
3413 ql_log(ql_log_info, base_vha, 0x00fb,
3414 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3415 ql_log(ql_log_info, base_vha, 0x00fc,
3416 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3417 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3419 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3421 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3423 qlt_add_target(ha, base_vha);
3425 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3427 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3430 if (ha->flags.detected_lr_sfp) {
3431 ql_log(ql_log_info, base_vha, 0xffff,
3432 "Reset chip to pick up LR SFP setting\n");
3433 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3434 qla2xxx_wake_dpc(base_vha);
3440 if (base_vha->gnl.l) {
3441 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3442 base_vha->gnl.l, base_vha->gnl.ldma);
3443 base_vha->gnl.l = NULL;
3446 if (base_vha->timer_active)
3447 qla2x00_stop_timer(base_vha);
3448 base_vha->flags.online = 0;
3449 if (ha->dpc_thread) {
3450 struct task_struct *t = ha->dpc_thread;
3452 ha->dpc_thread = NULL;
3456 qla2x00_free_device(base_vha);
3457 scsi_host_put(base_vha->host);
3459 * Need to NULL out local req/rsp after
3460 * qla2x00_free_device => qla2x00_free_queues frees
3461 * what these are pointing to. Or else we'll
3462 * fall over below in qla2x00_free_req/rsp_que.
3468 qla2x00_mem_free(ha);
3469 qla2x00_free_req_que(ha, req);
3470 qla2x00_free_rsp_que(ha, rsp);
3471 qla2x00_clear_drv_active(ha);
3473 iospace_config_failed:
3474 if (IS_P3P_TYPE(ha)) {
3475 if (!ha->nx_pcibase)
3476 iounmap((device_reg_t *)ha->nx_pcibase);
3478 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3481 iounmap(ha->iobase);
3483 iounmap(ha->cregbase);
3485 pci_release_selected_regions(ha->pdev, ha->bars);
3489 pci_disable_device(pdev);
3494 qla2x00_shutdown(struct pci_dev *pdev)
3496 scsi_qla_host_t *vha;
3497 struct qla_hw_data *ha;
3499 vha = pci_get_drvdata(pdev);
3502 ql_log(ql_log_info, vha, 0xfffa,
3503 "Adapter shutdown\n");
3506 * Prevent future board_disable and wait
3507 * until any pending board_disable has completed.
3509 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3510 cancel_work_sync(&ha->board_disable);
3512 if (!atomic_read(&pdev->enable_cnt))
3515 /* Notify ISPFX00 firmware */
3517 qlafx00_driver_shutdown(vha, 20);
3519 /* Turn-off FCE trace */
3520 if (ha->flags.fce_enabled) {
3521 qla2x00_disable_fce_trace(vha, NULL, NULL);
3522 ha->flags.fce_enabled = 0;
3525 /* Turn-off EFT trace */
3527 qla2x00_disable_eft_trace(vha);
3529 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3531 if (ha->flags.fw_started)
3532 qla2x00_abort_isp_cleanup(vha);
3534 /* Stop currently executing firmware. */
3535 qla2x00_try_to_stop_firmware(vha);
3538 /* Turn adapter off line */
3539 vha->flags.online = 0;
3541 /* turn-off interrupts on the card */
3542 if (ha->interrupts_on) {
3543 vha->flags.init_done = 0;
3544 ha->isp_ops->disable_intrs(ha);
3547 qla2x00_free_irqs(vha);
3549 qla2x00_free_fw_dump(ha);
3551 pci_disable_device(pdev);
3552 ql_log(ql_log_info, vha, 0xfffe,
3553 "Adapter shutdown successfully.\n");
3556 /* Deletes all the virtual ports for a given ha */
3558 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3560 scsi_qla_host_t *vha;
3561 unsigned long flags;
3563 mutex_lock(&ha->vport_lock);
3564 while (ha->cur_vport_count) {
3565 spin_lock_irqsave(&ha->vport_slock, flags);
3567 BUG_ON(base_vha->list.next == &ha->vp_list);
3568 /* This assumes first entry in ha->vp_list is always base vha */
3569 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3570 scsi_host_get(vha->host);
3572 spin_unlock_irqrestore(&ha->vport_slock, flags);
3573 mutex_unlock(&ha->vport_lock);
3575 qla_nvme_delete(vha);
3577 fc_vport_terminate(vha->fc_vport);
3578 scsi_host_put(vha->host);
3580 mutex_lock(&ha->vport_lock);
3582 mutex_unlock(&ha->vport_lock);
3585 /* Stops all deferred work threads */
3587 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3589 /* Cancel all work and destroy DPC workqueues */
3590 if (ha->dpc_lp_wq) {
3591 cancel_work_sync(&ha->idc_aen);
3592 destroy_workqueue(ha->dpc_lp_wq);
3593 ha->dpc_lp_wq = NULL;
3596 if (ha->dpc_hp_wq) {
3597 cancel_work_sync(&ha->nic_core_reset);
3598 cancel_work_sync(&ha->idc_state_handler);
3599 cancel_work_sync(&ha->nic_core_unrecoverable);
3600 destroy_workqueue(ha->dpc_hp_wq);
3601 ha->dpc_hp_wq = NULL;
3604 /* Kill the kernel thread for this host */
3605 if (ha->dpc_thread) {
3606 struct task_struct *t = ha->dpc_thread;
3609 * qla2xxx_wake_dpc checks for ->dpc_thread
3610 * so we need to zero it out.
3612 ha->dpc_thread = NULL;
3618 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3620 if (IS_QLA82XX(ha)) {
3622 iounmap((device_reg_t *)ha->nx_pcibase);
3624 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3627 iounmap(ha->iobase);
3630 iounmap(ha->cregbase);
3633 iounmap(ha->mqiobase);
3635 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3637 iounmap(ha->msixbase);
3642 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3644 if (IS_QLA8044(ha)) {
3645 qla8044_idc_lock(ha);
3646 qla8044_clear_drv_active(ha);
3647 qla8044_idc_unlock(ha);
3648 } else if (IS_QLA82XX(ha)) {
3649 qla82xx_idc_lock(ha);
3650 qla82xx_clear_drv_active(ha);
3651 qla82xx_idc_unlock(ha);
3656 qla2x00_remove_one(struct pci_dev *pdev)
3658 scsi_qla_host_t *base_vha;
3659 struct qla_hw_data *ha;
3661 base_vha = pci_get_drvdata(pdev);
3663 ql_log(ql_log_info, base_vha, 0xb079,
3664 "Removing driver\n");
3666 /* Indicate device removal to prevent future board_disable and wait
3667 * until any pending board_disable has completed. */
3668 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3669 cancel_work_sync(&ha->board_disable);
3672 * If the PCI device is disabled then there was a PCI-disconnect and
3673 * qla2x00_disable_board_on_pci_error has taken care of most of the
3676 if (!atomic_read(&pdev->enable_cnt)) {
3677 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3678 base_vha->gnl.l, base_vha->gnl.ldma);
3679 base_vha->gnl.l = NULL;
3680 scsi_host_put(base_vha->host);
3682 pci_set_drvdata(pdev, NULL);
3685 qla2x00_wait_for_hba_ready(base_vha);
3687 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3689 if (ha->flags.fw_started)
3690 qla2x00_abort_isp_cleanup(base_vha);
3691 } else if (!IS_QLAFX00(ha)) {
3692 if (IS_QLA8031(ha)) {
3693 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3694 "Clearing fcoe driver presence.\n");
3695 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3696 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3697 "Error while clearing DRV-Presence.\n");
3700 qla2x00_try_to_stop_firmware(base_vha);
3703 qla2x00_wait_for_sess_deletion(base_vha);
3706 * if UNLOAD flag is already set, then continue unload,
3707 * where it was set first.
3709 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3712 set_bit(UNLOADING, &base_vha->dpc_flags);
3714 qla_nvme_delete(base_vha);
3716 dma_free_coherent(&ha->pdev->dev,
3717 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3719 base_vha->gnl.l = NULL;
3721 vfree(base_vha->scan.l);
3724 qlafx00_driver_shutdown(base_vha, 20);
3726 qla2x00_delete_all_vps(ha, base_vha);
3728 qla2x00_dfs_remove(base_vha);
3730 qla84xx_put_chip(base_vha);
3733 if (base_vha->timer_active)
3734 qla2x00_stop_timer(base_vha);
3736 base_vha->flags.online = 0;
3738 /* free DMA memory */
3739 if (ha->exlogin_buf)
3740 qla2x00_free_exlogin_buffer(ha);
3742 /* free DMA memory */
3743 if (ha->exchoffld_buf)
3744 qla2x00_free_exchoffld_buffer(ha);
3746 qla2x00_destroy_deferred_work(ha);
3748 qlt_remove_target(ha, base_vha);
3750 qla2x00_free_sysfs_attr(base_vha, true);
3752 fc_remove_host(base_vha->host);
3753 qlt_remove_target_resources(ha);
3755 scsi_remove_host(base_vha->host);
3757 qla2x00_free_device(base_vha);
3759 qla2x00_clear_drv_active(ha);
3761 scsi_host_put(base_vha->host);
3763 qla2x00_unmap_iobases(ha);
3765 pci_release_selected_regions(ha->pdev, ha->bars);
3768 pci_disable_pcie_error_reporting(pdev);
3770 pci_disable_device(pdev);
3774 qla2x00_free_device(scsi_qla_host_t *vha)
3776 struct qla_hw_data *ha = vha->hw;
3778 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3781 if (vha->timer_active)
3782 qla2x00_stop_timer(vha);
3784 qla25xx_delete_queues(vha);
3785 vha->flags.online = 0;
3787 /* turn-off interrupts on the card */
3788 if (ha->interrupts_on) {
3789 vha->flags.init_done = 0;
3790 ha->isp_ops->disable_intrs(ha);
3793 qla2x00_free_fcports(vha);
3795 qla2x00_free_irqs(vha);
3797 /* Flush the work queue and remove it */
3799 flush_workqueue(ha->wq);
3800 destroy_workqueue(ha->wq);
3805 qla2x00_mem_free(ha);
3807 qla82xx_md_free(vha);
3809 qla2x00_free_queues(ha);
3812 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3814 fc_port_t *fcport, *tfcport;
3816 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3817 qla2x00_free_fcport(fcport);
3821 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3824 struct fc_rport *rport;
3825 scsi_qla_host_t *base_vha;
3826 unsigned long flags;
3831 rport = fcport->rport;
3833 base_vha = pci_get_drvdata(vha->hw->pdev);
3834 spin_lock_irqsave(vha->host->host_lock, flags);
3835 fcport->drport = rport;
3836 spin_unlock_irqrestore(vha->host->host_lock, flags);
3837 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
3838 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3839 qla2xxx_wake_dpc(base_vha);
3844 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3845 "%s %8phN. rport %p roles %x\n",
3846 __func__, fcport->port_name, rport,
3848 fc_remote_port_delete(rport);
3850 qlt_do_generation_tick(vha, &now);
3855 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3857 * Input: ha = adapter block pointer. fcport = port structure pointer.
3863 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3864 int do_login, int defer)
3866 if (IS_QLAFX00(vha->hw)) {
3867 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3868 qla2x00_schedule_rport_del(vha, fcport, defer);
3872 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3873 vha->vp_idx == fcport->vha->vp_idx) {
3874 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3875 qla2x00_schedule_rport_del(vha, fcport, defer);
3878 * We may need to retry the login, so don't change the state of the
3879 * port but do the retries.
3881 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3882 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3887 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3891 * qla2x00_mark_all_devices_lost
3892 * Updates fcport state when device goes offline.
3895 * ha = adapter block pointer.
3896 * fcport = port structure pointer.
3904 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3908 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3909 "Mark all dev lost\n");
3911 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3912 fcport->scan_state = 0;
3913 qlt_schedule_sess_for_deletion(fcport);
3915 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3919 * No point in marking the device as lost, if the device is
3922 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3924 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3925 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3927 qla2x00_schedule_rport_del(vha, fcport, defer);
3928 else if (vha->vp_idx == fcport->vha->vp_idx)
3929 qla2x00_schedule_rport_del(vha, fcport, defer);
3934 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
3938 if (IS_FWI2_CAPABLE(ha))
3941 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
3942 set_bit(i, ha->loop_id_map);
3943 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
3944 set_bit(BROADCAST, ha->loop_id_map);
3949 * Allocates adapter memory.
3956 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3957 struct req_que **req, struct rsp_que **rsp)
3961 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3962 &ha->init_cb_dma, GFP_KERNEL);
3966 if (qlt_mem_alloc(ha) < 0)
3967 goto fail_free_init_cb;
3969 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3970 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3972 goto fail_free_tgt_mem;
3974 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3975 if (!ha->srb_mempool)
3976 goto fail_free_gid_list;
3978 if (IS_P3P_TYPE(ha)) {
3979 /* Allocate cache for CT6 Ctx. */
3981 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3982 sizeof(struct ct6_dsd), 0,
3983 SLAB_HWCACHE_ALIGN, NULL);
3985 goto fail_free_srb_mempool;
3987 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3989 if (!ha->ctx_mempool)
3990 goto fail_free_srb_mempool;
3991 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3992 "ctx_cachep=%p ctx_mempool=%p.\n",
3993 ctx_cachep, ha->ctx_mempool);
3996 /* Get memory for cached NVRAM */
3997 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3999 goto fail_free_ctx_mempool;
4001 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4003 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4004 DMA_POOL_SIZE, 8, 0);
4005 if (!ha->s_dma_pool)
4006 goto fail_free_nvram;
4008 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4009 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4010 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4012 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
4013 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4014 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4015 if (!ha->dl_dma_pool) {
4016 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4017 "Failed to allocate memory for dl_dma_pool.\n");
4018 goto fail_s_dma_pool;
4021 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4022 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4023 if (!ha->fcp_cmnd_dma_pool) {
4024 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4025 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4026 goto fail_dl_dma_pool;
4029 if (ql2xenabledif) {
4030 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4031 struct dsd_dma *dsd, *nxt;
4033 /* Creata a DMA pool of buffers for DIF bundling */
4034 ha->dif_bundl_pool = dma_pool_create(name,
4035 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4036 if (!ha->dif_bundl_pool) {
4037 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4038 "%s: failed create dif_bundl_pool\n",
4040 goto fail_dif_bundl_dma_pool;
4043 INIT_LIST_HEAD(&ha->pool.good.head);
4044 INIT_LIST_HEAD(&ha->pool.unusable.head);
4045 ha->pool.good.count = 0;
4046 ha->pool.unusable.count = 0;
4047 for (i = 0; i < 128; i++) {
4048 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4050 ql_dbg_pci(ql_dbg_init, ha->pdev,
4051 0xe0ee, "%s: failed alloc dsd\n",
4055 ha->dif_bundle_kallocs++;
4057 dsd->dsd_addr = dma_pool_alloc(
4058 ha->dif_bundl_pool, GFP_ATOMIC,
4059 &dsd->dsd_list_dma);
4060 if (!dsd->dsd_addr) {
4061 ql_dbg_pci(ql_dbg_init, ha->pdev,
4063 "%s: failed alloc ->dsd_addr\n",
4066 ha->dif_bundle_kallocs--;
4069 ha->dif_bundle_dma_allocs++;
4072 * if DMA buffer crosses 4G boundary,
4073 * put it on bad list
4075 if (MSD(dsd->dsd_list_dma) ^
4076 MSD(dsd->dsd_list_dma + bufsize)) {
4077 list_add_tail(&dsd->list,
4078 &ha->pool.unusable.head);
4079 ha->pool.unusable.count++;
4081 list_add_tail(&dsd->list,
4082 &ha->pool.good.head);
4083 ha->pool.good.count++;
4087 /* return the good ones back to the pool */
4088 list_for_each_entry_safe(dsd, nxt,
4089 &ha->pool.good.head, list) {
4090 list_del(&dsd->list);
4091 dma_pool_free(ha->dif_bundl_pool,
4092 dsd->dsd_addr, dsd->dsd_list_dma);
4093 ha->dif_bundle_dma_allocs--;
4095 ha->dif_bundle_kallocs--;
4098 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4099 "%s: dif dma pool (good=%u unusable=%u)\n",
4100 __func__, ha->pool.good.count,
4101 ha->pool.unusable.count);
4104 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4105 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4106 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4107 ha->dif_bundl_pool);
4110 /* Allocate memory for SNS commands */
4111 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4112 /* Get consistent memory allocated for SNS commands */
4113 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4114 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4117 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4118 "sns_cmd: %p.\n", ha->sns_cmd);
4120 /* Get consistent memory allocated for MS IOCB */
4121 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4125 /* Get consistent memory allocated for CT SNS commands */
4126 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4127 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4129 goto fail_free_ms_iocb;
4130 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4131 "ms_iocb=%p ct_sns=%p.\n",
4132 ha->ms_iocb, ha->ct_sns);
4135 /* Allocate memory for request ring */
4136 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4138 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4139 "Failed to allocate memory for req.\n");
4142 (*req)->length = req_len;
4143 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4144 ((*req)->length + 1) * sizeof(request_t),
4145 &(*req)->dma, GFP_KERNEL);
4146 if (!(*req)->ring) {
4147 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4148 "Failed to allocate memory for req_ring.\n");
4151 /* Allocate memory for response ring */
4152 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4154 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4155 "Failed to allocate memory for rsp.\n");
4159 (*rsp)->length = rsp_len;
4160 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4161 ((*rsp)->length + 1) * sizeof(response_t),
4162 &(*rsp)->dma, GFP_KERNEL);
4163 if (!(*rsp)->ring) {
4164 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4165 "Failed to allocate memory for rsp_ring.\n");
4170 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4171 "req=%p req->length=%d req->ring=%p rsp=%p "
4172 "rsp->length=%d rsp->ring=%p.\n",
4173 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4175 /* Allocate memory for NVRAM data for vports */
4176 if (ha->nvram_npiv_size) {
4177 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4178 sizeof(struct qla_npiv_entry),
4180 if (!ha->npiv_info) {
4181 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4182 "Failed to allocate memory for npiv_info.\n");
4183 goto fail_npiv_info;
4186 ha->npiv_info = NULL;
4188 /* Get consistent memory allocated for EX-INIT-CB. */
4189 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4191 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4192 &ha->ex_init_cb_dma);
4193 if (!ha->ex_init_cb)
4194 goto fail_ex_init_cb;
4195 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4196 "ex_init_cb=%p.\n", ha->ex_init_cb);
4199 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4201 /* Get consistent memory allocated for Async Port-Database. */
4202 if (!IS_FWI2_CAPABLE(ha)) {
4203 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4207 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4208 "async_pd=%p.\n", ha->async_pd);
4211 INIT_LIST_HEAD(&ha->vp_list);
4213 /* Allocate memory for our loop_id bitmap */
4214 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4217 if (!ha->loop_id_map)
4218 goto fail_loop_id_map;
4220 qla2x00_set_reserved_loop_ids(ha);
4221 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4222 "loop_id_map=%p.\n", ha->loop_id_map);
4225 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4226 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4227 if (!ha->sfp_data) {
4228 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4229 "Unable to allocate memory for SFP read-data.\n");
4233 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4234 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4237 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4238 "Unable to allocate memory for FLT.\n");
4239 goto fail_flt_buffer;
4245 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4246 ha->sfp_data, ha->sfp_data_dma);
4248 kfree(ha->loop_id_map);
4250 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4252 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4254 kfree(ha->npiv_info);
4256 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4257 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4258 (*rsp)->ring = NULL;
4264 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4265 sizeof(request_t), (*req)->ring, (*req)->dma);
4266 (*req)->ring = NULL;
4272 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4273 ha->ct_sns, ha->ct_sns_dma);
4277 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4279 ha->ms_iocb_dma = 0;
4282 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4283 ha->sns_cmd, ha->sns_cmd_dma);
4285 if (ql2xenabledif) {
4286 struct dsd_dma *dsd, *nxt;
4288 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4290 list_del(&dsd->list);
4291 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4293 ha->dif_bundle_dma_allocs--;
4295 ha->dif_bundle_kallocs--;
4296 ha->pool.unusable.count--;
4298 dma_pool_destroy(ha->dif_bundl_pool);
4299 ha->dif_bundl_pool = NULL;
4302 fail_dif_bundl_dma_pool:
4303 if (IS_QLA82XX(ha) || ql2xenabledif) {
4304 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4305 ha->fcp_cmnd_dma_pool = NULL;
4308 if (IS_QLA82XX(ha) || ql2xenabledif) {
4309 dma_pool_destroy(ha->dl_dma_pool);
4310 ha->dl_dma_pool = NULL;
4313 dma_pool_destroy(ha->s_dma_pool);
4314 ha->s_dma_pool = NULL;
4318 fail_free_ctx_mempool:
4319 mempool_destroy(ha->ctx_mempool);
4320 ha->ctx_mempool = NULL;
4321 fail_free_srb_mempool:
4322 mempool_destroy(ha->srb_mempool);
4323 ha->srb_mempool = NULL;
4325 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4328 ha->gid_list = NULL;
4329 ha->gid_list_dma = 0;
4333 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4336 ha->init_cb_dma = 0;
4338 ql_log(ql_log_fatal, NULL, 0x0030,
4339 "Memory allocation failure.\n");
4344 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4347 uint16_t size, max_cnt, temp;
4348 struct qla_hw_data *ha = vha->hw;
4350 /* Return if we don't need to alloacate any extended logins */
4354 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4357 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4359 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4360 if (rval != QLA_SUCCESS) {
4361 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4362 "Failed to get exlogin status.\n");
4366 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4369 if (temp != ha->exlogin_size) {
4370 qla2x00_free_exlogin_buffer(ha);
4371 ha->exlogin_size = temp;
4373 ql_log(ql_log_info, vha, 0xd024,
4374 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4375 max_cnt, size, temp);
4377 ql_log(ql_log_info, vha, 0xd025,
4378 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4380 /* Get consistent memory for extended logins */
4381 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4382 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4383 if (!ha->exlogin_buf) {
4384 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4385 "Failed to allocate memory for exlogin_buf_dma.\n");
4390 /* Now configure the dma buffer */
4391 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4393 ql_log(ql_log_fatal, vha, 0xd033,
4394 "Setup extended login buffer ****FAILED****.\n");
4395 qla2x00_free_exlogin_buffer(ha);
4402 * qla2x00_free_exlogin_buffer
4405 * ha = adapter block pointer
4408 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4410 if (ha->exlogin_buf) {
4411 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4412 ha->exlogin_buf, ha->exlogin_buf_dma);
4413 ha->exlogin_buf = NULL;
4414 ha->exlogin_size = 0;
4419 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4422 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
4423 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4425 if (max_cnt > vha->hw->max_exchg)
4426 max_cnt = vha->hw->max_exchg;
4428 if (qla_ini_mode_enabled(vha)) {
4429 if (vha->ql2xiniexchg > max_cnt)
4430 vha->ql2xiniexchg = max_cnt;
4432 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4433 *ret_cnt = vha->ql2xiniexchg;
4435 } else if (qla_tgt_mode_enabled(vha)) {
4436 if (vha->ql2xexchoffld > max_cnt) {
4437 vha->ql2xexchoffld = max_cnt;
4438 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4441 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4442 *ret_cnt = vha->ql2xexchoffld;
4443 } else if (qla_dual_mode_enabled(vha)) {
4444 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4445 if (temp > max_cnt) {
4446 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4447 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4449 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4452 if (temp > FW_DEF_EXCHANGES_CNT)
4458 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4462 u32 actual_cnt, totsz;
4463 struct qla_hw_data *ha = vha->hw;
4465 if (!ha->flags.exchoffld_enabled)
4468 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4472 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4473 if (rval != QLA_SUCCESS) {
4474 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4475 "Failed to get exlogin status.\n");
4479 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4480 ql_log(ql_log_info, vha, 0xd014,
4481 "Actual exchange offload count: %d.\n", actual_cnt);
4483 totsz = actual_cnt * size;
4485 if (totsz != ha->exchoffld_size) {
4486 qla2x00_free_exchoffld_buffer(ha);
4487 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4488 ha->exchoffld_size = 0;
4489 ha->flags.exchoffld_enabled = 0;
4493 ha->exchoffld_size = totsz;
4495 ql_log(ql_log_info, vha, 0xd016,
4496 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4497 max_cnt, actual_cnt, size, totsz);
4499 ql_log(ql_log_info, vha, 0xd017,
4500 "Exchange Buffers requested size = 0x%x\n",
4501 ha->exchoffld_size);
4503 /* Get consistent memory for extended logins */
4504 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4505 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4506 if (!ha->exchoffld_buf) {
4507 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4508 "Failed to allocate memory for Exchange Offload.\n");
4511 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4512 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4513 } else if (ha->max_exchg >
4514 (FW_DEF_EXCHANGES_CNT + 512)) {
4515 ha->max_exchg -= 512;
4517 ha->flags.exchoffld_enabled = 0;
4518 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4519 "Disabling Exchange offload due to lack of memory\n");
4521 ha->exchoffld_size = 0;
4525 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4526 /* pathological case */
4527 qla2x00_free_exchoffld_buffer(ha);
4528 ha->exchoffld_size = 0;
4529 ha->flags.exchoffld_enabled = 0;
4530 ql_log(ql_log_info, vha, 0xd016,
4531 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4532 ha->exchoffld_size, actual_cnt, size, totsz);
4536 /* Now configure the dma buffer */
4537 rval = qla_set_exchoffld_mem_cfg(vha);
4539 ql_log(ql_log_fatal, vha, 0xd02e,
4540 "Setup exchange offload buffer ****FAILED****.\n");
4541 qla2x00_free_exchoffld_buffer(ha);
4543 /* re-adjust number of target exchange */
4544 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4546 if (qla_ini_mode_enabled(vha))
4547 icb->exchange_count = 0;
4549 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4556 * qla2x00_free_exchoffld_buffer
4559 * ha = adapter block pointer
4562 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4564 if (ha->exchoffld_buf) {
4565 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4566 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4567 ha->exchoffld_buf = NULL;
4568 ha->exchoffld_size = 0;
4573 * qla2x00_free_fw_dump
4574 * Frees fw dump stuff.
4577 * ha = adapter block pointer
4580 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4582 struct fwdt *fwdt = ha->fwdt;
4586 dma_free_coherent(&ha->pdev->dev,
4587 FCE_SIZE, ha->fce, ha->fce_dma);
4590 dma_free_coherent(&ha->pdev->dev,
4591 EFT_SIZE, ha->eft, ha->eft_dma);
4598 ha->flags.fce_enabled = 0;
4602 ha->fw_dump_cap_flags = 0;
4603 ha->fw_dump_reading = 0;
4605 ha->fw_dump_len = 0;
4607 for (j = 0; j < 2; j++, fwdt++) {
4609 vfree(fwdt->template);
4610 fwdt->template = NULL;
4617 * Frees all adapter allocated memory.
4620 * ha = adapter block pointer.
4623 qla2x00_mem_free(struct qla_hw_data *ha)
4625 qla2x00_free_fw_dump(ha);
4628 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4630 ha->mctp_dump = NULL;
4632 mempool_destroy(ha->srb_mempool);
4633 ha->srb_mempool = NULL;
4636 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4637 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4638 ha->dcbx_tlv = NULL;
4641 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4642 ha->xgmac_data, ha->xgmac_data_dma);
4643 ha->xgmac_data = NULL;
4646 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4647 ha->sns_cmd, ha->sns_cmd_dma);
4649 ha->sns_cmd_dma = 0;
4652 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4653 ha->ct_sns, ha->ct_sns_dma);
4658 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4660 ha->sfp_data = NULL;
4663 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4664 ha->flt, ha->flt_dma);
4669 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4671 ha->ms_iocb_dma = 0;
4674 dma_pool_free(ha->s_dma_pool,
4675 ha->ex_init_cb, ha->ex_init_cb_dma);
4676 ha->ex_init_cb = NULL;
4677 ha->ex_init_cb_dma = 0;
4680 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4681 ha->async_pd = NULL;
4682 ha->async_pd_dma = 0;
4684 dma_pool_destroy(ha->s_dma_pool);
4685 ha->s_dma_pool = NULL;
4688 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4689 ha->gid_list, ha->gid_list_dma);
4690 ha->gid_list = NULL;
4691 ha->gid_list_dma = 0;
4693 if (IS_QLA82XX(ha)) {
4694 if (!list_empty(&ha->gbl_dsd_list)) {
4695 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4697 /* clean up allocated prev pool */
4698 list_for_each_entry_safe(dsd_ptr,
4699 tdsd_ptr, &ha->gbl_dsd_list, list) {
4700 dma_pool_free(ha->dl_dma_pool,
4701 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4702 list_del(&dsd_ptr->list);
4708 dma_pool_destroy(ha->dl_dma_pool);
4709 ha->dl_dma_pool = NULL;
4711 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4712 ha->fcp_cmnd_dma_pool = NULL;
4714 mempool_destroy(ha->ctx_mempool);
4715 ha->ctx_mempool = NULL;
4717 if (ql2xenabledif && ha->dif_bundl_pool) {
4718 struct dsd_dma *dsd, *nxt;
4720 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4722 list_del(&dsd->list);
4723 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4725 ha->dif_bundle_dma_allocs--;
4727 ha->dif_bundle_kallocs--;
4728 ha->pool.unusable.count--;
4730 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4731 list_del(&dsd->list);
4732 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4734 ha->dif_bundle_dma_allocs--;
4736 ha->dif_bundle_kallocs--;
4740 dma_pool_destroy(ha->dif_bundl_pool);
4741 ha->dif_bundl_pool = NULL;
4746 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
4747 ha->init_cb, ha->init_cb_dma);
4749 ha->init_cb_dma = 0;
4751 vfree(ha->optrom_buffer);
4752 ha->optrom_buffer = NULL;
4755 kfree(ha->npiv_info);
4756 ha->npiv_info = NULL;
4759 kfree(ha->loop_id_map);
4760 ha->loop_id_map = NULL;
4763 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4764 struct qla_hw_data *ha)
4766 struct Scsi_Host *host;
4767 struct scsi_qla_host *vha = NULL;
4769 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4771 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4772 "Failed to allocate host from the scsi layer, aborting.\n");
4776 /* Clear our data area */
4777 vha = shost_priv(host);
4778 memset(vha, 0, sizeof(scsi_qla_host_t));
4781 vha->host_no = host->host_no;
4784 vha->qlini_mode = ql2x_ini_mode;
4785 vha->ql2xexchoffld = ql2xexchoffld;
4786 vha->ql2xiniexchg = ql2xiniexchg;
4788 INIT_LIST_HEAD(&vha->vp_fcports);
4789 INIT_LIST_HEAD(&vha->work_list);
4790 INIT_LIST_HEAD(&vha->list);
4791 INIT_LIST_HEAD(&vha->qla_cmd_list);
4792 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
4793 INIT_LIST_HEAD(&vha->logo_list);
4794 INIT_LIST_HEAD(&vha->plogi_ack_list);
4795 INIT_LIST_HEAD(&vha->qp_list);
4796 INIT_LIST_HEAD(&vha->gnl.fcports);
4797 INIT_LIST_HEAD(&vha->gpnid_list);
4798 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
4800 spin_lock_init(&vha->work_lock);
4801 spin_lock_init(&vha->cmd_list_lock);
4802 init_waitqueue_head(&vha->fcport_waitQ);
4803 init_waitqueue_head(&vha->vref_waitq);
4805 vha->gnl.size = sizeof(struct get_name_list_extended) *
4806 (ha->max_loop_id + 1);
4807 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4808 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4810 ql_log(ql_log_fatal, vha, 0xd04a,
4811 "Alloc failed for name list.\n");
4812 scsi_host_put(vha->host);
4816 /* todo: what about ext login? */
4817 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4818 vha->scan.l = vmalloc(vha->scan.size);
4820 ql_log(ql_log_fatal, vha, 0xd04a,
4821 "Alloc failed for scan database.\n");
4822 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4823 vha->gnl.l, vha->gnl.ldma);
4825 scsi_host_put(vha->host);
4828 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
4830 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
4831 ql_dbg(ql_dbg_init, vha, 0x0041,
4832 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4833 vha->host, vha->hw, vha,
4834 dev_name(&(ha->pdev->dev)));
4839 struct qla_work_evt *
4840 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
4842 struct qla_work_evt *e;
4845 QLA_VHA_MARK_BUSY(vha, bail);
4849 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
4851 QLA_VHA_MARK_NOT_BUSY(vha);
4855 INIT_LIST_HEAD(&e->list);
4857 e->flags = QLA_EVT_FLAG_FREE;
4862 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
4864 unsigned long flags;
4867 spin_lock_irqsave(&vha->work_lock, flags);
4868 list_add_tail(&e->list, &vha->work_list);
4870 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4873 spin_unlock_irqrestore(&vha->work_lock, flags);
4876 queue_work(vha->hw->wq, &vha->iocb_work);
4882 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
4885 struct qla_work_evt *e;
4887 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
4889 return QLA_FUNCTION_FAILED;
4891 e->u.aen.code = code;
4892 e->u.aen.data = data;
4893 return qla2x00_post_work(vha, e);
4897 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4899 struct qla_work_evt *e;
4901 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
4903 return QLA_FUNCTION_FAILED;
4905 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4906 return qla2x00_post_work(vha, e);
4909 #define qla2x00_post_async_work(name, type) \
4910 int qla2x00_post_async_##name##_work( \
4911 struct scsi_qla_host *vha, \
4912 fc_port_t *fcport, uint16_t *data) \
4914 struct qla_work_evt *e; \
4916 e = qla2x00_alloc_work(vha, type); \
4918 return QLA_FUNCTION_FAILED; \
4920 e->u.logio.fcport = fcport; \
4922 e->u.logio.data[0] = data[0]; \
4923 e->u.logio.data[1] = data[1]; \
4925 fcport->flags |= FCF_ASYNC_ACTIVE; \
4926 return qla2x00_post_work(vha, e); \
4929 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4930 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4931 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
4932 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4933 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4934 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
4937 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4939 struct qla_work_evt *e;
4941 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4943 return QLA_FUNCTION_FAILED;
4945 e->u.uevent.code = code;
4946 return qla2x00_post_work(vha, e);
4950 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4952 char event_string[40];
4953 char *envp[] = { event_string, NULL };
4956 case QLA_UEVENT_CODE_FW_DUMP:
4957 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4964 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4968 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4969 uint32_t *data, int cnt)
4971 struct qla_work_evt *e;
4973 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4975 return QLA_FUNCTION_FAILED;
4977 e->u.aenfx.evtcode = evtcode;
4978 e->u.aenfx.count = cnt;
4979 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4980 return qla2x00_post_work(vha, e);
4983 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
4985 unsigned long flags;
4987 if (IS_SW_RESV_ADDR(fcport->d_id))
4990 spin_lock_irqsave(&fcport->vha->work_lock, flags);
4991 if (fcport->disc_state == DSC_UPD_FCPORT) {
4992 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
4995 fcport->jiffies_at_registration = jiffies;
4996 fcport->sec_since_registration = 0;
4997 fcport->next_disc_state = DSC_DELETED;
4998 fcport->disc_state = DSC_UPD_FCPORT;
4999 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5001 queue_work(system_unbound_wq, &fcport->reg_work);
5005 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5007 unsigned long flags;
5008 fc_port_t *fcport = NULL, *tfcp;
5009 struct qlt_plogi_ack_t *pla =
5010 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
5011 uint8_t free_fcport = 0;
5013 ql_dbg(ql_dbg_disc, vha, 0xffff,
5014 "%s %d %8phC enter\n",
5015 __func__, __LINE__, e->u.new_sess.port_name);
5017 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5018 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5020 fcport->d_id = e->u.new_sess.id;
5022 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5023 memcpy(fcport->node_name,
5024 pla->iocb.u.isp24.u.plogi.node_name,
5026 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5027 /* we took an extra ref_count to prevent PLOGI ACK when
5028 * fcport/sess has not been created.
5033 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5034 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5036 fcport->d_id = e->u.new_sess.id;
5037 fcport->flags |= FCF_FABRIC_DEVICE;
5038 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
5039 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP)
5040 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
5042 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) {
5043 fcport->fc4_type = FC4_TYPE_OTHER;
5044 fcport->fc4f_nvme = FC4_TYPE_NVME;
5047 memcpy(fcport->port_name, e->u.new_sess.port_name,
5050 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N)
5051 fcport->n2n_flag = 1;
5054 ql_dbg(ql_dbg_disc, vha, 0xffff,
5055 "%s %8phC mem alloc fail.\n",
5056 __func__, e->u.new_sess.port_name);
5059 list_del(&pla->list);
5060 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5065 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5066 /* search again to make sure no one else got ahead */
5067 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5068 e->u.new_sess.port_name, 1);
5070 /* should rarily happen */
5071 ql_dbg(ql_dbg_disc, vha, 0xffff,
5072 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5073 __func__, tfcp->port_name, tfcp->disc_state,
5074 tfcp->fw_login_state);
5078 list_add_tail(&fcport->list, &vha->vp_fcports);
5082 qlt_plogi_ack_link(vha, pla, fcport,
5083 QLT_PLOGI_LINK_SAME_WWN);
5087 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5090 fcport->id_changed = 1;
5091 fcport->scan_state = QLA_FCPORT_FOUND;
5092 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5093 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5096 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5099 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5103 pla->iocb.u.isp24.nport_handle);
5104 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5107 pla->iocb.u.isp24.u.prli.wd3_lo);
5110 fcport->conf_compl_supported = 1;
5112 if ((wd3_lo & BIT_4) == 0)
5113 fcport->port_type = FCT_INITIATOR;
5115 fcport->port_type = FCT_TARGET;
5117 qlt_plogi_ack_unref(vha, pla);
5119 fc_port_t *dfcp = NULL;
5121 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5122 tfcp = qla2x00_find_fcport_by_nportid(vha,
5123 &e->u.new_sess.id, 1);
5124 if (tfcp && (tfcp != fcport)) {
5126 * We have a conflict fcport with same NportID.
5128 ql_dbg(ql_dbg_disc, vha, 0xffff,
5129 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5130 __func__, tfcp->port_name, tfcp->disc_state,
5131 tfcp->fw_login_state);
5133 switch (tfcp->disc_state) {
5136 case DSC_DELETE_PEND:
5137 fcport->login_pause = 1;
5138 tfcp->conflict = fcport;
5141 fcport->login_pause = 1;
5142 tfcp->conflict = fcport;
5147 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5149 qlt_schedule_sess_for_deletion(tfcp);
5151 if (N2N_TOPO(vha->hw)) {
5152 fcport->flags &= ~FCF_FABRIC_DEVICE;
5153 fcport->keep_nport_handle = 1;
5154 if (vha->flags.nvme_enabled) {
5155 fcport->fc4f_nvme = 1;
5156 fcport->n2n_flag = 1;
5158 fcport->fw_login_state = 0;
5160 * wait link init done before sending login
5163 qla24xx_fcport_handle_login(vha, fcport);
5169 qla2x00_free_fcport(fcport);
5171 list_del(&pla->list);
5172 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5177 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5179 struct srb *sp = e->u.iosb.sp;
5182 rval = qla2x00_start_sp(sp);
5183 if (rval != QLA_SUCCESS) {
5184 ql_dbg(ql_dbg_disc, vha, 0x2043,
5185 "%s: %s: Re-issue IOCB failed (%d).\n",
5186 __func__, sp->name, rval);
5187 qla24xx_sp_unmap(vha, sp);
5192 qla2x00_do_work(struct scsi_qla_host *vha)
5194 struct qla_work_evt *e, *tmp;
5195 unsigned long flags;
5199 spin_lock_irqsave(&vha->work_lock, flags);
5200 list_splice_init(&vha->work_list, &work);
5201 spin_unlock_irqrestore(&vha->work_lock, flags);
5203 list_for_each_entry_safe(e, tmp, &work, list) {
5207 fc_host_post_event(vha->host, fc_get_event_number(),
5208 e->u.aen.code, e->u.aen.data);
5210 case QLA_EVT_IDC_ACK:
5211 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5213 case QLA_EVT_ASYNC_LOGIN:
5214 qla2x00_async_login(vha, e->u.logio.fcport,
5217 case QLA_EVT_ASYNC_LOGOUT:
5218 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
5220 case QLA_EVT_ASYNC_LOGOUT_DONE:
5221 qla2x00_async_logout_done(vha, e->u.logio.fcport,
5224 case QLA_EVT_ASYNC_ADISC:
5225 qla2x00_async_adisc(vha, e->u.logio.fcport,
5228 case QLA_EVT_UEVENT:
5229 qla2x00_uevent_emit(vha, e->u.uevent.code);
5232 qlafx00_process_aen(vha, e);
5235 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5238 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5240 case QLA_EVT_RELOGIN:
5241 qla2x00_relogin(vha);
5243 case QLA_EVT_NEW_SESS:
5244 qla24xx_create_new_sess(vha, e);
5247 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5251 qla24xx_async_prli(vha, e->u.fcport.fcport);
5254 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5257 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5260 qla24xx_do_nack_work(vha, e);
5262 case QLA_EVT_ASYNC_PRLO:
5263 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
5265 case QLA_EVT_ASYNC_PRLO_DONE:
5266 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5270 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5273 case QLA_EVT_GPNFT_DONE:
5274 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5276 case QLA_EVT_GNNFT_DONE:
5277 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5280 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5282 case QLA_EVT_GFPNID:
5283 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5285 case QLA_EVT_SP_RETRY:
5286 qla_sp_retry(vha, e);
5289 qla_do_iidma_work(vha, e->u.fcport.fcport);
5291 case QLA_EVT_ELS_PLOGI:
5292 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5293 e->u.fcport.fcport, false);
5298 /* put 'work' at head of 'vha->work_list' */
5299 spin_lock_irqsave(&vha->work_lock, flags);
5300 list_splice(&work, &vha->work_list);
5301 spin_unlock_irqrestore(&vha->work_lock, flags);
5304 list_del_init(&e->list);
5305 if (e->flags & QLA_EVT_FLAG_FREE)
5308 /* For each work completed decrement vha ref count */
5309 QLA_VHA_MARK_NOT_BUSY(vha);
5313 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5315 struct qla_work_evt *e;
5317 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5320 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5321 return QLA_FUNCTION_FAILED;
5324 return qla2x00_post_work(vha, e);
5327 /* Relogins all the fcports of a vport
5328 * Context: dpc thread
5330 void qla2x00_relogin(struct scsi_qla_host *vha)
5333 int status, relogin_needed = 0;
5334 struct event_arg ea;
5336 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5338 * If the port is not ONLINE then try to login
5339 * to it if we haven't run out of retries.
5341 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5342 fcport->login_retry) {
5343 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5344 fcport->disc_state == DSC_LOGIN_COMPLETE)
5347 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5348 fcport->disc_state == DSC_DELETE_PEND) {
5351 if (vha->hw->current_topology != ISP_CFG_NL) {
5352 memset(&ea, 0, sizeof(ea));
5354 qla24xx_handle_relogin_event(vha, &ea);
5355 } else if (vha->hw->current_topology ==
5357 fcport->login_retry--;
5359 qla2x00_local_device_login(vha,
5361 if (status == QLA_SUCCESS) {
5362 fcport->old_loop_id =
5364 ql_dbg(ql_dbg_disc, vha, 0x2003,
5365 "Port login OK: logged in ID 0x%x.\n",
5367 qla2x00_update_fcport
5369 } else if (status == 1) {
5370 set_bit(RELOGIN_NEEDED,
5372 /* retry the login again */
5373 ql_dbg(ql_dbg_disc, vha, 0x2007,
5374 "Retrying %d login again loop_id 0x%x.\n",
5375 fcport->login_retry,
5378 fcport->login_retry = 0;
5381 if (fcport->login_retry == 0 &&
5382 status != QLA_SUCCESS)
5383 qla2x00_clear_loop_id(fcport);
5387 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5392 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5394 ql_dbg(ql_dbg_disc, vha, 0x400e,
5398 /* Schedule work on any of the dpc-workqueues */
5400 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5402 struct qla_hw_data *ha = base_vha->hw;
5404 switch (work_code) {
5405 case MBA_IDC_AEN: /* 0x8200 */
5407 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5410 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5411 if (!ha->flags.nic_core_reset_hdlr_active) {
5413 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5415 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5416 "NIC Core reset is already active. Skip "
5417 "scheduling it again.\n");
5419 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5421 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5423 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5425 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5428 ql_log(ql_log_warn, base_vha, 0xb05f,
5429 "Unknown work-code=0x%x.\n", work_code);
5435 /* Work: Perform NIC Core Unrecoverable state handling */
5437 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5439 struct qla_hw_data *ha =
5440 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5441 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5442 uint32_t dev_state = 0;
5444 qla83xx_idc_lock(base_vha, 0);
5445 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5446 qla83xx_reset_ownership(base_vha);
5447 if (ha->flags.nic_core_reset_owner) {
5448 ha->flags.nic_core_reset_owner = 0;
5449 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5450 QLA8XXX_DEV_FAILED);
5451 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5452 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5454 qla83xx_idc_unlock(base_vha, 0);
5457 /* Work: Execute IDC state handler */
5459 qla83xx_idc_state_handler_work(struct work_struct *work)
5461 struct qla_hw_data *ha =
5462 container_of(work, struct qla_hw_data, idc_state_handler);
5463 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5464 uint32_t dev_state = 0;
5466 qla83xx_idc_lock(base_vha, 0);
5467 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5468 if (dev_state == QLA8XXX_DEV_FAILED ||
5469 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5470 qla83xx_idc_state_handler(base_vha);
5471 qla83xx_idc_unlock(base_vha, 0);
5475 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5477 int rval = QLA_SUCCESS;
5478 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5479 uint32_t heart_beat_counter1, heart_beat_counter2;
5482 if (time_after(jiffies, heart_beat_wait)) {
5483 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5484 "Nic Core f/w is not alive.\n");
5485 rval = QLA_FUNCTION_FAILED;
5489 qla83xx_idc_lock(base_vha, 0);
5490 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5491 &heart_beat_counter1);
5492 qla83xx_idc_unlock(base_vha, 0);
5494 qla83xx_idc_lock(base_vha, 0);
5495 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5496 &heart_beat_counter2);
5497 qla83xx_idc_unlock(base_vha, 0);
5498 } while (heart_beat_counter1 == heart_beat_counter2);
5503 /* Work: Perform NIC Core Reset handling */
5505 qla83xx_nic_core_reset_work(struct work_struct *work)
5507 struct qla_hw_data *ha =
5508 container_of(work, struct qla_hw_data, nic_core_reset);
5509 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5510 uint32_t dev_state = 0;
5512 if (IS_QLA2031(ha)) {
5513 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5514 ql_log(ql_log_warn, base_vha, 0xb081,
5515 "Failed to dump mctp\n");
5519 if (!ha->flags.nic_core_reset_hdlr_active) {
5520 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5521 qla83xx_idc_lock(base_vha, 0);
5522 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5524 qla83xx_idc_unlock(base_vha, 0);
5525 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5526 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5527 "Nic Core f/w is alive.\n");
5532 ha->flags.nic_core_reset_hdlr_active = 1;
5533 if (qla83xx_nic_core_reset(base_vha)) {
5534 /* NIC Core reset failed. */
5535 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5536 "NIC Core reset failed.\n");
5538 ha->flags.nic_core_reset_hdlr_active = 0;
5542 /* Work: Handle 8200 IDC aens */
5544 qla83xx_service_idc_aen(struct work_struct *work)
5546 struct qla_hw_data *ha =
5547 container_of(work, struct qla_hw_data, idc_aen);
5548 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5549 uint32_t dev_state, idc_control;
5551 qla83xx_idc_lock(base_vha, 0);
5552 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5553 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5554 qla83xx_idc_unlock(base_vha, 0);
5555 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5556 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5557 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5558 "Application requested NIC Core Reset.\n");
5559 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5560 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5562 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5563 "Other protocol driver requested NIC Core Reset.\n");
5564 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5566 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5567 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5568 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5573 qla83xx_wait_logic(void)
5578 if (!in_interrupt()) {
5580 * Wait about 200ms before retrying again.
5581 * This controls the number of retries for single
5587 for (i = 0; i < 20; i++)
5588 cpu_relax(); /* This a nop instr on i386 */
5593 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5597 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5598 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5599 struct qla_hw_data *ha = base_vha->hw;
5601 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5602 "Trying force recovery of the IDC lock.\n");
5604 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5608 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5611 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5612 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5619 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5624 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5625 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5626 ~(idc_lck_rcvry_stage_mask));
5627 rval = qla83xx_wr_reg(base_vha,
5628 QLA83XX_IDC_LOCK_RECOVERY, data);
5632 /* Forcefully perform IDC UnLock */
5633 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5637 /* Clear lock-id by setting 0xff */
5638 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5642 /* Clear lock-recovery by setting 0x0 */
5643 rval = qla83xx_wr_reg(base_vha,
5644 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5655 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5657 int rval = QLA_SUCCESS;
5658 uint32_t o_drv_lockid, n_drv_lockid;
5659 unsigned long lock_recovery_timeout;
5661 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5663 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5667 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5668 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5669 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5672 return QLA_FUNCTION_FAILED;
5675 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5679 if (o_drv_lockid == n_drv_lockid) {
5680 qla83xx_wait_logic();
5690 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5693 uint32_t lock_owner;
5694 struct qla_hw_data *ha = base_vha->hw;
5696 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5698 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5701 /* Setting lock-id to our function-number */
5702 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5705 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5707 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5708 "Failed to acquire IDC lock, acquired by %d, "
5709 "retrying...\n", lock_owner);
5711 /* Retry/Perform IDC-Lock recovery */
5712 if (qla83xx_idc_lock_recovery(base_vha)
5714 qla83xx_wait_logic();
5717 ql_log(ql_log_warn, base_vha, 0xb075,
5718 "IDC Lock recovery FAILED.\n");
5727 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5730 uint16_t options = (requester_id << 15) | BIT_7;
5734 struct qla_hw_data *ha = base_vha->hw;
5736 /* IDC-unlock implementation using driver-unlock/lock-id
5741 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5743 if (data == ha->portnum) {
5744 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5745 /* Clearing lock-id by setting 0xff */
5746 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5747 } else if (retry < 10) {
5748 /* SV: XXX: IDC unlock retrying needed here? */
5750 /* Retry for IDC-unlock */
5751 qla83xx_wait_logic();
5753 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
5754 "Failed to release IDC lock, retrying=%d\n", retry);
5757 } else if (retry < 10) {
5758 /* Retry for IDC-unlock */
5759 qla83xx_wait_logic();
5761 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
5762 "Failed to read drv-lockid, retrying=%d\n", retry);
5769 /* XXX: IDC-unlock implementation using access-control mbx */
5772 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5774 /* Retry for IDC-unlock */
5775 qla83xx_wait_logic();
5777 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
5778 "Failed to release IDC lock, retrying=%d\n", retry);
5788 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5790 int rval = QLA_SUCCESS;
5791 struct qla_hw_data *ha = vha->hw;
5792 uint32_t drv_presence;
5794 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5795 if (rval == QLA_SUCCESS) {
5796 drv_presence |= (1 << ha->portnum);
5797 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5805 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5807 int rval = QLA_SUCCESS;
5809 qla83xx_idc_lock(vha, 0);
5810 rval = __qla83xx_set_drv_presence(vha);
5811 qla83xx_idc_unlock(vha, 0);
5817 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5819 int rval = QLA_SUCCESS;
5820 struct qla_hw_data *ha = vha->hw;
5821 uint32_t drv_presence;
5823 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5824 if (rval == QLA_SUCCESS) {
5825 drv_presence &= ~(1 << ha->portnum);
5826 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5834 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5836 int rval = QLA_SUCCESS;
5838 qla83xx_idc_lock(vha, 0);
5839 rval = __qla83xx_clear_drv_presence(vha);
5840 qla83xx_idc_unlock(vha, 0);
5846 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5848 struct qla_hw_data *ha = vha->hw;
5849 uint32_t drv_ack, drv_presence;
5850 unsigned long ack_timeout;
5852 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5853 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5855 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5856 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5857 if ((drv_ack & drv_presence) == drv_presence)
5860 if (time_after_eq(jiffies, ack_timeout)) {
5861 ql_log(ql_log_warn, vha, 0xb067,
5862 "RESET ACK TIMEOUT! drv_presence=0x%x "
5863 "drv_ack=0x%x\n", drv_presence, drv_ack);
5865 * The function(s) which did not ack in time are forced
5866 * to withdraw any further participation in the IDC
5869 if (drv_ack != drv_presence)
5870 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5875 qla83xx_idc_unlock(vha, 0);
5877 qla83xx_idc_lock(vha, 0);
5880 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5881 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5885 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5887 int rval = QLA_SUCCESS;
5888 uint32_t idc_control;
5890 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5891 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5893 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5894 __qla83xx_get_idc_control(vha, &idc_control);
5895 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5896 __qla83xx_set_idc_control(vha, 0);
5898 qla83xx_idc_unlock(vha, 0);
5899 rval = qla83xx_restart_nic_firmware(vha);
5900 qla83xx_idc_lock(vha, 0);
5902 if (rval != QLA_SUCCESS) {
5903 ql_log(ql_log_fatal, vha, 0xb06a,
5904 "Failed to restart NIC f/w.\n");
5905 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5906 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5908 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5909 "Success in restarting nic f/w.\n");
5910 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5911 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5917 /* Assumes idc_lock always held on entry */
5919 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5921 struct qla_hw_data *ha = base_vha->hw;
5922 int rval = QLA_SUCCESS;
5923 unsigned long dev_init_timeout;
5926 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5927 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5931 if (time_after_eq(jiffies, dev_init_timeout)) {
5932 ql_log(ql_log_warn, base_vha, 0xb06e,
5933 "Initialization TIMEOUT!\n");
5934 /* Init timeout. Disable further NIC Core
5937 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5938 QLA8XXX_DEV_FAILED);
5939 ql_log(ql_log_info, base_vha, 0xb06f,
5940 "HW State: FAILED.\n");
5943 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5944 switch (dev_state) {
5945 case QLA8XXX_DEV_READY:
5946 if (ha->flags.nic_core_reset_owner)
5947 qla83xx_idc_audit(base_vha,
5948 IDC_AUDIT_COMPLETION);
5949 ha->flags.nic_core_reset_owner = 0;
5950 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5951 "Reset_owner reset by 0x%x.\n",
5954 case QLA8XXX_DEV_COLD:
5955 if (ha->flags.nic_core_reset_owner)
5956 rval = qla83xx_device_bootstrap(base_vha);
5958 /* Wait for AEN to change device-state */
5959 qla83xx_idc_unlock(base_vha, 0);
5961 qla83xx_idc_lock(base_vha, 0);
5964 case QLA8XXX_DEV_INITIALIZING:
5965 /* Wait for AEN to change device-state */
5966 qla83xx_idc_unlock(base_vha, 0);
5968 qla83xx_idc_lock(base_vha, 0);
5970 case QLA8XXX_DEV_NEED_RESET:
5971 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5972 qla83xx_need_reset_handler(base_vha);
5974 /* Wait for AEN to change device-state */
5975 qla83xx_idc_unlock(base_vha, 0);
5977 qla83xx_idc_lock(base_vha, 0);
5979 /* reset timeout value after need reset handler */
5980 dev_init_timeout = jiffies +
5981 (ha->fcoe_dev_init_timeout * HZ);
5983 case QLA8XXX_DEV_NEED_QUIESCENT:
5984 /* XXX: DEBUG for now */
5985 qla83xx_idc_unlock(base_vha, 0);
5987 qla83xx_idc_lock(base_vha, 0);
5989 case QLA8XXX_DEV_QUIESCENT:
5990 /* XXX: DEBUG for now */
5991 if (ha->flags.quiesce_owner)
5994 qla83xx_idc_unlock(base_vha, 0);
5996 qla83xx_idc_lock(base_vha, 0);
5997 dev_init_timeout = jiffies +
5998 (ha->fcoe_dev_init_timeout * HZ);
6000 case QLA8XXX_DEV_FAILED:
6001 if (ha->flags.nic_core_reset_owner)
6002 qla83xx_idc_audit(base_vha,
6003 IDC_AUDIT_COMPLETION);
6004 ha->flags.nic_core_reset_owner = 0;
6005 __qla83xx_clear_drv_presence(base_vha);
6006 qla83xx_idc_unlock(base_vha, 0);
6007 qla8xxx_dev_failed_handler(base_vha);
6008 rval = QLA_FUNCTION_FAILED;
6009 qla83xx_idc_lock(base_vha, 0);
6011 case QLA8XXX_BAD_VALUE:
6012 qla83xx_idc_unlock(base_vha, 0);
6014 qla83xx_idc_lock(base_vha, 0);
6017 ql_log(ql_log_warn, base_vha, 0xb071,
6018 "Unknown Device State: %x.\n", dev_state);
6019 qla83xx_idc_unlock(base_vha, 0);
6020 qla8xxx_dev_failed_handler(base_vha);
6021 rval = QLA_FUNCTION_FAILED;
6022 qla83xx_idc_lock(base_vha, 0);
6032 qla2x00_disable_board_on_pci_error(struct work_struct *work)
6034 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6036 struct pci_dev *pdev = ha->pdev;
6037 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6040 * if UNLOAD flag is already set, then continue unload,
6041 * where it was set first.
6043 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6046 ql_log(ql_log_warn, base_vha, 0x015b,
6047 "Disabling adapter.\n");
6049 if (!atomic_read(&pdev->enable_cnt)) {
6050 ql_log(ql_log_info, base_vha, 0xfffc,
6051 "PCI device disabled, no action req for PCI error=%lx\n",
6052 base_vha->pci_flags);
6056 qla2x00_wait_for_sess_deletion(base_vha);
6058 set_bit(UNLOADING, &base_vha->dpc_flags);
6060 qla2x00_delete_all_vps(ha, base_vha);
6062 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6064 qla2x00_dfs_remove(base_vha);
6066 qla84xx_put_chip(base_vha);
6068 if (base_vha->timer_active)
6069 qla2x00_stop_timer(base_vha);
6071 base_vha->flags.online = 0;
6073 qla2x00_destroy_deferred_work(ha);
6076 * Do not try to stop beacon blink as it will issue a mailbox
6079 qla2x00_free_sysfs_attr(base_vha, false);
6081 fc_remove_host(base_vha->host);
6083 scsi_remove_host(base_vha->host);
6085 base_vha->flags.init_done = 0;
6086 qla25xx_delete_queues(base_vha);
6087 qla2x00_free_fcports(base_vha);
6088 qla2x00_free_irqs(base_vha);
6089 qla2x00_mem_free(ha);
6090 qla82xx_md_free(base_vha);
6091 qla2x00_free_queues(ha);
6093 qla2x00_unmap_iobases(ha);
6095 pci_release_selected_regions(ha->pdev, ha->bars);
6096 pci_disable_pcie_error_reporting(pdev);
6097 pci_disable_device(pdev);
6100 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6104 /**************************************************************************
6106 * This kernel thread is a task that is schedule by the interrupt handler
6107 * to perform the background processing for interrupts.
6110 * This task always run in the context of a kernel thread. It
6111 * is kick-off by the driver's detect code and starts up
6112 * up one per adapter. It immediately goes to sleep and waits for
6113 * some fibre event. When either the interrupt handler or
6114 * the timer routine detects a event it will one of the task
6115 * bits then wake us up.
6116 **************************************************************************/
6118 qla2x00_do_dpc(void *data)
6120 scsi_qla_host_t *base_vha;
6121 struct qla_hw_data *ha;
6123 struct qla_qpair *qpair;
6125 ha = (struct qla_hw_data *)data;
6126 base_vha = pci_get_drvdata(ha->pdev);
6128 set_user_nice(current, MIN_NICE);
6130 set_current_state(TASK_INTERRUPTIBLE);
6131 while (!kthread_should_stop()) {
6132 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6133 "DPC handler sleeping.\n");
6137 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6140 if (ha->flags.eeh_busy) {
6141 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6142 "eeh_busy=%d.\n", ha->flags.eeh_busy);
6148 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6149 "DPC handler waking up, dpc_flags=0x%lx.\n",
6150 base_vha->dpc_flags);
6152 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6155 if (IS_P3P_TYPE(ha)) {
6156 if (IS_QLA8044(ha)) {
6157 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6158 &base_vha->dpc_flags)) {
6159 qla8044_idc_lock(ha);
6160 qla8044_wr_direct(base_vha,
6161 QLA8044_CRB_DEV_STATE_INDEX,
6162 QLA8XXX_DEV_FAILED);
6163 qla8044_idc_unlock(ha);
6164 ql_log(ql_log_info, base_vha, 0x4004,
6165 "HW State: FAILED.\n");
6166 qla8044_device_state_handler(base_vha);
6171 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6172 &base_vha->dpc_flags)) {
6173 qla82xx_idc_lock(ha);
6174 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6175 QLA8XXX_DEV_FAILED);
6176 qla82xx_idc_unlock(ha);
6177 ql_log(ql_log_info, base_vha, 0x0151,
6178 "HW State: FAILED.\n");
6179 qla82xx_device_state_handler(base_vha);
6184 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6185 &base_vha->dpc_flags)) {
6187 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6188 "FCoE context reset scheduled.\n");
6189 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6190 &base_vha->dpc_flags))) {
6191 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6192 /* FCoE-ctx reset failed.
6193 * Escalate to chip-reset
6195 set_bit(ISP_ABORT_NEEDED,
6196 &base_vha->dpc_flags);
6198 clear_bit(ABORT_ISP_ACTIVE,
6199 &base_vha->dpc_flags);
6202 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6203 "FCoE context reset end.\n");
6205 } else if (IS_QLAFX00(ha)) {
6206 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6207 &base_vha->dpc_flags)) {
6208 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6209 "Firmware Reset Recovery\n");
6210 if (qlafx00_reset_initialize(base_vha)) {
6211 /* Failed. Abort isp later. */
6212 if (!test_bit(UNLOADING,
6213 &base_vha->dpc_flags)) {
6214 set_bit(ISP_UNRECOVERABLE,
6215 &base_vha->dpc_flags);
6216 ql_dbg(ql_dbg_dpc, base_vha,
6218 "Reset Recovery Failed\n");
6223 if (test_and_clear_bit(FX00_TARGET_SCAN,
6224 &base_vha->dpc_flags)) {
6225 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6226 "ISPFx00 Target Scan scheduled\n");
6227 if (qlafx00_rescan_isp(base_vha)) {
6228 if (!test_bit(UNLOADING,
6229 &base_vha->dpc_flags))
6230 set_bit(ISP_UNRECOVERABLE,
6231 &base_vha->dpc_flags);
6232 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6233 "ISPFx00 Target Scan Failed\n");
6235 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6236 "ISPFx00 Target Scan End\n");
6238 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6239 &base_vha->dpc_flags)) {
6240 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6241 "ISPFx00 Host Info resend scheduled\n");
6242 qlafx00_fx_disc(base_vha,
6243 &base_vha->hw->mr.fcport,
6244 FXDISC_REG_HOST_INFO);
6248 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6249 &base_vha->dpc_flags) &&
6250 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6251 qla24xx_detect_sfp(base_vha);
6253 if (ha->flags.detected_lr_sfp !=
6254 ha->flags.using_lr_setting)
6255 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6258 if (test_and_clear_bit
6259 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6260 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
6261 bool do_reset = true;
6263 switch (base_vha->qlini_mode) {
6264 case QLA2XXX_INI_MODE_ENABLED:
6266 case QLA2XXX_INI_MODE_DISABLED:
6267 if (!qla_tgt_mode_enabled(base_vha) &&
6268 !ha->flags.fw_started)
6271 case QLA2XXX_INI_MODE_DUAL:
6272 if (!qla_dual_mode_enabled(base_vha) &&
6273 !ha->flags.fw_started)
6280 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
6281 &base_vha->dpc_flags))) {
6282 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6283 "ISP abort scheduled.\n");
6284 if (ha->isp_ops->abort_isp(base_vha)) {
6285 /* failed. retry later */
6286 set_bit(ISP_ABORT_NEEDED,
6287 &base_vha->dpc_flags);
6289 clear_bit(ABORT_ISP_ACTIVE,
6290 &base_vha->dpc_flags);
6291 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6292 "ISP abort end.\n");
6296 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6297 &base_vha->dpc_flags)) {
6298 qla2x00_update_fcports(base_vha);
6302 goto loop_resync_check;
6304 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
6305 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6306 "Quiescence mode scheduled.\n");
6307 if (IS_P3P_TYPE(ha)) {
6309 qla82xx_device_state_handler(base_vha);
6311 qla8044_device_state_handler(base_vha);
6312 clear_bit(ISP_QUIESCE_NEEDED,
6313 &base_vha->dpc_flags);
6314 if (!ha->flags.quiesce_owner) {
6315 qla2x00_perform_loop_resync(base_vha);
6316 if (IS_QLA82XX(ha)) {
6317 qla82xx_idc_lock(ha);
6318 qla82xx_clear_qsnt_ready(
6320 qla82xx_idc_unlock(ha);
6321 } else if (IS_QLA8044(ha)) {
6322 qla8044_idc_lock(ha);
6323 qla8044_clear_qsnt_ready(
6325 qla8044_idc_unlock(ha);
6329 clear_bit(ISP_QUIESCE_NEEDED,
6330 &base_vha->dpc_flags);
6331 qla2x00_quiesce_io(base_vha);
6333 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6334 "Quiescence mode end.\n");
6337 if (test_and_clear_bit(RESET_MARKER_NEEDED,
6338 &base_vha->dpc_flags) &&
6339 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
6341 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6342 "Reset marker scheduled.\n");
6343 qla2x00_rst_aen(base_vha);
6344 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
6345 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6346 "Reset marker end.\n");
6349 /* Retry each device up to login retry count */
6350 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
6351 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6352 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
6354 if (!base_vha->relogin_jif ||
6355 time_after_eq(jiffies, base_vha->relogin_jif)) {
6356 base_vha->relogin_jif = jiffies + HZ;
6357 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6359 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
6360 "Relogin scheduled.\n");
6361 qla24xx_post_relogin_work(base_vha);
6365 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
6366 &base_vha->dpc_flags)) {
6368 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6369 "Loop resync scheduled.\n");
6371 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
6372 &base_vha->dpc_flags))) {
6374 qla2x00_loop_resync(base_vha);
6376 clear_bit(LOOP_RESYNC_ACTIVE,
6377 &base_vha->dpc_flags);
6380 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6381 "Loop resync end.\n");
6387 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6388 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6389 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6390 qla2xxx_flash_npiv_conf(base_vha);
6394 if (!ha->interrupts_on)
6395 ha->isp_ops->enable_intrs(ha);
6397 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
6398 &base_vha->dpc_flags)) {
6399 if (ha->beacon_blink_led == 1)
6400 ha->isp_ops->beacon_blink(base_vha);
6403 /* qpair online check */
6404 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6405 &base_vha->dpc_flags)) {
6406 if (ha->flags.eeh_busy ||
6407 ha->flags.pci_channel_io_perm_failure)
6412 mutex_lock(&ha->mq_lock);
6413 list_for_each_entry(qpair, &base_vha->qp_list,
6415 qpair->online = online;
6416 mutex_unlock(&ha->mq_lock);
6419 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6420 &base_vha->dpc_flags)) {
6421 ql_log(ql_log_info, base_vha, 0xffffff,
6422 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6423 ha->nvme_last_rptd_aen);
6424 if (qla27xx_set_zio_threshold(base_vha,
6425 ha->nvme_last_rptd_aen)) {
6426 ql_log(ql_log_info, base_vha, 0xffffff,
6427 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6428 ha->nvme_last_rptd_aen);
6432 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6433 &base_vha->dpc_flags)) {
6434 ql_log(ql_log_info, base_vha, 0xffffff,
6435 "SET ZIO Activity exchange threshold to %d.\n",
6436 ha->last_zio_threshold);
6437 qla27xx_set_zio_threshold(base_vha,
6438 ha->last_zio_threshold);
6441 if (!IS_QLAFX00(ha))
6442 qla2x00_do_dpc_all_vps(base_vha);
6444 if (test_and_clear_bit(N2N_LINK_RESET,
6445 &base_vha->dpc_flags)) {
6446 qla2x00_lip_reset(base_vha);
6451 set_current_state(TASK_INTERRUPTIBLE);
6452 } /* End of while(1) */
6453 __set_current_state(TASK_RUNNING);
6455 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6456 "DPC handler exiting.\n");
6459 * Make sure that nobody tries to wake us up again.
6463 /* Cleanup any residual CTX SRBs. */
6464 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6470 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
6472 struct qla_hw_data *ha = vha->hw;
6473 struct task_struct *t = ha->dpc_thread;
6475 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
6481 * Processes asynchronous reset.
6484 * ha = adapter block pointer.
6487 qla2x00_rst_aen(scsi_qla_host_t *vha)
6489 if (vha->flags.online && !vha->flags.reset_active &&
6490 !atomic_read(&vha->loop_down_timer) &&
6491 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
6493 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6496 * Issue marker command only when we are going to start
6499 vha->marker_needed = 1;
6500 } while (!atomic_read(&vha->loop_down_timer) &&
6501 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
6505 /**************************************************************************
6511 * Context: Interrupt
6512 ***************************************************************************/
6514 qla2x00_timer(struct timer_list *t)
6516 scsi_qla_host_t *vha = from_timer(vha, t, timer);
6517 unsigned long cpu_flags = 0;
6522 struct qla_hw_data *ha = vha->hw;
6523 struct req_que *req;
6525 if (ha->flags.eeh_busy) {
6526 ql_dbg(ql_dbg_timer, vha, 0x6000,
6527 "EEH = %d, restarting timer.\n",
6528 ha->flags.eeh_busy);
6529 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6534 * Hardware read to raise pending EEH errors during mailbox waits. If
6535 * the read returns -1 then disable the board.
6537 if (!pci_channel_offline(ha->pdev)) {
6538 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
6539 qla2x00_check_reg16_for_disconnect(vha, w);
6542 /* Make sure qla82xx_watchdog is run only for physical port */
6543 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
6544 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6547 qla82xx_watchdog(vha);
6548 else if (IS_QLA8044(ha))
6549 qla8044_watchdog(vha);
6552 if (!vha->vp_idx && IS_QLAFX00(ha))
6553 qlafx00_timer_routine(vha);
6555 /* Loop down handler. */
6556 if (atomic_read(&vha->loop_down_timer) > 0 &&
6557 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6558 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
6559 && vha->flags.online) {
6561 if (atomic_read(&vha->loop_down_timer) ==
6562 vha->loop_down_abort_time) {
6564 ql_log(ql_log_info, vha, 0x6008,
6565 "Loop down - aborting the queues before time expires.\n");
6567 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6568 atomic_set(&vha->loop_state, LOOP_DEAD);
6571 * Schedule an ISP abort to return any FCP2-device
6574 /* NPIV - scan physical port only */
6576 spin_lock_irqsave(&ha->hardware_lock,
6578 req = ha->req_q_map[0];
6580 index < req->num_outstanding_cmds;
6584 sp = req->outstanding_cmds[index];
6587 if (sp->cmd_type != TYPE_SRB)
6589 if (sp->type != SRB_SCSI_CMD)
6592 if (!(sfcp->flags & FCF_FCP2_DEVICE))
6596 set_bit(FCOE_CTX_RESET_NEEDED,
6599 set_bit(ISP_ABORT_NEEDED,
6603 spin_unlock_irqrestore(&ha->hardware_lock,
6609 /* if the loop has been down for 4 minutes, reinit adapter */
6610 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
6611 if (!(vha->device_flags & DFLG_NO_CABLE)) {
6612 ql_log(ql_log_warn, vha, 0x6009,
6613 "Loop down - aborting ISP.\n");
6616 set_bit(FCOE_CTX_RESET_NEEDED,
6619 set_bit(ISP_ABORT_NEEDED,
6623 ql_dbg(ql_dbg_timer, vha, 0x600a,
6624 "Loop down - seconds remaining %d.\n",
6625 atomic_read(&vha->loop_down_timer));
6627 /* Check if beacon LED needs to be blinked for physical host only */
6628 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
6629 /* There is no beacon_blink function for ISP82xx */
6630 if (!IS_P3P_TYPE(ha)) {
6631 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6636 /* Process any deferred work. */
6637 if (!list_empty(&vha->work_list)) {
6638 unsigned long flags;
6641 spin_lock_irqsave(&vha->work_lock, flags);
6642 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6644 spin_unlock_irqrestore(&vha->work_lock, flags);
6646 queue_work(vha->hw->wq, &vha->iocb_work);
6651 * see if the active AEN count has changed from what was last reported.
6654 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) &&
6655 ha->zio_mode == QLA_ZIO_MODE_6 &&
6656 !ha->flags.host_shutting_down) {
6657 ql_log(ql_log_info, vha, 0x3002,
6658 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6659 ha->nvme_last_rptd_aen);
6660 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6661 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6666 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
6667 (ha->zio_mode == QLA_ZIO_MODE_6) &&
6668 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
6669 ql_log(ql_log_info, vha, 0x3002,
6670 "Sched: Set ZIO exchange threshold to %d.\n",
6671 ha->last_zio_threshold);
6672 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
6673 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6677 /* Schedule the DPC routine if needed */
6678 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6679 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6680 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
6682 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6683 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
6684 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6685 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
6686 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
6687 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
6688 ql_dbg(ql_dbg_timer, vha, 0x600b,
6689 "isp_abort_needed=%d loop_resync_needed=%d "
6690 "fcport_update_needed=%d start_dpc=%d "
6691 "reset_marker_needed=%d",
6692 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6693 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6694 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6696 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6697 ql_dbg(ql_dbg_timer, vha, 0x600c,
6698 "beacon_blink_needed=%d isp_unrecoverable=%d "
6699 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
6700 "relogin_needed=%d.\n",
6701 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6702 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6703 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6704 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
6705 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
6706 qla2xxx_wake_dpc(vha);
6709 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6712 /* Firmware interface routines. */
6714 #define FW_ISP21XX 0
6715 #define FW_ISP22XX 1
6716 #define FW_ISP2300 2
6717 #define FW_ISP2322 3
6718 #define FW_ISP24XX 4
6719 #define FW_ISP25XX 5
6720 #define FW_ISP81XX 6
6721 #define FW_ISP82XX 7
6722 #define FW_ISP2031 8
6723 #define FW_ISP8031 9
6724 #define FW_ISP27XX 10
6725 #define FW_ISP28XX 11
6727 #define FW_FILE_ISP21XX "ql2100_fw.bin"
6728 #define FW_FILE_ISP22XX "ql2200_fw.bin"
6729 #define FW_FILE_ISP2300 "ql2300_fw.bin"
6730 #define FW_FILE_ISP2322 "ql2322_fw.bin"
6731 #define FW_FILE_ISP24XX "ql2400_fw.bin"
6732 #define FW_FILE_ISP25XX "ql2500_fw.bin"
6733 #define FW_FILE_ISP81XX "ql8100_fw.bin"
6734 #define FW_FILE_ISP82XX "ql8200_fw.bin"
6735 #define FW_FILE_ISP2031 "ql2600_fw.bin"
6736 #define FW_FILE_ISP8031 "ql8300_fw.bin"
6737 #define FW_FILE_ISP27XX "ql2700_fw.bin"
6738 #define FW_FILE_ISP28XX "ql2800_fw.bin"
6741 static DEFINE_MUTEX(qla_fw_lock);
6743 static struct fw_blob qla_fw_blobs[] = {
6744 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6745 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6746 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6747 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6748 { .name = FW_FILE_ISP24XX, },
6749 { .name = FW_FILE_ISP25XX, },
6750 { .name = FW_FILE_ISP81XX, },
6751 { .name = FW_FILE_ISP82XX, },
6752 { .name = FW_FILE_ISP2031, },
6753 { .name = FW_FILE_ISP8031, },
6754 { .name = FW_FILE_ISP27XX, },
6755 { .name = FW_FILE_ISP28XX, },
6760 qla2x00_request_firmware(scsi_qla_host_t *vha)
6762 struct qla_hw_data *ha = vha->hw;
6763 struct fw_blob *blob;
6765 if (IS_QLA2100(ha)) {
6766 blob = &qla_fw_blobs[FW_ISP21XX];
6767 } else if (IS_QLA2200(ha)) {
6768 blob = &qla_fw_blobs[FW_ISP22XX];
6769 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
6770 blob = &qla_fw_blobs[FW_ISP2300];
6771 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
6772 blob = &qla_fw_blobs[FW_ISP2322];
6773 } else if (IS_QLA24XX_TYPE(ha)) {
6774 blob = &qla_fw_blobs[FW_ISP24XX];
6775 } else if (IS_QLA25XX(ha)) {
6776 blob = &qla_fw_blobs[FW_ISP25XX];
6777 } else if (IS_QLA81XX(ha)) {
6778 blob = &qla_fw_blobs[FW_ISP81XX];
6779 } else if (IS_QLA82XX(ha)) {
6780 blob = &qla_fw_blobs[FW_ISP82XX];
6781 } else if (IS_QLA2031(ha)) {
6782 blob = &qla_fw_blobs[FW_ISP2031];
6783 } else if (IS_QLA8031(ha)) {
6784 blob = &qla_fw_blobs[FW_ISP8031];
6785 } else if (IS_QLA27XX(ha)) {
6786 blob = &qla_fw_blobs[FW_ISP27XX];
6787 } else if (IS_QLA28XX(ha)) {
6788 blob = &qla_fw_blobs[FW_ISP28XX];
6796 mutex_lock(&qla_fw_lock);
6800 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
6801 ql_log(ql_log_warn, vha, 0x0063,
6802 "Failed to load firmware image (%s).\n", blob->name);
6808 mutex_unlock(&qla_fw_lock);
6813 qla2x00_release_firmware(void)
6815 struct fw_blob *blob;
6817 mutex_lock(&qla_fw_lock);
6818 for (blob = qla_fw_blobs; blob->name; blob++)
6819 release_firmware(blob->fw);
6820 mutex_unlock(&qla_fw_lock);
6823 static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
6825 struct qla_hw_data *ha = vha->hw;
6826 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6827 struct qla_qpair *qpair = NULL;
6828 struct scsi_qla_host *vp;
6831 unsigned long flags;
6835 ha->base_qpair->chip_reset = ha->chip_reset;
6836 for (i = 0; i < ha->max_qpairs; i++) {
6837 if (ha->queue_pair_map[i])
6838 ha->queue_pair_map[i]->chip_reset =
6839 ha->base_qpair->chip_reset;
6842 /* purge MBox commands */
6843 if (atomic_read(&ha->num_pend_mbx_stage3)) {
6844 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6845 complete(&ha->mbx_intr_comp);
6850 while (atomic_read(&ha->num_pend_mbx_stage3) ||
6851 atomic_read(&ha->num_pend_mbx_stage2) ||
6852 atomic_read(&ha->num_pend_mbx_stage1)) {
6859 ha->flags.purge_mbox = 0;
6861 mutex_lock(&ha->mq_lock);
6862 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
6864 mutex_unlock(&ha->mq_lock);
6866 qla2x00_mark_all_devices_lost(vha, 0);
6868 spin_lock_irqsave(&ha->vport_slock, flags);
6869 list_for_each_entry(vp, &ha->vp_list, list) {
6870 atomic_inc(&vp->vref_count);
6871 spin_unlock_irqrestore(&ha->vport_slock, flags);
6872 qla2x00_mark_all_devices_lost(vp, 0);
6873 spin_lock_irqsave(&ha->vport_slock, flags);
6874 atomic_dec(&vp->vref_count);
6876 spin_unlock_irqrestore(&ha->vport_slock, flags);
6878 /* Clear all async request states across all VPs. */
6879 list_for_each_entry(fcport, &vha->vp_fcports, list)
6880 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6882 spin_lock_irqsave(&ha->vport_slock, flags);
6883 list_for_each_entry(vp, &ha->vp_list, list) {
6884 atomic_inc(&vp->vref_count);
6885 spin_unlock_irqrestore(&ha->vport_slock, flags);
6886 list_for_each_entry(fcport, &vp->vp_fcports, list)
6887 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6888 spin_lock_irqsave(&ha->vport_slock, flags);
6889 atomic_dec(&vp->vref_count);
6891 spin_unlock_irqrestore(&ha->vport_slock, flags);
6895 static pci_ers_result_t
6896 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6898 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6899 struct qla_hw_data *ha = vha->hw;
6901 ql_dbg(ql_dbg_aer, vha, 0x9000,
6902 "PCI error detected, state %x.\n", state);
6904 if (!atomic_read(&pdev->enable_cnt)) {
6905 ql_log(ql_log_info, vha, 0xffff,
6906 "PCI device is disabled,state %x\n", state);
6907 return PCI_ERS_RESULT_NEED_RESET;
6911 case pci_channel_io_normal:
6912 ha->flags.eeh_busy = 0;
6913 if (ql2xmqsupport || ql2xnvmeenable) {
6914 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6915 qla2xxx_wake_dpc(vha);
6917 return PCI_ERS_RESULT_CAN_RECOVER;
6918 case pci_channel_io_frozen:
6919 ha->flags.eeh_busy = 1;
6920 qla_pci_error_cleanup(vha);
6921 return PCI_ERS_RESULT_NEED_RESET;
6922 case pci_channel_io_perm_failure:
6923 ha->flags.pci_channel_io_perm_failure = 1;
6924 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
6925 if (ql2xmqsupport || ql2xnvmeenable) {
6926 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6927 qla2xxx_wake_dpc(vha);
6929 return PCI_ERS_RESULT_DISCONNECT;
6931 return PCI_ERS_RESULT_NEED_RESET;
6934 static pci_ers_result_t
6935 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6937 int risc_paused = 0;
6939 unsigned long flags;
6940 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6941 struct qla_hw_data *ha = base_vha->hw;
6942 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6943 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6946 return PCI_ERS_RESULT_RECOVERED;
6948 spin_lock_irqsave(&ha->hardware_lock, flags);
6949 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6950 stat = RD_REG_DWORD(®->hccr);
6951 if (stat & HCCR_RISC_PAUSE)
6953 } else if (IS_QLA23XX(ha)) {
6954 stat = RD_REG_DWORD(®->u.isp2300.host_status);
6955 if (stat & HSR_RISC_PAUSED)
6957 } else if (IS_FWI2_CAPABLE(ha)) {
6958 stat = RD_REG_DWORD(®24->host_status);
6959 if (stat & HSRX_RISC_PAUSED)
6962 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6965 ql_log(ql_log_info, base_vha, 0x9003,
6966 "RISC paused -- mmio_enabled, Dumping firmware.\n");
6967 ha->isp_ops->fw_dump(base_vha, 0);
6969 return PCI_ERS_RESULT_NEED_RESET;
6971 return PCI_ERS_RESULT_RECOVERED;
6974 static pci_ers_result_t
6975 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6977 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
6978 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6979 struct qla_hw_data *ha = base_vha->hw;
6981 struct qla_qpair *qpair = NULL;
6983 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6986 /* Workaround: qla2xxx driver which access hardware earlier
6987 * needs error state to be pci_channel_io_online.
6988 * Otherwise mailbox command timesout.
6990 pdev->error_state = pci_channel_io_normal;
6992 pci_restore_state(pdev);
6994 /* pci_restore_state() clears the saved_state flag of the device
6995 * save restored state which resets saved_state flag
6997 pci_save_state(pdev);
7000 rc = pci_enable_device_mem(pdev);
7002 rc = pci_enable_device(pdev);
7005 ql_log(ql_log_warn, base_vha, 0x9005,
7006 "Can't re-enable PCI device after reset.\n");
7007 goto exit_slot_reset;
7011 if (ha->isp_ops->pci_config(base_vha))
7012 goto exit_slot_reset;
7014 mutex_lock(&ha->mq_lock);
7015 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7017 mutex_unlock(&ha->mq_lock);
7019 base_vha->flags.online = 1;
7020 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7021 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
7022 ret = PCI_ERS_RESULT_RECOVERED;
7023 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7027 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7028 "slot_reset return %x.\n", ret);
7034 qla2xxx_pci_resume(struct pci_dev *pdev)
7036 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7037 struct qla_hw_data *ha = base_vha->hw;
7040 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7043 ha->flags.eeh_busy = 0;
7045 ret = qla2x00_wait_for_hba_online(base_vha);
7046 if (ret != QLA_SUCCESS) {
7047 ql_log(ql_log_fatal, base_vha, 0x9002,
7048 "The device failed to resume I/O from slot/link_reset.\n");
7053 qla_pci_reset_prepare(struct pci_dev *pdev)
7055 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7056 struct qla_hw_data *ha = base_vha->hw;
7057 struct qla_qpair *qpair;
7059 ql_log(ql_log_warn, base_vha, 0xffff,
7063 * PCI FLR/function reset is about to reset the
7064 * slot. Stop the chip to stop all DMA access.
7065 * It is assumed that pci_reset_done will be called
7066 * after FLR to resume Chip operation.
7068 ha->flags.eeh_busy = 1;
7069 mutex_lock(&ha->mq_lock);
7070 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7072 mutex_unlock(&ha->mq_lock);
7074 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7075 qla2x00_abort_isp_cleanup(base_vha);
7076 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7080 qla_pci_reset_done(struct pci_dev *pdev)
7082 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7083 struct qla_hw_data *ha = base_vha->hw;
7084 struct qla_qpair *qpair;
7086 ql_log(ql_log_warn, base_vha, 0xffff,
7090 * FLR just completed by PCI layer. Resume adapter
7092 ha->flags.eeh_busy = 0;
7093 mutex_lock(&ha->mq_lock);
7094 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7096 mutex_unlock(&ha->mq_lock);
7098 base_vha->flags.online = 1;
7099 ha->isp_ops->abort_isp(base_vha);
7100 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7103 static int qla2xxx_map_queues(struct Scsi_Host *shost)
7106 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
7107 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
7109 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
7110 rc = blk_mq_map_queues(qmap);
7112 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
7116 struct scsi_host_template qla2xxx_driver_template = {
7117 .module = THIS_MODULE,
7118 .name = QLA2XXX_DRIVER_NAME,
7119 .queuecommand = qla2xxx_queuecommand,
7121 .eh_timed_out = fc_eh_timed_out,
7122 .eh_abort_handler = qla2xxx_eh_abort,
7123 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7124 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7125 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7126 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7128 .slave_configure = qla2xxx_slave_configure,
7130 .slave_alloc = qla2xxx_slave_alloc,
7131 .slave_destroy = qla2xxx_slave_destroy,
7132 .scan_finished = qla2xxx_scan_finished,
7133 .scan_start = qla2xxx_scan_start,
7134 .change_queue_depth = scsi_change_queue_depth,
7135 .map_queues = qla2xxx_map_queues,
7138 .sg_tablesize = SG_ALL,
7140 .max_sectors = 0xFFFF,
7141 .shost_attrs = qla2x00_host_attrs,
7143 .supported_mode = MODE_INITIATOR,
7144 .track_queue_depth = 1,
7145 .cmd_size = sizeof(srb_t),
7148 static const struct pci_error_handlers qla2xxx_err_handler = {
7149 .error_detected = qla2xxx_pci_error_detected,
7150 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7151 .slot_reset = qla2xxx_pci_slot_reset,
7152 .resume = qla2xxx_pci_resume,
7153 .reset_prepare = qla_pci_reset_prepare,
7154 .reset_done = qla_pci_reset_done,
7157 static struct pci_device_id qla2xxx_pci_tbl[] = {
7158 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7159 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7160 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7161 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7162 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7163 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7164 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7165 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7166 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
7167 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
7168 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7169 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
7170 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
7171 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
7172 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
7173 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
7174 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
7175 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7176 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
7177 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
7178 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
7179 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
7180 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7181 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7182 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7183 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7184 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
7187 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7189 static struct pci_driver qla2xxx_pci_driver = {
7190 .name = QLA2XXX_DRIVER_NAME,
7192 .owner = THIS_MODULE,
7194 .id_table = qla2xxx_pci_tbl,
7195 .probe = qla2x00_probe_one,
7196 .remove = qla2x00_remove_one,
7197 .shutdown = qla2x00_shutdown,
7198 .err_handler = &qla2xxx_err_handler,
7201 static const struct file_operations apidev_fops = {
7202 .owner = THIS_MODULE,
7203 .llseek = noop_llseek,
7207 * qla2x00_module_init - Module initialization.
7210 qla2x00_module_init(void)
7214 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
7215 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
7216 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
7217 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
7218 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
7219 BUILD_BUG_ON(sizeof(request_t) != 64);
7220 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
7221 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
7222 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
7223 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
7224 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
7225 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
7226 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
7227 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
7228 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
7229 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
7230 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
7231 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
7232 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
7233 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
7234 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
7235 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
7236 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
7238 /* Allocate cache for SRBs. */
7239 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
7240 SLAB_HWCACHE_ALIGN, NULL);
7241 if (srb_cachep == NULL) {
7242 ql_log(ql_log_fatal, NULL, 0x0001,
7243 "Unable to allocate SRB cache...Failing load!.\n");
7247 /* Initialize target kmem_cache and mem_pools */
7251 } else if (ret > 0) {
7253 * If initiator mode is explictly disabled by qlt_init(),
7254 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7255 * performing scsi_scan_target() during LOOP UP event.
7257 qla2xxx_transport_functions.disable_target_scan = 1;
7258 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7261 /* Derive version string. */
7262 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
7263 if (ql2xextended_error_logging)
7264 strcat(qla2x00_version_str, "-debug");
7265 if (ql2xextended_error_logging == 1)
7266 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
7268 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7269 qla_insert_tgt_attrs();
7271 qla2xxx_transport_template =
7272 fc_attach_transport(&qla2xxx_transport_functions);
7273 if (!qla2xxx_transport_template) {
7274 ql_log(ql_log_fatal, NULL, 0x0002,
7275 "fc_attach_transport failed...Failing load!.\n");
7280 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7281 if (apidev_major < 0) {
7282 ql_log(ql_log_fatal, NULL, 0x0003,
7283 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
7286 qla2xxx_transport_vport_template =
7287 fc_attach_transport(&qla2xxx_transport_vport_functions);
7288 if (!qla2xxx_transport_vport_template) {
7289 ql_log(ql_log_fatal, NULL, 0x0004,
7290 "fc_attach_transport vport failed...Failing load!.\n");
7294 ql_log(ql_log_info, NULL, 0x0005,
7295 "QLogic Fibre Channel HBA Driver: %s.\n",
7296 qla2x00_version_str);
7297 ret = pci_register_driver(&qla2xxx_pci_driver);
7299 ql_log(ql_log_fatal, NULL, 0x0006,
7300 "pci_register_driver failed...ret=%d Failing load!.\n",
7302 goto release_vport_transport;
7306 release_vport_transport:
7307 fc_release_transport(qla2xxx_transport_vport_template);
7310 if (apidev_major >= 0)
7311 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7312 fc_release_transport(qla2xxx_transport_template);
7318 kmem_cache_destroy(srb_cachep);
7323 * qla2x00_module_exit - Module cleanup.
7326 qla2x00_module_exit(void)
7328 pci_unregister_driver(&qla2xxx_pci_driver);
7329 qla2x00_release_firmware();
7330 kmem_cache_destroy(ctx_cachep);
7331 fc_release_transport(qla2xxx_transport_vport_template);
7332 if (apidev_major >= 0)
7333 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7334 fc_release_transport(qla2xxx_transport_template);
7336 kmem_cache_destroy(srb_cachep);
7339 module_init(qla2x00_module_init);
7340 module_exit(qla2x00_module_exit);
7342 MODULE_AUTHOR("QLogic Corporation");
7343 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7344 MODULE_LICENSE("GPL");
7345 MODULE_VERSION(QLA2XXX_VERSION);
7346 MODULE_FIRMWARE(FW_FILE_ISP21XX);
7347 MODULE_FIRMWARE(FW_FILE_ISP22XX);
7348 MODULE_FIRMWARE(FW_FILE_ISP2300);
7349 MODULE_FIRMWARE(FW_FILE_ISP2322);
7350 MODULE_FIRMWARE(FW_FILE_ISP24XX);
7351 MODULE_FIRMWARE(FW_FILE_ISP25XX);