drivers/scsi/pm8001/pm8001_init.c

   1 /*
   2  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
   3  *
   4  * Copyright (c) 2008-2009 USI Co., Ltd.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14  *    substantially similar to the "NO WARRANTY" disclaimer below
  15  *    ("Disclaimer") and any redistribution must be conditioned upon
  16  *    including a substantially similar Disclaimer requirement for further
  17  *    binary redistribution.
  18  * 3. Neither the names of the above-listed copyright holders nor the names
  19  *    of any contributors may be used to endorse or promote products derived
  20  *    from this software without specific prior written permission.
  21  *
  22  * Alternatively, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2 as published by the Free
  24  * Software Foundation.
  25  *
  26  * NO WARRANTY
  27  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37  * POSSIBILITY OF SUCH DAMAGES.
  38  *
  39  */
  40
  41 #include <linux/slab.h>
  42 #include "pm8001_sas.h"
  43 #include "pm8001_chips.h"
  44 #include "pm80xx_hwi.h"
  45
  46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING |
  47                                 PM8001_EVENT_LOGGING | PM8001_INIT_LOGGING;
  48 module_param(logging_level, ulong, 0644);
  49 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
  50
  51 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
  52 module_param(link_rate, ulong, 0644);
  53 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
  54                 " 1: Link rate 1.5G\n"
  55                 " 2: Link rate 3.0G\n"
  56                 " 4: Link rate 6.0G\n"
  57                 " 8: Link rate 12.0G\n");
  58
  59 static struct scsi_transport_template *pm8001_stt;
  60 static int pm8001_init_ccb_tag(struct pm8001_hba_info *);
  61
  62 /*
  63  * chip info structure to identify chip key functionality as
  64  * encryption available/not, no of ports, hw specific function ref
  65  */
  66 static const struct pm8001_chip_info pm8001_chips[] = {
  67         [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
  68         [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
  69         [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
  70         [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
  71         [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
  72         [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
  73         [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
  74         [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
  75         [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
  76         [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
  77         [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
  78 };
  79 static int pm8001_id;
  80
  81 LIST_HEAD(hba_list);
  82
  83 struct workqueue_struct *pm8001_wq;
  84
  85 static void pm8001_map_queues(struct Scsi_Host *shost)
  86 {
  87         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  88         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
  89         struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
  90
  91         if (pm8001_ha->number_of_intr > 1)
  92                 blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1);
  93
  94         return blk_mq_map_queues(qmap);
  95 }
  96
  97 /*
  98  * The main structure which LLDD must register for scsi core.
  99  */
 100 static const struct scsi_host_template pm8001_sht = {
 101         .module                 = THIS_MODULE,
 102         .name                   = DRV_NAME,
 103         .proc_name              = DRV_NAME,
 104         .queuecommand           = sas_queuecommand,
 105         .dma_need_drain         = ata_scsi_dma_need_drain,
 106         .target_alloc           = sas_target_alloc,
 107         .slave_configure        = sas_slave_configure,
 108         .scan_finished          = pm8001_scan_finished,
 109         .scan_start             = pm8001_scan_start,
 110         .change_queue_depth     = sas_change_queue_depth,
 111         .bios_param             = sas_bios_param,
 112         .can_queue              = 1,
 113         .this_id                = -1,
 114         .sg_tablesize           = PM8001_MAX_DMA_SG,
 115         .max_sectors            = SCSI_DEFAULT_MAX_SECTORS,
 116         .eh_device_reset_handler = sas_eh_device_reset_handler,
 117         .eh_target_reset_handler = sas_eh_target_reset_handler,
 118         .slave_alloc            = sas_slave_alloc,
 119         .target_destroy         = sas_target_destroy,
 120         .ioctl                  = sas_ioctl,
 121 #ifdef CONFIG_COMPAT
 122         .compat_ioctl           = sas_ioctl,
 123 #endif
 124         .shost_groups           = pm8001_host_groups,
 125         .track_queue_depth      = 1,
 126         .cmd_per_lun            = 32,
 127         .map_queues             = pm8001_map_queues,
 128 };
 129
 130 /*
 131  * Sas layer call this function to execute specific task.
 132  */
 133 static struct sas_domain_function_template pm8001_transport_ops = {
 134         .lldd_dev_found         = pm8001_dev_found,
 135         .lldd_dev_gone          = pm8001_dev_gone,
 136
 137         .lldd_execute_task      = pm8001_queue_command,
 138         .lldd_control_phy       = pm8001_phy_control,
 139
 140         .lldd_abort_task        = pm8001_abort_task,
 141         .lldd_abort_task_set    = sas_abort_task_set,
 142         .lldd_clear_task_set    = pm8001_clear_task_set,
 143         .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
 144         .lldd_lu_reset          = pm8001_lu_reset,
 145         .lldd_query_task        = pm8001_query_task,
 146         .lldd_port_formed       = pm8001_port_formed,
 147         .lldd_tmf_exec_complete = pm8001_setds_completion,
 148         .lldd_tmf_aborted       = pm8001_tmf_aborted,
 149 };
 150
 151 /**
 152  * pm8001_phy_init - initiate our adapter phys
 153  * @pm8001_ha: our hba structure.
 154  * @phy_id: phy id.
 155  */
 156 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
 157 {
 158         struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
 159         struct asd_sas_phy *sas_phy = &phy->sas_phy;
 160         phy->phy_state = PHY_LINK_DISABLE;
 161         phy->pm8001_ha = pm8001_ha;
 162         phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
 163         phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
 164         sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
 165         sas_phy->class = SAS;
 166         sas_phy->iproto = SAS_PROTOCOL_ALL;
 167         sas_phy->tproto = 0;
 168         sas_phy->type = PHY_TYPE_PHYSICAL;
 169         sas_phy->role = PHY_ROLE_INITIATOR;
 170         sas_phy->oob_mode = OOB_NOT_CONNECTED;
 171         sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
 172         sas_phy->id = phy_id;
 173         sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
 174         sas_phy->frame_rcvd = &phy->frame_rcvd[0];
 175         sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
 176         sas_phy->lldd_phy = phy;
 177 }
 178
 179 /**
 180  * pm8001_free - free hba
 181  * @pm8001_ha:  our hba structure.
 182  */
 183 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
 184 {
 185         int i;
 186
 187         if (!pm8001_ha)
 188                 return;
 189
 190         for (i = 0; i < USI_MAX_MEMCNT; i++) {
 191                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 192                         dma_free_coherent(&pm8001_ha->pdev->dev,
 193                                 (pm8001_ha->memoryMap.region[i].total_len +
 194                                 pm8001_ha->memoryMap.region[i].alignment),
 195                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 196                                 pm8001_ha->memoryMap.region[i].phys_addr);
 197                         }
 198         }
 199         PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
 200         flush_workqueue(pm8001_wq);
 201         bitmap_free(pm8001_ha->rsvd_tags);
 202         kfree(pm8001_ha);
 203 }
 204
 205 #ifdef PM8001_USE_TASKLET
 206
 207 /**
 208  * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
 209  * @opaque: the passed general host adapter struct
 210  * Note: pm8001_tasklet is common for pm8001 & pm80xx
 211  */
 212 static void pm8001_tasklet(unsigned long opaque)
 213 {
 214         struct pm8001_hba_info *pm8001_ha;
 215         struct isr_param *irq_vector;
 216
 217         irq_vector = (struct isr_param *)opaque;
 218         pm8001_ha = irq_vector->drv_inst;
 219         if (unlikely(!pm8001_ha))
 220                 BUG_ON(1);
 221         PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 222 }
 223 #endif
 224
 225 /**
 226  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
 227  * It obtains the vector number and calls the equivalent bottom
 228  * half or services directly.
 229  * @irq: interrupt number
 230  * @opaque: the passed outbound queue/vector. Host structure is
 231  * retrieved from the same.
 232  */
 233 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
 234 {
 235         struct isr_param *irq_vector;
 236         struct pm8001_hba_info *pm8001_ha;
 237         irqreturn_t ret = IRQ_HANDLED;
 238         irq_vector = (struct isr_param *)opaque;
 239         pm8001_ha = irq_vector->drv_inst;
 240
 241         if (unlikely(!pm8001_ha))
 242                 return IRQ_NONE;
 243         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 244                 return IRQ_NONE;
 245 #ifdef PM8001_USE_TASKLET
 246         tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
 247 #else
 248         ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
 249 #endif
 250         return ret;
 251 }
 252
 253 /**
 254  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
 255  * @irq: interrupt number
 256  * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
 257  */
 258
 259 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
 260 {
 261         struct pm8001_hba_info *pm8001_ha;
 262         irqreturn_t ret = IRQ_HANDLED;
 263         struct sas_ha_struct *sha = dev_id;
 264         pm8001_ha = sha->lldd_ha;
 265         if (unlikely(!pm8001_ha))
 266                 return IRQ_NONE;
 267         if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
 268                 return IRQ_NONE;
 269
 270 #ifdef PM8001_USE_TASKLET
 271         tasklet_schedule(&pm8001_ha->tasklet[0]);
 272 #else
 273         ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
 274 #endif
 275         return ret;
 276 }
 277
 278 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
 279 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
 280
 281 /**
 282  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
 283  * @pm8001_ha: our hba structure.
 284  * @ent: PCI device ID structure to match on
 285  */
 286 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
 287                         const struct pci_device_id *ent)
 288 {
 289         int i, count = 0, rc = 0;
 290         u32 ci_offset, ib_offset, ob_offset, pi_offset;
 291         struct inbound_queue_table *ibq;
 292         struct outbound_queue_table *obq;
 293
 294         spin_lock_init(&pm8001_ha->lock);
 295         spin_lock_init(&pm8001_ha->bitmap_lock);
 296         pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
 297                    pm8001_ha->chip->n_phy);
 298
 299         /* Setup Interrupt */
 300         rc = pm8001_setup_irq(pm8001_ha);
 301         if (rc) {
 302                 pm8001_dbg(pm8001_ha, FAIL,
 303                            "pm8001_setup_irq failed [ret: %d]\n", rc);
 304                 goto err_out;
 305         }
 306         /* Request Interrupt */
 307         rc = pm8001_request_irq(pm8001_ha);
 308         if (rc)
 309                 goto err_out;
 310
 311         count = pm8001_ha->max_q_num;
 312         /* Queues are chosen based on the number of cores/msix availability */
 313         ib_offset = pm8001_ha->ib_offset  = USI_MAX_MEMCNT_BASE;
 314         ci_offset = pm8001_ha->ci_offset  = ib_offset + count;
 315         ob_offset = pm8001_ha->ob_offset  = ci_offset + count;
 316         pi_offset = pm8001_ha->pi_offset  = ob_offset + count;
 317         pm8001_ha->max_memcnt = pi_offset + count;
 318
 319         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 320                 pm8001_phy_init(pm8001_ha, i);
 321                 pm8001_ha->port[i].wide_port_phymap = 0;
 322                 pm8001_ha->port[i].port_attached = 0;
 323                 pm8001_ha->port[i].port_state = 0;
 324                 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
 325         }
 326
 327         /* MPI Memory region 1 for AAP Event Log for fw */
 328         pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
 329         pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
 330         pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
 331         pm8001_ha->memoryMap.region[AAP1].alignment = 32;
 332
 333         /* MPI Memory region 2 for IOP Event Log for fw */
 334         pm8001_ha->memoryMap.region[IOP].num_elements = 1;
 335         pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
 336         pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
 337         pm8001_ha->memoryMap.region[IOP].alignment = 32;
 338
 339         for (i = 0; i < count; i++) {
 340                 ibq = &pm8001_ha->inbnd_q_tbl[i];
 341                 spin_lock_init(&ibq->iq_lock);
 342                 /* MPI Memory region 3 for consumer Index of inbound queues */
 343                 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
 344                 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
 345                 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
 346                 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
 347
 348                 if ((ent->driver_data) != chip_8001) {
 349                         /* MPI Memory region 5 inbound queues */
 350                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 351                                                 PM8001_MPI_QUEUE;
 352                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 353                                                                 = 128;
 354                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 355                                                 PM8001_MPI_QUEUE * 128;
 356                         pm8001_ha->memoryMap.region[ib_offset+i].alignment
 357                                                                 = 128;
 358                 } else {
 359                         pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
 360                                                 PM8001_MPI_QUEUE;
 361                         pm8001_ha->memoryMap.region[ib_offset+i].element_size
 362                                                                 = 64;
 363                         pm8001_ha->memoryMap.region[ib_offset+i].total_len =
 364                                                 PM8001_MPI_QUEUE * 64;
 365                         pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
 366                 }
 367         }
 368
 369         for (i = 0; i < count; i++) {
 370                 obq = &pm8001_ha->outbnd_q_tbl[i];
 371                 spin_lock_init(&obq->oq_lock);
 372                 /* MPI Memory region 4 for producer Index of outbound queues */
 373                 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
 374                 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
 375                 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
 376                 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
 377
 378                 if (ent->driver_data != chip_8001) {
 379                         /* MPI Memory region 6 Outbound queues */
 380                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 381                                                 PM8001_MPI_QUEUE;
 382                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 383                                                                 = 128;
 384                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 385                                                 PM8001_MPI_QUEUE * 128;
 386                         pm8001_ha->memoryMap.region[ob_offset+i].alignment
 387                                                                 = 128;
 388                 } else {
 389                         /* MPI Memory region 6 Outbound queues */
 390                         pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
 391                                                 PM8001_MPI_QUEUE;
 392                         pm8001_ha->memoryMap.region[ob_offset+i].element_size
 393                                                                 = 64;
 394                         pm8001_ha->memoryMap.region[ob_offset+i].total_len =
 395                                                 PM8001_MPI_QUEUE * 64;
 396                         pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
 397                 }
 398
 399         }
 400         /* Memory region write DMA*/
 401         pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
 402         pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
 403         pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
 404
 405         /* Memory region for fw flash */
 406         pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
 407
 408         pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
 409         pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
 410         pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
 411         pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
 412         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 413                 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
 414
 415                 if (pm8001_mem_alloc(pm8001_ha->pdev,
 416                                      &region->virt_ptr,
 417                                      &region->phys_addr,
 418                                      &region->phys_addr_hi,
 419                                      &region->phys_addr_lo,
 420                                      region->total_len,
 421                                      region->alignment) != 0) {
 422                         pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
 423                         goto err_out;
 424                 }
 425         }
 426
 427         /* Memory region for devices*/
 428         pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
 429                                 * sizeof(struct pm8001_device), GFP_KERNEL);
 430         if (!pm8001_ha->devices) {
 431                 rc = -ENOMEM;
 432                 goto err_out_nodev;
 433         }
 434         for (i = 0; i < PM8001_MAX_DEVICES; i++) {
 435                 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
 436                 pm8001_ha->devices[i].id = i;
 437                 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
 438                 atomic_set(&pm8001_ha->devices[i].running_req, 0);
 439         }
 440         pm8001_ha->flags = PM8001F_INIT_TIME;
 441         return 0;
 442
 443 err_out_nodev:
 444         for (i = 0; i < pm8001_ha->max_memcnt; i++) {
 445                 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
 446                         dma_free_coherent(&pm8001_ha->pdev->dev,
 447                                 (pm8001_ha->memoryMap.region[i].total_len +
 448                                 pm8001_ha->memoryMap.region[i].alignment),
 449                                 pm8001_ha->memoryMap.region[i].virt_ptr,
 450                                 pm8001_ha->memoryMap.region[i].phys_addr);
 451                 }
 452         }
 453 err_out:
 454         return 1;
 455 }
 456
 457 /**
 458  * pm8001_ioremap - remap the pci high physical address to kernel virtual
 459  * address so that we can access them.
 460  * @pm8001_ha: our hba structure.
 461  */
 462 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
 463 {
 464         u32 bar;
 465         u32 logicalBar = 0;
 466         struct pci_dev *pdev;
 467
 468         pdev = pm8001_ha->pdev;
 469         /* map pci mem (PMC pci base 0-3)*/
 470         for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
 471                 /*
 472                 ** logical BARs for SPC:
 473                 ** bar 0 and 1 - logical BAR0
 474                 ** bar 2 and 3 - logical BAR1
 475                 ** bar4 - logical BAR2
 476                 ** bar5 - logical BAR3
 477                 ** Skip the appropriate assignments:
 478                 */
 479                 if ((bar == 1) || (bar == 3))
 480                         continue;
 481                 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
 482                         pm8001_ha->io_mem[logicalBar].membase =
 483                                 pci_resource_start(pdev, bar);
 484                         pm8001_ha->io_mem[logicalBar].memsize =
 485                                 pci_resource_len(pdev, bar);
 486                         pm8001_ha->io_mem[logicalBar].memvirtaddr =
 487                                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
 488                                 pm8001_ha->io_mem[logicalBar].memsize);
 489                         if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
 490                                 pm8001_dbg(pm8001_ha, INIT,
 491                                         "Failed to ioremap bar %d, logicalBar %d",
 492                                    bar, logicalBar);
 493                                 return -ENOMEM;
 494                         }
 495                         pm8001_dbg(pm8001_ha, INIT,
 496                                    "base addr %llx virt_addr=%llx len=%d\n",
 497                                    (u64)pm8001_ha->io_mem[logicalBar].membase,
 498                                    (u64)(unsigned long)
 499                                    pm8001_ha->io_mem[logicalBar].memvirtaddr,
 500                                    pm8001_ha->io_mem[logicalBar].memsize);
 501                 } else {
 502                         pm8001_ha->io_mem[logicalBar].membase   = 0;
 503                         pm8001_ha->io_mem[logicalBar].memsize   = 0;
 504                         pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
 505                 }
 506                 logicalBar++;
 507         }
 508         return 0;
 509 }
 510
 511 /**
 512  * pm8001_pci_alloc - initialize our ha card structure
 513  * @pdev: pci device.
 514  * @ent: ent
 515  * @shost: scsi host struct which has been initialized before.
 516  */
 517 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
 518                                  const struct pci_device_id *ent,
 519                                 struct Scsi_Host *shost)
 520
 521 {
 522         struct pm8001_hba_info *pm8001_ha;
 523         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 524         int j;
 525
 526         pm8001_ha = sha->lldd_ha;
 527         if (!pm8001_ha)
 528                 return NULL;
 529
 530         pm8001_ha->pdev = pdev;
 531         pm8001_ha->dev = &pdev->dev;
 532         pm8001_ha->chip_id = ent->driver_data;
 533         pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
 534         pm8001_ha->irq = pdev->irq;
 535         pm8001_ha->sas = sha;
 536         pm8001_ha->shost = shost;
 537         pm8001_ha->id = pm8001_id++;
 538         pm8001_ha->logging_level = logging_level;
 539         pm8001_ha->non_fatal_count = 0;
 540         if (link_rate >= 1 && link_rate <= 15)
 541                 pm8001_ha->link_rate = (link_rate << 8);
 542         else {
 543                 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
 544                         LINKRATE_60 | LINKRATE_120;
 545                 pm8001_dbg(pm8001_ha, FAIL,
 546                            "Setting link rate to default value\n");
 547         }
 548         sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
 549         /* IOMB size is 128 for 8088/89 controllers */
 550         if (pm8001_ha->chip_id != chip_8001)
 551                 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
 552         else
 553                 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
 554
 555 #ifdef PM8001_USE_TASKLET
 556         /* Tasklet for non msi-x interrupt handler */
 557         if ((!pdev->msix_cap || !pci_msi_enabled())
 558             || (pm8001_ha->chip_id == chip_8001))
 559                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
 560                         (unsigned long)&(pm8001_ha->irq_vector[0]));
 561         else
 562                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
 563                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
 564                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
 565 #endif
 566         if (pm8001_ioremap(pm8001_ha))
 567                 goto failed_pci_alloc;
 568         if (!pm8001_alloc(pm8001_ha, ent))
 569                 return pm8001_ha;
 570 failed_pci_alloc:
 571         pm8001_free(pm8001_ha);
 572         return NULL;
 573 }
 574
 575 /**
 576  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
 577  * @pdev: pci device.
 578  */
 579 static int pci_go_44(struct pci_dev *pdev)
 580 {
 581         int rc;
 582
 583         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
 584         if (rc) {
 585                 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 586                 if (rc)
 587                         dev_printk(KERN_ERR, &pdev->dev,
 588                                 "32-bit DMA enable failed\n");
 589         }
 590         return rc;
 591 }
 592
 593 /**
 594  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
 595  * @shost: scsi host which has been allocated outside.
 596  * @chip_info: our ha struct.
 597  */
 598 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
 599                                    const struct pm8001_chip_info *chip_info)
 600 {
 601         int phy_nr, port_nr;
 602         struct asd_sas_phy **arr_phy;
 603         struct asd_sas_port **arr_port;
 604         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 605
 606         phy_nr = chip_info->n_phy;
 607         port_nr = phy_nr;
 608         memset(sha, 0x00, sizeof(*sha));
 609         arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
 610         if (!arr_phy)
 611                 goto exit;
 612         arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
 613         if (!arr_port)
 614                 goto exit_free2;
 615
 616         sha->sas_phy = arr_phy;
 617         sha->sas_port = arr_port;
 618         sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
 619         if (!sha->lldd_ha)
 620                 goto exit_free1;
 621
 622         shost->transportt = pm8001_stt;
 623         shost->max_id = PM8001_MAX_DEVICES;
 624         shost->unique_id = pm8001_id;
 625         shost->max_cmd_len = 16;
 626         return 0;
 627 exit_free1:
 628         kfree(arr_port);
 629 exit_free2:
 630         kfree(arr_phy);
 631 exit:
 632         return -1;
 633 }
 634
 635 /**
 636  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
 637  * @shost: scsi host which has been allocated outside
 638  * @chip_info: our ha struct.
 639  */
 640 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
 641                                      const struct pm8001_chip_info *chip_info)
 642 {
 643         int i = 0;
 644         struct pm8001_hba_info *pm8001_ha;
 645         struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
 646
 647         pm8001_ha = sha->lldd_ha;
 648         for (i = 0; i < chip_info->n_phy; i++) {
 649                 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
 650                 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
 651                 sha->sas_phy[i]->sas_addr =
 652                         (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
 653         }
 654         sha->sas_ha_name = DRV_NAME;
 655         sha->dev = pm8001_ha->dev;
 656         sha->strict_wide_ports = 1;
 657         sha->lldd_module = THIS_MODULE;
 658         sha->sas_addr = &pm8001_ha->sas_addr[0];
 659         sha->num_phys = chip_info->n_phy;
 660         sha->core.shost = shost;
 661 }
 662
 663 /**
 664  * pm8001_init_sas_add - initialize sas address
 665  * @pm8001_ha: our ha struct.
 666  *
 667  * Currently we just set the fixed SAS address to our HBA, for manufacture,
 668  * it should read from the EEPROM
 669  */
 670 static int pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
 671 {
 672         u8 i, j;
 673         u8 sas_add[8];
 674 #ifdef PM8001_READ_VPD
 675         /* For new SPC controllers WWN is stored in flash vpd
 676         *  For SPC/SPCve controllers WWN is stored in EEPROM
 677         *  For Older SPC WWN is stored in NVMD
 678         */
 679         DECLARE_COMPLETION_ONSTACK(completion);
 680         struct pm8001_ioctl_payload payload;
 681         u16 deviceid;
 682         int rc;
 683         unsigned long time_remaining;
 684
 685         if (PM8001_CHIP_DISP->fatal_errors(pm8001_ha)) {
 686                 pm8001_dbg(pm8001_ha, FAIL, "controller is in fatal error state\n");
 687                 return -EIO;
 688         }
 689
 690         pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 691         pm8001_ha->nvmd_completion = &completion;
 692
 693         if (pm8001_ha->chip_id == chip_8001) {
 694                 if (deviceid == 0x8081 || deviceid == 0x0042) {
 695                         payload.minor_function = 4;
 696                         payload.rd_length = 4096;
 697                 } else {
 698                         payload.minor_function = 0;
 699                         payload.rd_length = 128;
 700                 }
 701         } else if ((pm8001_ha->chip_id == chip_8070 ||
 702                         pm8001_ha->chip_id == chip_8072) &&
 703                         pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 704                 payload.minor_function = 4;
 705                 payload.rd_length = 4096;
 706         } else {
 707                 payload.minor_function = 1;
 708                 payload.rd_length = 4096;
 709         }
 710         payload.offset = 0;
 711         payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
 712         if (!payload.func_specific) {
 713                 pm8001_dbg(pm8001_ha, FAIL, "mem alloc fail\n");
 714                 return -ENOMEM;
 715         }
 716         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 717         if (rc) {
 718                 kfree(payload.func_specific);
 719                 pm8001_dbg(pm8001_ha, FAIL, "nvmd failed\n");
 720                 return -EIO;
 721         }
 722         time_remaining = wait_for_completion_timeout(&completion,
 723                                 msecs_to_jiffies(60*1000)); // 1 min
 724         if (!time_remaining) {
 725                 kfree(payload.func_specific);
 726                 pm8001_dbg(pm8001_ha, FAIL, "get_nvmd_req timeout\n");
 727                 return -EIO;
 728         }
 729
 730
 731         for (i = 0, j = 0; i <= 7; i++, j++) {
 732                 if (pm8001_ha->chip_id == chip_8001) {
 733                         if (deviceid == 0x8081)
 734                                 pm8001_ha->sas_addr[j] =
 735                                         payload.func_specific[0x704 + i];
 736                         else if (deviceid == 0x0042)
 737                                 pm8001_ha->sas_addr[j] =
 738                                         payload.func_specific[0x010 + i];
 739                 } else if ((pm8001_ha->chip_id == chip_8070 ||
 740                                 pm8001_ha->chip_id == chip_8072) &&
 741                                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
 742                         pm8001_ha->sas_addr[j] =
 743                                         payload.func_specific[0x010 + i];
 744                 } else
 745                         pm8001_ha->sas_addr[j] =
 746                                         payload.func_specific[0x804 + i];
 747         }
 748         memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
 749         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 750                 if (i && ((i % 4) == 0))
 751                         sas_add[7] = sas_add[7] + 4;
 752                 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
 753                         sas_add, SAS_ADDR_SIZE);
 754                 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
 755                            pm8001_ha->phy[i].dev_sas_addr);
 756         }
 757         kfree(payload.func_specific);
 758 #else
 759         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 760                 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
 761                 pm8001_ha->phy[i].dev_sas_addr =
 762                         cpu_to_be64((u64)
 763                                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
 764         }
 765         memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
 766                 SAS_ADDR_SIZE);
 767 #endif
 768         return 0;
 769 }
 770
 771 /*
 772  * pm8001_get_phy_settings_info : Read phy setting values.
 773  * @pm8001_ha : our hba.
 774  */
 775 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
 776 {
 777
 778 #ifdef PM8001_READ_VPD
 779         /*OPTION ROM FLASH read for the SPC cards */
 780         DECLARE_COMPLETION_ONSTACK(completion);
 781         struct pm8001_ioctl_payload payload;
 782         int rc;
 783
 784         pm8001_ha->nvmd_completion = &completion;
 785         /* SAS ADDRESS read from flash / EEPROM */
 786         payload.minor_function = 6;
 787         payload.offset = 0;
 788         payload.rd_length = 4096;
 789         payload.func_specific = kzalloc(4096, GFP_KERNEL);
 790         if (!payload.func_specific)
 791                 return -ENOMEM;
 792         /* Read phy setting values from flash */
 793         rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
 794         if (rc) {
 795                 kfree(payload.func_specific);
 796                 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
 797                 return -ENOMEM;
 798         }
 799         wait_for_completion(&completion);
 800         pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
 801         kfree(payload.func_specific);
 802 #endif
 803         return 0;
 804 }
 805
 806 struct pm8001_mpi3_phy_pg_trx_config {
 807         u32 LaneLosCfg;
 808         u32 LanePgaCfg1;
 809         u32 LanePisoCfg1;
 810         u32 LanePisoCfg2;
 811         u32 LanePisoCfg3;
 812         u32 LanePisoCfg4;
 813         u32 LanePisoCfg5;
 814         u32 LanePisoCfg6;
 815         u32 LaneBctCtrl;
 816 };
 817
 818 /**
 819  * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
 820  * @pm8001_ha : our adapter
 821  * @phycfg : PHY config page to populate
 822  */
 823 static
 824 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
 825                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 826 {
 827         phycfg->LaneLosCfg   = 0x00000132;
 828         phycfg->LanePgaCfg1  = 0x00203949;
 829         phycfg->LanePisoCfg1 = 0x000000FF;
 830         phycfg->LanePisoCfg2 = 0xFF000001;
 831         phycfg->LanePisoCfg3 = 0xE7011300;
 832         phycfg->LanePisoCfg4 = 0x631C40C0;
 833         phycfg->LanePisoCfg5 = 0xF8102036;
 834         phycfg->LanePisoCfg6 = 0xF74A1000;
 835         phycfg->LaneBctCtrl  = 0x00FB33F8;
 836 }
 837
 838 /**
 839  * pm8001_get_external_phy_settings - Retrieves the external PHY settings
 840  * @pm8001_ha : our adapter
 841  * @phycfg : PHY config page to populate
 842  */
 843 static
 844 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
 845                 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
 846 {
 847         phycfg->LaneLosCfg   = 0x00000132;
 848         phycfg->LanePgaCfg1  = 0x00203949;
 849         phycfg->LanePisoCfg1 = 0x000000FF;
 850         phycfg->LanePisoCfg2 = 0xFF000001;
 851         phycfg->LanePisoCfg3 = 0xE7011300;
 852         phycfg->LanePisoCfg4 = 0x63349140;
 853         phycfg->LanePisoCfg5 = 0xF8102036;
 854         phycfg->LanePisoCfg6 = 0xF80D9300;
 855         phycfg->LaneBctCtrl  = 0x00FB33F8;
 856 }
 857
 858 /**
 859  * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
 860  * @pm8001_ha : our adapter
 861  * @phymask : The PHY mask
 862  */
 863 static
 864 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
 865 {
 866         switch (pm8001_ha->pdev->subsystem_device) {
 867         case 0x0070: /* H1280 - 8 external 0 internal */
 868         case 0x0072: /* H12F0 - 16 external 0 internal */
 869                 *phymask = 0x0000;
 870                 break;
 871
 872         case 0x0071: /* H1208 - 0 external 8 internal */
 873         case 0x0073: /* H120F - 0 external 16 internal */
 874                 *phymask = 0xFFFF;
 875                 break;
 876
 877         case 0x0080: /* H1244 - 4 external 4 internal */
 878                 *phymask = 0x00F0;
 879                 break;
 880
 881         case 0x0081: /* H1248 - 4 external 8 internal */
 882                 *phymask = 0x0FF0;
 883                 break;
 884
 885         case 0x0082: /* H1288 - 8 external 8 internal */
 886                 *phymask = 0xFF00;
 887                 break;
 888
 889         default:
 890                 pm8001_dbg(pm8001_ha, INIT,
 891                            "Unknown subsystem device=0x%.04x\n",
 892                            pm8001_ha->pdev->subsystem_device);
 893         }
 894 }
 895
 896 /**
 897  * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
 898  * @pm8001_ha : our adapter
 899  */
 900 static
 901 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
 902 {
 903         struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
 904         struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
 905         int phymask = 0;
 906         int i = 0;
 907
 908         memset(&phycfg_int, 0, sizeof(phycfg_int));
 909         memset(&phycfg_ext, 0, sizeof(phycfg_ext));
 910
 911         pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
 912         pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
 913         pm8001_get_phy_mask(pm8001_ha, &phymask);
 914
 915         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
 916                 if (phymask & (1 << i)) {/* Internal PHY */
 917                         pm8001_set_phy_profile_single(pm8001_ha, i,
 918                                         sizeof(phycfg_int) / sizeof(u32),
 919                                         (u32 *)&phycfg_int);
 920
 921                 } else { /* External PHY */
 922                         pm8001_set_phy_profile_single(pm8001_ha, i,
 923                                         sizeof(phycfg_ext) / sizeof(u32),
 924                                         (u32 *)&phycfg_ext);
 925                 }
 926         }
 927
 928         return 0;
 929 }
 930
 931 /**
 932  * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
 933  * @pm8001_ha : our hba.
 934  */
 935 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
 936 {
 937         switch (pm8001_ha->pdev->subsystem_vendor) {
 938         case PCI_VENDOR_ID_ATTO:
 939                 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
 940                         return 0;
 941                 else
 942                         return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
 943
 944         case PCI_VENDOR_ID_ADAPTEC2:
 945         case 0:
 946                 return 0;
 947
 948         default:
 949                 return pm8001_get_phy_settings_info(pm8001_ha);
 950         }
 951 }
 952
 953 #ifdef PM8001_USE_MSIX
 954 /**
 955  * pm8001_setup_msix - enable MSI-X interrupt
 956  * @pm8001_ha: our ha struct.
 957  */
 958 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
 959 {
 960         unsigned int allocated_irq_vectors;
 961         int rc;
 962
 963         /* SPCv controllers supports 64 msi-x */
 964         if (pm8001_ha->chip_id == chip_8001) {
 965                 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1,
 966                                            PCI_IRQ_MSIX);
 967         } else {
 968                 /*
 969                  * Queue index #0 is used always for housekeeping, so don't
 970                  * include in the affinity spreading.
 971                  */
 972                 struct irq_affinity desc = {
 973                         .pre_vectors = 1,
 974                 };
 975                 rc = pci_alloc_irq_vectors_affinity(
 976                                 pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC,
 977                                 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc);
 978         }
 979
 980         allocated_irq_vectors = rc;
 981         if (rc < 0)
 982                 return rc;
 983
 984         /* Assigns the number of interrupts */
 985         pm8001_ha->number_of_intr = allocated_irq_vectors;
 986
 987         /* Maximum queue number updating in HBA structure */
 988         pm8001_ha->max_q_num = allocated_irq_vectors;
 989
 990         pm8001_dbg(pm8001_ha, INIT,
 991                    "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
 992                    rc, pm8001_ha->number_of_intr);
 993         return 0;
 994 }
 995
 996 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
 997 {
 998         u32 i = 0, j = 0;
 999         int flag = 0, rc = 0;
1000         int nr_irqs = pm8001_ha->number_of_intr;
1001
1002         if (pm8001_ha->chip_id != chip_8001)
1003                 flag &= ~IRQF_SHARED;
1004
1005         pm8001_dbg(pm8001_ha, INIT,
1006                    "pci_enable_msix request number of intr %d\n",
1007                    pm8001_ha->number_of_intr);
1008
1009         if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
1010                 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
1011
1012         for (i = 0; i < nr_irqs; i++) {
1013                 snprintf(pm8001_ha->intr_drvname[i],
1014                         sizeof(pm8001_ha->intr_drvname[0]),
1015                         "%s-%d", pm8001_ha->name, i);
1016                 pm8001_ha->irq_vector[i].irq_id = i;
1017                 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
1018
1019                 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
1020                         pm8001_interrupt_handler_msix, flag,
1021                         pm8001_ha->intr_drvname[i],
1022                         &(pm8001_ha->irq_vector[i]));
1023                 if (rc) {
1024                         for (j = 0; j < i; j++) {
1025                                 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
1026                                         &(pm8001_ha->irq_vector[i]));
1027                         }
1028                         pci_free_irq_vectors(pm8001_ha->pdev);
1029                         break;
1030                 }
1031         }
1032
1033         return rc;
1034 }
1035 #endif
1036
1037 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
1038 {
1039         struct pci_dev *pdev;
1040
1041         pdev = pm8001_ha->pdev;
1042
1043 #ifdef PM8001_USE_MSIX
1044         if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1045                 return pm8001_setup_msix(pm8001_ha);
1046         pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1047 #endif
1048         return 0;
1049 }
1050
1051 /**
1052  * pm8001_request_irq - register interrupt
1053  * @pm8001_ha: our ha struct.
1054  */
1055 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1056 {
1057         struct pci_dev *pdev;
1058         int rc;
1059
1060         pdev = pm8001_ha->pdev;
1061
1062 #ifdef PM8001_USE_MSIX
1063         if (pdev->msix_cap && pci_msi_enabled())
1064                 return pm8001_request_msix(pm8001_ha);
1065         else {
1066                 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1067                 goto intx;
1068         }
1069 #endif
1070
1071 intx:
1072         /* initialize the INT-X interrupt */
1073         pm8001_ha->irq_vector[0].irq_id = 0;
1074         pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1075         rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1076                 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1077         return rc;
1078 }
1079
1080 /**
1081  * pm8001_pci_probe - probe supported device
1082  * @pdev: pci device which kernel has been prepared for.
1083  * @ent: pci device id
1084  *
1085  * This function is the main initialization function, when register a new
1086  * pci driver it is invoked, all struct and hardware initialization should be
1087  * done here, also, register interrupt.
1088  */
1089 static int pm8001_pci_probe(struct pci_dev *pdev,
1090                             const struct pci_device_id *ent)
1091 {
1092         unsigned int rc;
1093         u32     pci_reg;
1094         u8      i = 0;
1095         struct pm8001_hba_info *pm8001_ha;
1096         struct Scsi_Host *shost = NULL;
1097         const struct pm8001_chip_info *chip;
1098         struct sas_ha_struct *sha;
1099
1100         dev_printk(KERN_INFO, &pdev->dev,
1101                 "pm80xx: driver version %s\n", DRV_VERSION);
1102         rc = pci_enable_device(pdev);
1103         if (rc)
1104                 goto err_out_enable;
1105         pci_set_master(pdev);
1106         /*
1107          * Enable pci slot busmaster by setting pci command register.
1108          * This is required by FW for Cyclone card.
1109          */
1110
1111         pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1112         pci_reg |= 0x157;
1113         pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1114         rc = pci_request_regions(pdev, DRV_NAME);
1115         if (rc)
1116                 goto err_out_disable;
1117         rc = pci_go_44(pdev);
1118         if (rc)
1119                 goto err_out_regions;
1120
1121         shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1122         if (!shost) {
1123                 rc = -ENOMEM;
1124                 goto err_out_regions;
1125         }
1126         chip = &pm8001_chips[ent->driver_data];
1127         sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1128         if (!sha) {
1129                 rc = -ENOMEM;
1130                 goto err_out_free_host;
1131         }
1132         SHOST_TO_SAS_HA(shost) = sha;
1133
1134         rc = pm8001_prep_sas_ha_init(shost, chip);
1135         if (rc) {
1136                 rc = -ENOMEM;
1137                 goto err_out_free;
1138         }
1139         pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1140         /* ent->driver variable is used to differentiate between controllers */
1141         pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1142         if (!pm8001_ha) {
1143                 rc = -ENOMEM;
1144                 goto err_out_free;
1145         }
1146
1147         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1148         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1149         if (rc) {
1150                 pm8001_dbg(pm8001_ha, FAIL,
1151                            "chip_init failed [ret: %d]\n", rc);
1152                 goto err_out_ha_free;
1153         }
1154
1155         rc = pm8001_init_ccb_tag(pm8001_ha);
1156         if (rc)
1157                 goto err_out_enable;
1158
1159
1160         PM8001_CHIP_DISP->chip_post_init(pm8001_ha);
1161
1162         if (pm8001_ha->number_of_intr > 1) {
1163                 shost->nr_hw_queues = pm8001_ha->number_of_intr - 1;
1164                 /*
1165                  * For now, ensure we're not sent too many commands by setting
1166                  * host_tagset. This is also required if we start using request
1167                  * tag.
1168                  */
1169                 shost->host_tagset = 1;
1170         }
1171
1172         rc = scsi_add_host(shost, &pdev->dev);
1173         if (rc)
1174                 goto err_out_ha_free;
1175
1176         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1177         if (pm8001_ha->chip_id != chip_8001) {
1178                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1179                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1180                 /* setup thermal configuration. */
1181                 pm80xx_set_thermal_config(pm8001_ha);
1182         }
1183
1184         if (pm8001_init_sas_add(pm8001_ha))
1185                 goto err_out_shost;
1186         /* phy setting support for motherboard controller */
1187         rc = pm8001_configure_phy_settings(pm8001_ha);
1188         if (rc)
1189                 goto err_out_shost;
1190
1191         pm8001_post_sas_ha_init(shost, chip);
1192         rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1193         if (rc) {
1194                 pm8001_dbg(pm8001_ha, FAIL,
1195                            "sas_register_ha failed [ret: %d]\n", rc);
1196                 goto err_out_shost;
1197         }
1198         list_add_tail(&pm8001_ha->list, &hba_list);
1199         pm8001_ha->flags = PM8001F_RUN_TIME;
1200         scsi_scan_host(pm8001_ha->shost);
1201         return 0;
1202
1203 err_out_shost:
1204         scsi_remove_host(pm8001_ha->shost);
1205 err_out_ha_free:
1206         pm8001_free(pm8001_ha);
1207 err_out_free:
1208         kfree(sha);
1209 err_out_free_host:
1210         scsi_host_put(shost);
1211 err_out_regions:
1212         pci_release_regions(pdev);
1213 err_out_disable:
1214         pci_disable_device(pdev);
1215 err_out_enable:
1216         return rc;
1217 }
1218
1219 /**
1220  * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1221  * @pm8001_ha: our hba card information.
1222  */
1223 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha)
1224 {
1225         struct Scsi_Host *shost = pm8001_ha->shost;
1226         struct device *dev = pm8001_ha->dev;
1227         u32 max_out_io, ccb_count;
1228         int i;
1229
1230         max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1231         ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1232
1233         shost->can_queue = ccb_count - PM8001_RESERVE_SLOT;
1234
1235         pm8001_ha->rsvd_tags = bitmap_zalloc(PM8001_RESERVE_SLOT, GFP_KERNEL);
1236         if (!pm8001_ha->rsvd_tags)
1237                 goto err_out;
1238
1239         /* Memory region for ccb_info*/
1240         pm8001_ha->ccb_count = ccb_count;
1241         pm8001_ha->ccb_info =
1242                 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1243         if (!pm8001_ha->ccb_info) {
1244                 pm8001_dbg(pm8001_ha, FAIL,
1245                            "Unable to allocate memory for ccb\n");
1246                 goto err_out_noccb;
1247         }
1248         for (i = 0; i < ccb_count; i++) {
1249                 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev,
1250                                 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1251                                 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1252                                 GFP_KERNEL);
1253                 if (!pm8001_ha->ccb_info[i].buf_prd) {
1254                         pm8001_dbg(pm8001_ha, FAIL,
1255                                    "ccb prd memory allocation error\n");
1256                         goto err_out;
1257                 }
1258                 pm8001_ha->ccb_info[i].task = NULL;
1259                 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;
1260                 pm8001_ha->ccb_info[i].device = NULL;
1261         }
1262
1263         return 0;
1264
1265 err_out_noccb:
1266         kfree(pm8001_ha->devices);
1267 err_out:
1268         return -ENOMEM;
1269 }
1270
1271 static void pm8001_pci_remove(struct pci_dev *pdev)
1272 {
1273         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1274         struct pm8001_hba_info *pm8001_ha;
1275         int i, j;
1276         pm8001_ha = sha->lldd_ha;
1277         sas_unregister_ha(sha);
1278         sas_remove_host(pm8001_ha->shost);
1279         list_del(&pm8001_ha->list);
1280         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1281         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1282
1283 #ifdef PM8001_USE_MSIX
1284         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1285                 synchronize_irq(pci_irq_vector(pdev, i));
1286         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1287                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1288         pci_free_irq_vectors(pdev);
1289 #else
1290         free_irq(pm8001_ha->irq, sha);
1291 #endif
1292 #ifdef PM8001_USE_TASKLET
1293         /* For non-msix and msix interrupts */
1294         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1295             (pm8001_ha->chip_id == chip_8001))
1296                 tasklet_kill(&pm8001_ha->tasklet[0]);
1297         else
1298                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1299                         tasklet_kill(&pm8001_ha->tasklet[j]);
1300 #endif
1301         scsi_host_put(pm8001_ha->shost);
1302
1303         for (i = 0; i < pm8001_ha->ccb_count; i++) {
1304                 dma_free_coherent(&pm8001_ha->pdev->dev,
1305                         sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1306                         pm8001_ha->ccb_info[i].buf_prd,
1307                         pm8001_ha->ccb_info[i].ccb_dma_handle);
1308         }
1309         kfree(pm8001_ha->ccb_info);
1310         kfree(pm8001_ha->devices);
1311
1312         pm8001_free(pm8001_ha);
1313         kfree(sha->sas_phy);
1314         kfree(sha->sas_port);
1315         kfree(sha);
1316         pci_release_regions(pdev);
1317         pci_disable_device(pdev);
1318 }
1319
1320 /**
1321  * pm8001_pci_suspend - power management suspend main entry point
1322  * @dev: Device struct
1323  *
1324  * Return: 0 on success, anything else on error.
1325  */
1326 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1327 {
1328         struct pci_dev *pdev = to_pci_dev(dev);
1329         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1330         struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1331         int  i, j;
1332         sas_suspend_ha(sha);
1333         flush_workqueue(pm8001_wq);
1334         scsi_block_requests(pm8001_ha->shost);
1335         if (!pdev->pm_cap) {
1336                 dev_err(dev, " PCI PM not supported\n");
1337                 return -ENODEV;
1338         }
1339         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1340         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1341 #ifdef PM8001_USE_MSIX
1342         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1343                 synchronize_irq(pci_irq_vector(pdev, i));
1344         for (i = 0; i < pm8001_ha->number_of_intr; i++)
1345                 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1346         pci_free_irq_vectors(pdev);
1347 #else
1348         free_irq(pm8001_ha->irq, sha);
1349 #endif
1350 #ifdef PM8001_USE_TASKLET
1351         /* For non-msix and msix interrupts */
1352         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1353             (pm8001_ha->chip_id == chip_8001))
1354                 tasklet_kill(&pm8001_ha->tasklet[0]);
1355         else
1356                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1357                         tasklet_kill(&pm8001_ha->tasklet[j]);
1358 #endif
1359         pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1360                       "suspended state\n", pdev,
1361                       pm8001_ha->name);
1362         return 0;
1363 }
1364
1365 /**
1366  * pm8001_pci_resume - power management resume main entry point
1367  * @dev: Device struct
1368  *
1369  * Return: 0 on success, anything else on error.
1370  */
1371 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1372 {
1373         struct pci_dev *pdev = to_pci_dev(dev);
1374         struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1375         struct pm8001_hba_info *pm8001_ha;
1376         int rc;
1377         u8 i = 0, j;
1378         DECLARE_COMPLETION_ONSTACK(completion);
1379
1380         pm8001_ha = sha->lldd_ha;
1381
1382         pm8001_info(pm8001_ha,
1383                     "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1384                     pdev, pm8001_ha->name, pdev->current_state);
1385
1386         rc = pci_go_44(pdev);
1387         if (rc)
1388                 goto err_out_disable;
1389         sas_prep_resume_ha(sha);
1390         /* chip soft rst only for spc */
1391         if (pm8001_ha->chip_id == chip_8001) {
1392                 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1393                 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1394         }
1395         rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1396         if (rc)
1397                 goto err_out_disable;
1398
1399         /* disable all the interrupt bits */
1400         PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1401
1402         rc = pm8001_request_irq(pm8001_ha);
1403         if (rc)
1404                 goto err_out_disable;
1405 #ifdef PM8001_USE_TASKLET
1406         /*  Tasklet for non msi-x interrupt handler */
1407         if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1408             (pm8001_ha->chip_id == chip_8001))
1409                 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1410                         (unsigned long)&(pm8001_ha->irq_vector[0]));
1411         else
1412                 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1413                         tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1414                                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1415 #endif
1416         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1417         if (pm8001_ha->chip_id != chip_8001) {
1418                 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1419                         PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1420         }
1421
1422         /* Chip documentation for the 8070 and 8072 SPCv    */
1423         /* states that a 500ms minimum delay is required    */
1424         /* before issuing commands. Otherwise, the firmware */
1425         /* will enter an unrecoverable state.               */
1426
1427         if (pm8001_ha->chip_id == chip_8070 ||
1428                 pm8001_ha->chip_id == chip_8072) {
1429                 mdelay(500);
1430         }
1431
1432         /* Spin up the PHYs */
1433
1434         pm8001_ha->flags = PM8001F_RUN_TIME;
1435         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1436                 pm8001_ha->phy[i].enable_completion = &completion;
1437                 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1438                 wait_for_completion(&completion);
1439         }
1440         sas_resume_ha(sha);
1441         return 0;
1442
1443 err_out_disable:
1444         scsi_remove_host(pm8001_ha->shost);
1445
1446         return rc;
1447 }
1448
1449 /* update of pci device, vendor id and driver data with
1450  * unique value for each of the controller
1451  */
1452 static struct pci_device_id pm8001_pci_table[] = {
1453         { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1454         { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1455         { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1456         { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1457         /* Support for SPC/SPCv/SPCve controllers */
1458         { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1459         { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1460         { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1461         { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1462         { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1463         { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1464         { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1465         { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1466         { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1467         { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1468         { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1469         { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1470         { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1471         { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1472         { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1473         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1474                 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1475         { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1476                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1477         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1478                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1479         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1480                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1481         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1482                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1483         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1484                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1485         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1486                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1487         { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1488                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1489         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1490                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1491         { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1492                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1493         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1494                 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1495         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1496                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1497         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1498                 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1499         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1500                 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1501         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1502                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1503         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1504                 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1505         { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1506                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1507         { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1508                 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1509         { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1510                 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1511         { PCI_VENDOR_ID_ATTO, 0x8070,
1512                 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1513         { PCI_VENDOR_ID_ATTO, 0x8070,
1514                 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1515         { PCI_VENDOR_ID_ATTO, 0x8072,
1516                 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1517         { PCI_VENDOR_ID_ATTO, 0x8072,
1518                 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1519         { PCI_VENDOR_ID_ATTO, 0x8070,
1520                 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1521         { PCI_VENDOR_ID_ATTO, 0x8072,
1522                 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1523         { PCI_VENDOR_ID_ATTO, 0x8072,
1524                 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1525         {} /* terminate list */
1526 };
1527
1528 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1529                          pm8001_pci_suspend,
1530                          pm8001_pci_resume);
1531
1532 static struct pci_driver pm8001_pci_driver = {
1533         .name           = DRV_NAME,
1534         .id_table       = pm8001_pci_table,
1535         .probe          = pm8001_pci_probe,
1536         .remove         = pm8001_pci_remove,
1537         .driver.pm      = &pm8001_pci_pm_ops,
1538 };
1539
1540 /**
1541  *      pm8001_init - initialize scsi transport template
1542  */
1543 static int __init pm8001_init(void)
1544 {
1545         int rc = -ENOMEM;
1546
1547         pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1548         if (!pm8001_wq)
1549                 goto err;
1550
1551         pm8001_id = 0;
1552         pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1553         if (!pm8001_stt)
1554                 goto err_wq;
1555         rc = pci_register_driver(&pm8001_pci_driver);
1556         if (rc)
1557                 goto err_tp;
1558         return 0;
1559
1560 err_tp:
1561         sas_release_transport(pm8001_stt);
1562 err_wq:
1563         destroy_workqueue(pm8001_wq);
1564 err:
1565         return rc;
1566 }
1567
1568 static void __exit pm8001_exit(void)
1569 {
1570         pci_unregister_driver(&pm8001_pci_driver);
1571         sas_release_transport(pm8001_stt);
1572         destroy_workqueue(pm8001_wq);
1573 }
1574
1575 module_init(pm8001_init);
1576 module_exit(pm8001_exit);
1577
1578 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1579 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1580 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1581 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1582 MODULE_DESCRIPTION(
1583                 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1584                 "SAS/SATA controller driver");
1585 MODULE_VERSION(DRV_VERSION);
1586 MODULE_LICENSE("GPL");
1587 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1588