2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
4 * Copyright (c) 2008-2009 USI Co., Ltd.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm8001_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45 #include "pm80xx_tracepoints.h"
48 * read_main_config_table - read the configure table and save it.
49 * @pm8001_ha: our hba card information
51 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
53 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
54 pm8001_ha->main_cfg_tbl.pm8001_tbl.signature =
55 pm8001_mr32(address, 0x00);
56 pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
57 pm8001_mr32(address, 0x04);
58 pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
59 pm8001_mr32(address, 0x08);
60 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io =
61 pm8001_mr32(address, 0x0C);
62 pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl =
63 pm8001_mr32(address, 0x10);
64 pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
65 pm8001_mr32(address, 0x14);
66 pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset =
67 pm8001_mr32(address, 0x18);
68 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
69 pm8001_mr32(address, MAIN_IBQ_OFFSET);
70 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
71 pm8001_mr32(address, MAIN_OBQ_OFFSET);
72 pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag =
73 pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
75 /* read analog Setting offset from the configuration table */
76 pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
77 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
79 /* read Error Dump Offset and Length */
80 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
81 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
82 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
83 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
84 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
85 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
86 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
87 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
91 * read_general_status_table - read the general status table and save it.
92 * @pm8001_ha: our hba card information
94 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
96 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
97 pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate =
98 pm8001_mr32(address, 0x00);
99 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0 =
100 pm8001_mr32(address, 0x04);
101 pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1 =
102 pm8001_mr32(address, 0x08);
103 pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt =
104 pm8001_mr32(address, 0x0C);
105 pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt =
106 pm8001_mr32(address, 0x10);
107 pm8001_ha->gs_tbl.pm8001_tbl.rsvd =
108 pm8001_mr32(address, 0x14);
109 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0] =
110 pm8001_mr32(address, 0x18);
111 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1] =
112 pm8001_mr32(address, 0x1C);
113 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2] =
114 pm8001_mr32(address, 0x20);
115 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3] =
116 pm8001_mr32(address, 0x24);
117 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4] =
118 pm8001_mr32(address, 0x28);
119 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5] =
120 pm8001_mr32(address, 0x2C);
121 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6] =
122 pm8001_mr32(address, 0x30);
123 pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7] =
124 pm8001_mr32(address, 0x34);
125 pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val =
126 pm8001_mr32(address, 0x38);
127 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0] =
128 pm8001_mr32(address, 0x3C);
129 pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1] =
130 pm8001_mr32(address, 0x40);
131 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0] =
132 pm8001_mr32(address, 0x44);
133 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1] =
134 pm8001_mr32(address, 0x48);
135 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2] =
136 pm8001_mr32(address, 0x4C);
137 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3] =
138 pm8001_mr32(address, 0x50);
139 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4] =
140 pm8001_mr32(address, 0x54);
141 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5] =
142 pm8001_mr32(address, 0x58);
143 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6] =
144 pm8001_mr32(address, 0x5C);
145 pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7] =
146 pm8001_mr32(address, 0x60);
150 * read_inbnd_queue_table - read the inbound queue table and save it.
151 * @pm8001_ha: our hba card information
153 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
156 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
157 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
158 u32 offset = i * 0x20;
159 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
160 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
161 pm8001_ha->inbnd_q_tbl[i].pi_offset =
162 pm8001_mr32(address, (offset + 0x18));
167 * read_outbnd_queue_table - read the outbound queue table and save it.
168 * @pm8001_ha: our hba card information
170 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
173 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
174 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
175 u32 offset = i * 0x24;
176 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
177 get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
178 pm8001_ha->outbnd_q_tbl[i].ci_offset =
179 pm8001_mr32(address, (offset + 0x18));
184 * init_default_table_values - init the default table.
185 * @pm8001_ha: our hba card information
187 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
190 u32 offsetib, offsetob;
191 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
192 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
193 u32 ib_offset = pm8001_ha->ib_offset;
194 u32 ob_offset = pm8001_ha->ob_offset;
195 u32 ci_offset = pm8001_ha->ci_offset;
196 u32 pi_offset = pm8001_ha->pi_offset;
198 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd = 0;
199 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3 = 0;
200 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7 = 0;
201 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3 = 0;
202 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7 = 0;
203 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
205 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
207 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
208 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
209 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
210 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
212 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr =
213 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
214 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr =
215 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
216 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size =
217 PM8001_EVENT_LOG_SIZE;
218 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option = 0x01;
219 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr =
220 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
221 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr =
222 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
223 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size =
224 PM8001_EVENT_LOG_SIZE;
225 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option = 0x01;
226 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt = 0x01;
227 for (i = 0; i < pm8001_ha->max_q_num; i++) {
228 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
229 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
230 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
231 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
232 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
233 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
234 pm8001_ha->inbnd_q_tbl[i].base_virt =
235 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
236 pm8001_ha->inbnd_q_tbl[i].total_length =
237 pm8001_ha->memoryMap.region[ib_offset + i].total_len;
238 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
239 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
240 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
241 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
242 pm8001_ha->inbnd_q_tbl[i].ci_virt =
243 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
244 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
246 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
247 get_pci_bar_index(pm8001_mr32(addressib,
249 pm8001_ha->inbnd_q_tbl[i].pi_offset =
250 pm8001_mr32(addressib, (offsetib + 0x18));
251 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
252 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
254 for (i = 0; i < pm8001_ha->max_q_num; i++) {
255 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
256 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
257 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
258 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
259 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
260 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
261 pm8001_ha->outbnd_q_tbl[i].base_virt =
262 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
263 pm8001_ha->outbnd_q_tbl[i].total_length =
264 pm8001_ha->memoryMap.region[ob_offset + i].total_len;
265 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
266 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
267 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
268 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
269 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
270 0 | (10 << 16) | (i << 24);
271 pm8001_ha->outbnd_q_tbl[i].pi_virt =
272 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
273 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
275 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
276 get_pci_bar_index(pm8001_mr32(addressob,
278 pm8001_ha->outbnd_q_tbl[i].ci_offset =
279 pm8001_mr32(addressob, (offsetob + 0x18));
280 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
281 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
286 * update_main_config_table - update the main default table to the HBA.
287 * @pm8001_ha: our hba card information
289 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
291 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
292 pm8001_mw32(address, 0x24,
293 pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
294 pm8001_mw32(address, 0x28,
295 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
296 pm8001_mw32(address, 0x2C,
297 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
298 pm8001_mw32(address, 0x30,
299 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
300 pm8001_mw32(address, 0x34,
301 pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
302 pm8001_mw32(address, 0x38,
303 pm8001_ha->main_cfg_tbl.pm8001_tbl.
304 outbound_tgt_ITNexus_event_pid0_3);
305 pm8001_mw32(address, 0x3C,
306 pm8001_ha->main_cfg_tbl.pm8001_tbl.
307 outbound_tgt_ITNexus_event_pid4_7);
308 pm8001_mw32(address, 0x40,
309 pm8001_ha->main_cfg_tbl.pm8001_tbl.
310 outbound_tgt_ssp_event_pid0_3);
311 pm8001_mw32(address, 0x44,
312 pm8001_ha->main_cfg_tbl.pm8001_tbl.
313 outbound_tgt_ssp_event_pid4_7);
314 pm8001_mw32(address, 0x48,
315 pm8001_ha->main_cfg_tbl.pm8001_tbl.
316 outbound_tgt_smp_event_pid0_3);
317 pm8001_mw32(address, 0x4C,
318 pm8001_ha->main_cfg_tbl.pm8001_tbl.
319 outbound_tgt_smp_event_pid4_7);
320 pm8001_mw32(address, 0x50,
321 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
322 pm8001_mw32(address, 0x54,
323 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
324 pm8001_mw32(address, 0x58,
325 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
326 pm8001_mw32(address, 0x5C,
327 pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
328 pm8001_mw32(address, 0x60,
329 pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
330 pm8001_mw32(address, 0x64,
331 pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
332 pm8001_mw32(address, 0x68,
333 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
334 pm8001_mw32(address, 0x6C,
335 pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
336 pm8001_mw32(address, 0x70,
337 pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
341 * update_inbnd_queue_table - update the inbound queue table to the HBA.
342 * @pm8001_ha: our hba card information
343 * @number: entry in the queue
345 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
348 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
349 u16 offset = number * 0x20;
350 pm8001_mw32(address, offset + 0x00,
351 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
352 pm8001_mw32(address, offset + 0x04,
353 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
354 pm8001_mw32(address, offset + 0x08,
355 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
356 pm8001_mw32(address, offset + 0x0C,
357 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
358 pm8001_mw32(address, offset + 0x10,
359 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
363 * update_outbnd_queue_table - update the outbound queue table to the HBA.
364 * @pm8001_ha: our hba card information
365 * @number: entry in the queue
367 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
370 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
371 u16 offset = number * 0x24;
372 pm8001_mw32(address, offset + 0x00,
373 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
374 pm8001_mw32(address, offset + 0x04,
375 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
376 pm8001_mw32(address, offset + 0x08,
377 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
378 pm8001_mw32(address, offset + 0x0C,
379 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
380 pm8001_mw32(address, offset + 0x10,
381 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
382 pm8001_mw32(address, offset + 0x1C,
383 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
387 * pm8001_bar4_shift - function is called to shift BAR base address
388 * @pm8001_ha : our hba card information
389 * @shiftValue : shifting value in memory bar.
391 int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
396 /* program the inbound AXI translation Lower Address */
397 pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
399 /* confirm the setting is written */
400 start = jiffies + HZ; /* 1 sec */
402 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
403 } while ((regVal != shiftValue) && time_before(jiffies, start));
405 if (regVal != shiftValue) {
406 pm8001_dbg(pm8001_ha, INIT,
407 "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n",
415 * mpi_set_phys_g3_with_ssc
416 * @pm8001_ha: our hba card information
417 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
419 static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
425 #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
426 #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
427 #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
428 #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
429 #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
430 #define PHY_G3_WITH_SSC_BIT_SHIFT 13
431 #define SNW3_PHY_CAPABILITIES_PARITY 31
434 * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
435 * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
437 spin_lock_irqsave(&pm8001_ha->lock, flags);
438 if (-1 == pm8001_bar4_shift(pm8001_ha,
439 SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
440 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
444 for (i = 0; i < 4; i++) {
445 offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
446 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
448 /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
449 if (-1 == pm8001_bar4_shift(pm8001_ha,
450 SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
451 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
454 for (i = 4; i < 8; i++) {
455 offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
456 pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
458 /*************************************************************
459 Change the SSC upspreading value to 0x0 so that upspreading is disabled.
460 Device MABC SMOD0 Controls
461 Address: (via MEMBASE-III):
462 Using shifted destination address 0x0_0000: with Offset 0xD8
464 31:28 R/W Reserved Do not change
465 27:24 R/W SAS_SMOD_SPRDUP 0000
466 23:20 R/W SAS_SMOD_SPRDDN 0000
467 19:0 R/W Reserved Do not change
468 Upon power-up this register will read as 0x8990c016,
469 and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
470 so that the written value will be 0x8090c016.
471 This will ensure only down-spreading SSC is enabled on the SPC.
472 *************************************************************/
473 pm8001_cr32(pm8001_ha, 2, 0xd8);
474 pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
476 /*set the shifted destination address to 0x0 to avoid error operation */
477 pm8001_bar4_shift(pm8001_ha, 0x0);
478 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
483 * mpi_set_open_retry_interval_reg
484 * @pm8001_ha: our hba card information
485 * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us.
487 static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
495 #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
496 #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
497 #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
498 #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
499 #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
501 value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
502 spin_lock_irqsave(&pm8001_ha->lock, flags);
503 /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
504 if (-1 == pm8001_bar4_shift(pm8001_ha,
505 OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
506 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
509 for (i = 0; i < 4; i++) {
510 offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
511 pm8001_cw32(pm8001_ha, 2, offset, value);
514 if (-1 == pm8001_bar4_shift(pm8001_ha,
515 OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
516 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
519 for (i = 4; i < 8; i++) {
520 offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
521 pm8001_cw32(pm8001_ha, 2, offset, value);
523 /*set the shifted destination address to 0x0 to avoid error operation */
524 pm8001_bar4_shift(pm8001_ha, 0x0);
525 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
530 * mpi_init_check - check firmware initialization status.
531 * @pm8001_ha: our hba card information
533 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
537 u32 gst_len_mpistate;
538 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
540 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
541 /* wait until Inbound DoorBell Clear Register toggled */
542 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
545 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
546 value &= SPC_MSGU_CFG_TABLE_UPDATE;
547 } while ((value != 0) && (--max_wait_count));
551 /* check the MPI-State for initialization */
553 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
554 GST_GSTLEN_MPIS_OFFSET);
555 if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
557 /* check MPI Initialization error */
558 gst_len_mpistate = gst_len_mpistate >> 16;
559 if (0x0000 != gst_len_mpistate)
565 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
566 * @pm8001_ha: our hba card information
568 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
572 /* check error state */
573 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
574 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
575 /* check AAP error */
576 if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
578 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
582 /* check IOP error */
583 if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
585 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
589 /* bit 4-31 of scratch pad1 should be zeros if it is not
591 if (value & SCRATCH_PAD1_STATE_MASK) {
593 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
597 /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
599 if (value1 & SCRATCH_PAD2_STATE_MASK) {
604 max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
606 /* wait until scratch pad 1 and 2 registers in ready state */
609 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
611 value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
613 if ((--max_wait_count) == 0)
615 } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
619 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
621 void __iomem *base_addr;
627 value = pm8001_cr32(pm8001_ha, 0, 0x44);
628 offset = value & 0x03FFFFFF;
629 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset);
630 pcilogic = (value & 0xFC000000) >> 26;
631 pcibar = get_pci_bar_index(pcilogic);
632 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
633 pm8001_ha->main_cfg_tbl_addr = base_addr =
634 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
635 pm8001_ha->general_stat_tbl_addr =
636 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
637 pm8001_ha->inbnd_q_tbl_addr =
638 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
639 pm8001_ha->outbnd_q_tbl_addr =
640 base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
644 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
645 * @pm8001_ha: our hba card information
647 static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
651 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
652 /* 8081 controllers need BAR shift to access MPI space
653 * as this is shared with BIOS data */
654 if (deviceid == 0x8081 || deviceid == 0x0042) {
655 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
656 pm8001_dbg(pm8001_ha, FAIL,
657 "Shift Bar4 to 0x%x failed\n",
662 /* check the firmware status */
663 if (-1 == check_fw_ready(pm8001_ha)) {
664 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
668 /* Initialize pci space address eg: mpi offset */
669 init_pci_device_addresses(pm8001_ha);
670 init_default_table_values(pm8001_ha);
671 read_main_config_table(pm8001_ha);
672 read_general_status_table(pm8001_ha);
673 read_inbnd_queue_table(pm8001_ha);
674 read_outbnd_queue_table(pm8001_ha);
675 /* update main config table ,inbound table and outbound table */
676 update_main_config_table(pm8001_ha);
677 for (i = 0; i < pm8001_ha->max_q_num; i++)
678 update_inbnd_queue_table(pm8001_ha, i);
679 for (i = 0; i < pm8001_ha->max_q_num; i++)
680 update_outbnd_queue_table(pm8001_ha, i);
681 /* 8081 controller donot require these operations */
682 if (deviceid != 0x8081 && deviceid != 0x0042) {
683 mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
684 /* 7->130ms, 34->500ms, 119->1.5s */
685 mpi_set_open_retry_interval_reg(pm8001_ha, 119);
687 /* notify firmware update finished and check initialization status */
688 if (0 == mpi_init_check(pm8001_ha)) {
689 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
692 /*This register is a 16-bit timer with a resolution of 1us. This is the
693 timer used for interrupt delay/coalescing in the PCIe Application Layer.
694 Zero is not a valid value. A value of 1 in the register will cause the
695 interrupts to be normal. A value greater than 1 will cause coalescing
697 pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
698 pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
702 static void pm8001_chip_post_init(struct pm8001_hba_info *pm8001_ha)
706 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
710 u32 gst_len_mpistate;
712 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
713 if (deviceid == 0x8081 || deviceid == 0x0042) {
714 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
715 pm8001_dbg(pm8001_ha, FAIL,
716 "Shift Bar4 to 0x%x failed\n",
721 init_pci_device_addresses(pm8001_ha);
722 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
724 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
726 /* wait until Inbound DoorBell Clear Register toggled */
727 max_wait_count = 1 * 1000 * 1000;/* 1 sec */
730 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
731 value &= SPC_MSGU_CFG_TABLE_RESET;
732 } while ((value != 0) && (--max_wait_count));
734 if (!max_wait_count) {
735 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n",
740 /* check the MPI-State for termination in progress */
741 /* wait until Inbound DoorBell Clear Register toggled */
742 max_wait_count = 1 * 1000 * 1000; /* 1 sec */
746 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
747 GST_GSTLEN_MPIS_OFFSET);
748 if (GST_MPI_STATE_UNINIT ==
749 (gst_len_mpistate & GST_MPI_STATE_MASK))
751 } while (--max_wait_count);
752 if (!max_wait_count) {
753 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
754 gst_len_mpistate & GST_MPI_STATE_MASK);
761 * soft_reset_ready_check - Function to check FW is ready for soft reset.
762 * @pm8001_ha: our hba card information
764 static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
766 u32 regVal, regVal1, regVal2;
767 if (mpi_uninit_check(pm8001_ha) != 0) {
768 pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n");
771 /* read the scratch pad 2 register bit 2 */
772 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
773 & SCRATCH_PAD2_FWRDY_RST;
774 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
775 pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n");
778 /* Trigger NMI twice via RB6 */
779 spin_lock_irqsave(&pm8001_ha->lock, flags);
780 if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
781 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
782 pm8001_dbg(pm8001_ha, FAIL,
783 "Shift Bar4 to 0x%x failed\n",
787 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
788 RB6_MAGIC_NUMBER_RST);
789 pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
790 /* wait for 100 ms */
792 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
793 SCRATCH_PAD2_FWRDY_RST;
794 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
795 regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
796 regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
797 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
799 pm8001_dbg(pm8001_ha, FAIL,
800 "SCRATCH_PAD0 value = 0x%x\n",
801 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
802 pm8001_dbg(pm8001_ha, FAIL,
803 "SCRATCH_PAD3 value = 0x%x\n",
804 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
805 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
808 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
814 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
815 * the FW register status to the originated status.
816 * @pm8001_ha: our hba card information
819 pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
821 u32 regVal, toggleVal;
823 u32 regVal1, regVal2, regVal3;
824 u32 signature = 0x252acbcd; /* for host scratch pad0 */
827 /* step1: Check FW is ready for soft reset */
828 if (soft_reset_ready_check(pm8001_ha) != 0) {
829 pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n");
833 /* step 2: clear NMI status register on AAP1 and IOP, write the same
835 /* map 0x60000 to BAR4(0x20), BAR2(win) */
836 spin_lock_irqsave(&pm8001_ha->lock, flags);
837 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
838 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
839 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
840 MBIC_AAP1_ADDR_BASE);
843 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
844 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n",
846 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
847 /* map 0x70000 to BAR4(0x20), BAR2(win) */
848 if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
849 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
850 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
854 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
855 pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n",
857 pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
859 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
860 pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n",
862 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
864 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
865 pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt = 0x%x\n",
867 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
869 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
870 pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n",
872 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
874 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
875 pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);
876 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
878 /* read the scratch pad 1 register bit 2 */
879 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
881 toggleVal = regVal ^ SCRATCH_PAD1_RST;
883 /* set signature in host scratch pad0 register to tell SPC that the
884 host performs the soft reset */
885 pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
887 /* read required registers for confirmming */
888 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
889 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
890 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
891 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
895 pm8001_dbg(pm8001_ha, INIT,
896 "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n",
897 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
899 /* step 3: host read GSM Configuration and Reset register */
900 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
901 /* Put those bits to low */
902 /* GSM XCBI offset = 0x70 0000
903 0x00 Bit 13 COM_SLV_SW_RSTB 1
904 0x00 Bit 12 QSSP_SW_RSTB 1
905 0x00 Bit 11 RAAE_SW_RSTB 1
906 0x00 Bit 9 RB_1_SW_RSTB 1
907 0x00 Bit 8 SM_SW_RSTB 1
909 regVal &= ~(0x00003b00);
910 /* host write GSM Configuration and Reset register */
911 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
912 pm8001_dbg(pm8001_ha, INIT,
913 "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n",
914 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
917 /* disable GSM - Read Address Parity Check */
918 regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
919 pm8001_dbg(pm8001_ha, INIT,
920 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
922 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
923 pm8001_dbg(pm8001_ha, INIT,
924 "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
925 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
927 /* disable GSM - Write Address Parity Check */
928 regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
929 pm8001_dbg(pm8001_ha, INIT,
930 "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n",
932 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
933 pm8001_dbg(pm8001_ha, INIT,
934 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
935 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
937 /* disable GSM - Write Data Parity Check */
938 regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
939 pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n",
941 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
942 pm8001_dbg(pm8001_ha, INIT,
943 "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n",
944 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
946 /* step 5: delay 10 usec */
948 /* step 5-b: set GPIO-0 output control to tristate anyway */
949 if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
950 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
951 pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n",
955 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
956 pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n",
958 /* set GPIO-0 output control to tri-state */
959 regVal &= 0xFFFFFFFC;
960 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
962 /* Step 6: Reset the IOP and AAP1 */
963 /* map 0x00000 to BAR4(0x20), BAR2(win) */
964 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
965 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
966 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
967 SPC_TOP_LEVEL_ADDR_BASE);
970 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
971 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n",
973 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
974 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
976 /* step 7: Reset the BDMA/OSSP */
977 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
978 pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n",
980 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
981 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
983 /* step 8: delay 10 usec */
986 /* step 9: bring the BDMA and OSSP out of reset */
987 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
988 pm8001_dbg(pm8001_ha, INIT,
989 "Top Register before bringing up BDMA/OSSP:= 0x%x\n",
991 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
992 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
994 /* step 10: delay 10 usec */
997 /* step 11: reads and sets the GSM Configuration and Reset Register */
998 /* map 0x0700000 to BAR4(0x20), BAR2(win) */
999 if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
1000 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1001 pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
1005 pm8001_dbg(pm8001_ha, INIT,
1006 "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n",
1007 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1008 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1009 /* Put those bits to high */
1010 /* GSM XCBI offset = 0x70 0000
1011 0x00 Bit 13 COM_SLV_SW_RSTB 1
1012 0x00 Bit 12 QSSP_SW_RSTB 1
1013 0x00 Bit 11 RAAE_SW_RSTB 1
1014 0x00 Bit 9 RB_1_SW_RSTB 1
1015 0x00 Bit 8 SM_SW_RSTB 1
1017 regVal |= (GSM_CONFIG_RESET_VALUE);
1018 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1019 pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n",
1020 pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1022 /* step 12: Restore GSM - Read Address Parity Check */
1023 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1024 /* just for debugging */
1025 pm8001_dbg(pm8001_ha, INIT,
1026 "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
1028 pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1029 pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
1030 pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
1031 /* Restore GSM - Write Address Parity Check */
1032 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1033 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1034 pm8001_dbg(pm8001_ha, INIT,
1035 "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
1036 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
1037 /* Restore GSM - Write Data Parity Check */
1038 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1039 pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1040 pm8001_dbg(pm8001_ha, INIT,
1041 "GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n",
1042 pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
1044 /* step 13: bring the IOP and AAP1 out of reset */
1045 /* map 0x00000 to BAR4(0x20), BAR2(win) */
1046 if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1047 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1048 pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
1049 SPC_TOP_LEVEL_ADDR_BASE);
1052 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1053 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1054 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1056 /* step 14: delay 10 usec - Normal Mode */
1058 /* check Soft Reset Normal mode or Soft Reset HDA mode */
1059 if (signature == SPC_SOFT_RESET_SIGNATURE) {
1060 /* step 15 (Normal Mode): wait until scratch pad1 register
1062 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1065 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1067 } while ((regVal != toggleVal) && (--max_wait_count));
1069 if (!max_wait_count) {
1070 regVal = pm8001_cr32(pm8001_ha, 0,
1071 MSGU_SCRATCH_PAD_1);
1072 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n",
1074 pm8001_dbg(pm8001_ha, FAIL,
1075 "SCRATCH_PAD0 value = 0x%x\n",
1076 pm8001_cr32(pm8001_ha, 0,
1077 MSGU_SCRATCH_PAD_0));
1078 pm8001_dbg(pm8001_ha, FAIL,
1079 "SCRATCH_PAD2 value = 0x%x\n",
1080 pm8001_cr32(pm8001_ha, 0,
1081 MSGU_SCRATCH_PAD_2));
1082 pm8001_dbg(pm8001_ha, FAIL,
1083 "SCRATCH_PAD3 value = 0x%x\n",
1084 pm8001_cr32(pm8001_ha, 0,
1085 MSGU_SCRATCH_PAD_3));
1086 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1090 /* step 16 (Normal) - Clear ODMR and ODCR */
1091 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1092 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1094 /* step 17 (Normal Mode): wait for the FW and IOP to get
1095 ready - 1 sec timeout */
1096 /* Wait for the SPC Configuration Table to be ready */
1097 if (check_fw_ready(pm8001_ha) == -1) {
1098 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1099 /* return error if MPI Configuration Table not ready */
1100 pm8001_dbg(pm8001_ha, INIT,
1101 "FW not ready SCRATCH_PAD1 = 0x%x\n",
1103 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1104 /* return error if MPI Configuration Table not ready */
1105 pm8001_dbg(pm8001_ha, INIT,
1106 "FW not ready SCRATCH_PAD2 = 0x%x\n",
1108 pm8001_dbg(pm8001_ha, INIT,
1109 "SCRATCH_PAD0 value = 0x%x\n",
1110 pm8001_cr32(pm8001_ha, 0,
1111 MSGU_SCRATCH_PAD_0));
1112 pm8001_dbg(pm8001_ha, INIT,
1113 "SCRATCH_PAD3 value = 0x%x\n",
1114 pm8001_cr32(pm8001_ha, 0,
1115 MSGU_SCRATCH_PAD_3));
1116 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1120 pm8001_bar4_shift(pm8001_ha, 0);
1121 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1123 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1127 static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1131 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1133 /* do SPC chip reset. */
1134 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1135 regVal &= ~(SPC_REG_RESET_DEVICE);
1136 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1141 /* bring chip reset out of reset */
1142 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1143 regVal |= SPC_REG_RESET_DEVICE;
1144 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1149 /* wait for 20 msec until the firmware gets reloaded */
1153 } while ((--i) != 0);
1155 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1159 * pm8001_chip_iounmap - which mapped when initialized.
1160 * @pm8001_ha: our hba card information
1162 void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1164 s8 bar, logical = 0;
1165 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
1167 ** logical BARs for SPC:
1168 ** bar 0 and 1 - logical BAR0
1169 ** bar 2 and 3 - logical BAR1
1170 ** bar4 - logical BAR2
1171 ** bar5 - logical BAR3
1172 ** Skip the appropriate assignments:
1174 if ((bar == 1) || (bar == 3))
1176 if (pm8001_ha->io_mem[logical].memvirtaddr) {
1177 iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1183 #ifndef PM8001_USE_MSIX
1185 * pm8001_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1186 * @pm8001_ha: our hba card information
1189 pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1191 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1192 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1196 * pm8001_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1197 * @pm8001_ha: our hba card information
1200 pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1202 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1208 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1209 * @pm8001_ha: our hba card information
1210 * @int_vec_idx: interrupt number to enable
1213 pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1218 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1219 msi_index += MSIX_TABLE_BASE;
1220 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1221 value = (1 << int_vec_idx);
1222 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
1227 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1228 * @pm8001_ha: our hba card information
1229 * @int_vec_idx: interrupt number to disable
1232 pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1236 msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1237 msi_index += MSIX_TABLE_BASE;
1238 pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
1243 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1244 * @pm8001_ha: our hba card information
1248 pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1250 #ifdef PM8001_USE_MSIX
1251 pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1253 pm8001_chip_intx_interrupt_enable(pm8001_ha);
1258 * pm8001_chip_interrupt_disable - disable PM8001 chip interrupt
1259 * @pm8001_ha: our hba card information
1263 pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1265 #ifdef PM8001_USE_MSIX
1266 pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1268 pm8001_chip_intx_interrupt_disable(pm8001_ha);
1273 * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1275 * @circularQ: the inbound queue we want to transfer to HBA.
1276 * @messageSize: the message size of this transfer, normally it is 64 bytes
1277 * @messagePtr: the pointer to message.
1279 int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1280 u16 messageSize, void **messagePtr)
1282 u32 offset, consumer_index;
1283 struct mpi_msg_hdr *msgHeader;
1284 u8 bcCount = 1; /* only support single buffer */
1286 /* Checks is the requested message size can be allocated in this queue*/
1287 if (messageSize > IOMB_SIZE_SPCV) {
1292 /* Stores the new consumer index */
1293 consumer_index = pm8001_read_32(circularQ->ci_virt);
1294 circularQ->consumer_index = cpu_to_le32(consumer_index);
1295 if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1296 le32_to_cpu(circularQ->consumer_index)) {
1300 /* get memory IOMB buffer address */
1301 offset = circularQ->producer_idx * messageSize;
1302 /* increment to next bcCount element */
1303 circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1305 /* Adds that distance to the base of the region virtual address plus
1306 the message header size*/
1307 msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1308 *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1313 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1314 * FW to tell the fw to get this message from IOMB.
1315 * @pm8001_ha: our hba card information
1316 * @q_index: the index in the inbound queue we want to transfer to HBA.
1317 * @opCode: the operation code represents commands which LLDD and fw recognized.
1318 * @payload: the command payload of each operation command.
1319 * @nb: size in bytes of the command payload
1320 * @responseQueue: queue to interrupt on w/ command response (if any)
1322 int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1323 u32 q_index, u32 opCode, void *payload, size_t nb,
1326 u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1328 unsigned long flags;
1329 struct inbound_queue_table *circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
1331 u32 htag = le32_to_cpu(*(__le32 *)payload);
1333 trace_pm80xx_mpi_build_cmd(pm8001_ha->id, opCode, htag, q_index,
1334 circularQ->producer_idx, le32_to_cpu(circularQ->consumer_index));
1336 if (WARN_ON(q_index >= pm8001_ha->max_q_num))
1339 spin_lock_irqsave(&circularQ->iq_lock, flags);
1340 rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1343 pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n");
1348 if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr)))
1349 nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr);
1350 memcpy(pMessage, payload, nb);
1351 if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size)
1352 memset(pMessage + nb, 0, pm8001_ha->iomb_size -
1353 (nb + sizeof(struct mpi_msg_hdr)));
1355 /*Build the header*/
1356 Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1357 | ((responseQueue & 0x3F) << 16)
1358 | ((category & 0xF) << 12) | (opCode & 0xFFF));
1360 pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1361 /*Update the PI to the firmware*/
1362 pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1363 circularQ->pi_offset, circularQ->producer_idx);
1364 pm8001_dbg(pm8001_ha, DEVIO,
1365 "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1366 responseQueue, opCode, circularQ->producer_idx,
1367 circularQ->consumer_index);
1369 spin_unlock_irqrestore(&circularQ->iq_lock, flags);
1373 u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1374 struct outbound_queue_table *circularQ, u8 bc)
1377 struct mpi_msg_hdr *msgHeader;
1378 struct mpi_msg_hdr *pOutBoundMsgHeader;
1380 msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1381 pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1382 circularQ->consumer_idx * pm8001_ha->iomb_size);
1383 if (pOutBoundMsgHeader != msgHeader) {
1384 pm8001_dbg(pm8001_ha, FAIL,
1385 "consumer_idx = %d msgHeader = %p\n",
1386 circularQ->consumer_idx, msgHeader);
1388 /* Update the producer index from SPC */
1389 producer_index = pm8001_read_32(circularQ->pi_virt);
1390 circularQ->producer_index = cpu_to_le32(producer_index);
1391 pm8001_dbg(pm8001_ha, FAIL,
1392 "consumer_idx = %d producer_index = %dmsgHeader = %p\n",
1393 circularQ->consumer_idx,
1394 circularQ->producer_index, msgHeader);
1397 /* free the circular queue buffer elements associated with the message*/
1398 circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1400 /* update the CI of outbound queue */
1401 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1402 circularQ->consumer_idx);
1403 /* Update the producer index from SPC*/
1404 producer_index = pm8001_read_32(circularQ->pi_virt);
1405 circularQ->producer_index = cpu_to_le32(producer_index);
1406 pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n",
1407 circularQ->consumer_idx, circularQ->producer_index);
1412 * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1414 * @pm8001_ha: our hba card information
1415 * @circularQ: the outbound queue table.
1416 * @messagePtr1: the message contents of this outbound message.
1417 * @pBC: the message size.
1419 u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1420 struct outbound_queue_table *circularQ,
1421 void **messagePtr1, u8 *pBC)
1423 struct mpi_msg_hdr *msgHeader;
1424 __le32 msgHeader_tmp;
1427 /* If there are not-yet-delivered messages ... */
1428 if (le32_to_cpu(circularQ->producer_index)
1429 != circularQ->consumer_idx) {
1430 /*Get the pointer to the circular queue buffer element*/
1431 msgHeader = (struct mpi_msg_hdr *)
1432 (circularQ->base_virt +
1433 circularQ->consumer_idx * pm8001_ha->iomb_size);
1435 header_tmp = pm8001_read_32(msgHeader);
1436 msgHeader_tmp = cpu_to_le32(header_tmp);
1437 pm8001_dbg(pm8001_ha, DEVIO,
1438 "outbound opcode msgheader:%x ci=%d pi=%d\n",
1439 msgHeader_tmp, circularQ->consumer_idx,
1440 circularQ->producer_index);
1441 if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1442 if (OPC_OUB_SKIP_ENTRY !=
1443 (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1446 sizeof(struct mpi_msg_hdr);
1447 *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1449 pm8001_dbg(pm8001_ha, IO,
1450 ": CI=%d PI=%d msgHeader=%x\n",
1451 circularQ->consumer_idx,
1452 circularQ->producer_index,
1454 return MPI_IO_STATUS_SUCCESS;
1456 circularQ->consumer_idx =
1457 (circularQ->consumer_idx +
1458 ((le32_to_cpu(msgHeader_tmp)
1462 pm8001_write_32(msgHeader, 0, 0);
1463 /* update the CI of outbound queue */
1464 pm8001_cw32(pm8001_ha,
1465 circularQ->ci_pci_bar,
1466 circularQ->ci_offset,
1467 circularQ->consumer_idx);
1470 circularQ->consumer_idx =
1471 (circularQ->consumer_idx +
1472 ((le32_to_cpu(msgHeader_tmp) >> 24) &
1473 0x1f)) % PM8001_MPI_QUEUE;
1475 pm8001_write_32(msgHeader, 0, 0);
1476 /* update the CI of outbound queue */
1477 pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1478 circularQ->ci_offset,
1479 circularQ->consumer_idx);
1480 return MPI_IO_STATUS_FAIL;
1484 void *pi_virt = circularQ->pi_virt;
1485 /* spurious interrupt during setup if
1486 * kexec-ing and driver doing a doorbell access
1487 * with the pre-kexec oq interrupt setup
1491 /* Update the producer index from SPC */
1492 producer_index = pm8001_read_32(pi_virt);
1493 circularQ->producer_index = cpu_to_le32(producer_index);
1495 } while (le32_to_cpu(circularQ->producer_index) !=
1496 circularQ->consumer_idx);
1497 /* while we don't have any more not-yet-delivered message */
1499 return MPI_IO_STATUS_BUSY;
1502 void pm8001_work_fn(struct work_struct *work)
1504 struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1505 struct pm8001_device *pm8001_dev;
1506 struct domain_device *dev;
1509 * So far, all users of this stash an associated structure here.
1510 * If we get here, and this pointer is null, then the action
1511 * was cancelled. This nullification happens when the device
1514 if (pw->handler != IO_FATAL_ERROR) {
1515 pm8001_dev = pw->data; /* Most stash device structure */
1516 if ((pm8001_dev == NULL)
1517 || ((pw->handler != IO_XFER_ERROR_BREAK)
1518 && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1524 switch (pw->handler) {
1525 case IO_XFER_ERROR_BREAK:
1526 { /* This one stashes the sas_task instead */
1527 struct sas_task *t = (struct sas_task *)pm8001_dev;
1528 struct pm8001_ccb_info *ccb;
1529 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1530 unsigned long flags, flags1;
1531 struct task_status_struct *ts;
1534 if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1535 break; /* Task still on lu */
1536 spin_lock_irqsave(&pm8001_ha->lock, flags);
1538 spin_lock_irqsave(&t->task_state_lock, flags1);
1539 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1540 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1541 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1542 break; /* Task got completed by another */
1544 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1546 /* Search for a possible ccb that matches the task */
1547 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1548 ccb = &pm8001_ha->ccb_info[i];
1549 if ((ccb->ccb_tag != PM8001_INVALID_TAG) &&
1554 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1555 break; /* Task got freed by another */
1557 ts = &t->task_status;
1558 ts->resp = SAS_TASK_COMPLETE;
1559 /* Force the midlayer to retry */
1560 ts->stat = SAS_QUEUE_FULL;
1561 pm8001_dev = ccb->device;
1563 atomic_dec(&pm8001_dev->running_req);
1564 spin_lock_irqsave(&t->task_state_lock, flags1);
1565 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1566 t->task_state_flags |= SAS_TASK_STATE_DONE;
1567 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1568 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1569 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
1570 t, pw->handler, ts->resp, ts->stat);
1571 pm8001_ccb_task_free(pm8001_ha, ccb);
1572 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1574 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1575 pm8001_ccb_task_free(pm8001_ha, ccb);
1576 mb();/* in order to force CPU ordering */
1577 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1581 case IO_XFER_OPEN_RETRY_TIMEOUT:
1582 { /* This one stashes the sas_task instead */
1583 struct sas_task *t = (struct sas_task *)pm8001_dev;
1584 struct pm8001_ccb_info *ccb;
1585 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1586 unsigned long flags, flags1;
1589 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
1591 ret = pm8001_query_task(t);
1593 if (ret == TMF_RESP_FUNC_SUCC)
1594 pm8001_dbg(pm8001_ha, IO, "...Task on lu\n");
1595 else if (ret == TMF_RESP_FUNC_COMPLETE)
1596 pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n");
1598 pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n");
1600 spin_lock_irqsave(&pm8001_ha->lock, flags);
1602 spin_lock_irqsave(&t->task_state_lock, flags1);
1604 if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1605 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1606 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1607 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1608 (void)pm8001_abort_task(t);
1609 break; /* Task got completed by another */
1612 spin_unlock_irqrestore(&t->task_state_lock, flags1);
1614 /* Search for a possible ccb that matches the task */
1615 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1616 ccb = &pm8001_ha->ccb_info[i];
1617 if ((ccb->ccb_tag != PM8001_INVALID_TAG) &&
1622 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1623 if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1624 (void)pm8001_abort_task(t);
1625 break; /* Task got freed by another */
1628 pm8001_dev = ccb->device;
1629 dev = pm8001_dev->sas_device;
1632 case TMF_RESP_FUNC_SUCC: /* task on lu */
1633 ccb->open_retry = 1; /* Snub completion */
1634 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1635 ret = pm8001_abort_task(t);
1636 ccb->open_retry = 0;
1638 case TMF_RESP_FUNC_SUCC:
1639 case TMF_RESP_FUNC_COMPLETE:
1641 default: /* device misbehavior */
1642 ret = TMF_RESP_FUNC_FAILED;
1643 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1644 pm8001_I_T_nexus_reset(dev);
1649 case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1650 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1651 /* Do we need to abort the task locally? */
1654 default: /* device misbehavior */
1655 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1656 ret = TMF_RESP_FUNC_FAILED;
1657 pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1658 pm8001_I_T_nexus_reset(dev);
1661 if (ret == TMF_RESP_FUNC_FAILED)
1663 pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1664 pm8001_dbg(pm8001_ha, IO, "...Complete\n");
1666 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1667 dev = pm8001_dev->sas_device;
1668 pm8001_I_T_nexus_event_handler(dev);
1670 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1671 dev = pm8001_dev->sas_device;
1672 pm8001_I_T_nexus_reset(dev);
1674 case IO_DS_IN_ERROR:
1675 dev = pm8001_dev->sas_device;
1676 pm8001_I_T_nexus_reset(dev);
1678 case IO_DS_NON_OPERATIONAL:
1679 dev = pm8001_dev->sas_device;
1680 pm8001_I_T_nexus_reset(dev);
1682 case IO_FATAL_ERROR:
1684 struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1685 struct pm8001_ccb_info *ccb;
1686 struct task_status_struct *ts;
1687 struct sas_task *task;
1691 for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1692 ccb = &pm8001_ha->ccb_info[i];
1694 ts = &task->task_status;
1699 pm8001_dbg(pm8001_ha, FAIL,
1703 /*complete sas task and update to top layer */
1704 pm8001_ccb_task_free(pm8001_ha, ccb);
1705 ts->resp = SAS_TASK_COMPLETE;
1706 task->task_done(task);
1707 } else if (ccb->ccb_tag != PM8001_INVALID_TAG) {
1708 /* complete the internal commands/non-sas task */
1709 pm8001_dev = ccb->device;
1710 if (pm8001_dev->dcompletion) {
1711 complete(pm8001_dev->dcompletion);
1712 pm8001_dev->dcompletion = NULL;
1714 complete(pm8001_ha->nvmd_completion);
1715 pm8001_ccb_free(pm8001_ha, ccb);
1718 /* Deregister all the device ids */
1719 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
1720 pm8001_dev = &pm8001_ha->devices[i];
1721 device_id = pm8001_dev->device_id;
1723 PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id);
1724 pm8001_free_dev(pm8001_dev);
1732 int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1735 struct pm8001_work *pw;
1738 pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1740 pw->pm8001_ha = pm8001_ha;
1742 pw->handler = handler;
1743 INIT_WORK(&pw->work, pm8001_work_fn);
1744 queue_work(pm8001_wq, &pw->work);
1751 static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1752 struct pm8001_device *pm8001_ha_dev)
1754 struct pm8001_ccb_info *ccb;
1755 struct sas_task *task;
1756 struct task_abort_req task_abort;
1757 u32 opc = OPC_INB_SATA_ABORT;
1760 pm8001_ha_dev->id |= NCQ_ABORT_ALL_FLAG;
1761 pm8001_ha_dev->id &= ~NCQ_READ_LOG_FLAG;
1763 task = sas_alloc_slow_task(GFP_ATOMIC);
1765 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1769 task->task_done = pm8001_task_done;
1771 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1773 sas_free_task(task);
1777 memset(&task_abort, 0, sizeof(task_abort));
1778 task_abort.abort_all = cpu_to_le32(1);
1779 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1780 task_abort.tag = cpu_to_le32(ccb->ccb_tag);
1782 ret = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort,
1783 sizeof(task_abort), 0);
1785 sas_free_task(task);
1786 pm8001_ccb_free(pm8001_ha, ccb);
1790 static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1791 struct pm8001_device *pm8001_ha_dev)
1793 struct sata_start_req sata_cmd;
1795 struct pm8001_ccb_info *ccb;
1796 struct sas_task *task = NULL;
1797 struct host_to_dev_fis fis;
1798 struct domain_device *dev;
1799 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1801 task = sas_alloc_slow_task(GFP_ATOMIC);
1803 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1806 task->task_done = pm8001_task_done;
1809 * Allocate domain device by ourselves as libsas is not going to
1812 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1814 sas_free_task(task);
1815 pm8001_dbg(pm8001_ha, FAIL,
1816 "Domain device cannot be allocated\n");
1820 task->dev->lldd_dev = pm8001_ha_dev;
1822 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1824 sas_free_task(task);
1829 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1830 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1832 /* construct read log FIS */
1833 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1834 fis.fis_type = 0x27;
1836 fis.command = ATA_CMD_READ_LOG_EXT;
1838 fis.sector_count = 0x1;
1840 memset(&sata_cmd, 0, sizeof(sata_cmd));
1841 sata_cmd.tag = cpu_to_le32(ccb->ccb_tag);
1842 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1843 sata_cmd.ncqtag_atap_dir_m = cpu_to_le32((0x1 << 7) | (0x5 << 9));
1844 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1846 res = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd,
1847 sizeof(sata_cmd), 0);
1849 sas_free_task(task);
1850 pm8001_ccb_free(pm8001_ha, ccb);
1856 * mpi_ssp_completion- process the event that FW response to the SSP request.
1857 * @pm8001_ha: our hba card information
1858 * @piomb: the message contents of this outbound message.
1860 * When FW has completed a ssp request for example a IO request, after it has
1861 * filled the SG data with the data, it will trigger this event representing
1862 * that he has finished the job; please check the corresponding buffer.
1863 * So we will tell the caller who maybe waiting the result to tell upper layer
1864 * that the task has been finished.
1867 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1870 struct pm8001_ccb_info *ccb;
1871 unsigned long flags;
1875 struct ssp_completion_resp *psspPayload;
1876 struct task_status_struct *ts;
1877 struct ssp_response_iu *iu;
1878 struct pm8001_device *pm8001_dev;
1879 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1880 status = le32_to_cpu(psspPayload->status);
1881 tag = le32_to_cpu(psspPayload->tag);
1882 ccb = &pm8001_ha->ccb_info[tag];
1883 if ((status == IO_ABORTED) && ccb->open_retry) {
1884 /* Being completed by another */
1885 ccb->open_retry = 0;
1888 pm8001_dev = ccb->device;
1889 param = le32_to_cpu(psspPayload->param);
1893 if (status && status != IO_UNDERFLOW)
1894 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1895 if (unlikely(!t || !t->lldd_task || !t->dev))
1897 ts = &t->task_status;
1898 /* Print sas address of IO failed device */
1899 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1900 (status != IO_UNDERFLOW))
1901 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1902 SAS_ADDR(t->dev->sas_addr));
1905 pm8001_dbg(pm8001_ha, IOERR,
1906 "status:0x%x, tag:0x%x, task:0x%p\n",
1911 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n",
1914 ts->resp = SAS_TASK_COMPLETE;
1915 ts->stat = SAS_SAM_STAT_GOOD;
1917 ts->resp = SAS_TASK_COMPLETE;
1918 ts->stat = SAS_PROTO_RESPONSE;
1919 ts->residual = param;
1920 iu = &psspPayload->ssp_resp_iu;
1921 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1924 atomic_dec(&pm8001_dev->running_req);
1927 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1928 ts->resp = SAS_TASK_COMPLETE;
1929 ts->stat = SAS_ABORTED_TASK;
1932 /* SSP Completion with error */
1933 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n",
1935 ts->resp = SAS_TASK_COMPLETE;
1936 ts->stat = SAS_DATA_UNDERRUN;
1937 ts->residual = param;
1939 atomic_dec(&pm8001_dev->running_req);
1942 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1943 ts->resp = SAS_TASK_UNDELIVERED;
1944 ts->stat = SAS_PHY_DOWN;
1946 case IO_XFER_ERROR_BREAK:
1947 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1948 ts->resp = SAS_TASK_COMPLETE;
1949 ts->stat = SAS_OPEN_REJECT;
1950 /* Force the midlayer to retry */
1951 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1953 case IO_XFER_ERROR_PHY_NOT_READY:
1954 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1955 ts->resp = SAS_TASK_COMPLETE;
1956 ts->stat = SAS_OPEN_REJECT;
1957 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1959 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1960 pm8001_dbg(pm8001_ha, IO,
1961 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1962 ts->resp = SAS_TASK_COMPLETE;
1963 ts->stat = SAS_OPEN_REJECT;
1964 ts->open_rej_reason = SAS_OREJ_EPROTO;
1966 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1967 pm8001_dbg(pm8001_ha, IO,
1968 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1969 ts->resp = SAS_TASK_COMPLETE;
1970 ts->stat = SAS_OPEN_REJECT;
1971 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1973 case IO_OPEN_CNX_ERROR_BREAK:
1974 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
1975 ts->resp = SAS_TASK_COMPLETE;
1976 ts->stat = SAS_OPEN_REJECT;
1977 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1979 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1980 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
1981 ts->resp = SAS_TASK_COMPLETE;
1982 ts->stat = SAS_OPEN_REJECT;
1983 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1985 pm8001_handle_event(pm8001_ha,
1987 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1989 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1990 pm8001_dbg(pm8001_ha, IO,
1991 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
1992 ts->resp = SAS_TASK_COMPLETE;
1993 ts->stat = SAS_OPEN_REJECT;
1994 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1996 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1997 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
1998 ts->resp = SAS_TASK_COMPLETE;
1999 ts->stat = SAS_OPEN_REJECT;
2000 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2002 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2003 pm8001_dbg(pm8001_ha, IO,
2004 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2005 ts->resp = SAS_TASK_UNDELIVERED;
2006 ts->stat = SAS_OPEN_REJECT;
2007 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2009 case IO_XFER_ERROR_NAK_RECEIVED:
2010 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2011 ts->resp = SAS_TASK_COMPLETE;
2012 ts->stat = SAS_OPEN_REJECT;
2013 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2015 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2016 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2017 ts->resp = SAS_TASK_COMPLETE;
2018 ts->stat = SAS_NAK_R_ERR;
2020 case IO_XFER_ERROR_DMA:
2021 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2022 ts->resp = SAS_TASK_COMPLETE;
2023 ts->stat = SAS_OPEN_REJECT;
2025 case IO_XFER_OPEN_RETRY_TIMEOUT:
2026 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2027 ts->resp = SAS_TASK_COMPLETE;
2028 ts->stat = SAS_OPEN_REJECT;
2029 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2031 case IO_XFER_ERROR_OFFSET_MISMATCH:
2032 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2033 ts->resp = SAS_TASK_COMPLETE;
2034 ts->stat = SAS_OPEN_REJECT;
2036 case IO_PORT_IN_RESET:
2037 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2038 ts->resp = SAS_TASK_COMPLETE;
2039 ts->stat = SAS_OPEN_REJECT;
2041 case IO_DS_NON_OPERATIONAL:
2042 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2043 ts->resp = SAS_TASK_COMPLETE;
2044 ts->stat = SAS_OPEN_REJECT;
2046 pm8001_handle_event(pm8001_ha,
2048 IO_DS_NON_OPERATIONAL);
2050 case IO_DS_IN_RECOVERY:
2051 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2052 ts->resp = SAS_TASK_COMPLETE;
2053 ts->stat = SAS_OPEN_REJECT;
2055 case IO_TM_TAG_NOT_FOUND:
2056 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2057 ts->resp = SAS_TASK_COMPLETE;
2058 ts->stat = SAS_OPEN_REJECT;
2060 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2061 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2062 ts->resp = SAS_TASK_COMPLETE;
2063 ts->stat = SAS_OPEN_REJECT;
2065 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2066 pm8001_dbg(pm8001_ha, IO,
2067 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2068 ts->resp = SAS_TASK_COMPLETE;
2069 ts->stat = SAS_OPEN_REJECT;
2070 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2073 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2074 /* not allowed case. Therefore, return failed status */
2075 ts->resp = SAS_TASK_COMPLETE;
2076 ts->stat = SAS_OPEN_REJECT;
2079 pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n",
2080 psspPayload->ssp_resp_iu.status);
2081 spin_lock_irqsave(&t->task_state_lock, flags);
2082 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2083 t->task_state_flags |= SAS_TASK_STATE_DONE;
2084 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2085 spin_unlock_irqrestore(&t->task_state_lock, flags);
2086 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2087 t, status, ts->resp, ts->stat);
2088 pm8001_ccb_task_free(pm8001_ha, ccb);
2090 spin_unlock_irqrestore(&t->task_state_lock, flags);
2091 pm8001_ccb_task_free(pm8001_ha, ccb);
2092 mb();/* in order to force CPU ordering */
2097 /*See the comments for mpi_ssp_completion */
2098 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2101 unsigned long flags;
2102 struct task_status_struct *ts;
2103 struct pm8001_ccb_info *ccb;
2104 struct pm8001_device *pm8001_dev;
2105 struct ssp_event_resp *psspPayload =
2106 (struct ssp_event_resp *)(piomb + 4);
2107 u32 event = le32_to_cpu(psspPayload->event);
2108 u32 tag = le32_to_cpu(psspPayload->tag);
2109 u32 port_id = le32_to_cpu(psspPayload->port_id);
2110 u32 dev_id = le32_to_cpu(psspPayload->device_id);
2112 ccb = &pm8001_ha->ccb_info[tag];
2114 pm8001_dev = ccb->device;
2116 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2117 if (unlikely(!t || !t->lldd_task || !t->dev))
2119 ts = &t->task_status;
2120 pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n",
2124 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2125 ts->resp = SAS_TASK_COMPLETE;
2126 ts->stat = SAS_DATA_OVERRUN;
2129 atomic_dec(&pm8001_dev->running_req);
2131 case IO_XFER_ERROR_BREAK:
2132 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2133 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2135 case IO_XFER_ERROR_PHY_NOT_READY:
2136 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2137 ts->resp = SAS_TASK_COMPLETE;
2138 ts->stat = SAS_OPEN_REJECT;
2139 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2141 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2142 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2143 ts->resp = SAS_TASK_COMPLETE;
2144 ts->stat = SAS_OPEN_REJECT;
2145 ts->open_rej_reason = SAS_OREJ_EPROTO;
2147 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2148 pm8001_dbg(pm8001_ha, IO,
2149 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2150 ts->resp = SAS_TASK_COMPLETE;
2151 ts->stat = SAS_OPEN_REJECT;
2152 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2154 case IO_OPEN_CNX_ERROR_BREAK:
2155 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2156 ts->resp = SAS_TASK_COMPLETE;
2157 ts->stat = SAS_OPEN_REJECT;
2158 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2160 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2161 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2162 ts->resp = SAS_TASK_COMPLETE;
2163 ts->stat = SAS_OPEN_REJECT;
2164 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2166 pm8001_handle_event(pm8001_ha,
2168 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2170 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2171 pm8001_dbg(pm8001_ha, IO,
2172 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2173 ts->resp = SAS_TASK_COMPLETE;
2174 ts->stat = SAS_OPEN_REJECT;
2175 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2177 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2178 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2179 ts->resp = SAS_TASK_COMPLETE;
2180 ts->stat = SAS_OPEN_REJECT;
2181 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2183 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2184 pm8001_dbg(pm8001_ha, IO,
2185 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2186 ts->resp = SAS_TASK_COMPLETE;
2187 ts->stat = SAS_OPEN_REJECT;
2188 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2190 case IO_XFER_ERROR_NAK_RECEIVED:
2191 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2192 ts->resp = SAS_TASK_COMPLETE;
2193 ts->stat = SAS_OPEN_REJECT;
2194 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2196 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2197 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2198 ts->resp = SAS_TASK_COMPLETE;
2199 ts->stat = SAS_NAK_R_ERR;
2201 case IO_XFER_OPEN_RETRY_TIMEOUT:
2202 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2203 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2205 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2206 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2207 ts->resp = SAS_TASK_COMPLETE;
2208 ts->stat = SAS_DATA_OVERRUN;
2210 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2211 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2212 ts->resp = SAS_TASK_COMPLETE;
2213 ts->stat = SAS_DATA_OVERRUN;
2215 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2216 pm8001_dbg(pm8001_ha, IO,
2217 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2218 ts->resp = SAS_TASK_COMPLETE;
2219 ts->stat = SAS_DATA_OVERRUN;
2221 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2222 pm8001_dbg(pm8001_ha, IO,
2223 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2224 ts->resp = SAS_TASK_COMPLETE;
2225 ts->stat = SAS_DATA_OVERRUN;
2227 case IO_XFER_ERROR_OFFSET_MISMATCH:
2228 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2229 ts->resp = SAS_TASK_COMPLETE;
2230 ts->stat = SAS_DATA_OVERRUN;
2232 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2233 pm8001_dbg(pm8001_ha, IO,
2234 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2235 ts->resp = SAS_TASK_COMPLETE;
2236 ts->stat = SAS_DATA_OVERRUN;
2238 case IO_XFER_CMD_FRAME_ISSUED:
2239 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2242 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2243 /* not allowed case. Therefore, return failed status */
2244 ts->resp = SAS_TASK_COMPLETE;
2245 ts->stat = SAS_DATA_OVERRUN;
2248 spin_lock_irqsave(&t->task_state_lock, flags);
2249 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2250 t->task_state_flags |= SAS_TASK_STATE_DONE;
2251 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2252 spin_unlock_irqrestore(&t->task_state_lock, flags);
2253 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2254 t, event, ts->resp, ts->stat);
2255 pm8001_ccb_task_free(pm8001_ha, ccb);
2257 spin_unlock_irqrestore(&t->task_state_lock, flags);
2258 pm8001_ccb_task_free(pm8001_ha, ccb);
2259 mb();/* in order to force CPU ordering */
2264 /*See the comments for mpi_ssp_completion */
2266 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2269 struct pm8001_ccb_info *ccb;
2274 u8 sata_addr_low[4];
2275 u32 temp_sata_addr_low;
2277 u32 temp_sata_addr_hi;
2278 struct sata_completion_resp *psataPayload;
2279 struct task_status_struct *ts;
2280 struct ata_task_resp *resp ;
2282 struct pm8001_device *pm8001_dev;
2283 unsigned long flags;
2285 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2286 status = le32_to_cpu(psataPayload->status);
2287 param = le32_to_cpu(psataPayload->param);
2288 tag = le32_to_cpu(psataPayload->tag);
2290 ccb = &pm8001_ha->ccb_info[tag];
2292 pm8001_dev = ccb->device;
2295 if (t->dev && (t->dev->lldd_dev))
2296 pm8001_dev = t->dev->lldd_dev;
2298 pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2302 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2303 && unlikely(!t || !t->lldd_task || !t->dev)) {
2304 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2308 ts = &t->task_status;
2311 pm8001_dbg(pm8001_ha, IOERR,
2312 "status:0x%x, tag:0x%x, task::0x%p\n",
2315 /* Print sas address of IO failed device */
2316 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2317 (status != IO_UNDERFLOW)) {
2318 if (!((t->dev->parent) &&
2319 (dev_is_expander(t->dev->parent->dev_type)))) {
2320 for (i = 0, j = 4; j <= 7 && i <= 3; i++, j++)
2321 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2322 for (i = 0, j = 0; j <= 3 && i <= 3; i++, j++)
2323 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2324 memcpy(&temp_sata_addr_low, sata_addr_low,
2325 sizeof(sata_addr_low));
2326 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2327 sizeof(sata_addr_hi));
2328 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2329 |((temp_sata_addr_hi << 8) &
2331 ((temp_sata_addr_hi >> 8)
2333 ((temp_sata_addr_hi << 24) &
2335 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2337 ((temp_sata_addr_low << 8)
2339 ((temp_sata_addr_low >> 8)
2341 ((temp_sata_addr_low << 24)
2343 pm8001_dev->attached_phy +
2345 pm8001_dbg(pm8001_ha, FAIL,
2346 "SAS Address of IO Failure Drive:%08x%08x\n",
2348 temp_sata_addr_low);
2350 pm8001_dbg(pm8001_ha, FAIL,
2351 "SAS Address of IO Failure Drive:%016llx\n",
2352 SAS_ADDR(t->dev->sas_addr));
2357 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2359 ts->resp = SAS_TASK_COMPLETE;
2360 ts->stat = SAS_SAM_STAT_GOOD;
2361 /* check if response is for SEND READ LOG */
2363 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2364 pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2366 pm8001_tag_free(pm8001_ha, tag);
2372 ts->resp = SAS_TASK_COMPLETE;
2373 ts->stat = SAS_PROTO_RESPONSE;
2374 ts->residual = param;
2375 pm8001_dbg(pm8001_ha, IO,
2376 "SAS_PROTO_RESPONSE len = %d\n",
2378 sata_resp = &psataPayload->sata_resp[0];
2379 resp = (struct ata_task_resp *)ts->buf;
2380 if (t->ata_task.dma_xfer == 0 &&
2381 t->data_dir == DMA_FROM_DEVICE) {
2382 len = sizeof(struct pio_setup_fis);
2383 pm8001_dbg(pm8001_ha, IO,
2384 "PIO read len = %d\n", len);
2385 } else if (t->ata_task.use_ncq &&
2386 t->data_dir != DMA_NONE) {
2387 len = sizeof(struct set_dev_bits_fis);
2388 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2391 len = sizeof(struct dev_to_host_fis);
2392 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2395 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2396 resp->frame_len = len;
2397 memcpy(&resp->ending_fis[0], sata_resp, len);
2398 ts->buf_valid_size = sizeof(*resp);
2400 pm8001_dbg(pm8001_ha, IO,
2401 "response too large\n");
2404 atomic_dec(&pm8001_dev->running_req);
2407 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2408 ts->resp = SAS_TASK_COMPLETE;
2409 ts->stat = SAS_ABORTED_TASK;
2411 atomic_dec(&pm8001_dev->running_req);
2413 /* following cases are to do cases */
2415 /* SATA Completion with error */
2416 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2417 ts->resp = SAS_TASK_COMPLETE;
2418 ts->stat = SAS_DATA_UNDERRUN;
2419 ts->residual = param;
2421 atomic_dec(&pm8001_dev->running_req);
2424 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2425 ts->resp = SAS_TASK_UNDELIVERED;
2426 ts->stat = SAS_PHY_DOWN;
2428 atomic_dec(&pm8001_dev->running_req);
2430 case IO_XFER_ERROR_BREAK:
2431 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2432 ts->resp = SAS_TASK_COMPLETE;
2433 ts->stat = SAS_INTERRUPTED;
2435 atomic_dec(&pm8001_dev->running_req);
2437 case IO_XFER_ERROR_PHY_NOT_READY:
2438 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2439 ts->resp = SAS_TASK_COMPLETE;
2440 ts->stat = SAS_OPEN_REJECT;
2441 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2443 atomic_dec(&pm8001_dev->running_req);
2445 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2446 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2447 ts->resp = SAS_TASK_COMPLETE;
2448 ts->stat = SAS_OPEN_REJECT;
2449 ts->open_rej_reason = SAS_OREJ_EPROTO;
2451 atomic_dec(&pm8001_dev->running_req);
2453 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2454 pm8001_dbg(pm8001_ha, IO,
2455 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2456 ts->resp = SAS_TASK_COMPLETE;
2457 ts->stat = SAS_OPEN_REJECT;
2458 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2460 atomic_dec(&pm8001_dev->running_req);
2462 case IO_OPEN_CNX_ERROR_BREAK:
2463 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2464 ts->resp = SAS_TASK_COMPLETE;
2465 ts->stat = SAS_OPEN_REJECT;
2466 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2468 atomic_dec(&pm8001_dev->running_req);
2470 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2471 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2472 ts->resp = SAS_TASK_COMPLETE;
2473 ts->stat = SAS_DEV_NO_RESPONSE;
2474 if (!t->uldd_task) {
2475 pm8001_handle_event(pm8001_ha,
2477 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2478 ts->resp = SAS_TASK_UNDELIVERED;
2479 ts->stat = SAS_QUEUE_FULL;
2480 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2484 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2485 pm8001_dbg(pm8001_ha, IO,
2486 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2487 ts->resp = SAS_TASK_UNDELIVERED;
2488 ts->stat = SAS_OPEN_REJECT;
2489 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2490 if (!t->uldd_task) {
2491 pm8001_handle_event(pm8001_ha,
2493 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2494 ts->resp = SAS_TASK_UNDELIVERED;
2495 ts->stat = SAS_QUEUE_FULL;
2496 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2500 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2501 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2502 ts->resp = SAS_TASK_COMPLETE;
2503 ts->stat = SAS_OPEN_REJECT;
2504 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2506 atomic_dec(&pm8001_dev->running_req);
2508 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2509 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2510 ts->resp = SAS_TASK_COMPLETE;
2511 ts->stat = SAS_DEV_NO_RESPONSE;
2512 if (!t->uldd_task) {
2513 pm8001_handle_event(pm8001_ha,
2515 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2516 ts->resp = SAS_TASK_UNDELIVERED;
2517 ts->stat = SAS_QUEUE_FULL;
2518 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2522 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2523 pm8001_dbg(pm8001_ha, IO,
2524 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2525 ts->resp = SAS_TASK_COMPLETE;
2526 ts->stat = SAS_OPEN_REJECT;
2527 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2529 atomic_dec(&pm8001_dev->running_req);
2531 case IO_XFER_ERROR_NAK_RECEIVED:
2532 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2533 ts->resp = SAS_TASK_COMPLETE;
2534 ts->stat = SAS_NAK_R_ERR;
2536 atomic_dec(&pm8001_dev->running_req);
2538 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2539 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2540 ts->resp = SAS_TASK_COMPLETE;
2541 ts->stat = SAS_NAK_R_ERR;
2543 atomic_dec(&pm8001_dev->running_req);
2545 case IO_XFER_ERROR_DMA:
2546 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2547 ts->resp = SAS_TASK_COMPLETE;
2548 ts->stat = SAS_ABORTED_TASK;
2550 atomic_dec(&pm8001_dev->running_req);
2552 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2553 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2554 ts->resp = SAS_TASK_UNDELIVERED;
2555 ts->stat = SAS_DEV_NO_RESPONSE;
2557 atomic_dec(&pm8001_dev->running_req);
2559 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2560 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2561 ts->resp = SAS_TASK_COMPLETE;
2562 ts->stat = SAS_DATA_UNDERRUN;
2564 atomic_dec(&pm8001_dev->running_req);
2566 case IO_XFER_OPEN_RETRY_TIMEOUT:
2567 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2568 ts->resp = SAS_TASK_COMPLETE;
2569 ts->stat = SAS_OPEN_TO;
2571 atomic_dec(&pm8001_dev->running_req);
2573 case IO_PORT_IN_RESET:
2574 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2575 ts->resp = SAS_TASK_COMPLETE;
2576 ts->stat = SAS_DEV_NO_RESPONSE;
2578 atomic_dec(&pm8001_dev->running_req);
2580 case IO_DS_NON_OPERATIONAL:
2581 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2582 ts->resp = SAS_TASK_COMPLETE;
2583 ts->stat = SAS_DEV_NO_RESPONSE;
2584 if (!t->uldd_task) {
2585 pm8001_handle_event(pm8001_ha, pm8001_dev,
2586 IO_DS_NON_OPERATIONAL);
2587 ts->resp = SAS_TASK_UNDELIVERED;
2588 ts->stat = SAS_QUEUE_FULL;
2589 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2593 case IO_DS_IN_RECOVERY:
2594 pm8001_dbg(pm8001_ha, IO, " IO_DS_IN_RECOVERY\n");
2595 ts->resp = SAS_TASK_COMPLETE;
2596 ts->stat = SAS_DEV_NO_RESPONSE;
2598 atomic_dec(&pm8001_dev->running_req);
2600 case IO_DS_IN_ERROR:
2601 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2602 ts->resp = SAS_TASK_COMPLETE;
2603 ts->stat = SAS_DEV_NO_RESPONSE;
2604 if (!t->uldd_task) {
2605 pm8001_handle_event(pm8001_ha, pm8001_dev,
2607 ts->resp = SAS_TASK_UNDELIVERED;
2608 ts->stat = SAS_QUEUE_FULL;
2609 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2613 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2614 pm8001_dbg(pm8001_ha, IO,
2615 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2616 ts->resp = SAS_TASK_COMPLETE;
2617 ts->stat = SAS_OPEN_REJECT;
2618 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2620 atomic_dec(&pm8001_dev->running_req);
2623 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2624 /* not allowed case. Therefore, return failed status */
2625 ts->resp = SAS_TASK_COMPLETE;
2626 ts->stat = SAS_DEV_NO_RESPONSE;
2628 atomic_dec(&pm8001_dev->running_req);
2631 spin_lock_irqsave(&t->task_state_lock, flags);
2632 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2633 t->task_state_flags |= SAS_TASK_STATE_DONE;
2634 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2635 spin_unlock_irqrestore(&t->task_state_lock, flags);
2636 pm8001_dbg(pm8001_ha, FAIL,
2637 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2638 t, status, ts->resp, ts->stat);
2639 pm8001_ccb_task_free(pm8001_ha, ccb);
2641 spin_unlock_irqrestore(&t->task_state_lock, flags);
2642 pm8001_ccb_task_free_done(pm8001_ha, ccb);
2646 /*See the comments for mpi_ssp_completion */
2647 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2650 struct task_status_struct *ts;
2651 struct pm8001_ccb_info *ccb;
2652 struct pm8001_device *pm8001_dev;
2653 struct sata_event_resp *psataPayload =
2654 (struct sata_event_resp *)(piomb + 4);
2655 u32 event = le32_to_cpu(psataPayload->event);
2656 u32 tag = le32_to_cpu(psataPayload->tag);
2657 u32 port_id = le32_to_cpu(psataPayload->port_id);
2658 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2661 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2663 /* Check if this is NCQ error */
2664 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2665 /* find device using device id */
2666 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2667 /* send read log extension */
2669 pm8001_send_read_log(pm8001_ha, pm8001_dev);
2673 ccb = &pm8001_ha->ccb_info[tag];
2675 pm8001_dev = ccb->device;
2677 pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event);
2678 if (unlikely(!t || !t->lldd_task || !t->dev))
2680 ts = &t->task_status;
2681 pm8001_dbg(pm8001_ha, DEVIO,
2682 "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2683 port_id, dev_id, tag, event);
2686 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2687 ts->resp = SAS_TASK_COMPLETE;
2688 ts->stat = SAS_DATA_OVERRUN;
2691 case IO_XFER_ERROR_BREAK:
2692 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2693 ts->resp = SAS_TASK_COMPLETE;
2694 ts->stat = SAS_INTERRUPTED;
2696 case IO_XFER_ERROR_PHY_NOT_READY:
2697 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2698 ts->resp = SAS_TASK_COMPLETE;
2699 ts->stat = SAS_OPEN_REJECT;
2700 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2702 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2703 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2704 ts->resp = SAS_TASK_COMPLETE;
2705 ts->stat = SAS_OPEN_REJECT;
2706 ts->open_rej_reason = SAS_OREJ_EPROTO;
2708 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2709 pm8001_dbg(pm8001_ha, IO,
2710 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2711 ts->resp = SAS_TASK_COMPLETE;
2712 ts->stat = SAS_OPEN_REJECT;
2713 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2715 case IO_OPEN_CNX_ERROR_BREAK:
2716 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2717 ts->resp = SAS_TASK_COMPLETE;
2718 ts->stat = SAS_OPEN_REJECT;
2719 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2721 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2722 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2723 ts->resp = SAS_TASK_UNDELIVERED;
2724 ts->stat = SAS_DEV_NO_RESPONSE;
2725 if (!t->uldd_task) {
2726 pm8001_handle_event(pm8001_ha,
2728 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2729 ts->resp = SAS_TASK_COMPLETE;
2730 ts->stat = SAS_QUEUE_FULL;
2734 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2735 pm8001_dbg(pm8001_ha, IO,
2736 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2737 ts->resp = SAS_TASK_UNDELIVERED;
2738 ts->stat = SAS_OPEN_REJECT;
2739 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2741 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2742 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2743 ts->resp = SAS_TASK_COMPLETE;
2744 ts->stat = SAS_OPEN_REJECT;
2745 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2747 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2748 pm8001_dbg(pm8001_ha, IO,
2749 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2750 ts->resp = SAS_TASK_COMPLETE;
2751 ts->stat = SAS_OPEN_REJECT;
2752 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2754 case IO_XFER_ERROR_NAK_RECEIVED:
2755 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2756 ts->resp = SAS_TASK_COMPLETE;
2757 ts->stat = SAS_NAK_R_ERR;
2759 case IO_XFER_ERROR_PEER_ABORTED:
2760 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2761 ts->resp = SAS_TASK_COMPLETE;
2762 ts->stat = SAS_NAK_R_ERR;
2764 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2765 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2766 ts->resp = SAS_TASK_COMPLETE;
2767 ts->stat = SAS_DATA_UNDERRUN;
2769 case IO_XFER_OPEN_RETRY_TIMEOUT:
2770 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2771 ts->resp = SAS_TASK_COMPLETE;
2772 ts->stat = SAS_OPEN_TO;
2774 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2775 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2776 ts->resp = SAS_TASK_COMPLETE;
2777 ts->stat = SAS_OPEN_TO;
2779 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2780 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2781 ts->resp = SAS_TASK_COMPLETE;
2782 ts->stat = SAS_OPEN_TO;
2784 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2785 pm8001_dbg(pm8001_ha, IO,
2786 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2787 ts->resp = SAS_TASK_COMPLETE;
2788 ts->stat = SAS_OPEN_TO;
2790 case IO_XFER_ERROR_OFFSET_MISMATCH:
2791 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2792 ts->resp = SAS_TASK_COMPLETE;
2793 ts->stat = SAS_OPEN_TO;
2795 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2796 pm8001_dbg(pm8001_ha, IO,
2797 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2798 ts->resp = SAS_TASK_COMPLETE;
2799 ts->stat = SAS_OPEN_TO;
2801 case IO_XFER_CMD_FRAME_ISSUED:
2802 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2804 case IO_XFER_PIO_SETUP_ERROR:
2805 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2806 ts->resp = SAS_TASK_COMPLETE;
2807 ts->stat = SAS_OPEN_TO;
2810 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2811 /* not allowed case. Therefore, return failed status */
2812 ts->resp = SAS_TASK_COMPLETE;
2813 ts->stat = SAS_OPEN_TO;
2818 /*See the comments for mpi_ssp_completion */
2820 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2823 struct pm8001_ccb_info *ccb;
2824 unsigned long flags;
2827 struct smp_completion_resp *psmpPayload;
2828 struct task_status_struct *ts;
2829 struct pm8001_device *pm8001_dev;
2831 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2832 status = le32_to_cpu(psmpPayload->status);
2833 tag = le32_to_cpu(psmpPayload->tag);
2835 ccb = &pm8001_ha->ccb_info[tag];
2837 ts = &t->task_status;
2838 pm8001_dev = ccb->device;
2840 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2841 pm8001_dbg(pm8001_ha, IOERR,
2842 "status:0x%x, tag:0x%x, task:0x%p\n",
2845 if (unlikely(!t || !t->lldd_task || !t->dev))
2850 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2851 ts->resp = SAS_TASK_COMPLETE;
2852 ts->stat = SAS_SAM_STAT_GOOD;
2854 atomic_dec(&pm8001_dev->running_req);
2857 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
2858 ts->resp = SAS_TASK_COMPLETE;
2859 ts->stat = SAS_ABORTED_TASK;
2861 atomic_dec(&pm8001_dev->running_req);
2864 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2865 ts->resp = SAS_TASK_COMPLETE;
2866 ts->stat = SAS_DATA_OVERRUN;
2869 atomic_dec(&pm8001_dev->running_req);
2872 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2873 ts->resp = SAS_TASK_COMPLETE;
2874 ts->stat = SAS_PHY_DOWN;
2876 case IO_ERROR_HW_TIMEOUT:
2877 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
2878 ts->resp = SAS_TASK_COMPLETE;
2879 ts->stat = SAS_SAM_STAT_BUSY;
2881 case IO_XFER_ERROR_BREAK:
2882 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2883 ts->resp = SAS_TASK_COMPLETE;
2884 ts->stat = SAS_SAM_STAT_BUSY;
2886 case IO_XFER_ERROR_PHY_NOT_READY:
2887 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2888 ts->resp = SAS_TASK_COMPLETE;
2889 ts->stat = SAS_SAM_STAT_BUSY;
2891 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2892 pm8001_dbg(pm8001_ha, IO,
2893 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2894 ts->resp = SAS_TASK_COMPLETE;
2895 ts->stat = SAS_OPEN_REJECT;
2896 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2898 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2899 pm8001_dbg(pm8001_ha, IO,
2900 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2901 ts->resp = SAS_TASK_COMPLETE;
2902 ts->stat = SAS_OPEN_REJECT;
2903 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2905 case IO_OPEN_CNX_ERROR_BREAK:
2906 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2907 ts->resp = SAS_TASK_COMPLETE;
2908 ts->stat = SAS_OPEN_REJECT;
2909 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2911 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2912 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2913 ts->resp = SAS_TASK_COMPLETE;
2914 ts->stat = SAS_OPEN_REJECT;
2915 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2916 pm8001_handle_event(pm8001_ha,
2918 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2920 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2921 pm8001_dbg(pm8001_ha, IO,
2922 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2923 ts->resp = SAS_TASK_COMPLETE;
2924 ts->stat = SAS_OPEN_REJECT;
2925 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2927 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2928 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2929 ts->resp = SAS_TASK_COMPLETE;
2930 ts->stat = SAS_OPEN_REJECT;
2931 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2933 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2934 pm8001_dbg(pm8001_ha, IO,
2935 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2936 ts->resp = SAS_TASK_COMPLETE;
2937 ts->stat = SAS_OPEN_REJECT;
2938 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2940 case IO_XFER_ERROR_RX_FRAME:
2941 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
2942 ts->resp = SAS_TASK_COMPLETE;
2943 ts->stat = SAS_DEV_NO_RESPONSE;
2945 case IO_XFER_OPEN_RETRY_TIMEOUT:
2946 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2947 ts->resp = SAS_TASK_COMPLETE;
2948 ts->stat = SAS_OPEN_REJECT;
2949 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2951 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2952 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
2953 ts->resp = SAS_TASK_COMPLETE;
2954 ts->stat = SAS_QUEUE_FULL;
2956 case IO_PORT_IN_RESET:
2957 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2958 ts->resp = SAS_TASK_COMPLETE;
2959 ts->stat = SAS_OPEN_REJECT;
2960 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2962 case IO_DS_NON_OPERATIONAL:
2963 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2964 ts->resp = SAS_TASK_COMPLETE;
2965 ts->stat = SAS_DEV_NO_RESPONSE;
2967 case IO_DS_IN_RECOVERY:
2968 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2969 ts->resp = SAS_TASK_COMPLETE;
2970 ts->stat = SAS_OPEN_REJECT;
2971 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2973 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2974 pm8001_dbg(pm8001_ha, IO,
2975 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2976 ts->resp = SAS_TASK_COMPLETE;
2977 ts->stat = SAS_OPEN_REJECT;
2978 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2981 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2982 ts->resp = SAS_TASK_COMPLETE;
2983 ts->stat = SAS_DEV_NO_RESPONSE;
2984 /* not allowed case. Therefore, return failed status */
2987 spin_lock_irqsave(&t->task_state_lock, flags);
2988 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2989 t->task_state_flags |= SAS_TASK_STATE_DONE;
2990 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2991 spin_unlock_irqrestore(&t->task_state_lock, flags);
2992 pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2993 t, status, ts->resp, ts->stat);
2994 pm8001_ccb_task_free(pm8001_ha, ccb);
2996 spin_unlock_irqrestore(&t->task_state_lock, flags);
2997 pm8001_ccb_task_free_done(pm8001_ha, ccb);
3001 void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3004 struct set_dev_state_resp *pPayload =
3005 (struct set_dev_state_resp *)(piomb + 4);
3006 u32 tag = le32_to_cpu(pPayload->tag);
3007 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3008 struct pm8001_device *pm8001_dev = ccb->device;
3009 u32 status = le32_to_cpu(pPayload->status);
3010 u32 device_id = le32_to_cpu(pPayload->device_id);
3011 u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3012 u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3014 pm8001_dbg(pm8001_ha, MSG,
3015 "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n",
3016 device_id, pds, nds, status);
3017 complete(pm8001_dev->setds_completion);
3018 pm8001_ccb_free(pm8001_ha, ccb);
3021 void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3023 struct get_nvm_data_resp *pPayload =
3024 (struct get_nvm_data_resp *)(piomb + 4);
3025 u32 tag = le32_to_cpu(pPayload->tag);
3026 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3027 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3029 complete(pm8001_ha->nvmd_completion);
3030 pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n");
3031 if ((dlen_status & NVMD_STAT) != 0) {
3032 pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error %x\n",
3035 pm8001_ccb_free(pm8001_ha, ccb);
3039 pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3041 struct fw_control_ex *fw_control_context;
3042 struct get_nvm_data_resp *pPayload =
3043 (struct get_nvm_data_resp *)(piomb + 4);
3044 u32 tag = le32_to_cpu(pPayload->tag);
3045 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3046 u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3047 u32 ir_tds_bn_dps_das_nvm =
3048 le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3049 void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3050 fw_control_context = ccb->fw_control_context;
3052 pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n");
3053 if ((dlen_status & NVMD_STAT) != 0) {
3054 pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error %x\n",
3056 complete(pm8001_ha->nvmd_completion);
3057 /* We should free tag during failure also, the tag is not being
3058 * freed by requesting path anywhere.
3060 pm8001_ccb_free(pm8001_ha, ccb);
3063 if (ir_tds_bn_dps_das_nvm & IPMode) {
3064 /* indirect mode - IR bit set */
3065 pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n");
3066 if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3067 if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3068 memcpy(pm8001_ha->sas_addr,
3069 ((u8 *)virt_addr + 4),
3071 pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n");
3073 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3074 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3075 ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3077 } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3078 || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3081 /* Should not be happened*/
3082 pm8001_dbg(pm8001_ha, MSG,
3083 "(IR=1)Wrong Device type 0x%x\n",
3084 ir_tds_bn_dps_das_nvm);
3086 } else /* direct mode */{
3087 pm8001_dbg(pm8001_ha, MSG,
3088 "Get NVMD success, IR=0, dataLen=%d\n",
3089 (dlen_status & NVMD_LEN) >> 24);
3091 /* Though fw_control_context is freed below, usrAddr still needs
3092 * to be updated as this holds the response to the request function
3094 memcpy(fw_control_context->usrAddr,
3095 pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3096 fw_control_context->len);
3097 kfree(ccb->fw_control_context);
3098 /* To avoid race condition, complete should be
3099 * called after the message is copied to
3100 * fw_control_context->usrAddr
3102 complete(pm8001_ha->nvmd_completion);
3103 pm8001_dbg(pm8001_ha, MSG, "Get nvmd data complete!\n");
3104 pm8001_ccb_free(pm8001_ha, ccb);
3107 int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3110 struct local_phy_ctl_resp *pPayload =
3111 (struct local_phy_ctl_resp *)(piomb + 4);
3112 u32 status = le32_to_cpu(pPayload->status);
3113 u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3114 u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3115 tag = le32_to_cpu(pPayload->tag);
3117 pm8001_dbg(pm8001_ha, MSG,
3118 "%x phy execute %x phy op failed!\n",
3121 pm8001_dbg(pm8001_ha, MSG,
3122 "%x phy execute %x phy op success!\n",
3124 pm8001_ha->phy[phy_id].reset_success = true;
3126 if (pm8001_ha->phy[phy_id].enable_completion) {
3127 complete(pm8001_ha->phy[phy_id].enable_completion);
3128 pm8001_ha->phy[phy_id].enable_completion = NULL;
3130 pm8001_tag_free(pm8001_ha, tag);
3135 * pm8001_bytes_dmaed - one of the interface function communication with libsas
3136 * @pm8001_ha: our hba card information
3137 * @i: which phy that received the event.
3139 * when HBA driver received the identify done event or initiate FIS received
3140 * event(for SATA), it will invoke this function to notify the sas layer that
3141 * the sas toplogy has formed, please discover the the whole sas domain,
3142 * while receive a broadcast(change) primitive just tell the sas
3143 * layer to discover the changed domain rather than the whole domain.
3145 void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3147 struct pm8001_phy *phy = &pm8001_ha->phy[i];
3148 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3149 if (!phy->phy_attached)
3152 if (phy->phy_type & PORT_TYPE_SAS) {
3153 struct sas_identify_frame *id;
3154 id = (struct sas_identify_frame *)phy->frame_rcvd;
3155 id->dev_type = phy->identify.device_type;
3156 id->initiator_bits = SAS_PROTOCOL_ALL;
3157 id->target_bits = phy->identify.target_port_protocols;
3158 } else if (phy->phy_type & PORT_TYPE_SATA) {
3161 pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i);
3163 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3164 sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED, GFP_ATOMIC);
3167 /* Get the link rate speed */
3168 void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3170 struct sas_phy *sas_phy = phy->sas_phy.phy;
3172 switch (link_rate) {
3174 phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
3177 phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3180 phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3183 phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3186 sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3187 sas_phy->maximum_linkrate_hw = phy->maximum_linkrate;
3188 sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3189 sas_phy->maximum_linkrate = phy->maximum_linkrate;
3190 sas_phy->minimum_linkrate = phy->minimum_linkrate;
3194 * pm8001_get_attached_sas_addr - extract/generate attached SAS address
3195 * @phy: pointer to asd_phy
3196 * @sas_addr: pointer to buffer where the SAS address is to be written
3198 * This function extracts the SAS address from an IDENTIFY frame
3199 * received. If OOB is SATA, then a SAS address is generated from the
3202 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3205 void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3208 if (phy->sas_phy.frame_rcvd[0] == 0x34
3209 && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3210 struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3211 /* FIS device-to-host */
3212 u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3213 addr += phy->sas_phy.id;
3214 *(__be64 *)sas_addr = cpu_to_be64(addr);
3216 struct sas_identify_frame *idframe =
3217 (void *) phy->sas_phy.frame_rcvd;
3218 memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3223 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3224 * @pm8001_ha: our hba card information
3225 * @Qnum: the outbound queue message number.
3226 * @SEA: source of event to ack
3227 * @port_id: port id.
3229 * @param0: parameter 0.
3230 * @param1: parameter 1.
3232 static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3233 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3235 struct hw_event_ack_req payload;
3236 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3238 memset((u8 *)&payload, 0, sizeof(payload));
3239 payload.tag = cpu_to_le32(1);
3240 payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3241 ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3242 payload.param0 = cpu_to_le32(param0);
3243 payload.param1 = cpu_to_le32(param1);
3245 pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload, sizeof(payload), 0);
3248 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3249 u32 phyId, u32 phy_op);
3252 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3253 * @pm8001_ha: our hba card information
3254 * @piomb: IO message buffer
3257 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3259 struct hw_event_resp *pPayload =
3260 (struct hw_event_resp *)(piomb + 4);
3261 u32 lr_evt_status_phyid_portid =
3262 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3264 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3265 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3267 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3268 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3269 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3270 struct pm8001_port *port = &pm8001_ha->port[port_id];
3271 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3272 unsigned long flags;
3273 u8 deviceType = pPayload->sas_identify.dev_type;
3275 port->port_id = port_id;
3276 port->port_state = portstate;
3277 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3278 pm8001_dbg(pm8001_ha, MSG,
3279 "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3282 switch (deviceType) {
3283 case SAS_PHY_UNUSED:
3284 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3286 case SAS_END_DEVICE:
3287 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3288 pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3289 PHY_NOTIFY_ENABLE_SPINUP);
3290 port->port_attached = 1;
3291 pm8001_get_lrate_mode(phy, link_rate);
3293 case SAS_EDGE_EXPANDER_DEVICE:
3294 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3295 port->port_attached = 1;
3296 pm8001_get_lrate_mode(phy, link_rate);
3298 case SAS_FANOUT_EXPANDER_DEVICE:
3299 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3300 port->port_attached = 1;
3301 pm8001_get_lrate_mode(phy, link_rate);
3304 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3308 phy->phy_type |= PORT_TYPE_SAS;
3309 phy->identify.device_type = deviceType;
3310 phy->phy_attached = 1;
3311 if (phy->identify.device_type == SAS_END_DEVICE)
3312 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3313 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3314 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3315 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3316 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3317 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3318 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3319 sizeof(struct sas_identify_frame)-4);
3320 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3321 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3322 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3323 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3324 mdelay(200);/*delay a moment to wait disk to spinup*/
3325 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3329 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3330 * @pm8001_ha: our hba card information
3331 * @piomb: IO message buffer
3334 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3336 struct hw_event_resp *pPayload =
3337 (struct hw_event_resp *)(piomb + 4);
3338 u32 lr_evt_status_phyid_portid =
3339 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3341 (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3342 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3344 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3345 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3346 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3347 struct pm8001_port *port = &pm8001_ha->port[port_id];
3348 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3349 unsigned long flags;
3350 pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n",
3353 port->port_id = port_id;
3354 port->port_state = portstate;
3355 phy->phy_state = PHY_STATE_LINK_UP_SPC;
3356 port->port_attached = 1;
3357 pm8001_get_lrate_mode(phy, link_rate);
3358 phy->phy_type |= PORT_TYPE_SATA;
3359 phy->phy_attached = 1;
3360 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3361 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3362 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3363 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3364 sizeof(struct dev_to_host_fis));
3365 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3366 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3367 phy->identify.device_type = SAS_SATA_DEV;
3368 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3369 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3370 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3374 * hw_event_phy_down -we should notify the libsas the phy is down.
3375 * @pm8001_ha: our hba card information
3376 * @piomb: IO message buffer
3379 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3381 struct hw_event_resp *pPayload =
3382 (struct hw_event_resp *)(piomb + 4);
3383 u32 lr_evt_status_phyid_portid =
3384 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3385 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3387 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3388 u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3389 u8 portstate = (u8)(npip_portstate & 0x0000000F);
3390 struct pm8001_port *port = &pm8001_ha->port[port_id];
3391 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3392 port->port_state = portstate;
3394 phy->identify.device_type = 0;
3395 phy->phy_attached = 0;
3396 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3397 switch (portstate) {
3401 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3403 pm8001_dbg(pm8001_ha, MSG,
3404 " Last phy Down and port invalid\n");
3405 port->port_attached = 0;
3406 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3407 port_id, phy_id, 0, 0);
3410 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3413 case PORT_NOT_ESTABLISHED:
3414 pm8001_dbg(pm8001_ha, MSG,
3415 " phy Down and PORT_NOT_ESTABLISHED\n");
3416 port->port_attached = 0;
3419 pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n");
3420 pm8001_dbg(pm8001_ha, MSG,
3421 " Last phy Down and port invalid\n");
3422 port->port_attached = 0;
3423 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3424 port_id, phy_id, 0, 0);
3427 port->port_attached = 0;
3428 pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n",
3436 * pm8001_mpi_reg_resp -process register device ID response.
3437 * @pm8001_ha: our hba card information
3438 * @piomb: IO message buffer
3440 * when sas layer find a device it will notify LLDD, then the driver register
3441 * the domain device to FW, this event is the return device ID which the FW
3442 * has assigned, from now, inter-communication with FW is no longer using the
3443 * SAS address, use device ID which FW assigned.
3445 int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3450 struct pm8001_ccb_info *ccb;
3451 struct pm8001_device *pm8001_dev;
3452 struct dev_reg_resp *registerRespPayload =
3453 (struct dev_reg_resp *)(piomb + 4);
3455 htag = le32_to_cpu(registerRespPayload->tag);
3456 ccb = &pm8001_ha->ccb_info[htag];
3457 pm8001_dev = ccb->device;
3458 status = le32_to_cpu(registerRespPayload->status);
3459 device_id = le32_to_cpu(registerRespPayload->device_id);
3460 pm8001_dbg(pm8001_ha, MSG, " register device is status = %d\n",
3463 case DEVREG_SUCCESS:
3464 pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n");
3465 pm8001_dev->device_id = device_id;
3467 case DEVREG_FAILURE_OUT_OF_RESOURCE:
3468 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n");
3470 case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3471 pm8001_dbg(pm8001_ha, MSG,
3472 "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n");
3474 case DEVREG_FAILURE_INVALID_PHY_ID:
3475 pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n");
3477 case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3478 pm8001_dbg(pm8001_ha, MSG,
3479 "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n");
3481 case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3482 pm8001_dbg(pm8001_ha, MSG,
3483 "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n");
3485 case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3486 pm8001_dbg(pm8001_ha, MSG,
3487 "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n");
3489 case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3490 pm8001_dbg(pm8001_ha, MSG,
3491 "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n");
3494 pm8001_dbg(pm8001_ha, MSG,
3495 "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n");
3498 complete(pm8001_dev->dcompletion);
3499 pm8001_ccb_free(pm8001_ha, ccb);
3503 int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3507 struct dev_reg_resp *registerRespPayload =
3508 (struct dev_reg_resp *)(piomb + 4);
3510 status = le32_to_cpu(registerRespPayload->status);
3511 device_id = le32_to_cpu(registerRespPayload->device_id);
3513 pm8001_dbg(pm8001_ha, MSG,
3514 " deregister device failed ,status = %x, device_id = %x\n",
3520 * pm8001_mpi_fw_flash_update_resp - Response from FW for flash update command.
3521 * @pm8001_ha: our hba card information
3522 * @piomb: IO message buffer
3524 int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3528 struct fw_flash_Update_resp *ppayload =
3529 (struct fw_flash_Update_resp *)(piomb + 4);
3530 u32 tag = le32_to_cpu(ppayload->tag);
3531 struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3533 status = le32_to_cpu(ppayload->status);
3535 case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3536 pm8001_dbg(pm8001_ha, MSG,
3537 ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n");
3539 case FLASH_UPDATE_IN_PROGRESS:
3540 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n");
3542 case FLASH_UPDATE_HDR_ERR:
3543 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n");
3545 case FLASH_UPDATE_OFFSET_ERR:
3546 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n");
3548 case FLASH_UPDATE_CRC_ERR:
3549 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n");
3551 case FLASH_UPDATE_LENGTH_ERR:
3552 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n");
3554 case FLASH_UPDATE_HW_ERR:
3555 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n");
3557 case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3558 pm8001_dbg(pm8001_ha, MSG,
3559 ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n");
3561 case FLASH_UPDATE_DISABLED:
3562 pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n");
3565 pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n",
3569 kfree(ccb->fw_control_context);
3570 pm8001_ccb_free(pm8001_ha, ccb);
3571 complete(pm8001_ha->nvmd_completion);
3575 int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3579 struct general_event_resp *pPayload =
3580 (struct general_event_resp *)(piomb + 4);
3581 status = le32_to_cpu(pPayload->status);
3582 pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status);
3583 for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3584 pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n",
3586 pPayload->inb_IOMB_payload[i]);
3590 int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3593 struct pm8001_ccb_info *ccb;
3594 unsigned long flags;
3597 struct task_status_struct *ts;
3598 struct pm8001_device *pm8001_dev;
3600 struct task_abort_resp *pPayload =
3601 (struct task_abort_resp *)(piomb + 4);
3603 status = le32_to_cpu(pPayload->status);
3604 tag = le32_to_cpu(pPayload->tag);
3606 scp = le32_to_cpu(pPayload->scp);
3607 ccb = &pm8001_ha->ccb_info[tag];
3609 pm8001_dev = ccb->device; /* retrieve device */
3612 pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n");
3615 ts = &t->task_status;
3617 pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n",
3621 pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n");
3622 ts->resp = SAS_TASK_COMPLETE;
3623 ts->stat = SAS_SAM_STAT_GOOD;
3626 pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n");
3627 ts->resp = TMF_RESP_FUNC_FAILED;
3630 spin_lock_irqsave(&t->task_state_lock, flags);
3631 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3632 t->task_state_flags |= SAS_TASK_STATE_DONE;
3633 spin_unlock_irqrestore(&t->task_state_lock, flags);
3634 pm8001_ccb_task_free(pm8001_ha, ccb);
3637 if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3639 pm8001_dev->id &= ~NCQ_ABORT_ALL_FLAG;
3648 * mpi_hw_event -The hw event has come.
3649 * @pm8001_ha: our hba card information
3650 * @piomb: IO message buffer
3652 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3654 unsigned long flags;
3655 struct hw_event_resp *pPayload =
3656 (struct hw_event_resp *)(piomb + 4);
3657 u32 lr_evt_status_phyid_portid =
3658 le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3659 u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3661 (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3663 (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3665 (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3666 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3667 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3668 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3669 pm8001_dbg(pm8001_ha, DEVIO,
3670 "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n",
3671 port_id, phy_id, eventType, status);
3672 switch (eventType) {
3673 case HW_EVENT_PHY_START_STATUS:
3674 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n",
3679 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3680 phy->enable_completion != NULL) {
3681 complete(phy->enable_completion);
3682 phy->enable_completion = NULL;
3685 case HW_EVENT_SAS_PHY_UP:
3686 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3687 hw_event_sas_phy_up(pm8001_ha, piomb);
3689 case HW_EVENT_SATA_PHY_UP:
3690 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3691 hw_event_sata_phy_up(pm8001_ha, piomb);
3693 case HW_EVENT_PHY_STOP_STATUS:
3694 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n",
3699 case HW_EVENT_SATA_SPINUP_HOLD:
3700 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3701 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3704 case HW_EVENT_PHY_DOWN:
3705 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3706 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3708 phy->phy_attached = 0;
3710 hw_event_phy_down(pm8001_ha, piomb);
3712 case HW_EVENT_PORT_INVALID:
3713 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3714 sas_phy_disconnected(sas_phy);
3715 phy->phy_attached = 0;
3716 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3719 /* the broadcast change primitive received, tell the LIBSAS this event
3720 to revalidate the sas domain*/
3721 case HW_EVENT_BROADCAST_CHANGE:
3722 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3723 pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3724 port_id, phy_id, 1, 0);
3725 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3726 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3727 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3728 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3731 case HW_EVENT_PHY_ERROR:
3732 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3733 sas_phy_disconnected(&phy->sas_phy);
3734 phy->phy_attached = 0;
3735 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3737 case HW_EVENT_BROADCAST_EXP:
3738 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3739 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3740 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3741 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3742 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3745 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3746 pm8001_dbg(pm8001_ha, MSG,
3747 "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3748 pm8001_hw_event_ack_req(pm8001_ha, 0,
3749 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3750 sas_phy_disconnected(sas_phy);
3751 phy->phy_attached = 0;
3752 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3755 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3756 pm8001_dbg(pm8001_ha, MSG,
3757 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3758 pm8001_hw_event_ack_req(pm8001_ha, 0,
3759 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3760 port_id, phy_id, 0, 0);
3761 sas_phy_disconnected(sas_phy);
3762 phy->phy_attached = 0;
3763 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3766 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3767 pm8001_dbg(pm8001_ha, MSG,
3768 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3769 pm8001_hw_event_ack_req(pm8001_ha, 0,
3770 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3771 port_id, phy_id, 0, 0);
3772 sas_phy_disconnected(sas_phy);
3773 phy->phy_attached = 0;
3774 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3777 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3778 pm8001_dbg(pm8001_ha, MSG,
3779 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3780 pm8001_hw_event_ack_req(pm8001_ha, 0,
3781 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3782 port_id, phy_id, 0, 0);
3783 sas_phy_disconnected(sas_phy);
3784 phy->phy_attached = 0;
3785 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3788 case HW_EVENT_MALFUNCTION:
3789 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3791 case HW_EVENT_BROADCAST_SES:
3792 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3793 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3794 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3795 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3796 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3799 case HW_EVENT_INBOUND_CRC_ERROR:
3800 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3801 pm8001_hw_event_ack_req(pm8001_ha, 0,
3802 HW_EVENT_INBOUND_CRC_ERROR,
3803 port_id, phy_id, 0, 0);
3805 case HW_EVENT_HARD_RESET_RECEIVED:
3806 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3807 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3809 case HW_EVENT_ID_FRAME_TIMEOUT:
3810 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3811 sas_phy_disconnected(sas_phy);
3812 phy->phy_attached = 0;
3813 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3816 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3817 pm8001_dbg(pm8001_ha, MSG,
3818 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3819 pm8001_hw_event_ack_req(pm8001_ha, 0,
3820 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3821 port_id, phy_id, 0, 0);
3822 sas_phy_disconnected(sas_phy);
3823 phy->phy_attached = 0;
3824 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3827 case HW_EVENT_PORT_RESET_TIMER_TMO:
3828 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3829 sas_phy_disconnected(sas_phy);
3830 phy->phy_attached = 0;
3831 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3834 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3835 pm8001_dbg(pm8001_ha, MSG,
3836 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3837 sas_phy_disconnected(sas_phy);
3838 phy->phy_attached = 0;
3839 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3842 case HW_EVENT_PORT_RECOVER:
3843 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3845 case HW_EVENT_PORT_RESET_COMPLETE:
3846 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3848 case EVENT_BROADCAST_ASYNCH_EVENT:
3849 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3852 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type = %x\n",
3860 * process_one_iomb - process one outbound Queue memory block
3861 * @pm8001_ha: our hba card information
3862 * @piomb: IO message buffer
3864 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3866 __le32 pHeader = *(__le32 *)piomb;
3867 u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
3869 pm8001_dbg(pm8001_ha, MSG, "process_one_iomb:\n");
3873 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3875 case OPC_OUB_HW_EVENT:
3876 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3877 mpi_hw_event(pm8001_ha, piomb);
3879 case OPC_OUB_SSP_COMP:
3880 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3881 mpi_ssp_completion(pm8001_ha, piomb);
3883 case OPC_OUB_SMP_COMP:
3884 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3885 mpi_smp_completion(pm8001_ha, piomb);
3887 case OPC_OUB_LOCAL_PHY_CNTRL:
3888 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3889 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3891 case OPC_OUB_DEV_REGIST:
3892 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3893 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3895 case OPC_OUB_DEREG_DEV:
3896 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3897 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3899 case OPC_OUB_GET_DEV_HANDLE:
3900 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3902 case OPC_OUB_SATA_COMP:
3903 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3904 mpi_sata_completion(pm8001_ha, piomb);
3906 case OPC_OUB_SATA_EVENT:
3907 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3908 mpi_sata_event(pm8001_ha, piomb);
3910 case OPC_OUB_SSP_EVENT:
3911 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3912 mpi_ssp_event(pm8001_ha, piomb);
3914 case OPC_OUB_DEV_HANDLE_ARRIV:
3915 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3916 /*This is for target*/
3918 case OPC_OUB_SSP_RECV_EVENT:
3919 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3920 /*This is for target*/
3922 case OPC_OUB_DEV_INFO:
3923 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_INFO\n");
3925 case OPC_OUB_FW_FLASH_UPDATE:
3926 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3927 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3929 case OPC_OUB_GPIO_RESPONSE:
3930 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3932 case OPC_OUB_GPIO_EVENT:
3933 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3935 case OPC_OUB_GENERAL_EVENT:
3936 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3937 pm8001_mpi_general_event(pm8001_ha, piomb);
3939 case OPC_OUB_SSP_ABORT_RSP:
3940 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3941 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3943 case OPC_OUB_SATA_ABORT_RSP:
3944 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3945 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3947 case OPC_OUB_SAS_DIAG_MODE_START_END:
3948 pm8001_dbg(pm8001_ha, MSG,
3949 "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3951 case OPC_OUB_SAS_DIAG_EXECUTE:
3952 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3954 case OPC_OUB_GET_TIME_STAMP:
3955 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3957 case OPC_OUB_SAS_HW_EVENT_ACK:
3958 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3960 case OPC_OUB_PORT_CONTROL:
3961 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3963 case OPC_OUB_SMP_ABORT_RSP:
3964 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3965 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3967 case OPC_OUB_GET_NVMD_DATA:
3968 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3969 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3971 case OPC_OUB_SET_NVMD_DATA:
3972 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3973 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3975 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3976 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
3978 case OPC_OUB_SET_DEVICE_STATE:
3979 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
3980 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3982 case OPC_OUB_GET_DEVICE_STATE:
3983 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
3985 case OPC_OUB_SET_DEV_INFO:
3986 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
3988 case OPC_OUB_SAS_RE_INITIALIZE:
3989 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_RE_INITIALIZE\n");
3992 pm8001_dbg(pm8001_ha, DEVIO,
3993 "Unknown outbound Queue IOMB OPC = %x\n",
3999 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4001 struct outbound_queue_table *circularQ;
4004 u32 ret = MPI_IO_STATUS_FAIL;
4005 unsigned long flags;
4007 spin_lock_irqsave(&pm8001_ha->lock, flags);
4008 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4010 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4011 if (MPI_IO_STATUS_SUCCESS == ret) {
4012 /* process the outbound message */
4013 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
4014 /* free the message from the outbound circular buffer */
4015 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4018 if (MPI_IO_STATUS_BUSY == ret) {
4019 /* Update the producer index from SPC */
4020 circularQ->producer_index =
4021 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4022 if (le32_to_cpu(circularQ->producer_index) ==
4023 circularQ->consumer_idx)
4028 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
4032 /* DMA_... to our direction translation. */
4033 static const u8 data_dir_flags[] = {
4034 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4035 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4036 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4037 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4040 pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
4043 struct scatterlist *sg;
4044 struct pm8001_prd *buf_prd = prd;
4046 for_each_sg(scatter, sg, nr, i) {
4047 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
4048 buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
4049 buf_prd->im_len.e = 0;
4054 static void build_smp_cmd(u32 deviceID, __le32 hTag, struct smp_req *psmp_cmd)
4056 psmp_cmd->tag = hTag;
4057 psmp_cmd->device_id = cpu_to_le32(deviceID);
4058 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4062 * pm8001_chip_smp_req - send a SMP task to FW
4063 * @pm8001_ha: our hba card information.
4064 * @ccb: the ccb information this request used.
4066 static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4067 struct pm8001_ccb_info *ccb)
4070 struct sas_task *task = ccb->task;
4071 struct domain_device *dev = task->dev;
4072 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4073 struct scatterlist *sg_req, *sg_resp;
4074 u32 req_len, resp_len;
4075 struct smp_req smp_cmd;
4078 memset(&smp_cmd, 0, sizeof(smp_cmd));
4080 * DMA-map SMP request, response buffers
4082 sg_req = &task->smp_task.smp_req;
4083 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4086 req_len = sg_dma_len(sg_req);
4088 sg_resp = &task->smp_task.smp_resp;
4089 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4094 resp_len = sg_dma_len(sg_resp);
4095 /* must be in dwords */
4096 if ((req_len & 0x3) || (resp_len & 0x3)) {
4101 opc = OPC_INB_SMP_REQUEST;
4102 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4103 smp_cmd.long_smp_req.long_req_addr =
4104 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4105 smp_cmd.long_smp_req.long_req_size =
4106 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4107 smp_cmd.long_smp_req.long_resp_addr =
4108 cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
4109 smp_cmd.long_smp_req.long_resp_size =
4110 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4111 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
4112 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc,
4113 &smp_cmd, sizeof(smp_cmd), 0);
4120 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4123 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4129 * pm8001_chip_ssp_io_req - send a SSP task to FW
4130 * @pm8001_ha: our hba card information.
4131 * @ccb: the ccb information this request used.
4133 static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4134 struct pm8001_ccb_info *ccb)
4136 struct sas_task *task = ccb->task;
4137 struct domain_device *dev = task->dev;
4138 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4139 struct ssp_ini_io_start_req ssp_cmd;
4140 u32 tag = ccb->ccb_tag;
4142 u32 opc = OPC_INB_SSPINIIOSTART;
4143 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4144 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4146 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);/*0 for
4147 SAS 1.1 compatible TLR*/
4148 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4149 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4150 ssp_cmd.tag = cpu_to_le32(tag);
4151 if (task->ssp_task.enable_first_burst)
4152 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4153 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4154 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4155 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4156 task->ssp_task.cmd->cmd_len);
4158 /* fill in PRD (scatter/gather) table, if any */
4159 if (task->num_scatter > 1) {
4160 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4161 phys_addr = ccb->ccb_dma_handle;
4162 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(phys_addr));
4163 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(phys_addr));
4164 ssp_cmd.esgl = cpu_to_le32(1<<31);
4165 } else if (task->num_scatter == 1) {
4166 u64 dma_addr = sg_dma_address(task->scatter);
4167 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4168 ssp_cmd.addr_high = cpu_to_le32(upper_32_bits(dma_addr));
4169 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4171 } else if (task->num_scatter == 0) {
4172 ssp_cmd.addr_low = 0;
4173 ssp_cmd.addr_high = 0;
4174 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4178 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &ssp_cmd,
4179 sizeof(ssp_cmd), 0);
4182 static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4183 struct pm8001_ccb_info *ccb)
4185 struct sas_task *task = ccb->task;
4186 struct domain_device *dev = task->dev;
4187 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4188 u32 tag = ccb->ccb_tag;
4189 struct sata_start_req sata_cmd;
4190 u32 hdr_tag, ncg_tag = 0;
4194 unsigned long flags;
4195 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4197 memset(&sata_cmd, 0, sizeof(sata_cmd));
4199 if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4200 ATAP = 0x04; /* no data*/
4201 pm8001_dbg(pm8001_ha, IO, "no data\n");
4202 } else if (likely(!task->ata_task.device_control_reg_update)) {
4203 if (task->ata_task.use_ncq &&
4204 dev->sata_dev.class != ATA_DEV_ATAPI) {
4205 ATAP = 0x07; /* FPDMA */
4206 pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4207 } else if (task->ata_task.dma_xfer) {
4208 ATAP = 0x06; /* DMA */
4209 pm8001_dbg(pm8001_ha, IO, "DMA\n");
4211 ATAP = 0x05; /* PIO*/
4212 pm8001_dbg(pm8001_ha, IO, "PIO\n");
4215 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4216 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4219 dir = data_dir_flags[task->data_dir] << 8;
4220 sata_cmd.tag = cpu_to_le32(tag);
4221 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4222 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4223 sata_cmd.ncqtag_atap_dir_m =
4224 cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
4225 sata_cmd.sata_fis = task->ata_task.fis;
4226 if (likely(!task->ata_task.device_control_reg_update))
4227 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4228 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4229 /* fill in PRD (scatter/gather) table, if any */
4230 if (task->num_scatter > 1) {
4231 pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
4232 phys_addr = ccb->ccb_dma_handle;
4233 sata_cmd.addr_low = lower_32_bits(phys_addr);
4234 sata_cmd.addr_high = upper_32_bits(phys_addr);
4235 sata_cmd.esgl = cpu_to_le32(1 << 31);
4236 } else if (task->num_scatter == 1) {
4237 u64 dma_addr = sg_dma_address(task->scatter);
4238 sata_cmd.addr_low = lower_32_bits(dma_addr);
4239 sata_cmd.addr_high = upper_32_bits(dma_addr);
4240 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4242 } else if (task->num_scatter == 0) {
4243 sata_cmd.addr_low = 0;
4244 sata_cmd.addr_high = 0;
4245 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4249 /* Check for read log for failed drive and return */
4250 if (sata_cmd.sata_fis.command == 0x2f) {
4251 if (((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4252 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4253 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4254 struct task_status_struct *ts;
4256 pm8001_ha_dev->id &= 0xDFFFFFFF;
4257 ts = &task->task_status;
4259 spin_lock_irqsave(&task->task_state_lock, flags);
4260 ts->resp = SAS_TASK_COMPLETE;
4261 ts->stat = SAS_SAM_STAT_GOOD;
4262 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4263 task->task_state_flags |= SAS_TASK_STATE_DONE;
4264 if (unlikely((task->task_state_flags &
4265 SAS_TASK_STATE_ABORTED))) {
4266 spin_unlock_irqrestore(&task->task_state_lock,
4268 pm8001_dbg(pm8001_ha, FAIL,
4269 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n",
4272 pm8001_ccb_task_free(pm8001_ha, ccb);
4274 spin_unlock_irqrestore(&task->task_state_lock,
4276 pm8001_ccb_task_free_done(pm8001_ha, ccb);
4282 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd,
4283 sizeof(sata_cmd), 0);
4287 * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
4288 * @pm8001_ha: our hba card information.
4289 * @phy_id: the phy id which we wanted to start up.
4292 pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4294 struct phy_start_req payload;
4296 u32 opcode = OPC_INB_PHYSTART;
4298 memset(&payload, 0, sizeof(payload));
4299 payload.tag = cpu_to_le32(tag);
4301 ** [0:7] PHY Identifier
4302 ** [8:11] link rate 1.5G, 3G, 6G
4303 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
4304 ** [14] 0b disable spin up hold; 1b enable spin up hold
4306 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4307 LINKMODE_AUTO | LINKRATE_15 |
4308 LINKRATE_30 | LINKRATE_60 | phy_id);
4309 payload.sas_identify.dev_type = SAS_END_DEVICE;
4310 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4311 memcpy(payload.sas_identify.sas_addr,
4312 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4313 payload.sas_identify.phy_id = phy_id;
4315 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4316 sizeof(payload), 0);
4320 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4321 * @pm8001_ha: our hba card information.
4322 * @phy_id: the phy id which we wanted to start up.
4324 static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4327 struct phy_stop_req payload;
4329 u32 opcode = OPC_INB_PHYSTOP;
4331 memset(&payload, 0, sizeof(payload));
4332 payload.tag = cpu_to_le32(tag);
4333 payload.phy_id = cpu_to_le32(phy_id);
4335 return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4336 sizeof(payload), 0);
4340 * see comments on pm8001_mpi_reg_resp.
4342 static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4343 struct pm8001_device *pm8001_dev, u32 flag)
4345 struct reg_dev_req payload;
4347 u32 stp_sspsmp_sata = 0x4;
4348 u32 linkrate, phy_id;
4350 struct pm8001_ccb_info *ccb;
4352 u16 firstBurstSize = 0;
4354 struct domain_device *dev = pm8001_dev->sas_device;
4355 struct domain_device *parent_dev = dev->parent;
4356 struct pm8001_port *port = dev->port->lldd_port;
4358 memset(&payload, 0, sizeof(payload));
4359 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL);
4361 return -SAS_QUEUE_FULL;
4363 payload.tag = cpu_to_le32(ccb->ccb_tag);
4365 stp_sspsmp_sata = 0x02; /*direct attached sata */
4367 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4368 stp_sspsmp_sata = 0x00; /* stp*/
4369 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4370 dev_is_expander(pm8001_dev->dev_type))
4371 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4373 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4374 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4376 phy_id = pm8001_dev->attached_phy;
4377 opc = OPC_INB_REG_DEV;
4378 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4379 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4380 payload.phyid_portid =
4381 cpu_to_le32(((port->port_id) & 0x0F) |
4382 ((phy_id & 0x0F) << 4));
4383 payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
4384 ((linkrate & 0x0F) * 0x1000000) |
4385 ((stp_sspsmp_sata & 0x03) * 0x10000000));
4386 payload.firstburstsize_ITNexustimeout =
4387 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4388 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4391 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4392 sizeof(payload), 0);
4394 pm8001_ccb_free(pm8001_ha, ccb);
4400 * see comments on pm8001_mpi_reg_resp.
4402 int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
4405 struct dereg_dev_req payload;
4406 u32 opc = OPC_INB_DEREG_DEV_HANDLE;
4408 memset(&payload, 0, sizeof(payload));
4409 payload.tag = cpu_to_le32(1);
4410 payload.device_id = cpu_to_le32(device_id);
4411 pm8001_dbg(pm8001_ha, MSG, "unregister device device_id = %d\n",
4414 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4415 sizeof(payload), 0);
4419 * pm8001_chip_phy_ctl_req - support the local phy operation
4420 * @pm8001_ha: our hba card information.
4421 * @phyId: the phy id which we wanted to operate
4422 * @phy_op: the phy operation to request
4424 static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4425 u32 phyId, u32 phy_op)
4427 struct local_phy_ctl_req payload;
4428 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4430 memset(&payload, 0, sizeof(payload));
4431 payload.tag = cpu_to_le32(1);
4432 payload.phyop_phyid =
4433 cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
4435 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4436 sizeof(payload), 0);
4439 static u32 pm8001_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4441 #ifdef PM8001_USE_MSIX
4446 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4454 * pm8001_chip_isr - PM8001 isr handler.
4455 * @pm8001_ha: our hba card information.
4459 pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4461 pm8001_chip_interrupt_disable(pm8001_ha, vec);
4462 pm8001_dbg(pm8001_ha, DEVIO,
4463 "irq vec %d, ODMR:0x%x\n",
4464 vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4465 process_oq(pm8001_ha, vec);
4466 pm8001_chip_interrupt_enable(pm8001_ha, vec);
4470 static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
4471 u32 dev_id, enum sas_internal_abort type, u32 task_tag, u32 cmd_tag)
4473 struct task_abort_req task_abort;
4475 memset(&task_abort, 0, sizeof(task_abort));
4476 if (type == SAS_INTERNAL_ABORT_SINGLE) {
4477 task_abort.abort_all = 0;
4478 task_abort.device_id = cpu_to_le32(dev_id);
4479 task_abort.tag_to_abort = cpu_to_le32(task_tag);
4480 } else if (type == SAS_INTERNAL_ABORT_DEV) {
4481 task_abort.abort_all = cpu_to_le32(1);
4482 task_abort.device_id = cpu_to_le32(dev_id);
4484 pm8001_dbg(pm8001_ha, EH, "unknown type (%d)\n", type);
4488 task_abort.tag = cpu_to_le32(cmd_tag);
4490 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort,
4491 sizeof(task_abort), 0);
4495 * pm8001_chip_abort_task - SAS abort task when error or exception happened.
4497 int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
4498 struct pm8001_ccb_info *ccb)
4500 struct sas_task *task = ccb->task;
4501 struct sas_internal_abort_task *abort = &task->abort_task;
4502 struct pm8001_device *pm8001_dev = ccb->device;
4503 int rc = TMF_RESP_FUNC_FAILED;
4506 pm8001_dbg(pm8001_ha, EH, "cmd_tag = %x, abort task tag = 0x%x\n",
4507 ccb->ccb_tag, abort->tag);
4508 if (pm8001_dev->dev_type == SAS_END_DEVICE)
4509 opc = OPC_INB_SSP_ABORT;
4510 else if (pm8001_dev->dev_type == SAS_SATA_DEV)
4511 opc = OPC_INB_SATA_ABORT;
4513 opc = OPC_INB_SMP_ABORT;/* SMP */
4514 device_id = pm8001_dev->device_id;
4515 rc = send_task_abort(pm8001_ha, opc, device_id, abort->type,
4516 abort->tag, ccb->ccb_tag);
4517 if (rc != TMF_RESP_FUNC_COMPLETE)
4518 pm8001_dbg(pm8001_ha, EH, "rc= %d\n", rc);
4523 * pm8001_chip_ssp_tm_req - built the task management command.
4524 * @pm8001_ha: our hba card information.
4525 * @ccb: the ccb information.
4526 * @tmf: task management function.
4528 int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
4529 struct pm8001_ccb_info *ccb, struct sas_tmf_task *tmf)
4531 struct sas_task *task = ccb->task;
4532 struct domain_device *dev = task->dev;
4533 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4534 u32 opc = OPC_INB_SSPINITMSTART;
4535 struct ssp_ini_tm_start_req sspTMCmd;
4537 memset(&sspTMCmd, 0, sizeof(sspTMCmd));
4538 sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4539 sspTMCmd.relate_tag = cpu_to_le32((u32)tmf->tag_of_task_to_be_managed);
4540 sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
4541 memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
4542 sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
4543 if (pm8001_ha->chip_id != chip_8001)
4544 sspTMCmd.ds_ads_m = cpu_to_le32(0x08);
4546 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sspTMCmd,
4547 sizeof(sspTMCmd), 0);
4550 int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4553 u32 opc = OPC_INB_GET_NVMD_DATA;
4556 struct pm8001_ccb_info *ccb;
4557 struct get_nvm_data_req nvmd_req;
4558 struct fw_control_ex *fw_control_context;
4559 struct pm8001_ioctl_payload *ioctl_payload = payload;
4561 nvmd_type = ioctl_payload->minor_function;
4562 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4563 if (!fw_control_context)
4565 fw_control_context->usrAddr = (u8 *)ioctl_payload->func_specific;
4566 fw_control_context->len = ioctl_payload->rd_length;
4567 memset(&nvmd_req, 0, sizeof(nvmd_req));
4569 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4571 kfree(fw_control_context);
4572 return -SAS_QUEUE_FULL;
4574 ccb->fw_control_context = fw_control_context;
4576 nvmd_req.tag = cpu_to_le32(ccb->ccb_tag);
4578 switch (nvmd_type) {
4580 u32 twi_addr, twi_page_size;
4584 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4585 twi_page_size << 8 | TWI_DEVICE);
4586 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4587 nvmd_req.resp_addr_hi =
4588 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4589 nvmd_req.resp_addr_lo =
4590 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4594 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4595 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4596 nvmd_req.resp_addr_hi =
4597 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4598 nvmd_req.resp_addr_lo =
4599 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4603 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4604 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4605 nvmd_req.resp_addr_hi =
4606 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4607 nvmd_req.resp_addr_lo =
4608 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4612 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4613 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4614 nvmd_req.resp_addr_hi =
4615 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4616 nvmd_req.resp_addr_lo =
4617 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4621 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | IOP_RDUMP);
4622 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->rd_length);
4623 nvmd_req.vpd_offset = cpu_to_le32(ioctl_payload->offset);
4624 nvmd_req.resp_addr_hi =
4625 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4626 nvmd_req.resp_addr_lo =
4627 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4634 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &nvmd_req,
4635 sizeof(nvmd_req), 0);
4637 kfree(fw_control_context);
4638 pm8001_ccb_free(pm8001_ha, ccb);
4643 int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
4646 u32 opc = OPC_INB_SET_NVMD_DATA;
4649 struct pm8001_ccb_info *ccb;
4650 struct set_nvm_data_req nvmd_req;
4651 struct fw_control_ex *fw_control_context;
4652 struct pm8001_ioctl_payload *ioctl_payload = payload;
4654 nvmd_type = ioctl_payload->minor_function;
4655 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4656 if (!fw_control_context)
4659 memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
4660 &ioctl_payload->func_specific,
4661 ioctl_payload->wr_length);
4662 memset(&nvmd_req, 0, sizeof(nvmd_req));
4664 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4666 kfree(fw_control_context);
4667 return -SAS_QUEUE_FULL;
4669 ccb->fw_control_context = fw_control_context;
4671 nvmd_req.tag = cpu_to_le32(ccb->ccb_tag);
4672 switch (nvmd_type) {
4674 u32 twi_addr, twi_page_size;
4677 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4678 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
4679 twi_page_size << 8 | TWI_DEVICE);
4680 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4681 nvmd_req.resp_addr_hi =
4682 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4683 nvmd_req.resp_addr_lo =
4684 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4688 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
4689 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4690 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4691 nvmd_req.resp_addr_hi =
4692 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4693 nvmd_req.resp_addr_lo =
4694 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4697 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
4698 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4699 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4700 nvmd_req.resp_addr_hi =
4701 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4702 nvmd_req.resp_addr_lo =
4703 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4706 nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
4707 nvmd_req.resp_len = cpu_to_le32(ioctl_payload->wr_length);
4708 nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
4709 nvmd_req.resp_addr_hi =
4710 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
4711 nvmd_req.resp_addr_lo =
4712 cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
4718 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &nvmd_req,
4719 sizeof(nvmd_req), 0);
4721 kfree(fw_control_context);
4722 pm8001_ccb_free(pm8001_ha, ccb);
4728 * pm8001_chip_fw_flash_update_build - support the firmware update operation
4729 * @pm8001_ha: our hba card information.
4730 * @fw_flash_updata_info: firmware flash update param
4731 * @tag: Tag to apply to the payload
4734 pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
4735 void *fw_flash_updata_info, u32 tag)
4737 struct fw_flash_Update_req payload;
4738 struct fw_flash_updata_info *info;
4739 u32 opc = OPC_INB_FW_FLASH_UPDATE;
4741 memset(&payload, 0, sizeof(struct fw_flash_Update_req));
4742 info = fw_flash_updata_info;
4743 payload.tag = cpu_to_le32(tag);
4744 payload.cur_image_len = cpu_to_le32(info->cur_image_len);
4745 payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
4746 payload.total_image_len = cpu_to_le32(info->total_image_len);
4747 payload.len = info->sgl.im_len.len ;
4748 payload.sgl_addr_lo =
4749 cpu_to_le32(lower_32_bits(le64_to_cpu(info->sgl.addr)));
4750 payload.sgl_addr_hi =
4751 cpu_to_le32(upper_32_bits(le64_to_cpu(info->sgl.addr)));
4753 return pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4754 sizeof(payload), 0);
4758 pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
4761 struct fw_flash_updata_info flash_update_info;
4762 struct fw_control_info *fw_control;
4763 struct fw_control_ex *fw_control_context;
4765 struct pm8001_ccb_info *ccb;
4766 void *buffer = pm8001_ha->memoryMap.region[FW_FLASH].virt_ptr;
4767 dma_addr_t phys_addr = pm8001_ha->memoryMap.region[FW_FLASH].phys_addr;
4768 struct pm8001_ioctl_payload *ioctl_payload = payload;
4770 fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
4771 if (!fw_control_context)
4773 fw_control = (struct fw_control_info *)&ioctl_payload->func_specific;
4774 pm8001_dbg(pm8001_ha, DEVIO,
4775 "dma fw_control context input length :%x\n",
4777 memcpy(buffer, fw_control->buffer, fw_control->len);
4778 flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
4779 flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
4780 flash_update_info.sgl.im_len.e = 0;
4781 flash_update_info.cur_image_offset = fw_control->offset;
4782 flash_update_info.cur_image_len = fw_control->len;
4783 flash_update_info.total_image_len = fw_control->size;
4784 fw_control_context->fw_control = fw_control;
4785 fw_control_context->virtAddr = buffer;
4786 fw_control_context->phys_addr = phys_addr;
4787 fw_control_context->len = fw_control->len;
4789 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4791 kfree(fw_control_context);
4792 return -SAS_QUEUE_FULL;
4794 ccb->fw_control_context = fw_control_context;
4796 rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
4799 kfree(fw_control_context);
4800 pm8001_ccb_free(pm8001_ha, ccb);
4807 pm8001_get_gsm_dump(struct device *cdev, u32 length, char *buf)
4809 u32 value, rem, offset = 0, bar = 0;
4810 u32 index, work_offset, dw_length;
4811 u32 shift_value, gsm_base, gsm_dump_offset;
4813 struct Scsi_Host *shost = class_to_shost(cdev);
4814 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
4815 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
4818 gsm_dump_offset = pm8001_ha->fatal_forensic_shift_offset;
4820 /* check max is 1 Mbytes */
4821 if ((length > 0x100000) || (gsm_dump_offset & 3) ||
4822 ((gsm_dump_offset + length) > 0x1000000))
4825 if (pm8001_ha->chip_id == chip_8001)
4830 work_offset = gsm_dump_offset & 0xFFFF0000;
4831 offset = gsm_dump_offset & 0x0000FFFF;
4832 gsm_dump_offset = work_offset;
4833 /* adjust length to dword boundary */
4835 dw_length = length >> 2;
4837 for (index = 0; index < dw_length; index++) {
4838 if ((work_offset + offset) & 0xFFFF0000) {
4839 if (pm8001_ha->chip_id == chip_8001)
4840 shift_value = ((gsm_dump_offset + offset) &
4841 SHIFT_REG_64K_MASK);
4843 shift_value = (((gsm_dump_offset + offset) &
4844 SHIFT_REG_64K_MASK) >>
4845 SHIFT_REG_BIT_SHIFT);
4847 if (pm8001_ha->chip_id == chip_8001) {
4848 gsm_base = GSM_BASE;
4849 if (-1 == pm8001_bar4_shift(pm8001_ha,
4850 (gsm_base + shift_value)))
4854 if (-1 == pm80xx_bar4_shift(pm8001_ha,
4855 (gsm_base + shift_value)))
4858 gsm_dump_offset = (gsm_dump_offset + offset) &
4861 offset = offset & 0x0000FFFF;
4863 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4865 direct_data += sprintf(direct_data, "%08x ", value);
4869 value = pm8001_cr32(pm8001_ha, bar, (work_offset + offset) &
4871 /* xfr for non_dw */
4872 direct_data += sprintf(direct_data, "%08x ", value);
4874 /* Shift back to BAR4 original address */
4875 if (-1 == pm8001_bar4_shift(pm8001_ha, 0))
4877 pm8001_ha->fatal_forensic_shift_offset += 1024;
4879 if (pm8001_ha->fatal_forensic_shift_offset >= 0x100000)
4880 pm8001_ha->fatal_forensic_shift_offset = 0;
4881 return direct_data - buf;
4885 pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
4886 struct pm8001_device *pm8001_dev, u32 state)
4888 struct set_dev_state_req payload;
4889 struct pm8001_ccb_info *ccb;
4891 u32 opc = OPC_INB_SET_DEVICE_STATE;
4893 memset(&payload, 0, sizeof(payload));
4895 ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL);
4897 return -SAS_QUEUE_FULL;
4899 payload.tag = cpu_to_le32(ccb->ccb_tag);
4900 payload.device_id = cpu_to_le32(pm8001_dev->device_id);
4901 payload.nds = cpu_to_le32(state);
4903 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4904 sizeof(payload), 0);
4906 pm8001_ccb_free(pm8001_ha, ccb);
4912 pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
4914 struct sas_re_initialization_req payload;
4915 struct pm8001_ccb_info *ccb;
4917 u32 opc = OPC_INB_SAS_RE_INITIALIZE;
4919 memset(&payload, 0, sizeof(payload));
4921 ccb = pm8001_ccb_alloc(pm8001_ha, NULL, NULL);
4923 return -SAS_QUEUE_FULL;
4925 payload.tag = cpu_to_le32(ccb->ccb_tag);
4926 payload.SSAHOLT = cpu_to_le32(0xd << 25);
4927 payload.sata_hol_tmo = cpu_to_le32(80);
4928 payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
4930 rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4931 sizeof(payload), 0);
4933 pm8001_ccb_free(pm8001_ha, ccb);
4938 const struct pm8001_dispatch pm8001_8001_dispatch = {
4940 .chip_init = pm8001_chip_init,
4941 .chip_post_init = pm8001_chip_post_init,
4942 .chip_soft_rst = pm8001_chip_soft_rst,
4943 .chip_rst = pm8001_hw_chip_rst,
4944 .chip_iounmap = pm8001_chip_iounmap,
4945 .isr = pm8001_chip_isr,
4946 .is_our_interrupt = pm8001_chip_is_our_interrupt,
4947 .isr_process_oq = process_oq,
4948 .interrupt_enable = pm8001_chip_interrupt_enable,
4949 .interrupt_disable = pm8001_chip_interrupt_disable,
4950 .make_prd = pm8001_chip_make_sg,
4951 .smp_req = pm8001_chip_smp_req,
4952 .ssp_io_req = pm8001_chip_ssp_io_req,
4953 .sata_req = pm8001_chip_sata_req,
4954 .phy_start_req = pm8001_chip_phy_start_req,
4955 .phy_stop_req = pm8001_chip_phy_stop_req,
4956 .reg_dev_req = pm8001_chip_reg_dev_req,
4957 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4958 .phy_ctl_req = pm8001_chip_phy_ctl_req,
4959 .task_abort = pm8001_chip_abort_task,
4960 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4961 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4962 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4963 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4964 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4965 .sas_re_init_req = pm8001_chip_sas_re_initialization,
4966 .fatal_errors = pm80xx_fatal_errors,