drivers/scsi/mpi3mr/mpi3mr_fw.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for Broadcom MPI3 Storage Controllers
   4  *
   5  * Copyright (C) 2017-2023 Broadcom Inc.
   6  *  (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
   7  *
   8  */
   9
  10 #include "mpi3mr.h"
  11 #include <linux/io-64-nonatomic-lo-hi.h>
  12
  13 static int
  14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason);
  15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
  16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
  17         struct mpi3_ioc_facts_data *facts_data);
  18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
  19         struct mpi3mr_drv_cmd *drv_cmd);
  20
  21 static int poll_queues;
  22 module_param(poll_queues, int, 0444);
  23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
  24
  25 #if defined(writeq) && defined(CONFIG_64BIT)
  26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
  27 {
  28         writeq(b, addr);
  29 }
  30 #else
  31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
  32 {
  33         __u64 data_out = b;
  34
  35         writel((u32)(data_out), addr);
  36         writel((u32)(data_out >> 32), (addr + 4));
  37 }
  38 #endif
  39
  40 static inline bool
  41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
  42 {
  43         u16 pi, ci, max_entries;
  44         bool is_qfull = false;
  45
  46         pi = op_req_q->pi;
  47         ci = READ_ONCE(op_req_q->ci);
  48         max_entries = op_req_q->num_requests;
  49
  50         if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
  51                 is_qfull = true;
  52
  53         return is_qfull;
  54 }
  55
  56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
  57 {
  58         u16 i, max_vectors;
  59
  60         max_vectors = mrioc->intr_info_count;
  61
  62         for (i = 0; i < max_vectors; i++)
  63                 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
  64 }
  65
  66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
  67 {
  68         mrioc->intr_enabled = 0;
  69         mpi3mr_sync_irqs(mrioc);
  70 }
  71
  72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
  73 {
  74         mrioc->intr_enabled = 1;
  75 }
  76
  77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
  78 {
  79         u16 i;
  80
  81         mpi3mr_ioc_disable_intr(mrioc);
  82
  83         if (!mrioc->intr_info)
  84                 return;
  85
  86         for (i = 0; i < mrioc->intr_info_count; i++)
  87                 free_irq(pci_irq_vector(mrioc->pdev, i),
  88                     (mrioc->intr_info + i));
  89
  90         kfree(mrioc->intr_info);
  91         mrioc->intr_info = NULL;
  92         mrioc->intr_info_count = 0;
  93         mrioc->is_intr_info_set = false;
  94         pci_free_irq_vectors(mrioc->pdev);
  95 }
  96
  97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
  98         dma_addr_t dma_addr)
  99 {
 100         struct mpi3_sge_common *sgel = paddr;
 101
 102         sgel->flags = flags;
 103         sgel->length = cpu_to_le32(length);
 104         sgel->address = cpu_to_le64(dma_addr);
 105 }
 106
 107 void mpi3mr_build_zero_len_sge(void *paddr)
 108 {
 109         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
 110
 111         mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
 112 }
 113
 114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
 115         dma_addr_t phys_addr)
 116 {
 117         if (!phys_addr)
 118                 return NULL;
 119
 120         if ((phys_addr < mrioc->reply_buf_dma) ||
 121             (phys_addr > mrioc->reply_buf_dma_max_address))
 122                 return NULL;
 123
 124         return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
 125 }
 126
 127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
 128         dma_addr_t phys_addr)
 129 {
 130         if (!phys_addr)
 131                 return NULL;
 132
 133         return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
 134 }
 135
 136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
 137         u64 reply_dma)
 138 {
 139         u32 old_idx = 0;
 140         unsigned long flags;
 141
 142         spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
 143         old_idx  =  mrioc->reply_free_queue_host_index;
 144         mrioc->reply_free_queue_host_index = (
 145             (mrioc->reply_free_queue_host_index ==
 146             (mrioc->reply_free_qsz - 1)) ? 0 :
 147             (mrioc->reply_free_queue_host_index + 1));
 148         mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
 149         writel(mrioc->reply_free_queue_host_index,
 150             &mrioc->sysif_regs->reply_free_host_index);
 151         spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
 152 }
 153
 154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
 155         u64 sense_buf_dma)
 156 {
 157         u32 old_idx = 0;
 158         unsigned long flags;
 159
 160         spin_lock_irqsave(&mrioc->sbq_lock, flags);
 161         old_idx  =  mrioc->sbq_host_index;
 162         mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
 163             (mrioc->sense_buf_q_sz - 1)) ? 0 :
 164             (mrioc->sbq_host_index + 1));
 165         mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
 166         writel(mrioc->sbq_host_index,
 167             &mrioc->sysif_regs->sense_buffer_free_host_index);
 168         spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
 169 }
 170
 171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
 172         struct mpi3_event_notification_reply *event_reply)
 173 {
 174         char *desc = NULL;
 175         u16 event;
 176
 177         event = event_reply->event;
 178
 179         switch (event) {
 180         case MPI3_EVENT_LOG_DATA:
 181                 desc = "Log Data";
 182                 break;
 183         case MPI3_EVENT_CHANGE:
 184                 desc = "Event Change";
 185                 break;
 186         case MPI3_EVENT_GPIO_INTERRUPT:
 187                 desc = "GPIO Interrupt";
 188                 break;
 189         case MPI3_EVENT_CABLE_MGMT:
 190                 desc = "Cable Management";
 191                 break;
 192         case MPI3_EVENT_ENERGY_PACK_CHANGE:
 193                 desc = "Energy Pack Change";
 194                 break;
 195         case MPI3_EVENT_DEVICE_ADDED:
 196         {
 197                 struct mpi3_device_page0 *event_data =
 198                     (struct mpi3_device_page0 *)event_reply->event_data;
 199                 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
 200                     event_data->dev_handle, event_data->device_form);
 201                 return;
 202         }
 203         case MPI3_EVENT_DEVICE_INFO_CHANGED:
 204         {
 205                 struct mpi3_device_page0 *event_data =
 206                     (struct mpi3_device_page0 *)event_reply->event_data;
 207                 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
 208                     event_data->dev_handle, event_data->device_form);
 209                 return;
 210         }
 211         case MPI3_EVENT_DEVICE_STATUS_CHANGE:
 212         {
 213                 struct mpi3_event_data_device_status_change *event_data =
 214                     (struct mpi3_event_data_device_status_change *)event_reply->event_data;
 215                 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
 216                     event_data->dev_handle, event_data->reason_code);
 217                 return;
 218         }
 219         case MPI3_EVENT_SAS_DISCOVERY:
 220         {
 221                 struct mpi3_event_data_sas_discovery *event_data =
 222                     (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
 223                 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
 224                     (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
 225                     "start" : "stop",
 226                     le32_to_cpu(event_data->discovery_status));
 227                 return;
 228         }
 229         case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
 230                 desc = "SAS Broadcast Primitive";
 231                 break;
 232         case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
 233                 desc = "SAS Notify Primitive";
 234                 break;
 235         case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
 236                 desc = "SAS Init Device Status Change";
 237                 break;
 238         case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
 239                 desc = "SAS Init Table Overflow";
 240                 break;
 241         case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
 242                 desc = "SAS Topology Change List";
 243                 break;
 244         case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
 245                 desc = "Enclosure Device Status Change";
 246                 break;
 247         case MPI3_EVENT_ENCL_DEVICE_ADDED:
 248                 desc = "Enclosure Added";
 249                 break;
 250         case MPI3_EVENT_HARD_RESET_RECEIVED:
 251                 desc = "Hard Reset Received";
 252                 break;
 253         case MPI3_EVENT_SAS_PHY_COUNTER:
 254                 desc = "SAS PHY Counter";
 255                 break;
 256         case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
 257                 desc = "SAS Device Discovery Error";
 258                 break;
 259         case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
 260                 desc = "PCIE Topology Change List";
 261                 break;
 262         case MPI3_EVENT_PCIE_ENUMERATION:
 263         {
 264                 struct mpi3_event_data_pcie_enumeration *event_data =
 265                     (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
 266                 ioc_info(mrioc, "PCIE Enumeration: (%s)",
 267                     (event_data->reason_code ==
 268                     MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
 269                 if (event_data->enumeration_status)
 270                         ioc_info(mrioc, "enumeration_status(0x%08x)\n",
 271                             le32_to_cpu(event_data->enumeration_status));
 272                 return;
 273         }
 274         case MPI3_EVENT_PREPARE_FOR_RESET:
 275                 desc = "Prepare For Reset";
 276                 break;
 277         }
 278
 279         if (!desc)
 280                 return;
 281
 282         ioc_info(mrioc, "%s\n", desc);
 283 }
 284
 285 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
 286         struct mpi3_default_reply *def_reply)
 287 {
 288         struct mpi3_event_notification_reply *event_reply =
 289             (struct mpi3_event_notification_reply *)def_reply;
 290
 291         mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
 292         mpi3mr_print_event_data(mrioc, event_reply);
 293         mpi3mr_os_handle_events(mrioc, event_reply);
 294 }
 295
 296 static struct mpi3mr_drv_cmd *
 297 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
 298         struct mpi3_default_reply *def_reply)
 299 {
 300         u16 idx;
 301
 302         switch (host_tag) {
 303         case MPI3MR_HOSTTAG_INITCMDS:
 304                 return &mrioc->init_cmds;
 305         case MPI3MR_HOSTTAG_CFG_CMDS:
 306                 return &mrioc->cfg_cmds;
 307         case MPI3MR_HOSTTAG_BSG_CMDS:
 308                 return &mrioc->bsg_cmds;
 309         case MPI3MR_HOSTTAG_BLK_TMS:
 310                 return &mrioc->host_tm_cmds;
 311         case MPI3MR_HOSTTAG_PEL_ABORT:
 312                 return &mrioc->pel_abort_cmd;
 313         case MPI3MR_HOSTTAG_PEL_WAIT:
 314                 return &mrioc->pel_cmds;
 315         case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
 316                 return &mrioc->transport_cmds;
 317         case MPI3MR_HOSTTAG_INVALID:
 318                 if (def_reply && def_reply->function ==
 319                     MPI3_FUNCTION_EVENT_NOTIFICATION)
 320                         mpi3mr_handle_events(mrioc, def_reply);
 321                 return NULL;
 322         default:
 323                 break;
 324         }
 325         if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
 326             host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
 327                 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
 328                 return &mrioc->dev_rmhs_cmds[idx];
 329         }
 330
 331         if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
 332             host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
 333                 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
 334                 return &mrioc->evtack_cmds[idx];
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
 341         struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
 342 {
 343         u16 reply_desc_type, host_tag = 0;
 344         u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
 345         u32 ioc_loginfo = 0;
 346         struct mpi3_status_reply_descriptor *status_desc;
 347         struct mpi3_address_reply_descriptor *addr_desc;
 348         struct mpi3_success_reply_descriptor *success_desc;
 349         struct mpi3_default_reply *def_reply = NULL;
 350         struct mpi3mr_drv_cmd *cmdptr = NULL;
 351         struct mpi3_scsi_io_reply *scsi_reply;
 352         u8 *sense_buf = NULL;
 353
 354         *reply_dma = 0;
 355         reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
 356             MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
 357         switch (reply_desc_type) {
 358         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
 359                 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
 360                 host_tag = le16_to_cpu(status_desc->host_tag);
 361                 ioc_status = le16_to_cpu(status_desc->ioc_status);
 362                 if (ioc_status &
 363                     MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
 364                         ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
 365                 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
 366                 break;
 367         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
 368                 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
 369                 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
 370                 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
 371                 if (!def_reply)
 372                         goto out;
 373                 host_tag = le16_to_cpu(def_reply->host_tag);
 374                 ioc_status = le16_to_cpu(def_reply->ioc_status);
 375                 if (ioc_status &
 376                     MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
 377                         ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
 378                 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
 379                 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
 380                         scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
 381                         sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
 382                             le64_to_cpu(scsi_reply->sense_data_buffer_address));
 383                 }
 384                 break;
 385         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
 386                 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
 387                 host_tag = le16_to_cpu(success_desc->host_tag);
 388                 break;
 389         default:
 390                 break;
 391         }
 392
 393         cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
 394         if (cmdptr) {
 395                 if (cmdptr->state & MPI3MR_CMD_PENDING) {
 396                         cmdptr->state |= MPI3MR_CMD_COMPLETE;
 397                         cmdptr->ioc_loginfo = ioc_loginfo;
 398                         cmdptr->ioc_status = ioc_status;
 399                         cmdptr->state &= ~MPI3MR_CMD_PENDING;
 400                         if (def_reply) {
 401                                 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
 402                                 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
 403                                     mrioc->reply_sz);
 404                         }
 405                         if (cmdptr->is_waiting) {
 406                                 complete(&cmdptr->done);
 407                                 cmdptr->is_waiting = 0;
 408                         } else if (cmdptr->callback)
 409                                 cmdptr->callback(mrioc, cmdptr);
 410                 }
 411         }
 412 out:
 413         if (sense_buf)
 414                 mpi3mr_repost_sense_buf(mrioc,
 415                     le64_to_cpu(scsi_reply->sense_data_buffer_address));
 416 }
 417
 418 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
 419 {
 420         u32 exp_phase = mrioc->admin_reply_ephase;
 421         u32 admin_reply_ci = mrioc->admin_reply_ci;
 422         u32 num_admin_replies = 0;
 423         u64 reply_dma = 0;
 424         struct mpi3_default_reply_descriptor *reply_desc;
 425
 426         if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1))
 427                 return 0;
 428
 429         reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
 430             admin_reply_ci;
 431
 432         if ((le16_to_cpu(reply_desc->reply_flags) &
 433             MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
 434                 atomic_dec(&mrioc->admin_reply_q_in_use);
 435                 return 0;
 436         }
 437
 438         do {
 439                 if (mrioc->unrecoverable)
 440                         break;
 441
 442                 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
 443                 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
 444                 if (reply_dma)
 445                         mpi3mr_repost_reply_buf(mrioc, reply_dma);
 446                 num_admin_replies++;
 447                 if (++admin_reply_ci == mrioc->num_admin_replies) {
 448                         admin_reply_ci = 0;
 449                         exp_phase ^= 1;
 450                 }
 451                 reply_desc =
 452                     (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
 453                     admin_reply_ci;
 454                 if ((le16_to_cpu(reply_desc->reply_flags) &
 455                     MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 456                         break;
 457         } while (1);
 458
 459         writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
 460         mrioc->admin_reply_ci = admin_reply_ci;
 461         mrioc->admin_reply_ephase = exp_phase;
 462         atomic_dec(&mrioc->admin_reply_q_in_use);
 463
 464         return num_admin_replies;
 465 }
 466
 467 /**
 468  * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
 469  *      queue's consumer index from operational reply descriptor queue.
 470  * @op_reply_q: op_reply_qinfo object
 471  * @reply_ci: operational reply descriptor's queue consumer index
 472  *
 473  * Returns reply descriptor frame address
 474  */
 475 static inline struct mpi3_default_reply_descriptor *
 476 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
 477 {
 478         void *segment_base_addr;
 479         struct segments *segments = op_reply_q->q_segments;
 480         struct mpi3_default_reply_descriptor *reply_desc = NULL;
 481
 482         segment_base_addr =
 483             segments[reply_ci / op_reply_q->segment_qd].segment;
 484         reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
 485             (reply_ci % op_reply_q->segment_qd);
 486         return reply_desc;
 487 }
 488
 489 /**
 490  * mpi3mr_process_op_reply_q - Operational reply queue handler
 491  * @mrioc: Adapter instance reference
 492  * @op_reply_q: Operational reply queue info
 493  *
 494  * Checks the specific operational reply queue and drains the
 495  * reply queue entries until the queue is empty and process the
 496  * individual reply descriptors.
 497  *
 498  * Return: 0 if queue is already processed,or number of reply
 499  *          descriptors processed.
 500  */
 501 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
 502         struct op_reply_qinfo *op_reply_q)
 503 {
 504         struct op_req_qinfo *op_req_q;
 505         u32 exp_phase;
 506         u32 reply_ci;
 507         u32 num_op_reply = 0;
 508         u64 reply_dma = 0;
 509         struct mpi3_default_reply_descriptor *reply_desc;
 510         u16 req_q_idx = 0, reply_qidx;
 511
 512         reply_qidx = op_reply_q->qid - 1;
 513
 514         if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
 515                 return 0;
 516
 517         exp_phase = op_reply_q->ephase;
 518         reply_ci = op_reply_q->ci;
 519
 520         reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
 521         if ((le16_to_cpu(reply_desc->reply_flags) &
 522             MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
 523                 atomic_dec(&op_reply_q->in_use);
 524                 return 0;
 525         }
 526
 527         do {
 528                 if (mrioc->unrecoverable)
 529                         break;
 530
 531                 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
 532                 op_req_q = &mrioc->req_qinfo[req_q_idx];
 533
 534                 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
 535                 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
 536                     reply_qidx);
 537                 atomic_dec(&op_reply_q->pend_ios);
 538                 if (reply_dma)
 539                         mpi3mr_repost_reply_buf(mrioc, reply_dma);
 540                 num_op_reply++;
 541
 542                 if (++reply_ci == op_reply_q->num_replies) {
 543                         reply_ci = 0;
 544                         exp_phase ^= 1;
 545                 }
 546
 547                 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
 548
 549                 if ((le16_to_cpu(reply_desc->reply_flags) &
 550                     MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 551                         break;
 552 #ifndef CONFIG_PREEMPT_RT
 553                 /*
 554                  * Exit completion loop to avoid CPU lockup
 555                  * Ensure remaining completion happens from threaded ISR.
 556                  */
 557                 if (num_op_reply > mrioc->max_host_ios) {
 558                         op_reply_q->enable_irq_poll = true;
 559                         break;
 560                 }
 561 #endif
 562         } while (1);
 563
 564         writel(reply_ci,
 565             &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
 566         op_reply_q->ci = reply_ci;
 567         op_reply_q->ephase = exp_phase;
 568
 569         atomic_dec(&op_reply_q->in_use);
 570         return num_op_reply;
 571 }
 572
 573 /**
 574  * mpi3mr_blk_mq_poll - Operational reply queue handler
 575  * @shost: SCSI Host reference
 576  * @queue_num: Request queue number (w.r.t OS it is hardware context number)
 577  *
 578  * Checks the specific operational reply queue and drains the
 579  * reply queue entries until the queue is empty and process the
 580  * individual reply descriptors.
 581  *
 582  * Return: 0 if queue is already processed,or number of reply
 583  *          descriptors processed.
 584  */
 585 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
 586 {
 587         int num_entries = 0;
 588         struct mpi3mr_ioc *mrioc;
 589
 590         mrioc = (struct mpi3mr_ioc *)shost->hostdata;
 591
 592         if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
 593             mrioc->unrecoverable))
 594                 return 0;
 595
 596         num_entries = mpi3mr_process_op_reply_q(mrioc,
 597                         &mrioc->op_reply_qinfo[queue_num]);
 598
 599         return num_entries;
 600 }
 601
 602 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
 603 {
 604         struct mpi3mr_intr_info *intr_info = privdata;
 605         struct mpi3mr_ioc *mrioc;
 606         u16 midx;
 607         u32 num_admin_replies = 0, num_op_reply = 0;
 608
 609         if (!intr_info)
 610                 return IRQ_NONE;
 611
 612         mrioc = intr_info->mrioc;
 613
 614         if (!mrioc->intr_enabled)
 615                 return IRQ_NONE;
 616
 617         midx = intr_info->msix_index;
 618
 619         if (!midx)
 620                 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
 621         if (intr_info->op_reply_q)
 622                 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
 623                     intr_info->op_reply_q);
 624
 625         if (num_admin_replies || num_op_reply)
 626                 return IRQ_HANDLED;
 627         else
 628                 return IRQ_NONE;
 629 }
 630
 631 #ifndef CONFIG_PREEMPT_RT
 632
 633 static irqreturn_t mpi3mr_isr(int irq, void *privdata)
 634 {
 635         struct mpi3mr_intr_info *intr_info = privdata;
 636         int ret;
 637
 638         if (!intr_info)
 639                 return IRQ_NONE;
 640
 641         /* Call primary ISR routine */
 642         ret = mpi3mr_isr_primary(irq, privdata);
 643
 644         /*
 645          * If more IOs are expected, schedule IRQ polling thread.
 646          * Otherwise exit from ISR.
 647          */
 648         if (!intr_info->op_reply_q)
 649                 return ret;
 650
 651         if (!intr_info->op_reply_q->enable_irq_poll ||
 652             !atomic_read(&intr_info->op_reply_q->pend_ios))
 653                 return ret;
 654
 655         disable_irq_nosync(intr_info->os_irq);
 656
 657         return IRQ_WAKE_THREAD;
 658 }
 659
 660 /**
 661  * mpi3mr_isr_poll - Reply queue polling routine
 662  * @irq: IRQ
 663  * @privdata: Interrupt info
 664  *
 665  * poll for pending I/O completions in a loop until pending I/Os
 666  * present or controller queue depth I/Os are processed.
 667  *
 668  * Return: IRQ_NONE or IRQ_HANDLED
 669  */
 670 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
 671 {
 672         struct mpi3mr_intr_info *intr_info = privdata;
 673         struct mpi3mr_ioc *mrioc;
 674         u16 midx;
 675         u32 num_op_reply = 0;
 676
 677         if (!intr_info || !intr_info->op_reply_q)
 678                 return IRQ_NONE;
 679
 680         mrioc = intr_info->mrioc;
 681         midx = intr_info->msix_index;
 682
 683         /* Poll for pending IOs completions */
 684         do {
 685                 if (!mrioc->intr_enabled || mrioc->unrecoverable)
 686                         break;
 687
 688                 if (!midx)
 689                         mpi3mr_process_admin_reply_q(mrioc);
 690                 if (intr_info->op_reply_q)
 691                         num_op_reply +=
 692                             mpi3mr_process_op_reply_q(mrioc,
 693                                 intr_info->op_reply_q);
 694
 695                 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP);
 696
 697         } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
 698             (num_op_reply < mrioc->max_host_ios));
 699
 700         intr_info->op_reply_q->enable_irq_poll = false;
 701         enable_irq(intr_info->os_irq);
 702
 703         return IRQ_HANDLED;
 704 }
 705
 706 #endif
 707
 708 /**
 709  * mpi3mr_request_irq - Request IRQ and register ISR
 710  * @mrioc: Adapter instance reference
 711  * @index: IRQ vector index
 712  *
 713  * Request threaded ISR with primary ISR and secondary
 714  *
 715  * Return: 0 on success and non zero on failures.
 716  */
 717 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
 718 {
 719         struct pci_dev *pdev = mrioc->pdev;
 720         struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
 721         int retval = 0;
 722
 723         intr_info->mrioc = mrioc;
 724         intr_info->msix_index = index;
 725         intr_info->op_reply_q = NULL;
 726
 727         snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
 728             mrioc->driver_name, mrioc->id, index);
 729
 730 #ifndef CONFIG_PREEMPT_RT
 731         retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
 732             mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
 733 #else
 734         retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
 735             NULL, IRQF_SHARED, intr_info->name, intr_info);
 736 #endif
 737         if (retval) {
 738                 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
 739                     intr_info->name, pci_irq_vector(pdev, index));
 740                 return retval;
 741         }
 742
 743         intr_info->os_irq = pci_irq_vector(pdev, index);
 744         return retval;
 745 }
 746
 747 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
 748 {
 749         if (!mrioc->requested_poll_qcount)
 750                 return;
 751
 752         /* Reserved for Admin and Default Queue */
 753         if (max_vectors > 2 &&
 754                 (mrioc->requested_poll_qcount < max_vectors - 2)) {
 755                 ioc_info(mrioc,
 756                     "enabled polled queues (%d) msix (%d)\n",
 757                     mrioc->requested_poll_qcount, max_vectors);
 758         } else {
 759                 ioc_info(mrioc,
 760                     "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
 761                     mrioc->requested_poll_qcount, max_vectors);
 762                 mrioc->requested_poll_qcount = 0;
 763         }
 764 }
 765
 766 /**
 767  * mpi3mr_setup_isr - Setup ISR for the controller
 768  * @mrioc: Adapter instance reference
 769  * @setup_one: Request one IRQ or more
 770  *
 771  * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
 772  *
 773  * Return: 0 on success and non zero on failures.
 774  */
 775 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
 776 {
 777         unsigned int irq_flags = PCI_IRQ_MSIX;
 778         int max_vectors, min_vec;
 779         int retval;
 780         int i;
 781         struct irq_affinity desc = { .pre_vectors =  1, .post_vectors = 1 };
 782
 783         if (mrioc->is_intr_info_set)
 784                 return 0;
 785
 786         mpi3mr_cleanup_isr(mrioc);
 787
 788         if (setup_one || reset_devices) {
 789                 max_vectors = 1;
 790                 retval = pci_alloc_irq_vectors(mrioc->pdev,
 791                     1, max_vectors, irq_flags);
 792                 if (retval < 0) {
 793                         ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
 794                             retval);
 795                         goto out_failed;
 796                 }
 797         } else {
 798                 max_vectors =
 799                     min_t(int, mrioc->cpu_count + 1 +
 800                         mrioc->requested_poll_qcount, mrioc->msix_count);
 801
 802                 mpi3mr_calc_poll_queues(mrioc, max_vectors);
 803
 804                 ioc_info(mrioc,
 805                     "MSI-X vectors supported: %d, no of cores: %d,",
 806                     mrioc->msix_count, mrioc->cpu_count);
 807                 ioc_info(mrioc,
 808                     "MSI-x vectors requested: %d poll_queues %d\n",
 809                     max_vectors, mrioc->requested_poll_qcount);
 810
 811                 desc.post_vectors = mrioc->requested_poll_qcount;
 812                 min_vec = desc.pre_vectors + desc.post_vectors;
 813                 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
 814
 815                 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
 816                         min_vec, max_vectors, irq_flags, &desc);
 817
 818                 if (retval < 0) {
 819                         ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
 820                             retval);
 821                         goto out_failed;
 822                 }
 823
 824
 825                 /*
 826                  * If only one MSI-x is allocated, then MSI-x 0 will be shared
 827                  * between Admin queue and operational queue
 828                  */
 829                 if (retval == min_vec)
 830                         mrioc->op_reply_q_offset = 0;
 831                 else if (retval != (max_vectors)) {
 832                         ioc_info(mrioc,
 833                             "allocated vectors (%d) are less than configured (%d)\n",
 834                             retval, max_vectors);
 835                 }
 836
 837                 max_vectors = retval;
 838                 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
 839
 840                 mpi3mr_calc_poll_queues(mrioc, max_vectors);
 841
 842         }
 843
 844         mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
 845             GFP_KERNEL);
 846         if (!mrioc->intr_info) {
 847                 retval = -ENOMEM;
 848                 pci_free_irq_vectors(mrioc->pdev);
 849                 goto out_failed;
 850         }
 851         for (i = 0; i < max_vectors; i++) {
 852                 retval = mpi3mr_request_irq(mrioc, i);
 853                 if (retval) {
 854                         mrioc->intr_info_count = i;
 855                         goto out_failed;
 856                 }
 857         }
 858         if (reset_devices || !setup_one)
 859                 mrioc->is_intr_info_set = true;
 860         mrioc->intr_info_count = max_vectors;
 861         mpi3mr_ioc_enable_intr(mrioc);
 862         return 0;
 863
 864 out_failed:
 865         mpi3mr_cleanup_isr(mrioc);
 866
 867         return retval;
 868 }
 869
 870 static const struct {
 871         enum mpi3mr_iocstate value;
 872         char *name;
 873 } mrioc_states[] = {
 874         { MRIOC_STATE_READY, "ready" },
 875         { MRIOC_STATE_FAULT, "fault" },
 876         { MRIOC_STATE_RESET, "reset" },
 877         { MRIOC_STATE_BECOMING_READY, "becoming ready" },
 878         { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
 879         { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
 880 };
 881
 882 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
 883 {
 884         int i;
 885         char *name = NULL;
 886
 887         for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
 888                 if (mrioc_states[i].value == mrioc_state) {
 889                         name = mrioc_states[i].name;
 890                         break;
 891                 }
 892         }
 893         return name;
 894 }
 895
 896 /* Reset reason to name mapper structure*/
 897 static const struct {
 898         enum mpi3mr_reset_reason value;
 899         char *name;
 900 } mpi3mr_reset_reason_codes[] = {
 901         { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
 902         { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
 903         { MPI3MR_RESET_FROM_APP, "application invocation" },
 904         { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
 905         { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
 906         { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
 907         { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
 908         { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
 909         { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
 910         { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
 911         { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
 912         { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
 913         { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
 914         {
 915                 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
 916                 "create request queue timeout"
 917         },
 918         {
 919                 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
 920                 "create reply queue timeout"
 921         },
 922         { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
 923         { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
 924         { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
 925         { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
 926         {
 927                 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
 928                 "component image activation timeout"
 929         },
 930         {
 931                 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
 932                 "get package version timeout"
 933         },
 934         { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
 935         { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
 936         { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
 937         { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
 938         { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
 939 };
 940
 941 /**
 942  * mpi3mr_reset_rc_name - get reset reason code name
 943  * @reason_code: reset reason code value
 944  *
 945  * Map reset reason to an NULL terminated ASCII string
 946  *
 947  * Return: name corresponding to reset reason value or NULL.
 948  */
 949 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
 950 {
 951         int i;
 952         char *name = NULL;
 953
 954         for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
 955                 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
 956                         name = mpi3mr_reset_reason_codes[i].name;
 957                         break;
 958                 }
 959         }
 960         return name;
 961 }
 962
 963 /* Reset type to name mapper structure*/
 964 static const struct {
 965         u16 reset_type;
 966         char *name;
 967 } mpi3mr_reset_types[] = {
 968         { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
 969         { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
 970 };
 971
 972 /**
 973  * mpi3mr_reset_type_name - get reset type name
 974  * @reset_type: reset type value
 975  *
 976  * Map reset type to an NULL terminated ASCII string
 977  *
 978  * Return: name corresponding to reset type value or NULL.
 979  */
 980 static const char *mpi3mr_reset_type_name(u16 reset_type)
 981 {
 982         int i;
 983         char *name = NULL;
 984
 985         for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
 986                 if (mpi3mr_reset_types[i].reset_type == reset_type) {
 987                         name = mpi3mr_reset_types[i].name;
 988                         break;
 989                 }
 990         }
 991         return name;
 992 }
 993
 994 /**
 995  * mpi3mr_print_fault_info - Display fault information
 996  * @mrioc: Adapter instance reference
 997  *
 998  * Display the controller fault information if there is a
 999  * controller fault.
1000  *
1001  * Return: Nothing.
1002  */
1003 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1004 {
1005         u32 ioc_status, code, code1, code2, code3;
1006
1007         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1008
1009         if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1010                 code = readl(&mrioc->sysif_regs->fault);
1011                 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1012                 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1013                 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1014
1015                 ioc_info(mrioc,
1016                     "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1017                     code, code1, code2, code3);
1018         }
1019 }
1020
1021 /**
1022  * mpi3mr_get_iocstate - Get IOC State
1023  * @mrioc: Adapter instance reference
1024  *
1025  * Return a proper IOC state enum based on the IOC status and
1026  * IOC configuration and unrcoverable state of the controller.
1027  *
1028  * Return: Current IOC state.
1029  */
1030 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1031 {
1032         u32 ioc_status, ioc_config;
1033         u8 ready, enabled;
1034
1035         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1036         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1037
1038         if (mrioc->unrecoverable)
1039                 return MRIOC_STATE_UNRECOVERABLE;
1040         if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1041                 return MRIOC_STATE_FAULT;
1042
1043         ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1044         enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1045
1046         if (ready && enabled)
1047                 return MRIOC_STATE_READY;
1048         if ((!ready) && (!enabled))
1049                 return MRIOC_STATE_RESET;
1050         if ((!ready) && (enabled))
1051                 return MRIOC_STATE_BECOMING_READY;
1052
1053         return MRIOC_STATE_RESET_REQUESTED;
1054 }
1055
1056 /**
1057  * mpi3mr_clear_reset_history - clear reset history
1058  * @mrioc: Adapter instance reference
1059  *
1060  * Write the reset history bit in IOC status to clear the bit,
1061  * if it is already set.
1062  *
1063  * Return: Nothing.
1064  */
1065 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1066 {
1067         u32 ioc_status;
1068
1069         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1070         if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1071                 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1072 }
1073
1074 /**
1075  * mpi3mr_issue_and_process_mur - Message unit Reset handler
1076  * @mrioc: Adapter instance reference
1077  * @reset_reason: Reset reason code
1078  *
1079  * Issue Message unit Reset to the controller and wait for it to
1080  * be complete.
1081  *
1082  * Return: 0 on success, -1 on failure.
1083  */
1084 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1085         u32 reset_reason)
1086 {
1087         u32 ioc_config, timeout, ioc_status;
1088         int retval = -1;
1089
1090         ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1091         if (mrioc->unrecoverable) {
1092                 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1093                 return retval;
1094         }
1095         mpi3mr_clear_reset_history(mrioc);
1096         writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1097         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1098         ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1099         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1100
1101         timeout = MPI3MR_MUR_TIMEOUT * 10;
1102         do {
1103                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1104                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1105                         mpi3mr_clear_reset_history(mrioc);
1106                         break;
1107                 }
1108                 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1109                         mpi3mr_print_fault_info(mrioc);
1110                         break;
1111                 }
1112                 msleep(100);
1113         } while (--timeout);
1114
1115         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1116         if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1117               (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1118               (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1119                 retval = 0;
1120
1121         ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
1122             (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1123         return retval;
1124 }
1125
1126 /**
1127  * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1128  * during reset/resume
1129  * @mrioc: Adapter instance reference
1130  *
1131  * Return zero if the new IOCFacts parameters value is compatible with
1132  * older values else return -EPERM
1133  */
1134 static int
1135 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1136 {
1137         void *removepend_bitmap;
1138
1139         if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1140                 ioc_err(mrioc,
1141                     "cannot increase reply size from %d to %d\n",
1142                     mrioc->reply_sz, mrioc->facts.reply_sz);
1143                 return -EPERM;
1144         }
1145
1146         if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1147                 ioc_err(mrioc,
1148                     "cannot reduce number of operational reply queues from %d to %d\n",
1149                     mrioc->num_op_reply_q,
1150                     mrioc->facts.max_op_reply_q);
1151                 return -EPERM;
1152         }
1153
1154         if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1155                 ioc_err(mrioc,
1156                     "cannot reduce number of operational request queues from %d to %d\n",
1157                     mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1158                 return -EPERM;
1159         }
1160
1161         if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1162             MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED))
1163                 ioc_err(mrioc,
1164                     "critical error: multipath capability is enabled at the\n"
1165                     "\tcontroller while sas transport support is enabled at the\n"
1166                     "\tdriver, please reboot the system or reload the driver\n");
1167
1168         if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) {
1169                 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle,
1170                                                   GFP_KERNEL);
1171                 if (!removepend_bitmap) {
1172                         ioc_err(mrioc,
1173                                 "failed to increase removepend_bitmap bits from %d to %d\n",
1174                                 mrioc->dev_handle_bitmap_bits,
1175                                 mrioc->facts.max_devhandle);
1176                         return -EPERM;
1177                 }
1178                 bitmap_free(mrioc->removepend_bitmap);
1179                 mrioc->removepend_bitmap = removepend_bitmap;
1180                 ioc_info(mrioc,
1181                          "increased bits of dev_handle_bitmap from %d to %d\n",
1182                          mrioc->dev_handle_bitmap_bits,
1183                          mrioc->facts.max_devhandle);
1184                 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
1185         }
1186
1187         return 0;
1188 }
1189
1190 /**
1191  * mpi3mr_bring_ioc_ready - Bring controller to ready state
1192  * @mrioc: Adapter instance reference
1193  *
1194  * Set Enable IOC bit in IOC configuration register and wait for
1195  * the controller to become ready.
1196  *
1197  * Return: 0 on success, appropriate error on failure.
1198  */
1199 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1200 {
1201         u32 ioc_config, ioc_status, timeout, host_diagnostic;
1202         int retval = 0;
1203         enum mpi3mr_iocstate ioc_state;
1204         u64 base_info;
1205
1206         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1207         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1208         base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1209         ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1210             ioc_status, ioc_config, base_info);
1211
1212         /*The timeout value is in 2sec unit, changing it to seconds*/
1213         mrioc->ready_timeout =
1214             ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1215             MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1216
1217         ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1218
1219         ioc_state = mpi3mr_get_iocstate(mrioc);
1220         ioc_info(mrioc, "controller is in %s state during detection\n",
1221             mpi3mr_iocstate_name(ioc_state));
1222
1223         if (ioc_state == MRIOC_STATE_BECOMING_READY ||
1224             ioc_state == MRIOC_STATE_RESET_REQUESTED) {
1225                 timeout = mrioc->ready_timeout * 10;
1226                 do {
1227                         msleep(100);
1228                 } while (--timeout);
1229
1230                 if (!pci_device_is_present(mrioc->pdev)) {
1231                         mrioc->unrecoverable = 1;
1232                         ioc_err(mrioc,
1233                             "controller is not present while waiting to reset\n");
1234                         retval = -1;
1235                         goto out_device_not_present;
1236                 }
1237
1238                 ioc_state = mpi3mr_get_iocstate(mrioc);
1239                 ioc_info(mrioc,
1240                     "controller is in %s state after waiting to reset\n",
1241                     mpi3mr_iocstate_name(ioc_state));
1242         }
1243
1244         if (ioc_state == MRIOC_STATE_READY) {
1245                 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1246                 retval = mpi3mr_issue_and_process_mur(mrioc,
1247                     MPI3MR_RESET_FROM_BRINGUP);
1248                 ioc_state = mpi3mr_get_iocstate(mrioc);
1249                 if (retval)
1250                         ioc_err(mrioc,
1251                             "message unit reset failed with error %d current state %s\n",
1252                             retval, mpi3mr_iocstate_name(ioc_state));
1253         }
1254         if (ioc_state != MRIOC_STATE_RESET) {
1255                 if (ioc_state == MRIOC_STATE_FAULT) {
1256                         timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
1257                         mpi3mr_print_fault_info(mrioc);
1258                         do {
1259                                 host_diagnostic =
1260                                         readl(&mrioc->sysif_regs->host_diagnostic);
1261                                 if (!(host_diagnostic &
1262                                       MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
1263                                         break;
1264                                 if (!pci_device_is_present(mrioc->pdev)) {
1265                                         mrioc->unrecoverable = 1;
1266                                         ioc_err(mrioc, "controller is not present at the bringup\n");
1267                                         goto out_device_not_present;
1268                                 }
1269                                 msleep(100);
1270                         } while (--timeout);
1271                 }
1272                 mpi3mr_print_fault_info(mrioc);
1273                 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1274                 retval = mpi3mr_issue_reset(mrioc,
1275                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1276                     MPI3MR_RESET_FROM_BRINGUP);
1277                 if (retval) {
1278                         ioc_err(mrioc,
1279                             "soft reset failed with error %d\n", retval);
1280                         goto out_failed;
1281                 }
1282         }
1283         ioc_state = mpi3mr_get_iocstate(mrioc);
1284         if (ioc_state != MRIOC_STATE_RESET) {
1285                 ioc_err(mrioc,
1286                     "cannot bring controller to reset state, current state: %s\n",
1287                     mpi3mr_iocstate_name(ioc_state));
1288                 goto out_failed;
1289         }
1290         mpi3mr_clear_reset_history(mrioc);
1291         retval = mpi3mr_setup_admin_qpair(mrioc);
1292         if (retval) {
1293                 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1294                     retval);
1295                 goto out_failed;
1296         }
1297
1298         ioc_info(mrioc, "bringing controller to ready state\n");
1299         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1300         ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1301         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1302
1303         timeout = mrioc->ready_timeout * 10;
1304         do {
1305                 ioc_state = mpi3mr_get_iocstate(mrioc);
1306                 if (ioc_state == MRIOC_STATE_READY) {
1307                         ioc_info(mrioc,
1308                             "successfully transitioned to %s state\n",
1309                             mpi3mr_iocstate_name(ioc_state));
1310                         return 0;
1311                 }
1312                 if (!pci_device_is_present(mrioc->pdev)) {
1313                         mrioc->unrecoverable = 1;
1314                         ioc_err(mrioc,
1315                             "controller is not present at the bringup\n");
1316                         retval = -1;
1317                         goto out_device_not_present;
1318                 }
1319                 msleep(100);
1320         } while (--timeout);
1321
1322 out_failed:
1323         ioc_state = mpi3mr_get_iocstate(mrioc);
1324         ioc_err(mrioc,
1325             "failed to bring to ready state,  current state: %s\n",
1326             mpi3mr_iocstate_name(ioc_state));
1327 out_device_not_present:
1328         return retval;
1329 }
1330
1331 /**
1332  * mpi3mr_soft_reset_success - Check softreset is success or not
1333  * @ioc_status: IOC status register value
1334  * @ioc_config: IOC config register value
1335  *
1336  * Check whether the soft reset is successful or not based on
1337  * IOC status and IOC config register values.
1338  *
1339  * Return: True when the soft reset is success, false otherwise.
1340  */
1341 static inline bool
1342 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1343 {
1344         if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1345             (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1346                 return true;
1347         return false;
1348 }
1349
1350 /**
1351  * mpi3mr_diagfault_success - Check diag fault is success or not
1352  * @mrioc: Adapter reference
1353  * @ioc_status: IOC status register value
1354  *
1355  * Check whether the controller hit diag reset fault code.
1356  *
1357  * Return: True when there is diag fault, false otherwise.
1358  */
1359 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1360         u32 ioc_status)
1361 {
1362         u32 fault;
1363
1364         if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1365                 return false;
1366         fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1367         if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1368                 mpi3mr_print_fault_info(mrioc);
1369                 return true;
1370         }
1371         return false;
1372 }
1373
1374 /**
1375  * mpi3mr_set_diagsave - Set diag save bit for snapdump
1376  * @mrioc: Adapter reference
1377  *
1378  * Set diag save bit in IOC configuration register to enable
1379  * snapdump.
1380  *
1381  * Return: Nothing.
1382  */
1383 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1384 {
1385         u32 ioc_config;
1386
1387         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1388         ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1389         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1390 }
1391
1392 /**
1393  * mpi3mr_issue_reset - Issue reset to the controller
1394  * @mrioc: Adapter reference
1395  * @reset_type: Reset type
1396  * @reset_reason: Reset reason code
1397  *
1398  * Unlock the host diagnostic registers and write the specific
1399  * reset type to that, wait for reset acknowledgment from the
1400  * controller, if the reset is not successful retry for the
1401  * predefined number of times.
1402  *
1403  * Return: 0 on success, non-zero on failure.
1404  */
1405 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1406         u32 reset_reason)
1407 {
1408         int retval = -1;
1409         u8 unlock_retry_count = 0;
1410         u32 host_diagnostic, ioc_status, ioc_config;
1411         u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1412
1413         if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1414             (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1415                 return retval;
1416         if (mrioc->unrecoverable)
1417                 return retval;
1418         if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1419                 retval = 0;
1420                 return retval;
1421         }
1422
1423         ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1424             mpi3mr_reset_type_name(reset_type),
1425             mpi3mr_reset_rc_name(reset_reason), reset_reason);
1426
1427         mpi3mr_clear_reset_history(mrioc);
1428         do {
1429                 ioc_info(mrioc,
1430                     "Write magic sequence to unlock host diag register (retry=%d)\n",
1431                     ++unlock_retry_count);
1432                 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1433                         ioc_err(mrioc,
1434                             "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1435                             mpi3mr_reset_type_name(reset_type),
1436                             host_diagnostic);
1437                         mrioc->unrecoverable = 1;
1438                         return retval;
1439                 }
1440
1441                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1442                     &mrioc->sysif_regs->write_sequence);
1443                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1444                     &mrioc->sysif_regs->write_sequence);
1445                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1446                     &mrioc->sysif_regs->write_sequence);
1447                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1448                     &mrioc->sysif_regs->write_sequence);
1449                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1450                     &mrioc->sysif_regs->write_sequence);
1451                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1452                     &mrioc->sysif_regs->write_sequence);
1453                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1454                     &mrioc->sysif_regs->write_sequence);
1455                 usleep_range(1000, 1100);
1456                 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1457                 ioc_info(mrioc,
1458                     "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1459                     unlock_retry_count, host_diagnostic);
1460         } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1461
1462         writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1463         writel(host_diagnostic | reset_type,
1464             &mrioc->sysif_regs->host_diagnostic);
1465         switch (reset_type) {
1466         case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1467                 do {
1468                         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1469                         ioc_config =
1470                             readl(&mrioc->sysif_regs->ioc_configuration);
1471                         if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1472                             && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1473                             ) {
1474                                 mpi3mr_clear_reset_history(mrioc);
1475                                 retval = 0;
1476                                 break;
1477                         }
1478                         msleep(100);
1479                 } while (--timeout);
1480                 mpi3mr_print_fault_info(mrioc);
1481                 break;
1482         case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1483                 do {
1484                         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1485                         if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1486                                 retval = 0;
1487                                 break;
1488                         }
1489                         msleep(100);
1490                 } while (--timeout);
1491                 break;
1492         default:
1493                 break;
1494         }
1495
1496         writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1497             &mrioc->sysif_regs->write_sequence);
1498
1499         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1500         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1501         ioc_info(mrioc,
1502             "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1503             (!retval)?"successful":"failed", ioc_status,
1504             ioc_config);
1505         if (retval)
1506                 mrioc->unrecoverable = 1;
1507         return retval;
1508 }
1509
1510 /**
1511  * mpi3mr_admin_request_post - Post request to admin queue
1512  * @mrioc: Adapter reference
1513  * @admin_req: MPI3 request
1514  * @admin_req_sz: Request size
1515  * @ignore_reset: Ignore reset in process
1516  *
1517  * Post the MPI3 request into admin request queue and
1518  * inform the controller, if the queue is full return
1519  * appropriate error.
1520  *
1521  * Return: 0 on success, non-zero on failure.
1522  */
1523 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1524         u16 admin_req_sz, u8 ignore_reset)
1525 {
1526         u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1527         int retval = 0;
1528         unsigned long flags;
1529         u8 *areq_entry;
1530
1531         if (mrioc->unrecoverable) {
1532                 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1533                 return -EFAULT;
1534         }
1535
1536         spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1537         areq_pi = mrioc->admin_req_pi;
1538         areq_ci = mrioc->admin_req_ci;
1539         max_entries = mrioc->num_admin_req;
1540         if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1541             (areq_pi == (max_entries - 1)))) {
1542                 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1543                 retval = -EAGAIN;
1544                 goto out;
1545         }
1546         if (!ignore_reset && mrioc->reset_in_progress) {
1547                 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1548                 retval = -EAGAIN;
1549                 goto out;
1550         }
1551         areq_entry = (u8 *)mrioc->admin_req_base +
1552             (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1553         memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1554         memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1555
1556         if (++areq_pi == max_entries)
1557                 areq_pi = 0;
1558         mrioc->admin_req_pi = areq_pi;
1559
1560         writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1561
1562 out:
1563         spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1564
1565         return retval;
1566 }
1567
1568 /**
1569  * mpi3mr_free_op_req_q_segments - free request memory segments
1570  * @mrioc: Adapter instance reference
1571  * @q_idx: operational request queue index
1572  *
1573  * Free memory segments allocated for operational request queue
1574  *
1575  * Return: Nothing.
1576  */
1577 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1578 {
1579         u16 j;
1580         int size;
1581         struct segments *segments;
1582
1583         segments = mrioc->req_qinfo[q_idx].q_segments;
1584         if (!segments)
1585                 return;
1586
1587         if (mrioc->enable_segqueue) {
1588                 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1589                 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1590                         dma_free_coherent(&mrioc->pdev->dev,
1591                             MPI3MR_MAX_SEG_LIST_SIZE,
1592                             mrioc->req_qinfo[q_idx].q_segment_list,
1593                             mrioc->req_qinfo[q_idx].q_segment_list_dma);
1594                         mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1595                 }
1596         } else
1597                 size = mrioc->req_qinfo[q_idx].segment_qd *
1598                     mrioc->facts.op_req_sz;
1599
1600         for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1601                 if (!segments[j].segment)
1602                         continue;
1603                 dma_free_coherent(&mrioc->pdev->dev,
1604                     size, segments[j].segment, segments[j].segment_dma);
1605                 segments[j].segment = NULL;
1606         }
1607         kfree(mrioc->req_qinfo[q_idx].q_segments);
1608         mrioc->req_qinfo[q_idx].q_segments = NULL;
1609         mrioc->req_qinfo[q_idx].qid = 0;
1610 }
1611
1612 /**
1613  * mpi3mr_free_op_reply_q_segments - free reply memory segments
1614  * @mrioc: Adapter instance reference
1615  * @q_idx: operational reply queue index
1616  *
1617  * Free memory segments allocated for operational reply queue
1618  *
1619  * Return: Nothing.
1620  */
1621 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1622 {
1623         u16 j;
1624         int size;
1625         struct segments *segments;
1626
1627         segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1628         if (!segments)
1629                 return;
1630
1631         if (mrioc->enable_segqueue) {
1632                 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1633                 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1634                         dma_free_coherent(&mrioc->pdev->dev,
1635                             MPI3MR_MAX_SEG_LIST_SIZE,
1636                             mrioc->op_reply_qinfo[q_idx].q_segment_list,
1637                             mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1638                         mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1639                 }
1640         } else
1641                 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1642                     mrioc->op_reply_desc_sz;
1643
1644         for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1645                 if (!segments[j].segment)
1646                         continue;
1647                 dma_free_coherent(&mrioc->pdev->dev,
1648                     size, segments[j].segment, segments[j].segment_dma);
1649                 segments[j].segment = NULL;
1650         }
1651
1652         kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1653         mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1654         mrioc->op_reply_qinfo[q_idx].qid = 0;
1655 }
1656
1657 /**
1658  * mpi3mr_delete_op_reply_q - delete operational reply queue
1659  * @mrioc: Adapter instance reference
1660  * @qidx: operational reply queue index
1661  *
1662  * Delete operatinal reply queue by issuing MPI request
1663  * through admin queue.
1664  *
1665  * Return:  0 on success, non-zero on failure.
1666  */
1667 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1668 {
1669         struct mpi3_delete_reply_queue_request delq_req;
1670         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1671         int retval = 0;
1672         u16 reply_qid = 0, midx;
1673
1674         reply_qid = op_reply_q->qid;
1675
1676         midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1677
1678         if (!reply_qid) {
1679                 retval = -1;
1680                 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1681                 goto out;
1682         }
1683
1684         (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1685             mrioc->active_poll_qcount--;
1686
1687         memset(&delq_req, 0, sizeof(delq_req));
1688         mutex_lock(&mrioc->init_cmds.mutex);
1689         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1690                 retval = -1;
1691                 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1692                 mutex_unlock(&mrioc->init_cmds.mutex);
1693                 goto out;
1694         }
1695         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1696         mrioc->init_cmds.is_waiting = 1;
1697         mrioc->init_cmds.callback = NULL;
1698         delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1699         delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1700         delq_req.queue_id = cpu_to_le16(reply_qid);
1701
1702         init_completion(&mrioc->init_cmds.done);
1703         retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1704             1);
1705         if (retval) {
1706                 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1707                 goto out_unlock;
1708         }
1709         wait_for_completion_timeout(&mrioc->init_cmds.done,
1710             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1711         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1712                 ioc_err(mrioc, "delete reply queue timed out\n");
1713                 mpi3mr_check_rh_fault_ioc(mrioc,
1714                     MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1715                 retval = -1;
1716                 goto out_unlock;
1717         }
1718         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1719             != MPI3_IOCSTATUS_SUCCESS) {
1720                 ioc_err(mrioc,
1721                     "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1722                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1723                     mrioc->init_cmds.ioc_loginfo);
1724                 retval = -1;
1725                 goto out_unlock;
1726         }
1727         mrioc->intr_info[midx].op_reply_q = NULL;
1728
1729         mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1730 out_unlock:
1731         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1732         mutex_unlock(&mrioc->init_cmds.mutex);
1733 out:
1734
1735         return retval;
1736 }
1737
1738 /**
1739  * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1740  * @mrioc: Adapter instance reference
1741  * @qidx: request queue index
1742  *
1743  * Allocate segmented memory pools for operational reply
1744  * queue.
1745  *
1746  * Return: 0 on success, non-zero on failure.
1747  */
1748 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1749 {
1750         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1751         int i, size;
1752         u64 *q_segment_list_entry = NULL;
1753         struct segments *segments;
1754
1755         if (mrioc->enable_segqueue) {
1756                 op_reply_q->segment_qd =
1757                     MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1758
1759                 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1760
1761                 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1762                     MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1763                     GFP_KERNEL);
1764                 if (!op_reply_q->q_segment_list)
1765                         return -ENOMEM;
1766                 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1767         } else {
1768                 op_reply_q->segment_qd = op_reply_q->num_replies;
1769                 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1770         }
1771
1772         op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1773             op_reply_q->segment_qd);
1774
1775         op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
1776             sizeof(struct segments), GFP_KERNEL);
1777         if (!op_reply_q->q_segments)
1778                 return -ENOMEM;
1779
1780         segments = op_reply_q->q_segments;
1781         for (i = 0; i < op_reply_q->num_segments; i++) {
1782                 segments[i].segment =
1783                     dma_alloc_coherent(&mrioc->pdev->dev,
1784                     size, &segments[i].segment_dma, GFP_KERNEL);
1785                 if (!segments[i].segment)
1786                         return -ENOMEM;
1787                 if (mrioc->enable_segqueue)
1788                         q_segment_list_entry[i] =
1789                             (unsigned long)segments[i].segment_dma;
1790         }
1791
1792         return 0;
1793 }
1794
1795 /**
1796  * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
1797  * @mrioc: Adapter instance reference
1798  * @qidx: request queue index
1799  *
1800  * Allocate segmented memory pools for operational request
1801  * queue.
1802  *
1803  * Return: 0 on success, non-zero on failure.
1804  */
1805 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1806 {
1807         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
1808         int i, size;
1809         u64 *q_segment_list_entry = NULL;
1810         struct segments *segments;
1811
1812         if (mrioc->enable_segqueue) {
1813                 op_req_q->segment_qd =
1814                     MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
1815
1816                 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1817
1818                 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1819                     MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
1820                     GFP_KERNEL);
1821                 if (!op_req_q->q_segment_list)
1822                         return -ENOMEM;
1823                 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
1824
1825         } else {
1826                 op_req_q->segment_qd = op_req_q->num_requests;
1827                 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
1828         }
1829
1830         op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
1831             op_req_q->segment_qd);
1832
1833         op_req_q->q_segments = kcalloc(op_req_q->num_segments,
1834             sizeof(struct segments), GFP_KERNEL);
1835         if (!op_req_q->q_segments)
1836                 return -ENOMEM;
1837
1838         segments = op_req_q->q_segments;
1839         for (i = 0; i < op_req_q->num_segments; i++) {
1840                 segments[i].segment =
1841                     dma_alloc_coherent(&mrioc->pdev->dev,
1842                     size, &segments[i].segment_dma, GFP_KERNEL);
1843                 if (!segments[i].segment)
1844                         return -ENOMEM;
1845                 if (mrioc->enable_segqueue)
1846                         q_segment_list_entry[i] =
1847                             (unsigned long)segments[i].segment_dma;
1848         }
1849
1850         return 0;
1851 }
1852
1853 /**
1854  * mpi3mr_create_op_reply_q - create operational reply queue
1855  * @mrioc: Adapter instance reference
1856  * @qidx: operational reply queue index
1857  *
1858  * Create operatinal reply queue by issuing MPI request
1859  * through admin queue.
1860  *
1861  * Return:  0 on success, non-zero on failure.
1862  */
1863 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1864 {
1865         struct mpi3_create_reply_queue_request create_req;
1866         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1867         int retval = 0;
1868         u16 reply_qid = 0, midx;
1869
1870         reply_qid = op_reply_q->qid;
1871
1872         midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1873
1874         if (reply_qid) {
1875                 retval = -1;
1876                 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
1877                     reply_qid);
1878
1879                 return retval;
1880         }
1881
1882         reply_qid = qidx + 1;
1883         op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
1884         if (!mrioc->pdev->revision)
1885                 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
1886         op_reply_q->ci = 0;
1887         op_reply_q->ephase = 1;
1888         atomic_set(&op_reply_q->pend_ios, 0);
1889         atomic_set(&op_reply_q->in_use, 0);
1890         op_reply_q->enable_irq_poll = false;
1891
1892         if (!op_reply_q->q_segments) {
1893                 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
1894                 if (retval) {
1895                         mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1896                         goto out;
1897                 }
1898         }
1899
1900         memset(&create_req, 0, sizeof(create_req));
1901         mutex_lock(&mrioc->init_cmds.mutex);
1902         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1903                 retval = -1;
1904                 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
1905                 goto out_unlock;
1906         }
1907         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1908         mrioc->init_cmds.is_waiting = 1;
1909         mrioc->init_cmds.callback = NULL;
1910         create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1911         create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
1912         create_req.queue_id = cpu_to_le16(reply_qid);
1913
1914         if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
1915                 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
1916         else
1917                 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
1918
1919         if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
1920                 create_req.flags =
1921                         MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
1922                 create_req.msix_index =
1923                         cpu_to_le16(mrioc->intr_info[midx].msix_index);
1924         } else {
1925                 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
1926                 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
1927                         reply_qid, midx);
1928                 if (!mrioc->active_poll_qcount)
1929                         disable_irq_nosync(pci_irq_vector(mrioc->pdev,
1930                             mrioc->intr_info_count - 1));
1931         }
1932
1933         if (mrioc->enable_segqueue) {
1934                 create_req.flags |=
1935                     MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
1936                 create_req.base_address = cpu_to_le64(
1937                     op_reply_q->q_segment_list_dma);
1938         } else
1939                 create_req.base_address = cpu_to_le64(
1940                     op_reply_q->q_segments[0].segment_dma);
1941
1942         create_req.size = cpu_to_le16(op_reply_q->num_replies);
1943
1944         init_completion(&mrioc->init_cmds.done);
1945         retval = mpi3mr_admin_request_post(mrioc, &create_req,
1946             sizeof(create_req), 1);
1947         if (retval) {
1948                 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
1949                 goto out_unlock;
1950         }
1951         wait_for_completion_timeout(&mrioc->init_cmds.done,
1952             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1953         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1954                 ioc_err(mrioc, "create reply queue timed out\n");
1955                 mpi3mr_check_rh_fault_ioc(mrioc,
1956                     MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
1957                 retval = -1;
1958                 goto out_unlock;
1959         }
1960         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1961             != MPI3_IOCSTATUS_SUCCESS) {
1962                 ioc_err(mrioc,
1963                     "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1964                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1965                     mrioc->init_cmds.ioc_loginfo);
1966                 retval = -1;
1967                 goto out_unlock;
1968         }
1969         op_reply_q->qid = reply_qid;
1970         if (midx < mrioc->intr_info_count)
1971                 mrioc->intr_info[midx].op_reply_q = op_reply_q;
1972
1973         (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
1974             mrioc->active_poll_qcount++;
1975
1976 out_unlock:
1977         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1978         mutex_unlock(&mrioc->init_cmds.mutex);
1979 out:
1980
1981         return retval;
1982 }
1983
1984 /**
1985  * mpi3mr_create_op_req_q - create operational request queue
1986  * @mrioc: Adapter instance reference
1987  * @idx: operational request queue index
1988  * @reply_qid: Reply queue ID
1989  *
1990  * Create operatinal request queue by issuing MPI request
1991  * through admin queue.
1992  *
1993  * Return:  0 on success, non-zero on failure.
1994  */
1995 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
1996         u16 reply_qid)
1997 {
1998         struct mpi3_create_request_queue_request create_req;
1999         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
2000         int retval = 0;
2001         u16 req_qid = 0;
2002
2003         req_qid = op_req_q->qid;
2004
2005         if (req_qid) {
2006                 retval = -1;
2007                 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
2008                     req_qid);
2009
2010                 return retval;
2011         }
2012         req_qid = idx + 1;
2013
2014         op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
2015         op_req_q->ci = 0;
2016         op_req_q->pi = 0;
2017         op_req_q->reply_qid = reply_qid;
2018         spin_lock_init(&op_req_q->q_lock);
2019
2020         if (!op_req_q->q_segments) {
2021                 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2022                 if (retval) {
2023                         mpi3mr_free_op_req_q_segments(mrioc, idx);
2024                         goto out;
2025                 }
2026         }
2027
2028         memset(&create_req, 0, sizeof(create_req));
2029         mutex_lock(&mrioc->init_cmds.mutex);
2030         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2031                 retval = -1;
2032                 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2033                 goto out_unlock;
2034         }
2035         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2036         mrioc->init_cmds.is_waiting = 1;
2037         mrioc->init_cmds.callback = NULL;
2038         create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2039         create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2040         create_req.queue_id = cpu_to_le16(req_qid);
2041         if (mrioc->enable_segqueue) {
2042                 create_req.flags =
2043                     MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2044                 create_req.base_address = cpu_to_le64(
2045                     op_req_q->q_segment_list_dma);
2046         } else
2047                 create_req.base_address = cpu_to_le64(
2048                     op_req_q->q_segments[0].segment_dma);
2049         create_req.reply_queue_id = cpu_to_le16(reply_qid);
2050         create_req.size = cpu_to_le16(op_req_q->num_requests);
2051
2052         init_completion(&mrioc->init_cmds.done);
2053         retval = mpi3mr_admin_request_post(mrioc, &create_req,
2054             sizeof(create_req), 1);
2055         if (retval) {
2056                 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2057                 goto out_unlock;
2058         }
2059         wait_for_completion_timeout(&mrioc->init_cmds.done,
2060             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2061         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2062                 ioc_err(mrioc, "create request queue timed out\n");
2063                 mpi3mr_check_rh_fault_ioc(mrioc,
2064                     MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2065                 retval = -1;
2066                 goto out_unlock;
2067         }
2068         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2069             != MPI3_IOCSTATUS_SUCCESS) {
2070                 ioc_err(mrioc,
2071                     "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2072                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2073                     mrioc->init_cmds.ioc_loginfo);
2074                 retval = -1;
2075                 goto out_unlock;
2076         }
2077         op_req_q->qid = req_qid;
2078
2079 out_unlock:
2080         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2081         mutex_unlock(&mrioc->init_cmds.mutex);
2082 out:
2083
2084         return retval;
2085 }
2086
2087 /**
2088  * mpi3mr_create_op_queues - create operational queue pairs
2089  * @mrioc: Adapter instance reference
2090  *
2091  * Allocate memory for operational queue meta data and call
2092  * create request and reply queue functions.
2093  *
2094  * Return: 0 on success, non-zero on failures.
2095  */
2096 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2097 {
2098         int retval = 0;
2099         u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2100
2101         num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2102             mrioc->facts.max_op_req_q);
2103
2104         msix_count_op_q =
2105             mrioc->intr_info_count - mrioc->op_reply_q_offset;
2106         if (!mrioc->num_queues)
2107                 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2108         /*
2109          * During reset set the num_queues to the number of queues
2110          * that was set before the reset.
2111          */
2112         num_queues = mrioc->num_op_reply_q ?
2113             mrioc->num_op_reply_q : mrioc->num_queues;
2114         ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2115             num_queues);
2116
2117         if (!mrioc->req_qinfo) {
2118                 mrioc->req_qinfo = kcalloc(num_queues,
2119                     sizeof(struct op_req_qinfo), GFP_KERNEL);
2120                 if (!mrioc->req_qinfo) {
2121                         retval = -1;
2122                         goto out_failed;
2123                 }
2124
2125                 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2126                     num_queues, GFP_KERNEL);
2127                 if (!mrioc->op_reply_qinfo) {
2128                         retval = -1;
2129                         goto out_failed;
2130                 }
2131         }
2132
2133         if (mrioc->enable_segqueue)
2134                 ioc_info(mrioc,
2135                     "allocating operational queues through segmented queues\n");
2136
2137         for (i = 0; i < num_queues; i++) {
2138                 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2139                         ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2140                         break;
2141                 }
2142                 if (mpi3mr_create_op_req_q(mrioc, i,
2143                     mrioc->op_reply_qinfo[i].qid)) {
2144                         ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2145                         mpi3mr_delete_op_reply_q(mrioc, i);
2146                         break;
2147                 }
2148         }
2149
2150         if (i == 0) {
2151                 /* Not even one queue is created successfully*/
2152                 retval = -1;
2153                 goto out_failed;
2154         }
2155         mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2156         ioc_info(mrioc,
2157             "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2158             mrioc->num_op_reply_q, mrioc->default_qcount,
2159             mrioc->active_poll_qcount);
2160
2161         return retval;
2162 out_failed:
2163         kfree(mrioc->req_qinfo);
2164         mrioc->req_qinfo = NULL;
2165
2166         kfree(mrioc->op_reply_qinfo);
2167         mrioc->op_reply_qinfo = NULL;
2168
2169         return retval;
2170 }
2171
2172 /**
2173  * mpi3mr_op_request_post - Post request to operational queue
2174  * @mrioc: Adapter reference
2175  * @op_req_q: Operational request queue info
2176  * @req: MPI3 request
2177  *
2178  * Post the MPI3 request into operational request queue and
2179  * inform the controller, if the queue is full return
2180  * appropriate error.
2181  *
2182  * Return: 0 on success, non-zero on failure.
2183  */
2184 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2185         struct op_req_qinfo *op_req_q, u8 *req)
2186 {
2187         u16 pi = 0, max_entries, reply_qidx = 0, midx;
2188         int retval = 0;
2189         unsigned long flags;
2190         u8 *req_entry;
2191         void *segment_base_addr;
2192         u16 req_sz = mrioc->facts.op_req_sz;
2193         struct segments *segments = op_req_q->q_segments;
2194
2195         reply_qidx = op_req_q->reply_qid - 1;
2196
2197         if (mrioc->unrecoverable)
2198                 return -EFAULT;
2199
2200         spin_lock_irqsave(&op_req_q->q_lock, flags);
2201         pi = op_req_q->pi;
2202         max_entries = op_req_q->num_requests;
2203
2204         if (mpi3mr_check_req_qfull(op_req_q)) {
2205                 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2206                     reply_qidx, mrioc->op_reply_q_offset);
2207                 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2208
2209                 if (mpi3mr_check_req_qfull(op_req_q)) {
2210                         retval = -EAGAIN;
2211                         goto out;
2212                 }
2213         }
2214
2215         if (mrioc->reset_in_progress) {
2216                 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2217                 retval = -EAGAIN;
2218                 goto out;
2219         }
2220
2221         segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2222         req_entry = (u8 *)segment_base_addr +
2223             ((pi % op_req_q->segment_qd) * req_sz);
2224
2225         memset(req_entry, 0, req_sz);
2226         memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2227
2228         if (++pi == max_entries)
2229                 pi = 0;
2230         op_req_q->pi = pi;
2231
2232 #ifndef CONFIG_PREEMPT_RT
2233         if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2234             > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2235                 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2236 #else
2237         atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2238 #endif
2239
2240         writel(op_req_q->pi,
2241             &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2242
2243 out:
2244         spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2245         return retval;
2246 }
2247
2248 /**
2249  * mpi3mr_check_rh_fault_ioc - check reset history and fault
2250  * controller
2251  * @mrioc: Adapter instance reference
2252  * @reason_code: reason code for the fault.
2253  *
2254  * This routine will save snapdump and fault the controller with
2255  * the given reason code if it is not already in the fault or
2256  * not asynchronosuly reset. This will be used to handle
2257  * initilaization time faults/resets/timeout as in those cases
2258  * immediate soft reset invocation is not required.
2259  *
2260  * Return:  None.
2261  */
2262 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2263 {
2264         u32 ioc_status, host_diagnostic, timeout;
2265
2266         if (mrioc->unrecoverable) {
2267                 ioc_err(mrioc, "controller is unrecoverable\n");
2268                 return;
2269         }
2270
2271         if (!pci_device_is_present(mrioc->pdev)) {
2272                 mrioc->unrecoverable = 1;
2273                 ioc_err(mrioc, "controller is not present\n");
2274                 return;
2275         }
2276
2277         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2278         if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2279             (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
2280                 mpi3mr_print_fault_info(mrioc);
2281                 return;
2282         }
2283         mpi3mr_set_diagsave(mrioc);
2284         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2285             reason_code);
2286         timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2287         do {
2288                 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2289                 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2290                         break;
2291                 msleep(100);
2292         } while (--timeout);
2293 }
2294
2295 /**
2296  * mpi3mr_sync_timestamp - Issue time stamp sync request
2297  * @mrioc: Adapter reference
2298  *
2299  * Issue IO unit control MPI request to synchornize firmware
2300  * timestamp with host time.
2301  *
2302  * Return: 0 on success, non-zero on failure.
2303  */
2304 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2305 {
2306         ktime_t current_time;
2307         struct mpi3_iounit_control_request iou_ctrl;
2308         int retval = 0;
2309
2310         memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2311         mutex_lock(&mrioc->init_cmds.mutex);
2312         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2313                 retval = -1;
2314                 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2315                 mutex_unlock(&mrioc->init_cmds.mutex);
2316                 goto out;
2317         }
2318         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2319         mrioc->init_cmds.is_waiting = 1;
2320         mrioc->init_cmds.callback = NULL;
2321         iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2322         iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2323         iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2324         current_time = ktime_get_real();
2325         iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2326
2327         init_completion(&mrioc->init_cmds.done);
2328         retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2329             sizeof(iou_ctrl), 0);
2330         if (retval) {
2331                 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2332                 goto out_unlock;
2333         }
2334
2335         wait_for_completion_timeout(&mrioc->init_cmds.done,
2336             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2337         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2338                 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2339                 mrioc->init_cmds.is_waiting = 0;
2340                 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2341                         mpi3mr_soft_reset_handler(mrioc,
2342                             MPI3MR_RESET_FROM_TSU_TIMEOUT, 1);
2343                 retval = -1;
2344                 goto out_unlock;
2345         }
2346         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2347             != MPI3_IOCSTATUS_SUCCESS) {
2348                 ioc_err(mrioc,
2349                     "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2350                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2351                     mrioc->init_cmds.ioc_loginfo);
2352                 retval = -1;
2353                 goto out_unlock;
2354         }
2355
2356 out_unlock:
2357         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2358         mutex_unlock(&mrioc->init_cmds.mutex);
2359
2360 out:
2361         return retval;
2362 }
2363
2364 /**
2365  * mpi3mr_print_pkg_ver - display controller fw package version
2366  * @mrioc: Adapter reference
2367  *
2368  * Retrieve firmware package version from the component image
2369  * header of the controller flash and display it.
2370  *
2371  * Return: 0 on success and non-zero on failure.
2372  */
2373 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2374 {
2375         struct mpi3_ci_upload_request ci_upload;
2376         int retval = -1;
2377         void *data = NULL;
2378         dma_addr_t data_dma;
2379         struct mpi3_ci_manifest_mpi *manifest;
2380         u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2381         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2382
2383         data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2384             GFP_KERNEL);
2385         if (!data)
2386                 return -ENOMEM;
2387
2388         memset(&ci_upload, 0, sizeof(ci_upload));
2389         mutex_lock(&mrioc->init_cmds.mutex);
2390         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2391                 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2392                 mutex_unlock(&mrioc->init_cmds.mutex);
2393                 goto out;
2394         }
2395         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2396         mrioc->init_cmds.is_waiting = 1;
2397         mrioc->init_cmds.callback = NULL;
2398         ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2399         ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2400         ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2401         ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2402         ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2403         ci_upload.segment_size = cpu_to_le32(data_len);
2404
2405         mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2406             data_dma);
2407         init_completion(&mrioc->init_cmds.done);
2408         retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2409             sizeof(ci_upload), 1);
2410         if (retval) {
2411                 ioc_err(mrioc, "posting get package version failed\n");
2412                 goto out_unlock;
2413         }
2414         wait_for_completion_timeout(&mrioc->init_cmds.done,
2415             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2416         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2417                 ioc_err(mrioc, "get package version timed out\n");
2418                 mpi3mr_check_rh_fault_ioc(mrioc,
2419                     MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2420                 retval = -1;
2421                 goto out_unlock;
2422         }
2423         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2424             == MPI3_IOCSTATUS_SUCCESS) {
2425                 manifest = (struct mpi3_ci_manifest_mpi *) data;
2426                 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2427                         ioc_info(mrioc,
2428                             "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2429                             manifest->package_version.gen_major,
2430                             manifest->package_version.gen_minor,
2431                             manifest->package_version.phase_major,
2432                             manifest->package_version.phase_minor,
2433                             manifest->package_version.customer_id,
2434                             manifest->package_version.build_num);
2435                 }
2436         }
2437         retval = 0;
2438 out_unlock:
2439         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2440         mutex_unlock(&mrioc->init_cmds.mutex);
2441
2442 out:
2443         if (data)
2444                 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2445                     data_dma);
2446         return retval;
2447 }
2448
2449 /**
2450  * mpi3mr_watchdog_work - watchdog thread to monitor faults
2451  * @work: work struct
2452  *
2453  * Watch dog work periodically executed (1 second interval) to
2454  * monitor firmware fault and to issue periodic timer sync to
2455  * the firmware.
2456  *
2457  * Return: Nothing.
2458  */
2459 static void mpi3mr_watchdog_work(struct work_struct *work)
2460 {
2461         struct mpi3mr_ioc *mrioc =
2462             container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2463         unsigned long flags;
2464         enum mpi3mr_iocstate ioc_state;
2465         u32 fault, host_diagnostic, ioc_status;
2466         u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2467
2468         if (mrioc->reset_in_progress)
2469                 return;
2470
2471         if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2472                 ioc_err(mrioc, "watchdog could not detect the controller\n");
2473                 mrioc->unrecoverable = 1;
2474         }
2475
2476         if (mrioc->unrecoverable) {
2477                 ioc_err(mrioc,
2478                     "flush pending commands for unrecoverable controller\n");
2479                 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2480                 return;
2481         }
2482
2483         if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) {
2484                 mrioc->ts_update_counter = 0;
2485                 mpi3mr_sync_timestamp(mrioc);
2486         }
2487
2488         if ((mrioc->prepare_for_reset) &&
2489             ((mrioc->prepare_for_reset_timeout_counter++) >=
2490              MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2491                 mpi3mr_soft_reset_handler(mrioc,
2492                     MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2493                 return;
2494         }
2495
2496         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2497         if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2498                 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2499                 return;
2500         }
2501
2502         /*Check for fault state every one second and issue Soft reset*/
2503         ioc_state = mpi3mr_get_iocstate(mrioc);
2504         if (ioc_state != MRIOC_STATE_FAULT)
2505                 goto schedule_work;
2506
2507         fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2508         host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2509         if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2510                 if (!mrioc->diagsave_timeout) {
2511                         mpi3mr_print_fault_info(mrioc);
2512                         ioc_warn(mrioc, "diag save in progress\n");
2513                 }
2514                 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2515                         goto schedule_work;
2516         }
2517
2518         mpi3mr_print_fault_info(mrioc);
2519         mrioc->diagsave_timeout = 0;
2520
2521         switch (fault) {
2522         case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2523         case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2524                 ioc_warn(mrioc,
2525                     "controller requires system power cycle, marking controller as unrecoverable\n");
2526                 mrioc->unrecoverable = 1;
2527                 goto schedule_work;
2528         case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2529                 goto schedule_work;
2530         case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2531                 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2532                 break;
2533         default:
2534                 break;
2535         }
2536         mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2537         return;
2538
2539 schedule_work:
2540         spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2541         if (mrioc->watchdog_work_q)
2542                 queue_delayed_work(mrioc->watchdog_work_q,
2543                     &mrioc->watchdog_work,
2544                     msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2545         spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2546         return;
2547 }
2548
2549 /**
2550  * mpi3mr_start_watchdog - Start watchdog
2551  * @mrioc: Adapter instance reference
2552  *
2553  * Create and start the watchdog thread to monitor controller
2554  * faults.
2555  *
2556  * Return: Nothing.
2557  */
2558 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2559 {
2560         if (mrioc->watchdog_work_q)
2561                 return;
2562
2563         INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2564         snprintf(mrioc->watchdog_work_q_name,
2565             sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2566             mrioc->id);
2567         mrioc->watchdog_work_q =
2568             create_singlethread_workqueue(mrioc->watchdog_work_q_name);
2569         if (!mrioc->watchdog_work_q) {
2570                 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2571                 return;
2572         }
2573
2574         if (mrioc->watchdog_work_q)
2575                 queue_delayed_work(mrioc->watchdog_work_q,
2576                     &mrioc->watchdog_work,
2577                     msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2578 }
2579
2580 /**
2581  * mpi3mr_stop_watchdog - Stop watchdog
2582  * @mrioc: Adapter instance reference
2583  *
2584  * Stop the watchdog thread created to monitor controller
2585  * faults.
2586  *
2587  * Return: Nothing.
2588  */
2589 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2590 {
2591         unsigned long flags;
2592         struct workqueue_struct *wq;
2593
2594         spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2595         wq = mrioc->watchdog_work_q;
2596         mrioc->watchdog_work_q = NULL;
2597         spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2598         if (wq) {
2599                 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2600                         flush_workqueue(wq);
2601                 destroy_workqueue(wq);
2602         }
2603 }
2604
2605 /**
2606  * mpi3mr_setup_admin_qpair - Setup admin queue pair
2607  * @mrioc: Adapter instance reference
2608  *
2609  * Allocate memory for admin queue pair if required and register
2610  * the admin queue with the controller.
2611  *
2612  * Return: 0 on success, non-zero on failures.
2613  */
2614 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2615 {
2616         int retval = 0;
2617         u32 num_admin_entries = 0;
2618
2619         mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2620         mrioc->num_admin_req = mrioc->admin_req_q_sz /
2621             MPI3MR_ADMIN_REQ_FRAME_SZ;
2622         mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2623
2624         mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2625         mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2626             MPI3MR_ADMIN_REPLY_FRAME_SZ;
2627         mrioc->admin_reply_ci = 0;
2628         mrioc->admin_reply_ephase = 1;
2629         atomic_set(&mrioc->admin_reply_q_in_use, 0);
2630
2631         if (!mrioc->admin_req_base) {
2632                 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2633                     mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2634
2635                 if (!mrioc->admin_req_base) {
2636                         retval = -1;
2637                         goto out_failed;
2638                 }
2639
2640                 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2641                     mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2642                     GFP_KERNEL);
2643
2644                 if (!mrioc->admin_reply_base) {
2645                         retval = -1;
2646                         goto out_failed;
2647                 }
2648         }
2649
2650         num_admin_entries = (mrioc->num_admin_replies << 16) |
2651             (mrioc->num_admin_req);
2652         writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2653         mpi3mr_writeq(mrioc->admin_req_dma,
2654             &mrioc->sysif_regs->admin_request_queue_address);
2655         mpi3mr_writeq(mrioc->admin_reply_dma,
2656             &mrioc->sysif_regs->admin_reply_queue_address);
2657         writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2658         writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2659         return retval;
2660
2661 out_failed:
2662
2663         if (mrioc->admin_reply_base) {
2664                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2665                     mrioc->admin_reply_base, mrioc->admin_reply_dma);
2666                 mrioc->admin_reply_base = NULL;
2667         }
2668         if (mrioc->admin_req_base) {
2669                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2670                     mrioc->admin_req_base, mrioc->admin_req_dma);
2671                 mrioc->admin_req_base = NULL;
2672         }
2673         return retval;
2674 }
2675
2676 /**
2677  * mpi3mr_issue_iocfacts - Send IOC Facts
2678  * @mrioc: Adapter instance reference
2679  * @facts_data: Cached IOC facts data
2680  *
2681  * Issue IOC Facts MPI request through admin queue and wait for
2682  * the completion of it or time out.
2683  *
2684  * Return: 0 on success, non-zero on failures.
2685  */
2686 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2687         struct mpi3_ioc_facts_data *facts_data)
2688 {
2689         struct mpi3_ioc_facts_request iocfacts_req;
2690         void *data = NULL;
2691         dma_addr_t data_dma;
2692         u32 data_len = sizeof(*facts_data);
2693         int retval = 0;
2694         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2695
2696         data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2697             GFP_KERNEL);
2698
2699         if (!data) {
2700                 retval = -1;
2701                 goto out;
2702         }
2703
2704         memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2705         mutex_lock(&mrioc->init_cmds.mutex);
2706         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2707                 retval = -1;
2708                 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2709                 mutex_unlock(&mrioc->init_cmds.mutex);
2710                 goto out;
2711         }
2712         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2713         mrioc->init_cmds.is_waiting = 1;
2714         mrioc->init_cmds.callback = NULL;
2715         iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2716         iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2717
2718         mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2719             data_dma);
2720
2721         init_completion(&mrioc->init_cmds.done);
2722         retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2723             sizeof(iocfacts_req), 1);
2724         if (retval) {
2725                 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
2726                 goto out_unlock;
2727         }
2728         wait_for_completion_timeout(&mrioc->init_cmds.done,
2729             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2730         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2731                 ioc_err(mrioc, "ioc_facts timed out\n");
2732                 mpi3mr_check_rh_fault_ioc(mrioc,
2733                     MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2734                 retval = -1;
2735                 goto out_unlock;
2736         }
2737         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2738             != MPI3_IOCSTATUS_SUCCESS) {
2739                 ioc_err(mrioc,
2740                     "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2741                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2742                     mrioc->init_cmds.ioc_loginfo);
2743                 retval = -1;
2744                 goto out_unlock;
2745         }
2746         memcpy(facts_data, (u8 *)data, data_len);
2747         mpi3mr_process_factsdata(mrioc, facts_data);
2748 out_unlock:
2749         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2750         mutex_unlock(&mrioc->init_cmds.mutex);
2751
2752 out:
2753         if (data)
2754                 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
2755
2756         return retval;
2757 }
2758
2759 /**
2760  * mpi3mr_check_reset_dma_mask - Process IOC facts data
2761  * @mrioc: Adapter instance reference
2762  *
2763  * Check whether the new DMA mask requested through IOCFacts by
2764  * firmware needs to be set, if so set it .
2765  *
2766  * Return: 0 on success, non-zero on failure.
2767  */
2768 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
2769 {
2770         struct pci_dev *pdev = mrioc->pdev;
2771         int r;
2772         u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
2773
2774         if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
2775                 return 0;
2776
2777         ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
2778             mrioc->dma_mask, facts_dma_mask);
2779
2780         r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
2781         if (r) {
2782                 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
2783                     facts_dma_mask, r);
2784                 return r;
2785         }
2786         mrioc->dma_mask = facts_dma_mask;
2787         return r;
2788 }
2789
2790 /**
2791  * mpi3mr_process_factsdata - Process IOC facts data
2792  * @mrioc: Adapter instance reference
2793  * @facts_data: Cached IOC facts data
2794  *
2795  * Convert IOC facts data into cpu endianness and cache it in
2796  * the driver .
2797  *
2798  * Return: Nothing.
2799  */
2800 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
2801         struct mpi3_ioc_facts_data *facts_data)
2802 {
2803         u32 ioc_config, req_sz, facts_flags;
2804
2805         if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
2806             (sizeof(*facts_data) / 4)) {
2807                 ioc_warn(mrioc,
2808                     "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
2809                     sizeof(*facts_data),
2810                     le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
2811         }
2812
2813         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
2814         req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
2815             MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
2816         if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
2817                 ioc_err(mrioc,
2818                     "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
2819                     req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
2820         }
2821
2822         memset(&mrioc->facts, 0, sizeof(mrioc->facts));
2823
2824         facts_flags = le32_to_cpu(facts_data->flags);
2825         mrioc->facts.op_req_sz = req_sz;
2826         mrioc->op_reply_desc_sz = 1 << ((ioc_config &
2827             MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
2828             MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
2829
2830         mrioc->facts.ioc_num = facts_data->ioc_number;
2831         mrioc->facts.who_init = facts_data->who_init;
2832         mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
2833         mrioc->facts.personality = (facts_flags &
2834             MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
2835         mrioc->facts.dma_mask = (facts_flags &
2836             MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
2837             MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
2838         mrioc->facts.protocol_flags = facts_data->protocol_flags;
2839         mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
2840         mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
2841         mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
2842         mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
2843         mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
2844         mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
2845         mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
2846         mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
2847         mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
2848         mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
2849         mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
2850         mrioc->facts.max_pcie_switches =
2851             le16_to_cpu(facts_data->max_pcie_switches);
2852         mrioc->facts.max_sasexpanders =
2853             le16_to_cpu(facts_data->max_sas_expanders);
2854         mrioc->facts.max_sasinitiators =
2855             le16_to_cpu(facts_data->max_sas_initiators);
2856         mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
2857         mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
2858         mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
2859         mrioc->facts.max_op_req_q =
2860             le16_to_cpu(facts_data->max_operational_request_queues);
2861         mrioc->facts.max_op_reply_q =
2862             le16_to_cpu(facts_data->max_operational_reply_queues);
2863         mrioc->facts.ioc_capabilities =
2864             le32_to_cpu(facts_data->ioc_capabilities);
2865         mrioc->facts.fw_ver.build_num =
2866             le16_to_cpu(facts_data->fw_version.build_num);
2867         mrioc->facts.fw_ver.cust_id =
2868             le16_to_cpu(facts_data->fw_version.customer_id);
2869         mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
2870         mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
2871         mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
2872         mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
2873         mrioc->msix_count = min_t(int, mrioc->msix_count,
2874             mrioc->facts.max_msix_vectors);
2875         mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
2876         mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
2877         mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
2878         mrioc->facts.shutdown_timeout =
2879             le16_to_cpu(facts_data->shutdown_timeout);
2880
2881         mrioc->facts.max_dev_per_tg =
2882             facts_data->max_devices_per_throttle_group;
2883         mrioc->facts.io_throttle_data_length =
2884             le16_to_cpu(facts_data->io_throttle_data_length);
2885         mrioc->facts.max_io_throttle_group =
2886             le16_to_cpu(facts_data->max_io_throttle_group);
2887         mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
2888         mrioc->facts.io_throttle_high =
2889             le16_to_cpu(facts_data->io_throttle_high);
2890
2891         /* Store in 512b block count */
2892         if (mrioc->facts.io_throttle_data_length)
2893                 mrioc->io_throttle_data_length =
2894                     (mrioc->facts.io_throttle_data_length * 2 * 4);
2895         else
2896                 /* set the length to 1MB + 1K to disable throttle */
2897                 mrioc->io_throttle_data_length = MPI3MR_MAX_SECTORS + 2;
2898
2899         mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
2900         mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
2901
2902         ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
2903             mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
2904             mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
2905         ioc_info(mrioc,
2906             "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
2907             mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
2908             mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
2909         ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
2910             mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
2911             mrioc->facts.sge_mod_shift);
2912         ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n",
2913             mrioc->facts.dma_mask, (facts_flags &
2914             MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK));
2915         ioc_info(mrioc,
2916             "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
2917             mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
2918         ioc_info(mrioc,
2919            "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
2920            mrioc->facts.io_throttle_data_length * 4,
2921            mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
2922 }
2923
2924 /**
2925  * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
2926  * @mrioc: Adapter instance reference
2927  *
2928  * Allocate and initialize the reply free buffers, sense
2929  * buffers, reply free queue and sense buffer queue.
2930  *
2931  * Return: 0 on success, non-zero on failures.
2932  */
2933 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
2934 {
2935         int retval = 0;
2936         u32 sz, i;
2937
2938         if (mrioc->init_cmds.reply)
2939                 return retval;
2940
2941         mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2942         if (!mrioc->init_cmds.reply)
2943                 goto out_failed;
2944
2945         mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2946         if (!mrioc->bsg_cmds.reply)
2947                 goto out_failed;
2948
2949         mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2950         if (!mrioc->transport_cmds.reply)
2951                 goto out_failed;
2952
2953         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
2954                 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
2955                     GFP_KERNEL);
2956                 if (!mrioc->dev_rmhs_cmds[i].reply)
2957                         goto out_failed;
2958         }
2959
2960         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
2961                 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
2962                     GFP_KERNEL);
2963                 if (!mrioc->evtack_cmds[i].reply)
2964                         goto out_failed;
2965         }
2966
2967         mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2968         if (!mrioc->host_tm_cmds.reply)
2969                 goto out_failed;
2970
2971         mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2972         if (!mrioc->pel_cmds.reply)
2973                 goto out_failed;
2974
2975         mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2976         if (!mrioc->pel_abort_cmd.reply)
2977                 goto out_failed;
2978
2979         mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
2980         mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits,
2981                                                  GFP_KERNEL);
2982         if (!mrioc->removepend_bitmap)
2983                 goto out_failed;
2984
2985         mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL);
2986         if (!mrioc->devrem_bitmap)
2987                 goto out_failed;
2988
2989         mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD,
2990                                                   GFP_KERNEL);
2991         if (!mrioc->evtack_cmds_bitmap)
2992                 goto out_failed;
2993
2994         mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
2995         mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
2996         mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
2997         mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
2998
2999         /* reply buffer pool, 16 byte align */
3000         sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3001         mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
3002             &mrioc->pdev->dev, sz, 16, 0);
3003         if (!mrioc->reply_buf_pool) {
3004                 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
3005                 goto out_failed;
3006         }
3007
3008         mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3009             &mrioc->reply_buf_dma);
3010         if (!mrioc->reply_buf)
3011                 goto out_failed;
3012
3013         mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3014
3015         /* reply free queue, 8 byte align */
3016         sz = mrioc->reply_free_qsz * 8;
3017         mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3018             &mrioc->pdev->dev, sz, 8, 0);
3019         if (!mrioc->reply_free_q_pool) {
3020                 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3021                 goto out_failed;
3022         }
3023         mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3024             GFP_KERNEL, &mrioc->reply_free_q_dma);
3025         if (!mrioc->reply_free_q)
3026                 goto out_failed;
3027
3028         /* sense buffer pool,  4 byte align */
3029         sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3030         mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3031             &mrioc->pdev->dev, sz, 4, 0);
3032         if (!mrioc->sense_buf_pool) {
3033                 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3034                 goto out_failed;
3035         }
3036         mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3037             &mrioc->sense_buf_dma);
3038         if (!mrioc->sense_buf)
3039                 goto out_failed;
3040
3041         /* sense buffer queue, 8 byte align */
3042         sz = mrioc->sense_buf_q_sz * 8;
3043         mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3044             &mrioc->pdev->dev, sz, 8, 0);
3045         if (!mrioc->sense_buf_q_pool) {
3046                 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3047                 goto out_failed;
3048         }
3049         mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3050             GFP_KERNEL, &mrioc->sense_buf_q_dma);
3051         if (!mrioc->sense_buf_q)
3052                 goto out_failed;
3053
3054         return retval;
3055
3056 out_failed:
3057         retval = -1;
3058         return retval;
3059 }
3060
3061 /**
3062  * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3063  * buffers
3064  * @mrioc: Adapter instance reference
3065  *
3066  * Helper function to initialize reply and sense buffers along
3067  * with some debug prints.
3068  *
3069  * Return:  None.
3070  */
3071 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3072 {
3073         u32 sz, i;
3074         dma_addr_t phy_addr;
3075
3076         sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3077         ioc_info(mrioc,
3078             "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3079             mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3080             (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3081         sz = mrioc->reply_free_qsz * 8;
3082         ioc_info(mrioc,
3083             "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3084             mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3085             (unsigned long long)mrioc->reply_free_q_dma);
3086         sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3087         ioc_info(mrioc,
3088             "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3089             mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3090             (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3091         sz = mrioc->sense_buf_q_sz * 8;
3092         ioc_info(mrioc,
3093             "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3094             mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3095             (unsigned long long)mrioc->sense_buf_q_dma);
3096
3097         /* initialize Reply buffer Queue */
3098         for (i = 0, phy_addr = mrioc->reply_buf_dma;
3099             i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3100                 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3101         mrioc->reply_free_q[i] = cpu_to_le64(0);
3102
3103         /* initialize Sense Buffer Queue */
3104         for (i = 0, phy_addr = mrioc->sense_buf_dma;
3105             i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3106                 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3107         mrioc->sense_buf_q[i] = cpu_to_le64(0);
3108 }
3109
3110 /**
3111  * mpi3mr_issue_iocinit - Send IOC Init
3112  * @mrioc: Adapter instance reference
3113  *
3114  * Issue IOC Init MPI request through admin queue and wait for
3115  * the completion of it or time out.
3116  *
3117  * Return: 0 on success, non-zero on failures.
3118  */
3119 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3120 {
3121         struct mpi3_ioc_init_request iocinit_req;
3122         struct mpi3_driver_info_layout *drv_info;
3123         dma_addr_t data_dma;
3124         u32 data_len = sizeof(*drv_info);
3125         int retval = 0;
3126         ktime_t current_time;
3127
3128         drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3129             GFP_KERNEL);
3130         if (!drv_info) {
3131                 retval = -1;
3132                 goto out;
3133         }
3134         mpimr_initialize_reply_sbuf_queues(mrioc);
3135
3136         drv_info->information_length = cpu_to_le32(data_len);
3137         strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3138         strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3139         strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3140         strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3141         strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3142         strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3143             sizeof(drv_info->driver_release_date));
3144         drv_info->driver_capabilities = 0;
3145         memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3146             sizeof(mrioc->driver_info));
3147
3148         memset(&iocinit_req, 0, sizeof(iocinit_req));
3149         mutex_lock(&mrioc->init_cmds.mutex);
3150         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3151                 retval = -1;
3152                 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3153                 mutex_unlock(&mrioc->init_cmds.mutex);
3154                 goto out;
3155         }
3156         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3157         mrioc->init_cmds.is_waiting = 1;
3158         mrioc->init_cmds.callback = NULL;
3159         iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3160         iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3161         iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3162         iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3163         iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3164         iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3165         iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3166         iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3167         iocinit_req.reply_free_queue_address =
3168             cpu_to_le64(mrioc->reply_free_q_dma);
3169         iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3170         iocinit_req.sense_buffer_free_queue_depth =
3171             cpu_to_le16(mrioc->sense_buf_q_sz);
3172         iocinit_req.sense_buffer_free_queue_address =
3173             cpu_to_le64(mrioc->sense_buf_q_dma);
3174         iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3175
3176         current_time = ktime_get_real();
3177         iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3178
3179         init_completion(&mrioc->init_cmds.done);
3180         retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3181             sizeof(iocinit_req), 1);
3182         if (retval) {
3183                 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3184                 goto out_unlock;
3185         }
3186         wait_for_completion_timeout(&mrioc->init_cmds.done,
3187             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3188         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3189                 mpi3mr_check_rh_fault_ioc(mrioc,
3190                     MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3191                 ioc_err(mrioc, "ioc_init timed out\n");
3192                 retval = -1;
3193                 goto out_unlock;
3194         }
3195         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3196             != MPI3_IOCSTATUS_SUCCESS) {
3197                 ioc_err(mrioc,
3198                     "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3199                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3200                     mrioc->init_cmds.ioc_loginfo);
3201                 retval = -1;
3202                 goto out_unlock;
3203         }
3204
3205         mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3206         writel(mrioc->reply_free_queue_host_index,
3207             &mrioc->sysif_regs->reply_free_host_index);
3208
3209         mrioc->sbq_host_index = mrioc->num_sense_bufs;
3210         writel(mrioc->sbq_host_index,
3211             &mrioc->sysif_regs->sense_buffer_free_host_index);
3212 out_unlock:
3213         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3214         mutex_unlock(&mrioc->init_cmds.mutex);
3215
3216 out:
3217         if (drv_info)
3218                 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3219                     data_dma);
3220
3221         return retval;
3222 }
3223
3224 /**
3225  * mpi3mr_unmask_events - Unmask events in event mask bitmap
3226  * @mrioc: Adapter instance reference
3227  * @event: MPI event ID
3228  *
3229  * Un mask the specific event by resetting the event_mask
3230  * bitmap.
3231  *
3232  * Return: 0 on success, non-zero on failures.
3233  */
3234 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3235 {
3236         u32 desired_event;
3237         u8 word;
3238
3239         if (event >= 128)
3240                 return;
3241
3242         desired_event = (1 << (event % 32));
3243         word = event / 32;
3244
3245         mrioc->event_masks[word] &= ~desired_event;
3246 }
3247
3248 /**
3249  * mpi3mr_issue_event_notification - Send event notification
3250  * @mrioc: Adapter instance reference
3251  *
3252  * Issue event notification MPI request through admin queue and
3253  * wait for the completion of it or time out.
3254  *
3255  * Return: 0 on success, non-zero on failures.
3256  */
3257 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3258 {
3259         struct mpi3_event_notification_request evtnotify_req;
3260         int retval = 0;
3261         u8 i;
3262
3263         memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3264         mutex_lock(&mrioc->init_cmds.mutex);
3265         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3266                 retval = -1;
3267                 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3268                 mutex_unlock(&mrioc->init_cmds.mutex);
3269                 goto out;
3270         }
3271         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3272         mrioc->init_cmds.is_waiting = 1;
3273         mrioc->init_cmds.callback = NULL;
3274         evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3275         evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3276         for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3277                 evtnotify_req.event_masks[i] =
3278                     cpu_to_le32(mrioc->event_masks[i]);
3279         init_completion(&mrioc->init_cmds.done);
3280         retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3281             sizeof(evtnotify_req), 1);
3282         if (retval) {
3283                 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3284                 goto out_unlock;
3285         }
3286         wait_for_completion_timeout(&mrioc->init_cmds.done,
3287             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3288         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3289                 ioc_err(mrioc, "event notification timed out\n");
3290                 mpi3mr_check_rh_fault_ioc(mrioc,
3291                     MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3292                 retval = -1;
3293                 goto out_unlock;
3294         }
3295         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3296             != MPI3_IOCSTATUS_SUCCESS) {
3297                 ioc_err(mrioc,
3298                     "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3299                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3300                     mrioc->init_cmds.ioc_loginfo);
3301                 retval = -1;
3302                 goto out_unlock;
3303         }
3304
3305 out_unlock:
3306         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3307         mutex_unlock(&mrioc->init_cmds.mutex);
3308 out:
3309         return retval;
3310 }
3311
3312 /**
3313  * mpi3mr_process_event_ack - Process event acknowledgment
3314  * @mrioc: Adapter instance reference
3315  * @event: MPI3 event ID
3316  * @event_ctx: event context
3317  *
3318  * Send event acknowledgment through admin queue and wait for
3319  * it to complete.
3320  *
3321  * Return: 0 on success, non-zero on failures.
3322  */
3323 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3324         u32 event_ctx)
3325 {
3326         struct mpi3_event_ack_request evtack_req;
3327         int retval = 0;
3328
3329         memset(&evtack_req, 0, sizeof(evtack_req));
3330         mutex_lock(&mrioc->init_cmds.mutex);
3331         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3332                 retval = -1;
3333                 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3334                 mutex_unlock(&mrioc->init_cmds.mutex);
3335                 goto out;
3336         }
3337         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3338         mrioc->init_cmds.is_waiting = 1;
3339         mrioc->init_cmds.callback = NULL;
3340         evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3341         evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3342         evtack_req.event = event;
3343         evtack_req.event_context = cpu_to_le32(event_ctx);
3344
3345         init_completion(&mrioc->init_cmds.done);
3346         retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3347             sizeof(evtack_req), 1);
3348         if (retval) {
3349                 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3350                 goto out_unlock;
3351         }
3352         wait_for_completion_timeout(&mrioc->init_cmds.done,
3353             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3354         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3355                 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3356                 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3357                         mpi3mr_soft_reset_handler(mrioc,
3358                             MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1);
3359                 retval = -1;
3360                 goto out_unlock;
3361         }
3362         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3363             != MPI3_IOCSTATUS_SUCCESS) {
3364                 ioc_err(mrioc,
3365                     "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3366                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3367                     mrioc->init_cmds.ioc_loginfo);
3368                 retval = -1;
3369                 goto out_unlock;
3370         }
3371
3372 out_unlock:
3373         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3374         mutex_unlock(&mrioc->init_cmds.mutex);
3375 out:
3376         return retval;
3377 }
3378
3379 /**
3380  * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3381  * @mrioc: Adapter instance reference
3382  *
3383  * Allocate chain buffers and set a bitmap to indicate free
3384  * chain buffers. Chain buffers are used to pass the SGE
3385  * information along with MPI3 SCSI IO requests for host I/O.
3386  *
3387  * Return: 0 on success, non-zero on failure
3388  */
3389 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3390 {
3391         int retval = 0;
3392         u32 sz, i;
3393         u16 num_chains;
3394
3395         if (mrioc->chain_sgl_list)
3396                 return retval;
3397
3398         num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3399
3400         if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3401             | SHOST_DIX_TYPE1_PROTECTION
3402             | SHOST_DIX_TYPE2_PROTECTION
3403             | SHOST_DIX_TYPE3_PROTECTION))
3404                 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3405
3406         mrioc->chain_buf_count = num_chains;
3407         sz = sizeof(struct chain_element) * num_chains;
3408         mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3409         if (!mrioc->chain_sgl_list)
3410                 goto out_failed;
3411
3412         sz = MPI3MR_PAGE_SIZE_4K;
3413         mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3414             &mrioc->pdev->dev, sz, 16, 0);
3415         if (!mrioc->chain_buf_pool) {
3416                 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3417                 goto out_failed;
3418         }
3419
3420         for (i = 0; i < num_chains; i++) {
3421                 mrioc->chain_sgl_list[i].addr =
3422                     dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3423                     &mrioc->chain_sgl_list[i].dma_addr);
3424
3425                 if (!mrioc->chain_sgl_list[i].addr)
3426                         goto out_failed;
3427         }
3428         mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL);
3429         if (!mrioc->chain_bitmap)
3430                 goto out_failed;
3431         return retval;
3432 out_failed:
3433         retval = -1;
3434         return retval;
3435 }
3436
3437 /**
3438  * mpi3mr_port_enable_complete - Mark port enable complete
3439  * @mrioc: Adapter instance reference
3440  * @drv_cmd: Internal command tracker
3441  *
3442  * Call back for asynchronous port enable request sets the
3443  * driver command to indicate port enable request is complete.
3444  *
3445  * Return: Nothing
3446  */
3447 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3448         struct mpi3mr_drv_cmd *drv_cmd)
3449 {
3450         drv_cmd->callback = NULL;
3451         mrioc->scan_started = 0;
3452         if (drv_cmd->state & MPI3MR_CMD_RESET)
3453                 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3454         else
3455                 mrioc->scan_failed = drv_cmd->ioc_status;
3456         drv_cmd->state = MPI3MR_CMD_NOTUSED;
3457 }
3458
3459 /**
3460  * mpi3mr_issue_port_enable - Issue Port Enable
3461  * @mrioc: Adapter instance reference
3462  * @async: Flag to wait for completion or not
3463  *
3464  * Issue Port Enable MPI request through admin queue and if the
3465  * async flag is not set wait for the completion of the port
3466  * enable or time out.
3467  *
3468  * Return: 0 on success, non-zero on failures.
3469  */
3470 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3471 {
3472         struct mpi3_port_enable_request pe_req;
3473         int retval = 0;
3474         u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3475
3476         memset(&pe_req, 0, sizeof(pe_req));
3477         mutex_lock(&mrioc->init_cmds.mutex);
3478         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3479                 retval = -1;
3480                 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3481                 mutex_unlock(&mrioc->init_cmds.mutex);
3482                 goto out;
3483         }
3484         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3485         if (async) {
3486                 mrioc->init_cmds.is_waiting = 0;
3487                 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3488         } else {
3489                 mrioc->init_cmds.is_waiting = 1;
3490                 mrioc->init_cmds.callback = NULL;
3491                 init_completion(&mrioc->init_cmds.done);
3492         }
3493         pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3494         pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3495
3496         retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3497         if (retval) {
3498                 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3499                 goto out_unlock;
3500         }
3501         if (async) {
3502                 mutex_unlock(&mrioc->init_cmds.mutex);
3503                 goto out;
3504         }
3505
3506         wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3507         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3508                 ioc_err(mrioc, "port enable timed out\n");
3509                 retval = -1;
3510                 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3511                 goto out_unlock;
3512         }
3513         mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3514
3515 out_unlock:
3516         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3517         mutex_unlock(&mrioc->init_cmds.mutex);
3518 out:
3519         return retval;
3520 }
3521
3522 /* Protocol type to name mapper structure */
3523 static const struct {
3524         u8 protocol;
3525         char *name;
3526 } mpi3mr_protocols[] = {
3527         { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3528         { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3529         { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3530 };
3531
3532 /* Capability to name mapper structure*/
3533 static const struct {
3534         u32 capability;
3535         char *name;
3536 } mpi3mr_capabilities[] = {
3537         { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" },
3538         { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" },
3539 };
3540
3541 /**
3542  * mpi3mr_print_ioc_info - Display controller information
3543  * @mrioc: Adapter instance reference
3544  *
3545  * Display controller personalit, capability, supported
3546  * protocols etc.
3547  *
3548  * Return: Nothing
3549  */
3550 static void
3551 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3552 {
3553         int i = 0, bytes_written = 0;
3554         char personality[16];
3555         char protocol[50] = {0};
3556         char capabilities[100] = {0};
3557         struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3558
3559         switch (mrioc->facts.personality) {
3560         case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3561                 strncpy(personality, "Enhanced HBA", sizeof(personality));
3562                 break;
3563         case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3564                 strncpy(personality, "RAID", sizeof(personality));
3565                 break;
3566         default:
3567                 strncpy(personality, "Unknown", sizeof(personality));
3568                 break;
3569         }
3570
3571         ioc_info(mrioc, "Running in %s Personality", personality);
3572
3573         ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3574             fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3575             fwver->ph_minor, fwver->cust_id, fwver->build_num);
3576
3577         for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3578                 if (mrioc->facts.protocol_flags &
3579                     mpi3mr_protocols[i].protocol) {
3580                         bytes_written += scnprintf(protocol + bytes_written,
3581                                     sizeof(protocol) - bytes_written, "%s%s",
3582                                     bytes_written ? "," : "",
3583                                     mpi3mr_protocols[i].name);
3584                 }
3585         }
3586
3587         bytes_written = 0;
3588         for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3589                 if (mrioc->facts.protocol_flags &
3590                     mpi3mr_capabilities[i].capability) {
3591                         bytes_written += scnprintf(capabilities + bytes_written,
3592                                     sizeof(capabilities) - bytes_written, "%s%s",
3593                                     bytes_written ? "," : "",
3594                                     mpi3mr_capabilities[i].name);
3595                 }
3596         }
3597
3598         ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
3599                  protocol, capabilities);
3600 }
3601
3602 /**
3603  * mpi3mr_cleanup_resources - Free PCI resources
3604  * @mrioc: Adapter instance reference
3605  *
3606  * Unmap PCI device memory and disable PCI device.
3607  *
3608  * Return: 0 on success and non-zero on failure.
3609  */
3610 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
3611 {
3612         struct pci_dev *pdev = mrioc->pdev;
3613
3614         mpi3mr_cleanup_isr(mrioc);
3615
3616         if (mrioc->sysif_regs) {
3617                 iounmap((void __iomem *)mrioc->sysif_regs);
3618                 mrioc->sysif_regs = NULL;
3619         }
3620
3621         if (pci_is_enabled(pdev)) {
3622                 if (mrioc->bars)
3623                         pci_release_selected_regions(pdev, mrioc->bars);
3624                 pci_disable_device(pdev);
3625         }
3626 }
3627
3628 /**
3629  * mpi3mr_setup_resources - Enable PCI resources
3630  * @mrioc: Adapter instance reference
3631  *
3632  * Enable PCI device memory, MSI-x registers and set DMA mask.
3633  *
3634  * Return: 0 on success and non-zero on failure.
3635  */
3636 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
3637 {
3638         struct pci_dev *pdev = mrioc->pdev;
3639         u32 memap_sz = 0;
3640         int i, retval = 0, capb = 0;
3641         u16 message_control;
3642         u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
3643             ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
3644
3645         if (pci_enable_device_mem(pdev)) {
3646                 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
3647                 retval = -ENODEV;
3648                 goto out_failed;
3649         }
3650
3651         capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3652         if (!capb) {
3653                 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
3654                 retval = -ENODEV;
3655                 goto out_failed;
3656         }
3657         mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3658
3659         if (pci_request_selected_regions(pdev, mrioc->bars,
3660             mrioc->driver_name)) {
3661                 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
3662                 retval = -ENODEV;
3663                 goto out_failed;
3664         }
3665
3666         for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
3667                 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3668                         mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
3669                         memap_sz = pci_resource_len(pdev, i);
3670                         mrioc->sysif_regs =
3671                             ioremap(mrioc->sysif_regs_phys, memap_sz);
3672                         break;
3673                 }
3674         }
3675
3676         pci_set_master(pdev);
3677
3678         retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
3679         if (retval) {
3680                 if (dma_mask != DMA_BIT_MASK(32)) {
3681                         ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
3682                         dma_mask = DMA_BIT_MASK(32);
3683                         retval = dma_set_mask_and_coherent(&pdev->dev,
3684                             dma_mask);
3685                 }
3686                 if (retval) {
3687                         mrioc->dma_mask = 0;
3688                         ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
3689                         goto out_failed;
3690                 }
3691         }
3692         mrioc->dma_mask = dma_mask;
3693
3694         if (!mrioc->sysif_regs) {
3695                 ioc_err(mrioc,
3696                     "Unable to map adapter memory or resource not found\n");
3697                 retval = -EINVAL;
3698                 goto out_failed;
3699         }
3700
3701         pci_read_config_word(pdev, capb + 2, &message_control);
3702         mrioc->msix_count = (message_control & 0x3FF) + 1;
3703
3704         pci_save_state(pdev);
3705
3706         pci_set_drvdata(pdev, mrioc->shost);
3707
3708         mpi3mr_ioc_disable_intr(mrioc);
3709
3710         ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
3711             (unsigned long long)mrioc->sysif_regs_phys,
3712             mrioc->sysif_regs, memap_sz);
3713         ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
3714             mrioc->msix_count);
3715
3716         if (!reset_devices && poll_queues > 0)
3717                 mrioc->requested_poll_qcount = min_t(int, poll_queues,
3718                                 mrioc->msix_count - 2);
3719         return retval;
3720
3721 out_failed:
3722         mpi3mr_cleanup_resources(mrioc);
3723         return retval;
3724 }
3725
3726 /**
3727  * mpi3mr_enable_events - Enable required events
3728  * @mrioc: Adapter instance reference
3729  *
3730  * This routine unmasks the events required by the driver by
3731  * sennding appropriate event mask bitmapt through an event
3732  * notification request.
3733  *
3734  * Return: 0 on success and non-zero on failure.
3735  */
3736 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
3737 {
3738         int retval = 0;
3739         u32  i;
3740
3741         for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3742                 mrioc->event_masks[i] = -1;
3743
3744         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
3745         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
3746         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
3747         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
3748         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
3749         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
3750         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
3751         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
3752         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
3753         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
3754         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
3755         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
3756         mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
3757         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
3758
3759         retval = mpi3mr_issue_event_notification(mrioc);
3760         if (retval)
3761                 ioc_err(mrioc, "failed to issue event notification %d\n",
3762                     retval);
3763         return retval;
3764 }
3765
3766 /**
3767  * mpi3mr_init_ioc - Initialize the controller
3768  * @mrioc: Adapter instance reference
3769  *
3770  * This the controller initialization routine, executed either
3771  * after soft reset or from pci probe callback.
3772  * Setup the required resources, memory map the controller
3773  * registers, create admin and operational reply queue pairs,
3774  * allocate required memory for reply pool, sense buffer pool,
3775  * issue IOC init request to the firmware, unmask the events and
3776  * issue port enable to discover SAS/SATA/NVMe devies and RAID
3777  * volumes.
3778  *
3779  * Return: 0 on success and non-zero on failure.
3780  */
3781 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
3782 {
3783         int retval = 0;
3784         u8 retry = 0;
3785         struct mpi3_ioc_facts_data facts_data;
3786         u32 sz;
3787
3788 retry_init:
3789         retval = mpi3mr_bring_ioc_ready(mrioc);
3790         if (retval) {
3791                 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
3792                     retval);
3793                 goto out_failed_noretry;
3794         }
3795
3796         retval = mpi3mr_setup_isr(mrioc, 1);
3797         if (retval) {
3798                 ioc_err(mrioc, "Failed to setup ISR error %d\n",
3799                     retval);
3800                 goto out_failed_noretry;
3801         }
3802
3803         retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3804         if (retval) {
3805                 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
3806                     retval);
3807                 goto out_failed;
3808         }
3809
3810         mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
3811
3812         mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
3813         atomic_set(&mrioc->pend_large_data_sz, 0);
3814
3815         if (reset_devices)
3816                 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
3817                     MPI3MR_HOST_IOS_KDUMP);
3818
3819         if (!(mrioc->facts.ioc_capabilities &
3820             MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) {
3821                 mrioc->sas_transport_enabled = 1;
3822                 mrioc->scsi_device_channel = 1;
3823                 mrioc->shost->max_channel = 1;
3824                 mrioc->shost->transportt = mpi3mr_transport_template;
3825         }
3826
3827         mrioc->reply_sz = mrioc->facts.reply_sz;
3828
3829         retval = mpi3mr_check_reset_dma_mask(mrioc);
3830         if (retval) {
3831                 ioc_err(mrioc, "Resetting dma mask failed %d\n",
3832                     retval);
3833                 goto out_failed_noretry;
3834         }
3835
3836         mpi3mr_print_ioc_info(mrioc);
3837
3838         if (!mrioc->cfg_page) {
3839                 dprint_init(mrioc, "allocating config page buffers\n");
3840                 mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ;
3841                 mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev,
3842                     mrioc->cfg_page_sz, &mrioc->cfg_page_dma, GFP_KERNEL);
3843                 if (!mrioc->cfg_page) {
3844                         retval = -1;
3845                         goto out_failed_noretry;
3846                 }
3847         }
3848
3849         if (!mrioc->init_cmds.reply) {
3850                 retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
3851                 if (retval) {
3852                         ioc_err(mrioc,
3853                             "%s :Failed to allocated reply sense buffers %d\n",
3854                             __func__, retval);
3855                         goto out_failed_noretry;
3856                 }
3857         }
3858
3859         if (!mrioc->chain_sgl_list) {
3860                 retval = mpi3mr_alloc_chain_bufs(mrioc);
3861                 if (retval) {
3862                         ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
3863                             retval);
3864                         goto out_failed_noretry;
3865                 }
3866         }
3867
3868         retval = mpi3mr_issue_iocinit(mrioc);
3869         if (retval) {
3870                 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
3871                     retval);
3872                 goto out_failed;
3873         }
3874
3875         retval = mpi3mr_print_pkg_ver(mrioc);
3876         if (retval) {
3877                 ioc_err(mrioc, "failed to get package version\n");
3878                 goto out_failed;
3879         }
3880
3881         retval = mpi3mr_setup_isr(mrioc, 0);
3882         if (retval) {
3883                 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
3884                     retval);
3885                 goto out_failed_noretry;
3886         }
3887
3888         retval = mpi3mr_create_op_queues(mrioc);
3889         if (retval) {
3890                 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
3891                     retval);
3892                 goto out_failed;
3893         }
3894
3895         if (!mrioc->pel_seqnum_virt) {
3896                 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
3897                 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
3898                 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
3899                     mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
3900                     GFP_KERNEL);
3901                 if (!mrioc->pel_seqnum_virt) {
3902                         retval = -ENOMEM;
3903                         goto out_failed_noretry;
3904                 }
3905         }
3906
3907         if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
3908                 dprint_init(mrioc, "allocating memory for throttle groups\n");
3909                 sz = sizeof(struct mpi3mr_throttle_group_info);
3910                 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
3911                 if (!mrioc->throttle_groups) {
3912                         retval = -1;
3913                         goto out_failed_noretry;
3914                 }
3915         }
3916
3917         retval = mpi3mr_enable_events(mrioc);
3918         if (retval) {
3919                 ioc_err(mrioc, "failed to enable events %d\n",
3920                     retval);
3921                 goto out_failed;
3922         }
3923
3924         ioc_info(mrioc, "controller initialization completed successfully\n");
3925         return retval;
3926 out_failed:
3927         if (retry < 2) {
3928                 retry++;
3929                 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
3930                     retry);
3931                 mpi3mr_memset_buffers(mrioc);
3932                 goto retry_init;
3933         }
3934         retval = -1;
3935 out_failed_noretry:
3936         ioc_err(mrioc, "controller initialization failed\n");
3937         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
3938             MPI3MR_RESET_FROM_CTLR_CLEANUP);
3939         mrioc->unrecoverable = 1;
3940         return retval;
3941 }
3942
3943 /**
3944  * mpi3mr_reinit_ioc - Re-Initialize the controller
3945  * @mrioc: Adapter instance reference
3946  * @is_resume: Called from resume or reset path
3947  *
3948  * This the controller re-initialization routine, executed from
3949  * the soft reset handler or resume callback. Creates
3950  * operational reply queue pairs, allocate required memory for
3951  * reply pool, sense buffer pool, issue IOC init request to the
3952  * firmware, unmask the events and issue port enable to discover
3953  * SAS/SATA/NVMe devices and RAID volumes.
3954  *
3955  * Return: 0 on success and non-zero on failure.
3956  */
3957 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
3958 {
3959         int retval = 0;
3960         u8 retry = 0;
3961         struct mpi3_ioc_facts_data facts_data;
3962         u32 pe_timeout, ioc_status;
3963
3964 retry_init:
3965         pe_timeout =
3966             (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
3967
3968         dprint_reset(mrioc, "bringing up the controller to ready state\n");
3969         retval = mpi3mr_bring_ioc_ready(mrioc);
3970         if (retval) {
3971                 ioc_err(mrioc, "failed to bring to ready state\n");
3972                 goto out_failed_noretry;
3973         }
3974
3975         if (is_resume) {
3976                 dprint_reset(mrioc, "setting up single ISR\n");
3977                 retval = mpi3mr_setup_isr(mrioc, 1);
3978                 if (retval) {
3979                         ioc_err(mrioc, "failed to setup ISR\n");
3980                         goto out_failed_noretry;
3981                 }
3982         } else
3983                 mpi3mr_ioc_enable_intr(mrioc);
3984
3985         dprint_reset(mrioc, "getting ioc_facts\n");
3986         retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3987         if (retval) {
3988                 ioc_err(mrioc, "failed to get ioc_facts\n");
3989                 goto out_failed;
3990         }
3991
3992         dprint_reset(mrioc, "validating ioc_facts\n");
3993         retval = mpi3mr_revalidate_factsdata(mrioc);
3994         if (retval) {
3995                 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
3996                 goto out_failed_noretry;
3997         }
3998
3999         mpi3mr_print_ioc_info(mrioc);
4000
4001         dprint_reset(mrioc, "sending ioc_init\n");
4002         retval = mpi3mr_issue_iocinit(mrioc);
4003         if (retval) {
4004                 ioc_err(mrioc, "failed to send ioc_init\n");
4005                 goto out_failed;
4006         }
4007
4008         dprint_reset(mrioc, "getting package version\n");
4009         retval = mpi3mr_print_pkg_ver(mrioc);
4010         if (retval) {
4011                 ioc_err(mrioc, "failed to get package version\n");
4012                 goto out_failed;
4013         }
4014
4015         if (is_resume) {
4016                 dprint_reset(mrioc, "setting up multiple ISR\n");
4017                 retval = mpi3mr_setup_isr(mrioc, 0);
4018                 if (retval) {
4019                         ioc_err(mrioc, "failed to re-setup ISR\n");
4020                         goto out_failed_noretry;
4021                 }
4022         }
4023
4024         dprint_reset(mrioc, "creating operational queue pairs\n");
4025         retval = mpi3mr_create_op_queues(mrioc);
4026         if (retval) {
4027                 ioc_err(mrioc, "failed to create operational queue pairs\n");
4028                 goto out_failed;
4029         }
4030
4031         if (!mrioc->pel_seqnum_virt) {
4032                 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4033                 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4034                 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4035                     mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4036                     GFP_KERNEL);
4037                 if (!mrioc->pel_seqnum_virt) {
4038                         retval = -ENOMEM;
4039                         goto out_failed_noretry;
4040                 }
4041         }
4042
4043         if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4044                 ioc_err(mrioc,
4045                     "cannot create minimum number of operational queues expected:%d created:%d\n",
4046                     mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4047                 retval = -1;
4048                 goto out_failed_noretry;
4049         }
4050
4051         dprint_reset(mrioc, "enabling events\n");
4052         retval = mpi3mr_enable_events(mrioc);
4053         if (retval) {
4054                 ioc_err(mrioc, "failed to enable events\n");
4055                 goto out_failed;
4056         }
4057
4058         mrioc->device_refresh_on = 1;
4059         mpi3mr_add_event_wait_for_device_refresh(mrioc);
4060
4061         ioc_info(mrioc, "sending port enable\n");
4062         retval = mpi3mr_issue_port_enable(mrioc, 1);
4063         if (retval) {
4064                 ioc_err(mrioc, "failed to issue port enable\n");
4065                 goto out_failed;
4066         }
4067         do {
4068                 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4069                 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4070                         break;
4071                 if (!pci_device_is_present(mrioc->pdev))
4072                         mrioc->unrecoverable = 1;
4073                 if (mrioc->unrecoverable) {
4074                         retval = -1;
4075                         goto out_failed_noretry;
4076                 }
4077                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4078                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4079                     (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4080                         mpi3mr_print_fault_info(mrioc);
4081                         mrioc->init_cmds.is_waiting = 0;
4082                         mrioc->init_cmds.callback = NULL;
4083                         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4084                         goto out_failed;
4085                 }
4086         } while (--pe_timeout);
4087
4088         if (!pe_timeout) {
4089                 ioc_err(mrioc, "port enable timed out\n");
4090                 mpi3mr_check_rh_fault_ioc(mrioc,
4091                     MPI3MR_RESET_FROM_PE_TIMEOUT);
4092                 mrioc->init_cmds.is_waiting = 0;
4093                 mrioc->init_cmds.callback = NULL;
4094                 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4095                 goto out_failed;
4096         } else if (mrioc->scan_failed) {
4097                 ioc_err(mrioc,
4098                     "port enable failed with status=0x%04x\n",
4099                     mrioc->scan_failed);
4100         } else
4101                 ioc_info(mrioc, "port enable completed successfully\n");
4102
4103         ioc_info(mrioc, "controller %s completed successfully\n",
4104             (is_resume)?"resume":"re-initialization");
4105         return retval;
4106 out_failed:
4107         if (retry < 2) {
4108                 retry++;
4109                 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4110                     (is_resume)?"resume":"re-initialization", retry);
4111                 mpi3mr_memset_buffers(mrioc);
4112                 goto retry_init;
4113         }
4114         retval = -1;
4115 out_failed_noretry:
4116         ioc_err(mrioc, "controller %s is failed\n",
4117             (is_resume)?"resume":"re-initialization");
4118         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4119             MPI3MR_RESET_FROM_CTLR_CLEANUP);
4120         mrioc->unrecoverable = 1;
4121         return retval;
4122 }
4123
4124 /**
4125  * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4126  *                                      segments
4127  * @mrioc: Adapter instance reference
4128  * @qidx: Operational reply queue index
4129  *
4130  * Return: Nothing.
4131  */
4132 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4133 {
4134         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4135         struct segments *segments;
4136         int i, size;
4137
4138         if (!op_reply_q->q_segments)
4139                 return;
4140
4141         size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4142         segments = op_reply_q->q_segments;
4143         for (i = 0; i < op_reply_q->num_segments; i++)
4144                 memset(segments[i].segment, 0, size);
4145 }
4146
4147 /**
4148  * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4149  *                                      segments
4150  * @mrioc: Adapter instance reference
4151  * @qidx: Operational request queue index
4152  *
4153  * Return: Nothing.
4154  */
4155 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4156 {
4157         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4158         struct segments *segments;
4159         int i, size;
4160
4161         if (!op_req_q->q_segments)
4162                 return;
4163
4164         size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4165         segments = op_req_q->q_segments;
4166         for (i = 0; i < op_req_q->num_segments; i++)
4167                 memset(segments[i].segment, 0, size);
4168 }
4169
4170 /**
4171  * mpi3mr_memset_buffers - memset memory for a controller
4172  * @mrioc: Adapter instance reference
4173  *
4174  * clear all the memory allocated for a controller, typically
4175  * called post reset to reuse the memory allocated during the
4176  * controller init.
4177  *
4178  * Return: Nothing.
4179  */
4180 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4181 {
4182         u16 i;
4183         struct mpi3mr_throttle_group_info *tg;
4184
4185         mrioc->change_count = 0;
4186         mrioc->active_poll_qcount = 0;
4187         mrioc->default_qcount = 0;
4188         if (mrioc->admin_req_base)
4189                 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4190         if (mrioc->admin_reply_base)
4191                 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4192         atomic_set(&mrioc->admin_reply_q_in_use, 0);
4193
4194         if (mrioc->init_cmds.reply) {
4195                 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4196                 memset(mrioc->bsg_cmds.reply, 0,
4197                     sizeof(*mrioc->bsg_cmds.reply));
4198                 memset(mrioc->host_tm_cmds.reply, 0,
4199                     sizeof(*mrioc->host_tm_cmds.reply));
4200                 memset(mrioc->pel_cmds.reply, 0,
4201                     sizeof(*mrioc->pel_cmds.reply));
4202                 memset(mrioc->pel_abort_cmd.reply, 0,
4203                     sizeof(*mrioc->pel_abort_cmd.reply));
4204                 memset(mrioc->transport_cmds.reply, 0,
4205                     sizeof(*mrioc->transport_cmds.reply));
4206                 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4207                         memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4208                             sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4209                 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4210                         memset(mrioc->evtack_cmds[i].reply, 0,
4211                             sizeof(*mrioc->evtack_cmds[i].reply));
4212                 bitmap_clear(mrioc->removepend_bitmap, 0,
4213                              mrioc->dev_handle_bitmap_bits);
4214                 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4215                 bitmap_clear(mrioc->evtack_cmds_bitmap, 0,
4216                              MPI3MR_NUM_EVTACKCMD);
4217         }
4218
4219         for (i = 0; i < mrioc->num_queues; i++) {
4220                 mrioc->op_reply_qinfo[i].qid = 0;
4221                 mrioc->op_reply_qinfo[i].ci = 0;
4222                 mrioc->op_reply_qinfo[i].num_replies = 0;
4223                 mrioc->op_reply_qinfo[i].ephase = 0;
4224                 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4225                 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4226                 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4227
4228                 mrioc->req_qinfo[i].ci = 0;
4229                 mrioc->req_qinfo[i].pi = 0;
4230                 mrioc->req_qinfo[i].num_requests = 0;
4231                 mrioc->req_qinfo[i].qid = 0;
4232                 mrioc->req_qinfo[i].reply_qid = 0;
4233                 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4234                 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4235         }
4236
4237         atomic_set(&mrioc->pend_large_data_sz, 0);
4238         if (mrioc->throttle_groups) {
4239                 tg = mrioc->throttle_groups;
4240                 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4241                         tg->id = 0;
4242                         tg->fw_qd = 0;
4243                         tg->modified_qd = 0;
4244                         tg->io_divert = 0;
4245                         tg->need_qd_reduction = 0;
4246                         tg->high = 0;
4247                         tg->low = 0;
4248                         tg->qd_reduction = 0;
4249                         atomic_set(&tg->pend_large_data_sz, 0);
4250                 }
4251         }
4252 }
4253
4254 /**
4255  * mpi3mr_free_mem - Free memory allocated for a controller
4256  * @mrioc: Adapter instance reference
4257  *
4258  * Free all the memory allocated for a controller.
4259  *
4260  * Return: Nothing.
4261  */
4262 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4263 {
4264         u16 i;
4265         struct mpi3mr_intr_info *intr_info;
4266
4267         mpi3mr_free_enclosure_list(mrioc);
4268
4269         if (mrioc->sense_buf_pool) {
4270                 if (mrioc->sense_buf)
4271                         dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4272                             mrioc->sense_buf_dma);
4273                 dma_pool_destroy(mrioc->sense_buf_pool);
4274                 mrioc->sense_buf = NULL;
4275                 mrioc->sense_buf_pool = NULL;
4276         }
4277         if (mrioc->sense_buf_q_pool) {
4278                 if (mrioc->sense_buf_q)
4279                         dma_pool_free(mrioc->sense_buf_q_pool,
4280                             mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4281                 dma_pool_destroy(mrioc->sense_buf_q_pool);
4282                 mrioc->sense_buf_q = NULL;
4283                 mrioc->sense_buf_q_pool = NULL;
4284         }
4285
4286         if (mrioc->reply_buf_pool) {
4287                 if (mrioc->reply_buf)
4288                         dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4289                             mrioc->reply_buf_dma);
4290                 dma_pool_destroy(mrioc->reply_buf_pool);
4291                 mrioc->reply_buf = NULL;
4292                 mrioc->reply_buf_pool = NULL;
4293         }
4294         if (mrioc->reply_free_q_pool) {
4295                 if (mrioc->reply_free_q)
4296                         dma_pool_free(mrioc->reply_free_q_pool,
4297                             mrioc->reply_free_q, mrioc->reply_free_q_dma);
4298                 dma_pool_destroy(mrioc->reply_free_q_pool);
4299                 mrioc->reply_free_q = NULL;
4300                 mrioc->reply_free_q_pool = NULL;
4301         }
4302
4303         for (i = 0; i < mrioc->num_op_req_q; i++)
4304                 mpi3mr_free_op_req_q_segments(mrioc, i);
4305
4306         for (i = 0; i < mrioc->num_op_reply_q; i++)
4307                 mpi3mr_free_op_reply_q_segments(mrioc, i);
4308
4309         for (i = 0; i < mrioc->intr_info_count; i++) {
4310                 intr_info = mrioc->intr_info + i;
4311                 intr_info->op_reply_q = NULL;
4312         }
4313
4314         kfree(mrioc->req_qinfo);
4315         mrioc->req_qinfo = NULL;
4316         mrioc->num_op_req_q = 0;
4317
4318         kfree(mrioc->op_reply_qinfo);
4319         mrioc->op_reply_qinfo = NULL;
4320         mrioc->num_op_reply_q = 0;
4321
4322         kfree(mrioc->init_cmds.reply);
4323         mrioc->init_cmds.reply = NULL;
4324
4325         kfree(mrioc->bsg_cmds.reply);
4326         mrioc->bsg_cmds.reply = NULL;
4327
4328         kfree(mrioc->host_tm_cmds.reply);
4329         mrioc->host_tm_cmds.reply = NULL;
4330
4331         kfree(mrioc->pel_cmds.reply);
4332         mrioc->pel_cmds.reply = NULL;
4333
4334         kfree(mrioc->pel_abort_cmd.reply);
4335         mrioc->pel_abort_cmd.reply = NULL;
4336
4337         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4338                 kfree(mrioc->evtack_cmds[i].reply);
4339                 mrioc->evtack_cmds[i].reply = NULL;
4340         }
4341
4342         bitmap_free(mrioc->removepend_bitmap);
4343         mrioc->removepend_bitmap = NULL;
4344
4345         bitmap_free(mrioc->devrem_bitmap);
4346         mrioc->devrem_bitmap = NULL;
4347
4348         bitmap_free(mrioc->evtack_cmds_bitmap);
4349         mrioc->evtack_cmds_bitmap = NULL;
4350
4351         bitmap_free(mrioc->chain_bitmap);
4352         mrioc->chain_bitmap = NULL;
4353
4354         kfree(mrioc->transport_cmds.reply);
4355         mrioc->transport_cmds.reply = NULL;
4356
4357         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4358                 kfree(mrioc->dev_rmhs_cmds[i].reply);
4359                 mrioc->dev_rmhs_cmds[i].reply = NULL;
4360         }
4361
4362         if (mrioc->chain_buf_pool) {
4363                 for (i = 0; i < mrioc->chain_buf_count; i++) {
4364                         if (mrioc->chain_sgl_list[i].addr) {
4365                                 dma_pool_free(mrioc->chain_buf_pool,
4366                                     mrioc->chain_sgl_list[i].addr,
4367                                     mrioc->chain_sgl_list[i].dma_addr);
4368                                 mrioc->chain_sgl_list[i].addr = NULL;
4369                         }
4370                 }
4371                 dma_pool_destroy(mrioc->chain_buf_pool);
4372                 mrioc->chain_buf_pool = NULL;
4373         }
4374
4375         kfree(mrioc->chain_sgl_list);
4376         mrioc->chain_sgl_list = NULL;
4377
4378         if (mrioc->admin_reply_base) {
4379                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4380                     mrioc->admin_reply_base, mrioc->admin_reply_dma);
4381                 mrioc->admin_reply_base = NULL;
4382         }
4383         if (mrioc->admin_req_base) {
4384                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4385                     mrioc->admin_req_base, mrioc->admin_req_dma);
4386                 mrioc->admin_req_base = NULL;
4387         }
4388         if (mrioc->cfg_page) {
4389                 dma_free_coherent(&mrioc->pdev->dev, mrioc->cfg_page_sz,
4390                     mrioc->cfg_page, mrioc->cfg_page_dma);
4391                 mrioc->cfg_page = NULL;
4392         }
4393         if (mrioc->pel_seqnum_virt) {
4394                 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4395                     mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4396                 mrioc->pel_seqnum_virt = NULL;
4397         }
4398
4399         kfree(mrioc->throttle_groups);
4400         mrioc->throttle_groups = NULL;
4401
4402         kfree(mrioc->logdata_buf);
4403         mrioc->logdata_buf = NULL;
4404
4405 }
4406
4407 /**
4408  * mpi3mr_issue_ioc_shutdown - shutdown controller
4409  * @mrioc: Adapter instance reference
4410  *
4411  * Send shutodwn notification to the controller and wait for the
4412  * shutdown_timeout for it to be completed.
4413  *
4414  * Return: Nothing.
4415  */
4416 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4417 {
4418         u32 ioc_config, ioc_status;
4419         u8 retval = 1;
4420         u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4421
4422         ioc_info(mrioc, "Issuing shutdown Notification\n");
4423         if (mrioc->unrecoverable) {
4424                 ioc_warn(mrioc,
4425                     "IOC is unrecoverable shutdown is not issued\n");
4426                 return;
4427         }
4428         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4429         if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4430             == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4431                 ioc_info(mrioc, "shutdown already in progress\n");
4432                 return;
4433         }
4434
4435         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4436         ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4437         ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4438
4439         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4440
4441         if (mrioc->facts.shutdown_timeout)
4442                 timeout = mrioc->facts.shutdown_timeout * 10;
4443
4444         do {
4445                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4446                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4447                     == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4448                         retval = 0;
4449                         break;
4450                 }
4451                 msleep(100);
4452         } while (--timeout);
4453
4454         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4455         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4456
4457         if (retval) {
4458                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4459                     == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4460                         ioc_warn(mrioc,
4461                             "shutdown still in progress after timeout\n");
4462         }
4463
4464         ioc_info(mrioc,
4465             "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
4466             (!retval) ? "successful" : "failed", ioc_status,
4467             ioc_config);
4468 }
4469
4470 /**
4471  * mpi3mr_cleanup_ioc - Cleanup controller
4472  * @mrioc: Adapter instance reference
4473  *
4474  * controller cleanup handler, Message unit reset or soft reset
4475  * and shutdown notification is issued to the controller.
4476  *
4477  * Return: Nothing.
4478  */
4479 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
4480 {
4481         enum mpi3mr_iocstate ioc_state;
4482
4483         dprint_exit(mrioc, "cleaning up the controller\n");
4484         mpi3mr_ioc_disable_intr(mrioc);
4485
4486         ioc_state = mpi3mr_get_iocstate(mrioc);
4487
4488         if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) &&
4489             (ioc_state == MRIOC_STATE_READY)) {
4490                 if (mpi3mr_issue_and_process_mur(mrioc,
4491                     MPI3MR_RESET_FROM_CTLR_CLEANUP))
4492                         mpi3mr_issue_reset(mrioc,
4493                             MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
4494                             MPI3MR_RESET_FROM_MUR_FAILURE);
4495                 mpi3mr_issue_ioc_shutdown(mrioc);
4496         }
4497         dprint_exit(mrioc, "controller cleanup completed\n");
4498 }
4499
4500 /**
4501  * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
4502  * @mrioc: Adapter instance reference
4503  * @cmdptr: Internal command tracker
4504  *
4505  * Complete an internal driver commands with state indicating it
4506  * is completed due to reset.
4507  *
4508  * Return: Nothing.
4509  */
4510 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
4511         struct mpi3mr_drv_cmd *cmdptr)
4512 {
4513         if (cmdptr->state & MPI3MR_CMD_PENDING) {
4514                 cmdptr->state |= MPI3MR_CMD_RESET;
4515                 cmdptr->state &= ~MPI3MR_CMD_PENDING;
4516                 if (cmdptr->is_waiting) {
4517                         complete(&cmdptr->done);
4518                         cmdptr->is_waiting = 0;
4519                 } else if (cmdptr->callback)
4520                         cmdptr->callback(mrioc, cmdptr);
4521         }
4522 }
4523
4524 /**
4525  * mpi3mr_flush_drv_cmds - Flush internaldriver commands
4526  * @mrioc: Adapter instance reference
4527  *
4528  * Flush all internal driver commands post reset
4529  *
4530  * Return: Nothing.
4531  */
4532 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
4533 {
4534         struct mpi3mr_drv_cmd *cmdptr;
4535         u8 i;
4536
4537         cmdptr = &mrioc->init_cmds;
4538         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4539
4540         cmdptr = &mrioc->cfg_cmds;
4541         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4542
4543         cmdptr = &mrioc->bsg_cmds;
4544         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4545         cmdptr = &mrioc->host_tm_cmds;
4546         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4547
4548         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4549                 cmdptr = &mrioc->dev_rmhs_cmds[i];
4550                 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4551         }
4552
4553         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4554                 cmdptr = &mrioc->evtack_cmds[i];
4555                 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4556         }
4557
4558         cmdptr = &mrioc->pel_cmds;
4559         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4560
4561         cmdptr = &mrioc->pel_abort_cmd;
4562         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4563
4564         cmdptr = &mrioc->transport_cmds;
4565         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4566 }
4567
4568 /**
4569  * mpi3mr_pel_wait_post - Issue PEL Wait
4570  * @mrioc: Adapter instance reference
4571  * @drv_cmd: Internal command tracker
4572  *
4573  * Issue PEL Wait MPI request through admin queue and return.
4574  *
4575  * Return: Nothing.
4576  */
4577 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
4578         struct mpi3mr_drv_cmd *drv_cmd)
4579 {
4580         struct mpi3_pel_req_action_wait pel_wait;
4581
4582         mrioc->pel_abort_requested = false;
4583
4584         memset(&pel_wait, 0, sizeof(pel_wait));
4585         drv_cmd->state = MPI3MR_CMD_PENDING;
4586         drv_cmd->is_waiting = 0;
4587         drv_cmd->callback = mpi3mr_pel_wait_complete;
4588         drv_cmd->ioc_status = 0;
4589         drv_cmd->ioc_loginfo = 0;
4590         pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4591         pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4592         pel_wait.action = MPI3_PEL_ACTION_WAIT;
4593         pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
4594         pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
4595         pel_wait.class = cpu_to_le16(mrioc->pel_class);
4596         pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
4597         dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
4598             mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
4599
4600         if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
4601                 dprint_bsg_err(mrioc,
4602                             "Issuing PELWait: Admin post failed\n");
4603                 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4604                 drv_cmd->callback = NULL;
4605                 drv_cmd->retry_count = 0;
4606                 mrioc->pel_enabled = false;
4607         }
4608 }
4609
4610 /**
4611  * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
4612  * @mrioc: Adapter instance reference
4613  * @drv_cmd: Internal command tracker
4614  *
4615  * Issue PEL get sequence number MPI request through admin queue
4616  * and return.
4617  *
4618  * Return: 0 on success, non-zero on failure.
4619  */
4620 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
4621         struct mpi3mr_drv_cmd *drv_cmd)
4622 {
4623         struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
4624         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
4625         int retval = 0;
4626
4627         memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
4628         mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
4629         mrioc->pel_cmds.is_waiting = 0;
4630         mrioc->pel_cmds.ioc_status = 0;
4631         mrioc->pel_cmds.ioc_loginfo = 0;
4632         mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
4633         pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4634         pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4635         pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
4636         mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
4637             mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
4638
4639         retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
4640                         sizeof(pel_getseq_req), 0);
4641         if (retval) {
4642                 if (drv_cmd) {
4643                         drv_cmd->state = MPI3MR_CMD_NOTUSED;
4644                         drv_cmd->callback = NULL;
4645                         drv_cmd->retry_count = 0;
4646                 }
4647                 mrioc->pel_enabled = false;
4648         }
4649
4650         return retval;
4651 }
4652
4653 /**
4654  * mpi3mr_pel_wait_complete - PELWait Completion callback
4655  * @mrioc: Adapter instance reference
4656  * @drv_cmd: Internal command tracker
4657  *
4658  * This is a callback handler for the PELWait request and
4659  * firmware completes a PELWait request when it is aborted or a
4660  * new PEL entry is available. This sends AEN to the application
4661  * and if the PELwait completion is not due to PELAbort then
4662  * this will send a request for new PEL Sequence number
4663  *
4664  * Return: Nothing.
4665  */
4666 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
4667         struct mpi3mr_drv_cmd *drv_cmd)
4668 {
4669         struct mpi3_pel_reply *pel_reply = NULL;
4670         u16 ioc_status, pe_log_status;
4671         bool do_retry = false;
4672
4673         if (drv_cmd->state & MPI3MR_CMD_RESET)
4674                 goto cleanup_drv_cmd;
4675
4676         ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4677         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4678                 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
4679                         __func__, ioc_status, drv_cmd->ioc_loginfo);
4680                 dprint_bsg_err(mrioc,
4681                     "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4682                     ioc_status, drv_cmd->ioc_loginfo);
4683                 do_retry = true;
4684         }
4685
4686         if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4687                 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4688
4689         if (!pel_reply) {
4690                 dprint_bsg_err(mrioc,
4691                     "pel_wait: failed due to no reply\n");
4692                 goto out_failed;
4693         }
4694
4695         pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
4696         if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
4697             (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
4698                 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
4699                         __func__, pe_log_status);
4700                 dprint_bsg_err(mrioc,
4701                     "pel_wait: failed due to pel_log_status(0x%04x)\n",
4702                     pe_log_status);
4703                 do_retry = true;
4704         }
4705
4706         if (do_retry) {
4707                 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4708                         drv_cmd->retry_count++;
4709                         dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
4710                             drv_cmd->retry_count);
4711                         mpi3mr_pel_wait_post(mrioc, drv_cmd);
4712                         return;
4713                 }
4714                 dprint_bsg_err(mrioc,
4715                     "pel_wait: failed after all retries(%d)\n",
4716                     drv_cmd->retry_count);
4717                 goto out_failed;
4718         }
4719         atomic64_inc(&event_counter);
4720         if (!mrioc->pel_abort_requested) {
4721                 mrioc->pel_cmds.retry_count = 0;
4722                 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
4723         }
4724
4725         return;
4726 out_failed:
4727         mrioc->pel_enabled = false;
4728 cleanup_drv_cmd:
4729         drv_cmd->state = MPI3MR_CMD_NOTUSED;
4730         drv_cmd->callback = NULL;
4731         drv_cmd->retry_count = 0;
4732 }
4733
4734 /**
4735  * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
4736  * @mrioc: Adapter instance reference
4737  * @drv_cmd: Internal command tracker
4738  *
4739  * This is a callback handler for the PEL get sequence number
4740  * request and a new PEL wait request will be issued to the
4741  * firmware from this
4742  *
4743  * Return: Nothing.
4744  */
4745 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
4746         struct mpi3mr_drv_cmd *drv_cmd)
4747 {
4748         struct mpi3_pel_reply *pel_reply = NULL;
4749         struct mpi3_pel_seq *pel_seqnum_virt;
4750         u16 ioc_status;
4751         bool do_retry = false;
4752
4753         pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
4754
4755         if (drv_cmd->state & MPI3MR_CMD_RESET)
4756                 goto cleanup_drv_cmd;
4757
4758         ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4759         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4760                 dprint_bsg_err(mrioc,
4761                     "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4762                     ioc_status, drv_cmd->ioc_loginfo);
4763                 do_retry = true;
4764         }
4765
4766         if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4767                 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4768         if (!pel_reply) {
4769                 dprint_bsg_err(mrioc,
4770                     "pel_get_seqnum: failed due to no reply\n");
4771                 goto out_failed;
4772         }
4773
4774         if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
4775                 dprint_bsg_err(mrioc,
4776                     "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
4777                     le16_to_cpu(pel_reply->pe_log_status));
4778                 do_retry = true;
4779         }
4780
4781         if (do_retry) {
4782                 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4783                         drv_cmd->retry_count++;
4784                         dprint_bsg_err(mrioc,
4785                             "pel_get_seqnum: retrying(%d)\n",
4786                             drv_cmd->retry_count);
4787                         mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
4788                         return;
4789                 }
4790
4791                 dprint_bsg_err(mrioc,
4792                     "pel_get_seqnum: failed after all retries(%d)\n",
4793                     drv_cmd->retry_count);
4794                 goto out_failed;
4795         }
4796         mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
4797         drv_cmd->retry_count = 0;
4798         mpi3mr_pel_wait_post(mrioc, drv_cmd);
4799
4800         return;
4801 out_failed:
4802         mrioc->pel_enabled = false;
4803 cleanup_drv_cmd:
4804         drv_cmd->state = MPI3MR_CMD_NOTUSED;
4805         drv_cmd->callback = NULL;
4806         drv_cmd->retry_count = 0;
4807 }
4808
4809 /**
4810  * mpi3mr_soft_reset_handler - Reset the controller
4811  * @mrioc: Adapter instance reference
4812  * @reset_reason: Reset reason code
4813  * @snapdump: Flag to generate snapdump in firmware or not
4814  *
4815  * This is an handler for recovering controller by issuing soft
4816  * reset are diag fault reset.  This is a blocking function and
4817  * when one reset is executed if any other resets they will be
4818  * blocked. All BSG requests will be blocked during the reset. If
4819  * controller reset is successful then the controller will be
4820  * reinitalized, otherwise the controller will be marked as not
4821  * recoverable
4822  *
4823  * In snapdump bit is set, the controller is issued with diag
4824  * fault reset so that the firmware can create a snap dump and
4825  * post that the firmware will result in F000 fault and the
4826  * driver will issue soft reset to recover from that.
4827  *
4828  * Return: 0 on success, non-zero on failure.
4829  */
4830 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
4831         u32 reset_reason, u8 snapdump)
4832 {
4833         int retval = 0, i;
4834         unsigned long flags;
4835         u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
4836
4837         /* Block the reset handler until diag save in progress*/
4838         dprint_reset(mrioc,
4839             "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
4840             mrioc->diagsave_timeout);
4841         while (mrioc->diagsave_timeout)
4842                 ssleep(1);
4843         /*
4844          * Block new resets until the currently executing one is finished and
4845          * return the status of the existing reset for all blocked resets
4846          */
4847         dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
4848         if (!mutex_trylock(&mrioc->reset_mutex)) {
4849                 ioc_info(mrioc,
4850                     "controller reset triggered by %s is blocked due to another reset in progress\n",
4851                     mpi3mr_reset_rc_name(reset_reason));
4852                 do {
4853                         ssleep(1);
4854                 } while (mrioc->reset_in_progress == 1);
4855                 ioc_info(mrioc,
4856                     "returning previous reset result(%d) for the reset triggered by %s\n",
4857                     mrioc->prev_reset_result,
4858                     mpi3mr_reset_rc_name(reset_reason));
4859                 return mrioc->prev_reset_result;
4860         }
4861         ioc_info(mrioc, "controller reset is triggered by %s\n",
4862             mpi3mr_reset_rc_name(reset_reason));
4863
4864         mrioc->device_refresh_on = 0;
4865         mrioc->reset_in_progress = 1;
4866         mrioc->stop_bsgs = 1;
4867         mrioc->prev_reset_result = -1;
4868
4869         if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
4870             (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
4871             (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
4872                 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4873                         mrioc->event_masks[i] = -1;
4874
4875                 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
4876                 mpi3mr_issue_event_notification(mrioc);
4877         }
4878
4879         mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
4880
4881         mpi3mr_ioc_disable_intr(mrioc);
4882
4883         if (snapdump) {
4884                 mpi3mr_set_diagsave(mrioc);
4885                 retval = mpi3mr_issue_reset(mrioc,
4886                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4887                 if (!retval) {
4888                         do {
4889                                 host_diagnostic =
4890                                     readl(&mrioc->sysif_regs->host_diagnostic);
4891                                 if (!(host_diagnostic &
4892                                     MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
4893                                         break;
4894                                 msleep(100);
4895                         } while (--timeout);
4896                 }
4897         }
4898
4899         retval = mpi3mr_issue_reset(mrioc,
4900             MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
4901         if (retval) {
4902                 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
4903                 goto out;
4904         }
4905         if (mrioc->num_io_throttle_group !=
4906             mrioc->facts.max_io_throttle_group) {
4907                 ioc_err(mrioc,
4908                     "max io throttle group doesn't match old(%d), new(%d)\n",
4909                     mrioc->num_io_throttle_group,
4910                     mrioc->facts.max_io_throttle_group);
4911                 retval = -EPERM;
4912                 goto out;
4913         }
4914
4915         mpi3mr_flush_delayed_cmd_lists(mrioc);
4916         mpi3mr_flush_drv_cmds(mrioc);
4917         bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4918         bitmap_clear(mrioc->removepend_bitmap, 0,
4919                      mrioc->dev_handle_bitmap_bits);
4920         bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD);
4921         mpi3mr_flush_host_io(mrioc);
4922         mpi3mr_cleanup_fwevt_list(mrioc);
4923         mpi3mr_invalidate_devhandles(mrioc);
4924         mpi3mr_free_enclosure_list(mrioc);
4925
4926         if (mrioc->prepare_for_reset) {
4927                 mrioc->prepare_for_reset = 0;
4928                 mrioc->prepare_for_reset_timeout_counter = 0;
4929         }
4930         mpi3mr_memset_buffers(mrioc);
4931         retval = mpi3mr_reinit_ioc(mrioc, 0);
4932         if (retval) {
4933                 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
4934                     mrioc->name, reset_reason);
4935                 goto out;
4936         }
4937         ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
4938
4939 out:
4940         if (!retval) {
4941                 mrioc->diagsave_timeout = 0;
4942                 mrioc->reset_in_progress = 0;
4943                 mrioc->pel_abort_requested = 0;
4944                 if (mrioc->pel_enabled) {
4945                         mrioc->pel_cmds.retry_count = 0;
4946                         mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
4947                 }
4948
4949                 mrioc->device_refresh_on = 0;
4950
4951                 mrioc->ts_update_counter = 0;
4952                 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
4953                 if (mrioc->watchdog_work_q)
4954                         queue_delayed_work(mrioc->watchdog_work_q,
4955                             &mrioc->watchdog_work,
4956                             msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
4957                 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
4958                 mrioc->stop_bsgs = 0;
4959                 if (mrioc->pel_enabled)
4960                         atomic64_inc(&event_counter);
4961         } else {
4962                 mpi3mr_issue_reset(mrioc,
4963                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4964                 mrioc->device_refresh_on = 0;
4965                 mrioc->unrecoverable = 1;
4966                 mrioc->reset_in_progress = 0;
4967                 retval = -1;
4968                 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
4969         }
4970         mrioc->prev_reset_result = retval;
4971         mutex_unlock(&mrioc->reset_mutex);
4972         ioc_info(mrioc, "controller reset is %s\n",
4973             ((retval == 0) ? "successful" : "failed"));
4974         return retval;
4975 }
4976
4977
4978 /**
4979  * mpi3mr_free_config_dma_memory - free memory for config page
4980  * @mrioc: Adapter instance reference
4981  * @mem_desc: memory descriptor structure
4982  *
4983  * Check whether the size of the buffer specified by the memory
4984  * descriptor is greater than the default page size if so then
4985  * free the memory pointed by the descriptor.
4986  *
4987  * Return: Nothing.
4988  */
4989 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc,
4990         struct dma_memory_desc *mem_desc)
4991 {
4992         if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) {
4993                 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
4994                     mem_desc->addr, mem_desc->dma_addr);
4995                 mem_desc->addr = NULL;
4996         }
4997 }
4998
4999 /**
5000  * mpi3mr_alloc_config_dma_memory - Alloc memory for config page
5001  * @mrioc: Adapter instance reference
5002  * @mem_desc: Memory descriptor to hold dma memory info
5003  *
5004  * This function allocates new dmaable memory or provides the
5005  * default config page dmaable memory based on the memory size
5006  * described by the descriptor.
5007  *
5008  * Return: 0 on success, non-zero on failure.
5009  */
5010 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc,
5011         struct dma_memory_desc *mem_desc)
5012 {
5013         if (mem_desc->size > mrioc->cfg_page_sz) {
5014                 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
5015                     mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL);
5016                 if (!mem_desc->addr)
5017                         return -ENOMEM;
5018         } else {
5019                 mem_desc->addr = mrioc->cfg_page;
5020                 mem_desc->dma_addr = mrioc->cfg_page_dma;
5021                 memset(mem_desc->addr, 0, mrioc->cfg_page_sz);
5022         }
5023         return 0;
5024 }
5025
5026 /**
5027  * mpi3mr_post_cfg_req - Issue config requests and wait
5028  * @mrioc: Adapter instance reference
5029  * @cfg_req: Configuration request
5030  * @timeout: Timeout in seconds
5031  * @ioc_status: Pointer to return ioc status
5032  *
5033  * A generic function for posting MPI3 configuration request to
5034  * the firmware. This blocks for the completion of request for
5035  * timeout seconds and if the request times out this function
5036  * faults the controller with proper reason code.
5037  *
5038  * On successful completion of the request this function returns
5039  * appropriate ioc status from the firmware back to the caller.
5040  *
5041  * Return: 0 on success, non-zero on failure.
5042  */
5043 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5044         struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5045 {
5046         int retval = 0;
5047
5048         mutex_lock(&mrioc->cfg_cmds.mutex);
5049         if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5050                 retval = -1;
5051                 ioc_err(mrioc, "sending config request failed due to command in use\n");
5052                 mutex_unlock(&mrioc->cfg_cmds.mutex);
5053                 goto out;
5054         }
5055         mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5056         mrioc->cfg_cmds.is_waiting = 1;
5057         mrioc->cfg_cmds.callback = NULL;
5058         mrioc->cfg_cmds.ioc_status = 0;
5059         mrioc->cfg_cmds.ioc_loginfo = 0;
5060
5061         cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5062         cfg_req->function = MPI3_FUNCTION_CONFIG;
5063
5064         init_completion(&mrioc->cfg_cmds.done);
5065         dprint_cfg_info(mrioc, "posting config request\n");
5066         if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5067                 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5068                     "mpi3_cfg_req");
5069         retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5070         if (retval) {
5071                 ioc_err(mrioc, "posting config request failed\n");
5072                 goto out_unlock;
5073         }
5074         wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5075         if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5076                 mpi3mr_check_rh_fault_ioc(mrioc,
5077                     MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5078                 ioc_err(mrioc, "config request timed out\n");
5079                 retval = -1;
5080                 goto out_unlock;
5081         }
5082         *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5083         if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5084                 dprint_cfg_err(mrioc,
5085                     "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5086                     *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5087
5088 out_unlock:
5089         mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5090         mutex_unlock(&mrioc->cfg_cmds.mutex);
5091
5092 out:
5093         return retval;
5094 }
5095
5096 /**
5097  * mpi3mr_process_cfg_req - config page request processor
5098  * @mrioc: Adapter instance reference
5099  * @cfg_req: Configuration request
5100  * @cfg_hdr: Configuration page header
5101  * @timeout: Timeout in seconds
5102  * @ioc_status: Pointer to return ioc status
5103  * @cfg_buf: Memory pointer to copy config page or header
5104  * @cfg_buf_sz: Size of the memory to get config page or header
5105  *
5106  * This is handler for config page read, write and config page
5107  * header read operations.
5108  *
5109  * This function expects the cfg_req to be populated with page
5110  * type, page number, action for the header read and with page
5111  * address for all other operations.
5112  *
5113  * The cfg_hdr can be passed as null for reading required header
5114  * details for read/write pages the cfg_hdr should point valid
5115  * configuration page header.
5116  *
5117  * This allocates dmaable memory based on the size of the config
5118  * buffer and set the SGE of the cfg_req.
5119  *
5120  * For write actions, the config page data has to be passed in
5121  * the cfg_buf and size of the data has to be mentioned in the
5122  * cfg_buf_sz.
5123  *
5124  * For read/header actions, on successful completion of the
5125  * request with successful ioc_status the data will be copied
5126  * into the cfg_buf limited to a minimum of actual page size and
5127  * cfg_buf_sz
5128  *
5129  *
5130  * Return: 0 on success, non-zero on failure.
5131  */
5132 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5133         struct mpi3_config_request *cfg_req,
5134         struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5135         void *cfg_buf, u32 cfg_buf_sz)
5136 {
5137         struct dma_memory_desc mem_desc;
5138         int retval = -1;
5139         u8 invalid_action = 0;
5140         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5141
5142         memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5143
5144         if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5145                 mem_desc.size = sizeof(struct mpi3_config_page_header);
5146         else {
5147                 if (!cfg_hdr) {
5148                         ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5149                             cfg_req->action, cfg_req->page_type,
5150                             cfg_req->page_number);
5151                         goto out;
5152                 }
5153                 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5154                 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5155                         if (cfg_req->action
5156                             != MPI3_CONFIG_ACTION_READ_CURRENT)
5157                                 invalid_action = 1;
5158                         break;
5159                 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5160                         if ((cfg_req->action ==
5161                              MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5162                             (cfg_req->action ==
5163                              MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5164                                 invalid_action = 1;
5165                         break;
5166                 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5167                 default:
5168                         break;
5169                 }
5170                 if (invalid_action) {
5171                         ioc_err(mrioc,
5172                             "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5173                             cfg_req->action, cfg_req->page_type,
5174                             cfg_req->page_number, cfg_hdr->page_attribute);
5175                         goto out;
5176                 }
5177                 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5178                 cfg_req->page_length = cfg_hdr->page_length;
5179                 cfg_req->page_version = cfg_hdr->page_version;
5180         }
5181         if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc))
5182                 goto out;
5183
5184         mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5185             mem_desc.dma_addr);
5186
5187         if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5188             (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5189                 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5190                     cfg_buf_sz));
5191                 dprint_cfg_info(mrioc, "config buffer to be written\n");
5192                 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5193                         dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5194         }
5195
5196         if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5197                 goto out;
5198
5199         retval = 0;
5200         if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5201             (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5202             (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5203                 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5204                     cfg_buf_sz));
5205                 dprint_cfg_info(mrioc, "config buffer read\n");
5206                 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5207                         dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5208         }
5209
5210 out:
5211         mpi3mr_free_config_dma_memory(mrioc, &mem_desc);
5212         return retval;
5213 }
5214
5215 /**
5216  * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5217  * @mrioc: Adapter instance reference
5218  * @ioc_status: Pointer to return ioc status
5219  * @dev_pg0: Pointer to return device page 0
5220  * @pg_sz: Size of the memory allocated to the page pointer
5221  * @form: The form to be used for addressing the page
5222  * @form_spec: Form specific information like device handle
5223  *
5224  * This is handler for config page read for a specific device
5225  * page0. The ioc_status has the controller returned ioc_status.
5226  * This routine doesn't check ioc_status to decide whether the
5227  * page read is success or not and it is the callers
5228  * responsibility.
5229  *
5230  * Return: 0 on success, non-zero on failure.
5231  */
5232 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5233         struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5234 {
5235         struct mpi3_config_page_header cfg_hdr;
5236         struct mpi3_config_request cfg_req;
5237         u32 page_address;
5238
5239         memset(dev_pg0, 0, pg_sz);
5240         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5241         memset(&cfg_req, 0, sizeof(cfg_req));
5242
5243         cfg_req.function = MPI3_FUNCTION_CONFIG;
5244         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5245         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5246         cfg_req.page_number = 0;
5247         cfg_req.page_address = 0;
5248
5249         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5250             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5251                 ioc_err(mrioc, "device page0 header read failed\n");
5252                 goto out_failed;
5253         }
5254         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5255                 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5256                     *ioc_status);
5257                 goto out_failed;
5258         }
5259         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5260         page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5261             (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5262         cfg_req.page_address = cpu_to_le32(page_address);
5263         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5264             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5265                 ioc_err(mrioc, "device page0 read failed\n");
5266                 goto out_failed;
5267         }
5268         return 0;
5269 out_failed:
5270         return -1;
5271 }
5272
5273
5274 /**
5275  * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5276  * @mrioc: Adapter instance reference
5277  * @ioc_status: Pointer to return ioc status
5278  * @phy_pg0: Pointer to return SAS Phy page 0
5279  * @pg_sz: Size of the memory allocated to the page pointer
5280  * @form: The form to be used for addressing the page
5281  * @form_spec: Form specific information like phy number
5282  *
5283  * This is handler for config page read for a specific SAS Phy
5284  * page0. The ioc_status has the controller returned ioc_status.
5285  * This routine doesn't check ioc_status to decide whether the
5286  * page read is success or not and it is the callers
5287  * responsibility.
5288  *
5289  * Return: 0 on success, non-zero on failure.
5290  */
5291 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5292         struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5293         u32 form_spec)
5294 {
5295         struct mpi3_config_page_header cfg_hdr;
5296         struct mpi3_config_request cfg_req;
5297         u32 page_address;
5298
5299         memset(phy_pg0, 0, pg_sz);
5300         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5301         memset(&cfg_req, 0, sizeof(cfg_req));
5302
5303         cfg_req.function = MPI3_FUNCTION_CONFIG;
5304         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5305         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5306         cfg_req.page_number = 0;
5307         cfg_req.page_address = 0;
5308
5309         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5310             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5311                 ioc_err(mrioc, "sas phy page0 header read failed\n");
5312                 goto out_failed;
5313         }
5314         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5315                 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5316                     *ioc_status);
5317                 goto out_failed;
5318         }
5319         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5320         page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5321             (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5322         cfg_req.page_address = cpu_to_le32(page_address);
5323         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5324             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5325                 ioc_err(mrioc, "sas phy page0 read failed\n");
5326                 goto out_failed;
5327         }
5328         return 0;
5329 out_failed:
5330         return -1;
5331 }
5332
5333 /**
5334  * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5335  * @mrioc: Adapter instance reference
5336  * @ioc_status: Pointer to return ioc status
5337  * @phy_pg1: Pointer to return SAS Phy page 1
5338  * @pg_sz: Size of the memory allocated to the page pointer
5339  * @form: The form to be used for addressing the page
5340  * @form_spec: Form specific information like phy number
5341  *
5342  * This is handler for config page read for a specific SAS Phy
5343  * page1. The ioc_status has the controller returned ioc_status.
5344  * This routine doesn't check ioc_status to decide whether the
5345  * page read is success or not and it is the callers
5346  * responsibility.
5347  *
5348  * Return: 0 on success, non-zero on failure.
5349  */
5350 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5351         struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5352         u32 form_spec)
5353 {
5354         struct mpi3_config_page_header cfg_hdr;
5355         struct mpi3_config_request cfg_req;
5356         u32 page_address;
5357
5358         memset(phy_pg1, 0, pg_sz);
5359         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5360         memset(&cfg_req, 0, sizeof(cfg_req));
5361
5362         cfg_req.function = MPI3_FUNCTION_CONFIG;
5363         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5364         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5365         cfg_req.page_number = 1;
5366         cfg_req.page_address = 0;
5367
5368         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5369             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5370                 ioc_err(mrioc, "sas phy page1 header read failed\n");
5371                 goto out_failed;
5372         }
5373         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5374                 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5375                     *ioc_status);
5376                 goto out_failed;
5377         }
5378         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5379         page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5380             (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5381         cfg_req.page_address = cpu_to_le32(page_address);
5382         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5383             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5384                 ioc_err(mrioc, "sas phy page1 read failed\n");
5385                 goto out_failed;
5386         }
5387         return 0;
5388 out_failed:
5389         return -1;
5390 }
5391
5392
5393 /**
5394  * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5395  * @mrioc: Adapter instance reference
5396  * @ioc_status: Pointer to return ioc status
5397  * @exp_pg0: Pointer to return SAS Expander page 0
5398  * @pg_sz: Size of the memory allocated to the page pointer
5399  * @form: The form to be used for addressing the page
5400  * @form_spec: Form specific information like device handle
5401  *
5402  * This is handler for config page read for a specific SAS
5403  * Expander page0. The ioc_status has the controller returned
5404  * ioc_status. This routine doesn't check ioc_status to decide
5405  * whether the page read is success or not and it is the callers
5406  * responsibility.
5407  *
5408  * Return: 0 on success, non-zero on failure.
5409  */
5410 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5411         struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5412         u32 form_spec)
5413 {
5414         struct mpi3_config_page_header cfg_hdr;
5415         struct mpi3_config_request cfg_req;
5416         u32 page_address;
5417
5418         memset(exp_pg0, 0, pg_sz);
5419         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5420         memset(&cfg_req, 0, sizeof(cfg_req));
5421
5422         cfg_req.function = MPI3_FUNCTION_CONFIG;
5423         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5424         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5425         cfg_req.page_number = 0;
5426         cfg_req.page_address = 0;
5427
5428         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5429             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5430                 ioc_err(mrioc, "expander page0 header read failed\n");
5431                 goto out_failed;
5432         }
5433         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5434                 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
5435                     *ioc_status);
5436                 goto out_failed;
5437         }
5438         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5439         page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5440             (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5441             MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5442         cfg_req.page_address = cpu_to_le32(page_address);
5443         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5444             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
5445                 ioc_err(mrioc, "expander page0 read failed\n");
5446                 goto out_failed;
5447         }
5448         return 0;
5449 out_failed:
5450         return -1;
5451 }
5452
5453 /**
5454  * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
5455  * @mrioc: Adapter instance reference
5456  * @ioc_status: Pointer to return ioc status
5457  * @exp_pg1: Pointer to return SAS Expander page 1
5458  * @pg_sz: Size of the memory allocated to the page pointer
5459  * @form: The form to be used for addressing the page
5460  * @form_spec: Form specific information like phy number
5461  *
5462  * This is handler for config page read for a specific SAS
5463  * Expander page1. The ioc_status has the controller returned
5464  * ioc_status. This routine doesn't check ioc_status to decide
5465  * whether the page read is success or not and it is the callers
5466  * responsibility.
5467  *
5468  * Return: 0 on success, non-zero on failure.
5469  */
5470 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5471         struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
5472         u32 form_spec)
5473 {
5474         struct mpi3_config_page_header cfg_hdr;
5475         struct mpi3_config_request cfg_req;
5476         u32 page_address;
5477
5478         memset(exp_pg1, 0, pg_sz);
5479         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5480         memset(&cfg_req, 0, sizeof(cfg_req));
5481
5482         cfg_req.function = MPI3_FUNCTION_CONFIG;
5483         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5484         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5485         cfg_req.page_number = 1;
5486         cfg_req.page_address = 0;
5487
5488         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5489             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5490                 ioc_err(mrioc, "expander page1 header read failed\n");
5491                 goto out_failed;
5492         }
5493         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5494                 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
5495                     *ioc_status);
5496                 goto out_failed;
5497         }
5498         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5499         page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5500             (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5501             MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5502         cfg_req.page_address = cpu_to_le32(page_address);
5503         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5504             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
5505                 ioc_err(mrioc, "expander page1 read failed\n");
5506                 goto out_failed;
5507         }
5508         return 0;
5509 out_failed:
5510         return -1;
5511 }
5512
5513 /**
5514  * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
5515  * @mrioc: Adapter instance reference
5516  * @ioc_status: Pointer to return ioc status
5517  * @encl_pg0: Pointer to return Enclosure page 0
5518  * @pg_sz: Size of the memory allocated to the page pointer
5519  * @form: The form to be used for addressing the page
5520  * @form_spec: Form specific information like device handle
5521  *
5522  * This is handler for config page read for a specific Enclosure
5523  * page0. The ioc_status has the controller returned ioc_status.
5524  * This routine doesn't check ioc_status to decide whether the
5525  * page read is success or not and it is the callers
5526  * responsibility.
5527  *
5528  * Return: 0 on success, non-zero on failure.
5529  */
5530 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5531         struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
5532         u32 form_spec)
5533 {
5534         struct mpi3_config_page_header cfg_hdr;
5535         struct mpi3_config_request cfg_req;
5536         u32 page_address;
5537
5538         memset(encl_pg0, 0, pg_sz);
5539         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5540         memset(&cfg_req, 0, sizeof(cfg_req));
5541
5542         cfg_req.function = MPI3_FUNCTION_CONFIG;
5543         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5544         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
5545         cfg_req.page_number = 0;
5546         cfg_req.page_address = 0;
5547
5548         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5549             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5550                 ioc_err(mrioc, "enclosure page0 header read failed\n");
5551                 goto out_failed;
5552         }
5553         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5554                 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
5555                     *ioc_status);
5556                 goto out_failed;
5557         }
5558         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5559         page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
5560             (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
5561         cfg_req.page_address = cpu_to_le32(page_address);
5562         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5563             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
5564                 ioc_err(mrioc, "enclosure page0 read failed\n");
5565                 goto out_failed;
5566         }
5567         return 0;
5568 out_failed:
5569         return -1;
5570 }
5571
5572
5573 /**
5574  * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
5575  * @mrioc: Adapter instance reference
5576  * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
5577  * @pg_sz: Size of the memory allocated to the page pointer
5578  *
5579  * This is handler for config page read for the SAS IO Unit
5580  * page0. This routine checks ioc_status to decide whether the
5581  * page read is success or not.
5582  *
5583  * Return: 0 on success, non-zero on failure.
5584  */
5585 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
5586         struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
5587 {
5588         struct mpi3_config_page_header cfg_hdr;
5589         struct mpi3_config_request cfg_req;
5590         u16 ioc_status = 0;
5591
5592         memset(sas_io_unit_pg0, 0, pg_sz);
5593         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5594         memset(&cfg_req, 0, sizeof(cfg_req));
5595
5596         cfg_req.function = MPI3_FUNCTION_CONFIG;
5597         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5598         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5599         cfg_req.page_number = 0;
5600         cfg_req.page_address = 0;
5601
5602         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5603             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5604                 ioc_err(mrioc, "sas io unit page0 header read failed\n");
5605                 goto out_failed;
5606         }
5607         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5608                 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
5609                     ioc_status);
5610                 goto out_failed;
5611         }
5612         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5613
5614         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5615             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
5616                 ioc_err(mrioc, "sas io unit page0 read failed\n");
5617                 goto out_failed;
5618         }
5619         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5620                 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
5621                     ioc_status);
5622                 goto out_failed;
5623         }
5624         return 0;
5625 out_failed:
5626         return -1;
5627 }
5628
5629 /**
5630  * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
5631  * @mrioc: Adapter instance reference
5632  * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
5633  * @pg_sz: Size of the memory allocated to the page pointer
5634  *
5635  * This is handler for config page read for the SAS IO Unit
5636  * page1. This routine checks ioc_status to decide whether the
5637  * page read is success or not.
5638  *
5639  * Return: 0 on success, non-zero on failure.
5640  */
5641 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5642         struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5643 {
5644         struct mpi3_config_page_header cfg_hdr;
5645         struct mpi3_config_request cfg_req;
5646         u16 ioc_status = 0;
5647
5648         memset(sas_io_unit_pg1, 0, pg_sz);
5649         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5650         memset(&cfg_req, 0, sizeof(cfg_req));
5651
5652         cfg_req.function = MPI3_FUNCTION_CONFIG;
5653         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5654         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5655         cfg_req.page_number = 1;
5656         cfg_req.page_address = 0;
5657
5658         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5659             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5660                 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5661                 goto out_failed;
5662         }
5663         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5664                 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5665                     ioc_status);
5666                 goto out_failed;
5667         }
5668         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5669
5670         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5671             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5672                 ioc_err(mrioc, "sas io unit page1 read failed\n");
5673                 goto out_failed;
5674         }
5675         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5676                 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
5677                     ioc_status);
5678                 goto out_failed;
5679         }
5680         return 0;
5681 out_failed:
5682         return -1;
5683 }
5684
5685 /**
5686  * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
5687  * @mrioc: Adapter instance reference
5688  * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
5689  * @pg_sz: Size of the memory allocated to the page pointer
5690  *
5691  * This is handler for config page write for the SAS IO Unit
5692  * page1. This routine checks ioc_status to decide whether the
5693  * page read is success or not. This will modify both current
5694  * and persistent page.
5695  *
5696  * Return: 0 on success, non-zero on failure.
5697  */
5698 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5699         struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5700 {
5701         struct mpi3_config_page_header cfg_hdr;
5702         struct mpi3_config_request cfg_req;
5703         u16 ioc_status = 0;
5704
5705         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5706         memset(&cfg_req, 0, sizeof(cfg_req));
5707
5708         cfg_req.function = MPI3_FUNCTION_CONFIG;
5709         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5710         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5711         cfg_req.page_number = 1;
5712         cfg_req.page_address = 0;
5713
5714         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5715             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5716                 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5717                 goto out_failed;
5718         }
5719         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5720                 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5721                     ioc_status);
5722                 goto out_failed;
5723         }
5724         cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
5725
5726         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5727             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5728                 ioc_err(mrioc, "sas io unit page1 write current failed\n");
5729                 goto out_failed;
5730         }
5731         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5732                 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
5733                     ioc_status);
5734                 goto out_failed;
5735         }
5736
5737         cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
5738
5739         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5740             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5741                 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
5742                 goto out_failed;
5743         }
5744         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5745                 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
5746                     ioc_status);
5747                 goto out_failed;
5748         }
5749         return 0;
5750 out_failed:
5751         return -1;
5752 }
5753
5754 /**
5755  * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
5756  * @mrioc: Adapter instance reference
5757  * @driver_pg1: Pointer to return Driver page 1
5758  * @pg_sz: Size of the memory allocated to the page pointer
5759  *
5760  * This is handler for config page read for the Driver page1.
5761  * This routine checks ioc_status to decide whether the page
5762  * read is success or not.
5763  *
5764  * Return: 0 on success, non-zero on failure.
5765  */
5766 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
5767         struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
5768 {
5769         struct mpi3_config_page_header cfg_hdr;
5770         struct mpi3_config_request cfg_req;
5771         u16 ioc_status = 0;
5772
5773         memset(driver_pg1, 0, pg_sz);
5774         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5775         memset(&cfg_req, 0, sizeof(cfg_req));
5776
5777         cfg_req.function = MPI3_FUNCTION_CONFIG;
5778         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5779         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
5780         cfg_req.page_number = 1;
5781         cfg_req.page_address = 0;
5782
5783         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5784             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5785                 ioc_err(mrioc, "driver page1 header read failed\n");
5786                 goto out_failed;
5787         }
5788         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5789                 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
5790                     ioc_status);
5791                 goto out_failed;
5792         }
5793         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5794
5795         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5796             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
5797                 ioc_err(mrioc, "driver page1 read failed\n");
5798                 goto out_failed;
5799         }
5800         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5801                 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
5802                     ioc_status);
5803                 goto out_failed;
5804         }
5805         return 0;
5806 out_failed:
5807         return -1;
5808 }