drivers/scsi/mpi3mr/mpi3mr_fw.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Driver for Broadcom MPI3 Storage Controllers
   4  *
   5  * Copyright (C) 2017-2022 Broadcom Inc.
   6  *  (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
   7  *
   8  */
   9
  10 #include "mpi3mr.h"
  11 #include <linux/io-64-nonatomic-lo-hi.h>
  12
  13 static int
  14 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason);
  15 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
  16 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
  17         struct mpi3_ioc_facts_data *facts_data);
  18 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
  19         struct mpi3mr_drv_cmd *drv_cmd);
  20
  21 static int poll_queues;
  22 module_param(poll_queues, int, 0444);
  23 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
  24
  25 #if defined(writeq) && defined(CONFIG_64BIT)
  26 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
  27 {
  28         writeq(b, addr);
  29 }
  30 #else
  31 static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
  32 {
  33         __u64 data_out = b;
  34
  35         writel((u32)(data_out), addr);
  36         writel((u32)(data_out >> 32), (addr + 4));
  37 }
  38 #endif
  39
  40 static inline bool
  41 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
  42 {
  43         u16 pi, ci, max_entries;
  44         bool is_qfull = false;
  45
  46         pi = op_req_q->pi;
  47         ci = READ_ONCE(op_req_q->ci);
  48         max_entries = op_req_q->num_requests;
  49
  50         if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
  51                 is_qfull = true;
  52
  53         return is_qfull;
  54 }
  55
  56 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
  57 {
  58         u16 i, max_vectors;
  59
  60         max_vectors = mrioc->intr_info_count;
  61
  62         for (i = 0; i < max_vectors; i++)
  63                 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
  64 }
  65
  66 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
  67 {
  68         mrioc->intr_enabled = 0;
  69         mpi3mr_sync_irqs(mrioc);
  70 }
  71
  72 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
  73 {
  74         mrioc->intr_enabled = 1;
  75 }
  76
  77 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
  78 {
  79         u16 i;
  80
  81         mpi3mr_ioc_disable_intr(mrioc);
  82
  83         if (!mrioc->intr_info)
  84                 return;
  85
  86         for (i = 0; i < mrioc->intr_info_count; i++)
  87                 free_irq(pci_irq_vector(mrioc->pdev, i),
  88                     (mrioc->intr_info + i));
  89
  90         kfree(mrioc->intr_info);
  91         mrioc->intr_info = NULL;
  92         mrioc->intr_info_count = 0;
  93         mrioc->is_intr_info_set = false;
  94         pci_free_irq_vectors(mrioc->pdev);
  95 }
  96
  97 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
  98         dma_addr_t dma_addr)
  99 {
 100         struct mpi3_sge_common *sgel = paddr;
 101
 102         sgel->flags = flags;
 103         sgel->length = cpu_to_le32(length);
 104         sgel->address = cpu_to_le64(dma_addr);
 105 }
 106
 107 void mpi3mr_build_zero_len_sge(void *paddr)
 108 {
 109         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
 110
 111         mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
 112 }
 113
 114 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
 115         dma_addr_t phys_addr)
 116 {
 117         if (!phys_addr)
 118                 return NULL;
 119
 120         if ((phys_addr < mrioc->reply_buf_dma) ||
 121             (phys_addr > mrioc->reply_buf_dma_max_address))
 122                 return NULL;
 123
 124         return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
 125 }
 126
 127 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
 128         dma_addr_t phys_addr)
 129 {
 130         if (!phys_addr)
 131                 return NULL;
 132
 133         return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
 134 }
 135
 136 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
 137         u64 reply_dma)
 138 {
 139         u32 old_idx = 0;
 140         unsigned long flags;
 141
 142         spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
 143         old_idx  =  mrioc->reply_free_queue_host_index;
 144         mrioc->reply_free_queue_host_index = (
 145             (mrioc->reply_free_queue_host_index ==
 146             (mrioc->reply_free_qsz - 1)) ? 0 :
 147             (mrioc->reply_free_queue_host_index + 1));
 148         mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
 149         writel(mrioc->reply_free_queue_host_index,
 150             &mrioc->sysif_regs->reply_free_host_index);
 151         spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
 152 }
 153
 154 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
 155         u64 sense_buf_dma)
 156 {
 157         u32 old_idx = 0;
 158         unsigned long flags;
 159
 160         spin_lock_irqsave(&mrioc->sbq_lock, flags);
 161         old_idx  =  mrioc->sbq_host_index;
 162         mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
 163             (mrioc->sense_buf_q_sz - 1)) ? 0 :
 164             (mrioc->sbq_host_index + 1));
 165         mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
 166         writel(mrioc->sbq_host_index,
 167             &mrioc->sysif_regs->sense_buffer_free_host_index);
 168         spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
 169 }
 170
 171 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
 172         struct mpi3_event_notification_reply *event_reply)
 173 {
 174         char *desc = NULL;
 175         u16 event;
 176
 177         event = event_reply->event;
 178
 179         switch (event) {
 180         case MPI3_EVENT_LOG_DATA:
 181                 desc = "Log Data";
 182                 break;
 183         case MPI3_EVENT_CHANGE:
 184                 desc = "Event Change";
 185                 break;
 186         case MPI3_EVENT_GPIO_INTERRUPT:
 187                 desc = "GPIO Interrupt";
 188                 break;
 189         case MPI3_EVENT_CABLE_MGMT:
 190                 desc = "Cable Management";
 191                 break;
 192         case MPI3_EVENT_ENERGY_PACK_CHANGE:
 193                 desc = "Energy Pack Change";
 194                 break;
 195         case MPI3_EVENT_DEVICE_ADDED:
 196         {
 197                 struct mpi3_device_page0 *event_data =
 198                     (struct mpi3_device_page0 *)event_reply->event_data;
 199                 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
 200                     event_data->dev_handle, event_data->device_form);
 201                 return;
 202         }
 203         case MPI3_EVENT_DEVICE_INFO_CHANGED:
 204         {
 205                 struct mpi3_device_page0 *event_data =
 206                     (struct mpi3_device_page0 *)event_reply->event_data;
 207                 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
 208                     event_data->dev_handle, event_data->device_form);
 209                 return;
 210         }
 211         case MPI3_EVENT_DEVICE_STATUS_CHANGE:
 212         {
 213                 struct mpi3_event_data_device_status_change *event_data =
 214                     (struct mpi3_event_data_device_status_change *)event_reply->event_data;
 215                 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
 216                     event_data->dev_handle, event_data->reason_code);
 217                 return;
 218         }
 219         case MPI3_EVENT_SAS_DISCOVERY:
 220         {
 221                 struct mpi3_event_data_sas_discovery *event_data =
 222                     (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
 223                 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
 224                     (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
 225                     "start" : "stop",
 226                     le32_to_cpu(event_data->discovery_status));
 227                 return;
 228         }
 229         case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
 230                 desc = "SAS Broadcast Primitive";
 231                 break;
 232         case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
 233                 desc = "SAS Notify Primitive";
 234                 break;
 235         case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
 236                 desc = "SAS Init Device Status Change";
 237                 break;
 238         case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
 239                 desc = "SAS Init Table Overflow";
 240                 break;
 241         case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
 242                 desc = "SAS Topology Change List";
 243                 break;
 244         case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
 245                 desc = "Enclosure Device Status Change";
 246                 break;
 247         case MPI3_EVENT_ENCL_DEVICE_ADDED:
 248                 desc = "Enclosure Added";
 249                 break;
 250         case MPI3_EVENT_HARD_RESET_RECEIVED:
 251                 desc = "Hard Reset Received";
 252                 break;
 253         case MPI3_EVENT_SAS_PHY_COUNTER:
 254                 desc = "SAS PHY Counter";
 255                 break;
 256         case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
 257                 desc = "SAS Device Discovery Error";
 258                 break;
 259         case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
 260                 desc = "PCIE Topology Change List";
 261                 break;
 262         case MPI3_EVENT_PCIE_ENUMERATION:
 263         {
 264                 struct mpi3_event_data_pcie_enumeration *event_data =
 265                     (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
 266                 ioc_info(mrioc, "PCIE Enumeration: (%s)",
 267                     (event_data->reason_code ==
 268                     MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
 269                 if (event_data->enumeration_status)
 270                         ioc_info(mrioc, "enumeration_status(0x%08x)\n",
 271                             le32_to_cpu(event_data->enumeration_status));
 272                 return;
 273         }
 274         case MPI3_EVENT_PREPARE_FOR_RESET:
 275                 desc = "Prepare For Reset";
 276                 break;
 277         }
 278
 279         if (!desc)
 280                 return;
 281
 282         ioc_info(mrioc, "%s\n", desc);
 283 }
 284
 285 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
 286         struct mpi3_default_reply *def_reply)
 287 {
 288         struct mpi3_event_notification_reply *event_reply =
 289             (struct mpi3_event_notification_reply *)def_reply;
 290
 291         mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
 292         mpi3mr_print_event_data(mrioc, event_reply);
 293         mpi3mr_os_handle_events(mrioc, event_reply);
 294 }
 295
 296 static struct mpi3mr_drv_cmd *
 297 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
 298         struct mpi3_default_reply *def_reply)
 299 {
 300         u16 idx;
 301
 302         switch (host_tag) {
 303         case MPI3MR_HOSTTAG_INITCMDS:
 304                 return &mrioc->init_cmds;
 305         case MPI3MR_HOSTTAG_CFG_CMDS:
 306                 return &mrioc->cfg_cmds;
 307         case MPI3MR_HOSTTAG_BSG_CMDS:
 308                 return &mrioc->bsg_cmds;
 309         case MPI3MR_HOSTTAG_BLK_TMS:
 310                 return &mrioc->host_tm_cmds;
 311         case MPI3MR_HOSTTAG_PEL_ABORT:
 312                 return &mrioc->pel_abort_cmd;
 313         case MPI3MR_HOSTTAG_PEL_WAIT:
 314                 return &mrioc->pel_cmds;
 315         case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
 316                 return &mrioc->transport_cmds;
 317         case MPI3MR_HOSTTAG_INVALID:
 318                 if (def_reply && def_reply->function ==
 319                     MPI3_FUNCTION_EVENT_NOTIFICATION)
 320                         mpi3mr_handle_events(mrioc, def_reply);
 321                 return NULL;
 322         default:
 323                 break;
 324         }
 325         if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
 326             host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
 327                 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
 328                 return &mrioc->dev_rmhs_cmds[idx];
 329         }
 330
 331         if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
 332             host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
 333                 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
 334                 return &mrioc->evtack_cmds[idx];
 335         }
 336
 337         return NULL;
 338 }
 339
 340 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
 341         struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
 342 {
 343         u16 reply_desc_type, host_tag = 0;
 344         u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
 345         u32 ioc_loginfo = 0;
 346         struct mpi3_status_reply_descriptor *status_desc;
 347         struct mpi3_address_reply_descriptor *addr_desc;
 348         struct mpi3_success_reply_descriptor *success_desc;
 349         struct mpi3_default_reply *def_reply = NULL;
 350         struct mpi3mr_drv_cmd *cmdptr = NULL;
 351         struct mpi3_scsi_io_reply *scsi_reply;
 352         u8 *sense_buf = NULL;
 353
 354         *reply_dma = 0;
 355         reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
 356             MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
 357         switch (reply_desc_type) {
 358         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
 359                 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
 360                 host_tag = le16_to_cpu(status_desc->host_tag);
 361                 ioc_status = le16_to_cpu(status_desc->ioc_status);
 362                 if (ioc_status &
 363                     MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
 364                         ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
 365                 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
 366                 break;
 367         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
 368                 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
 369                 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
 370                 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
 371                 if (!def_reply)
 372                         goto out;
 373                 host_tag = le16_to_cpu(def_reply->host_tag);
 374                 ioc_status = le16_to_cpu(def_reply->ioc_status);
 375                 if (ioc_status &
 376                     MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
 377                         ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
 378                 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
 379                 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
 380                         scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
 381                         sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
 382                             le64_to_cpu(scsi_reply->sense_data_buffer_address));
 383                 }
 384                 break;
 385         case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
 386                 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
 387                 host_tag = le16_to_cpu(success_desc->host_tag);
 388                 break;
 389         default:
 390                 break;
 391         }
 392
 393         cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
 394         if (cmdptr) {
 395                 if (cmdptr->state & MPI3MR_CMD_PENDING) {
 396                         cmdptr->state |= MPI3MR_CMD_COMPLETE;
 397                         cmdptr->ioc_loginfo = ioc_loginfo;
 398                         cmdptr->ioc_status = ioc_status;
 399                         cmdptr->state &= ~MPI3MR_CMD_PENDING;
 400                         if (def_reply) {
 401                                 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
 402                                 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
 403                                     mrioc->reply_sz);
 404                         }
 405                         if (cmdptr->is_waiting) {
 406                                 complete(&cmdptr->done);
 407                                 cmdptr->is_waiting = 0;
 408                         } else if (cmdptr->callback)
 409                                 cmdptr->callback(mrioc, cmdptr);
 410                 }
 411         }
 412 out:
 413         if (sense_buf)
 414                 mpi3mr_repost_sense_buf(mrioc,
 415                     le64_to_cpu(scsi_reply->sense_data_buffer_address));
 416 }
 417
 418 static int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
 419 {
 420         u32 exp_phase = mrioc->admin_reply_ephase;
 421         u32 admin_reply_ci = mrioc->admin_reply_ci;
 422         u32 num_admin_replies = 0;
 423         u64 reply_dma = 0;
 424         struct mpi3_default_reply_descriptor *reply_desc;
 425
 426         reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
 427             admin_reply_ci;
 428
 429         if ((le16_to_cpu(reply_desc->reply_flags) &
 430             MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 431                 return 0;
 432
 433         do {
 434                 if (mrioc->unrecoverable)
 435                         break;
 436
 437                 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
 438                 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
 439                 if (reply_dma)
 440                         mpi3mr_repost_reply_buf(mrioc, reply_dma);
 441                 num_admin_replies++;
 442                 if (++admin_reply_ci == mrioc->num_admin_replies) {
 443                         admin_reply_ci = 0;
 444                         exp_phase ^= 1;
 445                 }
 446                 reply_desc =
 447                     (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
 448                     admin_reply_ci;
 449                 if ((le16_to_cpu(reply_desc->reply_flags) &
 450                     MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 451                         break;
 452         } while (1);
 453
 454         writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
 455         mrioc->admin_reply_ci = admin_reply_ci;
 456         mrioc->admin_reply_ephase = exp_phase;
 457
 458         return num_admin_replies;
 459 }
 460
 461 /**
 462  * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
 463  *      queue's consumer index from operational reply descriptor queue.
 464  * @op_reply_q: op_reply_qinfo object
 465  * @reply_ci: operational reply descriptor's queue consumer index
 466  *
 467  * Returns reply descriptor frame address
 468  */
 469 static inline struct mpi3_default_reply_descriptor *
 470 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
 471 {
 472         void *segment_base_addr;
 473         struct segments *segments = op_reply_q->q_segments;
 474         struct mpi3_default_reply_descriptor *reply_desc = NULL;
 475
 476         segment_base_addr =
 477             segments[reply_ci / op_reply_q->segment_qd].segment;
 478         reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
 479             (reply_ci % op_reply_q->segment_qd);
 480         return reply_desc;
 481 }
 482
 483 /**
 484  * mpi3mr_process_op_reply_q - Operational reply queue handler
 485  * @mrioc: Adapter instance reference
 486  * @op_reply_q: Operational reply queue info
 487  *
 488  * Checks the specific operational reply queue and drains the
 489  * reply queue entries until the queue is empty and process the
 490  * individual reply descriptors.
 491  *
 492  * Return: 0 if queue is already processed,or number of reply
 493  *          descriptors processed.
 494  */
 495 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
 496         struct op_reply_qinfo *op_reply_q)
 497 {
 498         struct op_req_qinfo *op_req_q;
 499         u32 exp_phase;
 500         u32 reply_ci;
 501         u32 num_op_reply = 0;
 502         u64 reply_dma = 0;
 503         struct mpi3_default_reply_descriptor *reply_desc;
 504         u16 req_q_idx = 0, reply_qidx;
 505
 506         reply_qidx = op_reply_q->qid - 1;
 507
 508         if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
 509                 return 0;
 510
 511         exp_phase = op_reply_q->ephase;
 512         reply_ci = op_reply_q->ci;
 513
 514         reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
 515         if ((le16_to_cpu(reply_desc->reply_flags) &
 516             MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
 517                 atomic_dec(&op_reply_q->in_use);
 518                 return 0;
 519         }
 520
 521         do {
 522                 if (mrioc->unrecoverable)
 523                         break;
 524
 525                 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
 526                 op_req_q = &mrioc->req_qinfo[req_q_idx];
 527
 528                 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
 529                 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
 530                     reply_qidx);
 531                 atomic_dec(&op_reply_q->pend_ios);
 532                 if (reply_dma)
 533                         mpi3mr_repost_reply_buf(mrioc, reply_dma);
 534                 num_op_reply++;
 535
 536                 if (++reply_ci == op_reply_q->num_replies) {
 537                         reply_ci = 0;
 538                         exp_phase ^= 1;
 539                 }
 540
 541                 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
 542
 543                 if ((le16_to_cpu(reply_desc->reply_flags) &
 544                     MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
 545                         break;
 546 #ifndef CONFIG_PREEMPT_RT
 547                 /*
 548                  * Exit completion loop to avoid CPU lockup
 549                  * Ensure remaining completion happens from threaded ISR.
 550                  */
 551                 if (num_op_reply > mrioc->max_host_ios) {
 552                         op_reply_q->enable_irq_poll = true;
 553                         break;
 554                 }
 555 #endif
 556         } while (1);
 557
 558         writel(reply_ci,
 559             &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
 560         op_reply_q->ci = reply_ci;
 561         op_reply_q->ephase = exp_phase;
 562
 563         atomic_dec(&op_reply_q->in_use);
 564         return num_op_reply;
 565 }
 566
 567 /**
 568  * mpi3mr_blk_mq_poll - Operational reply queue handler
 569  * @shost: SCSI Host reference
 570  * @queue_num: Request queue number (w.r.t OS it is hardware context number)
 571  *
 572  * Checks the specific operational reply queue and drains the
 573  * reply queue entries until the queue is empty and process the
 574  * individual reply descriptors.
 575  *
 576  * Return: 0 if queue is already processed,or number of reply
 577  *          descriptors processed.
 578  */
 579 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
 580 {
 581         int num_entries = 0;
 582         struct mpi3mr_ioc *mrioc;
 583
 584         mrioc = (struct mpi3mr_ioc *)shost->hostdata;
 585
 586         if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
 587             mrioc->unrecoverable))
 588                 return 0;
 589
 590         num_entries = mpi3mr_process_op_reply_q(mrioc,
 591                         &mrioc->op_reply_qinfo[queue_num]);
 592
 593         return num_entries;
 594 }
 595
 596 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
 597 {
 598         struct mpi3mr_intr_info *intr_info = privdata;
 599         struct mpi3mr_ioc *mrioc;
 600         u16 midx;
 601         u32 num_admin_replies = 0, num_op_reply = 0;
 602
 603         if (!intr_info)
 604                 return IRQ_NONE;
 605
 606         mrioc = intr_info->mrioc;
 607
 608         if (!mrioc->intr_enabled)
 609                 return IRQ_NONE;
 610
 611         midx = intr_info->msix_index;
 612
 613         if (!midx)
 614                 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
 615         if (intr_info->op_reply_q)
 616                 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
 617                     intr_info->op_reply_q);
 618
 619         if (num_admin_replies || num_op_reply)
 620                 return IRQ_HANDLED;
 621         else
 622                 return IRQ_NONE;
 623 }
 624
 625 #ifndef CONFIG_PREEMPT_RT
 626
 627 static irqreturn_t mpi3mr_isr(int irq, void *privdata)
 628 {
 629         struct mpi3mr_intr_info *intr_info = privdata;
 630         struct mpi3mr_ioc *mrioc;
 631         u16 midx;
 632         int ret;
 633
 634         if (!intr_info)
 635                 return IRQ_NONE;
 636
 637         mrioc = intr_info->mrioc;
 638         midx = intr_info->msix_index;
 639         /* Call primary ISR routine */
 640         ret = mpi3mr_isr_primary(irq, privdata);
 641
 642         /*
 643          * If more IOs are expected, schedule IRQ polling thread.
 644          * Otherwise exit from ISR.
 645          */
 646         if (!intr_info->op_reply_q)
 647                 return ret;
 648
 649         if (!intr_info->op_reply_q->enable_irq_poll ||
 650             !atomic_read(&intr_info->op_reply_q->pend_ios))
 651                 return ret;
 652
 653         disable_irq_nosync(pci_irq_vector(mrioc->pdev, midx));
 654
 655         return IRQ_WAKE_THREAD;
 656 }
 657
 658 /**
 659  * mpi3mr_isr_poll - Reply queue polling routine
 660  * @irq: IRQ
 661  * @privdata: Interrupt info
 662  *
 663  * poll for pending I/O completions in a loop until pending I/Os
 664  * present or controller queue depth I/Os are processed.
 665  *
 666  * Return: IRQ_NONE or IRQ_HANDLED
 667  */
 668 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
 669 {
 670         struct mpi3mr_intr_info *intr_info = privdata;
 671         struct mpi3mr_ioc *mrioc;
 672         u16 midx;
 673         u32 num_op_reply = 0;
 674
 675         if (!intr_info || !intr_info->op_reply_q)
 676                 return IRQ_NONE;
 677
 678         mrioc = intr_info->mrioc;
 679         midx = intr_info->msix_index;
 680
 681         /* Poll for pending IOs completions */
 682         do {
 683                 if (!mrioc->intr_enabled || mrioc->unrecoverable)
 684                         break;
 685
 686                 if (!midx)
 687                         mpi3mr_process_admin_reply_q(mrioc);
 688                 if (intr_info->op_reply_q)
 689                         num_op_reply +=
 690                             mpi3mr_process_op_reply_q(mrioc,
 691                                 intr_info->op_reply_q);
 692
 693                 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP);
 694
 695         } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
 696             (num_op_reply < mrioc->max_host_ios));
 697
 698         intr_info->op_reply_q->enable_irq_poll = false;
 699         enable_irq(pci_irq_vector(mrioc->pdev, midx));
 700
 701         return IRQ_HANDLED;
 702 }
 703
 704 #endif
 705
 706 /**
 707  * mpi3mr_request_irq - Request IRQ and register ISR
 708  * @mrioc: Adapter instance reference
 709  * @index: IRQ vector index
 710  *
 711  * Request threaded ISR with primary ISR and secondary
 712  *
 713  * Return: 0 on success and non zero on failures.
 714  */
 715 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
 716 {
 717         struct pci_dev *pdev = mrioc->pdev;
 718         struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
 719         int retval = 0;
 720
 721         intr_info->mrioc = mrioc;
 722         intr_info->msix_index = index;
 723         intr_info->op_reply_q = NULL;
 724
 725         snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
 726             mrioc->driver_name, mrioc->id, index);
 727
 728 #ifndef CONFIG_PREEMPT_RT
 729         retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
 730             mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
 731 #else
 732         retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
 733             NULL, IRQF_SHARED, intr_info->name, intr_info);
 734 #endif
 735         if (retval) {
 736                 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
 737                     intr_info->name, pci_irq_vector(pdev, index));
 738                 return retval;
 739         }
 740
 741         return retval;
 742 }
 743
 744 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
 745 {
 746         if (!mrioc->requested_poll_qcount)
 747                 return;
 748
 749         /* Reserved for Admin and Default Queue */
 750         if (max_vectors > 2 &&
 751                 (mrioc->requested_poll_qcount < max_vectors - 2)) {
 752                 ioc_info(mrioc,
 753                     "enabled polled queues (%d) msix (%d)\n",
 754                     mrioc->requested_poll_qcount, max_vectors);
 755         } else {
 756                 ioc_info(mrioc,
 757                     "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
 758                     mrioc->requested_poll_qcount, max_vectors);
 759                 mrioc->requested_poll_qcount = 0;
 760         }
 761 }
 762
 763 /**
 764  * mpi3mr_setup_isr - Setup ISR for the controller
 765  * @mrioc: Adapter instance reference
 766  * @setup_one: Request one IRQ or more
 767  *
 768  * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
 769  *
 770  * Return: 0 on success and non zero on failures.
 771  */
 772 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
 773 {
 774         unsigned int irq_flags = PCI_IRQ_MSIX;
 775         int max_vectors, min_vec;
 776         int retval;
 777         int i;
 778         struct irq_affinity desc = { .pre_vectors =  1, .post_vectors = 1 };
 779
 780         if (mrioc->is_intr_info_set)
 781                 return 0;
 782
 783         mpi3mr_cleanup_isr(mrioc);
 784
 785         if (setup_one || reset_devices) {
 786                 max_vectors = 1;
 787                 retval = pci_alloc_irq_vectors(mrioc->pdev,
 788                     1, max_vectors, irq_flags);
 789                 if (retval < 0) {
 790                         ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
 791                             retval);
 792                         goto out_failed;
 793                 }
 794         } else {
 795                 max_vectors =
 796                     min_t(int, mrioc->cpu_count + 1 +
 797                         mrioc->requested_poll_qcount, mrioc->msix_count);
 798
 799                 mpi3mr_calc_poll_queues(mrioc, max_vectors);
 800
 801                 ioc_info(mrioc,
 802                     "MSI-X vectors supported: %d, no of cores: %d,",
 803                     mrioc->msix_count, mrioc->cpu_count);
 804                 ioc_info(mrioc,
 805                     "MSI-x vectors requested: %d poll_queues %d\n",
 806                     max_vectors, mrioc->requested_poll_qcount);
 807
 808                 desc.post_vectors = mrioc->requested_poll_qcount;
 809                 min_vec = desc.pre_vectors + desc.post_vectors;
 810                 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
 811
 812                 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
 813                         min_vec, max_vectors, irq_flags, &desc);
 814
 815                 if (retval < 0) {
 816                         ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
 817                             retval);
 818                         goto out_failed;
 819                 }
 820
 821
 822                 /*
 823                  * If only one MSI-x is allocated, then MSI-x 0 will be shared
 824                  * between Admin queue and operational queue
 825                  */
 826                 if (retval == min_vec)
 827                         mrioc->op_reply_q_offset = 0;
 828                 else if (retval != (max_vectors)) {
 829                         ioc_info(mrioc,
 830                             "allocated vectors (%d) are less than configured (%d)\n",
 831                             retval, max_vectors);
 832                 }
 833
 834                 max_vectors = retval;
 835                 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
 836
 837                 mpi3mr_calc_poll_queues(mrioc, max_vectors);
 838
 839         }
 840
 841         mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
 842             GFP_KERNEL);
 843         if (!mrioc->intr_info) {
 844                 retval = -ENOMEM;
 845                 pci_free_irq_vectors(mrioc->pdev);
 846                 goto out_failed;
 847         }
 848         for (i = 0; i < max_vectors; i++) {
 849                 retval = mpi3mr_request_irq(mrioc, i);
 850                 if (retval) {
 851                         mrioc->intr_info_count = i;
 852                         goto out_failed;
 853                 }
 854         }
 855         if (reset_devices || !setup_one)
 856                 mrioc->is_intr_info_set = true;
 857         mrioc->intr_info_count = max_vectors;
 858         mpi3mr_ioc_enable_intr(mrioc);
 859         return 0;
 860
 861 out_failed:
 862         mpi3mr_cleanup_isr(mrioc);
 863
 864         return retval;
 865 }
 866
 867 static const struct {
 868         enum mpi3mr_iocstate value;
 869         char *name;
 870 } mrioc_states[] = {
 871         { MRIOC_STATE_READY, "ready" },
 872         { MRIOC_STATE_FAULT, "fault" },
 873         { MRIOC_STATE_RESET, "reset" },
 874         { MRIOC_STATE_BECOMING_READY, "becoming ready" },
 875         { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
 876         { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
 877 };
 878
 879 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
 880 {
 881         int i;
 882         char *name = NULL;
 883
 884         for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
 885                 if (mrioc_states[i].value == mrioc_state) {
 886                         name = mrioc_states[i].name;
 887                         break;
 888                 }
 889         }
 890         return name;
 891 }
 892
 893 /* Reset reason to name mapper structure*/
 894 static const struct {
 895         enum mpi3mr_reset_reason value;
 896         char *name;
 897 } mpi3mr_reset_reason_codes[] = {
 898         { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
 899         { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
 900         { MPI3MR_RESET_FROM_APP, "application invocation" },
 901         { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
 902         { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
 903         { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
 904         { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
 905         { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
 906         { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
 907         { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
 908         { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
 909         { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
 910         { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
 911         {
 912                 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
 913                 "create request queue timeout"
 914         },
 915         {
 916                 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
 917                 "create reply queue timeout"
 918         },
 919         { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
 920         { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
 921         { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
 922         { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
 923         {
 924                 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
 925                 "component image activation timeout"
 926         },
 927         {
 928                 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
 929                 "get package version timeout"
 930         },
 931         { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
 932         { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
 933         { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
 934         { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
 935         { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
 936 };
 937
 938 /**
 939  * mpi3mr_reset_rc_name - get reset reason code name
 940  * @reason_code: reset reason code value
 941  *
 942  * Map reset reason to an NULL terminated ASCII string
 943  *
 944  * Return: name corresponding to reset reason value or NULL.
 945  */
 946 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
 947 {
 948         int i;
 949         char *name = NULL;
 950
 951         for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
 952                 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
 953                         name = mpi3mr_reset_reason_codes[i].name;
 954                         break;
 955                 }
 956         }
 957         return name;
 958 }
 959
 960 /* Reset type to name mapper structure*/
 961 static const struct {
 962         u16 reset_type;
 963         char *name;
 964 } mpi3mr_reset_types[] = {
 965         { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
 966         { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
 967 };
 968
 969 /**
 970  * mpi3mr_reset_type_name - get reset type name
 971  * @reset_type: reset type value
 972  *
 973  * Map reset type to an NULL terminated ASCII string
 974  *
 975  * Return: name corresponding to reset type value or NULL.
 976  */
 977 static const char *mpi3mr_reset_type_name(u16 reset_type)
 978 {
 979         int i;
 980         char *name = NULL;
 981
 982         for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
 983                 if (mpi3mr_reset_types[i].reset_type == reset_type) {
 984                         name = mpi3mr_reset_types[i].name;
 985                         break;
 986                 }
 987         }
 988         return name;
 989 }
 990
 991 /**
 992  * mpi3mr_print_fault_info - Display fault information
 993  * @mrioc: Adapter instance reference
 994  *
 995  * Display the controller fault information if there is a
 996  * controller fault.
 997  *
 998  * Return: Nothing.
 999  */
1000 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1001 {
1002         u32 ioc_status, code, code1, code2, code3;
1003
1004         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1005
1006         if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1007                 code = readl(&mrioc->sysif_regs->fault);
1008                 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1009                 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1010                 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1011
1012                 ioc_info(mrioc,
1013                     "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1014                     code, code1, code2, code3);
1015         }
1016 }
1017
1018 /**
1019  * mpi3mr_get_iocstate - Get IOC State
1020  * @mrioc: Adapter instance reference
1021  *
1022  * Return a proper IOC state enum based on the IOC status and
1023  * IOC configuration and unrcoverable state of the controller.
1024  *
1025  * Return: Current IOC state.
1026  */
1027 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1028 {
1029         u32 ioc_status, ioc_config;
1030         u8 ready, enabled;
1031
1032         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1033         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1034
1035         if (mrioc->unrecoverable)
1036                 return MRIOC_STATE_UNRECOVERABLE;
1037         if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1038                 return MRIOC_STATE_FAULT;
1039
1040         ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1041         enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1042
1043         if (ready && enabled)
1044                 return MRIOC_STATE_READY;
1045         if ((!ready) && (!enabled))
1046                 return MRIOC_STATE_RESET;
1047         if ((!ready) && (enabled))
1048                 return MRIOC_STATE_BECOMING_READY;
1049
1050         return MRIOC_STATE_RESET_REQUESTED;
1051 }
1052
1053 /**
1054  * mpi3mr_clear_reset_history - clear reset history
1055  * @mrioc: Adapter instance reference
1056  *
1057  * Write the reset history bit in IOC status to clear the bit,
1058  * if it is already set.
1059  *
1060  * Return: Nothing.
1061  */
1062 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1063 {
1064         u32 ioc_status;
1065
1066         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1067         if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1068                 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1069 }
1070
1071 /**
1072  * mpi3mr_issue_and_process_mur - Message unit Reset handler
1073  * @mrioc: Adapter instance reference
1074  * @reset_reason: Reset reason code
1075  *
1076  * Issue Message unit Reset to the controller and wait for it to
1077  * be complete.
1078  *
1079  * Return: 0 on success, -1 on failure.
1080  */
1081 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1082         u32 reset_reason)
1083 {
1084         u32 ioc_config, timeout, ioc_status;
1085         int retval = -1;
1086
1087         ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1088         if (mrioc->unrecoverable) {
1089                 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1090                 return retval;
1091         }
1092         mpi3mr_clear_reset_history(mrioc);
1093         writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1094         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1095         ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1096         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1097
1098         timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1099         do {
1100                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1101                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1102                         mpi3mr_clear_reset_history(mrioc);
1103                         break;
1104                 }
1105                 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1106                         mpi3mr_print_fault_info(mrioc);
1107                         break;
1108                 }
1109                 msleep(100);
1110         } while (--timeout);
1111
1112         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1113         if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1114               (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1115               (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1116                 retval = 0;
1117
1118         ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
1119             (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1120         return retval;
1121 }
1122
1123 /**
1124  * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1125  * during reset/resume
1126  * @mrioc: Adapter instance reference
1127  *
1128  * Return zero if the new IOCFacts parameters value is compatible with
1129  * older values else return -EPERM
1130  */
1131 static int
1132 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1133 {
1134         u16 dev_handle_bitmap_sz;
1135         void *removepend_bitmap;
1136
1137         if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1138                 ioc_err(mrioc,
1139                     "cannot increase reply size from %d to %d\n",
1140                     mrioc->reply_sz, mrioc->facts.reply_sz);
1141                 return -EPERM;
1142         }
1143
1144         if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1145                 ioc_err(mrioc,
1146                     "cannot reduce number of operational reply queues from %d to %d\n",
1147                     mrioc->num_op_reply_q,
1148                     mrioc->facts.max_op_reply_q);
1149                 return -EPERM;
1150         }
1151
1152         if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1153                 ioc_err(mrioc,
1154                     "cannot reduce number of operational request queues from %d to %d\n",
1155                     mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1156                 return -EPERM;
1157         }
1158
1159         if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1160             MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED))
1161                 ioc_err(mrioc,
1162                     "critical error: multipath capability is enabled at the\n"
1163                     "\tcontroller while sas transport support is enabled at the\n"
1164                     "\tdriver, please reboot the system or reload the driver\n");
1165
1166         dev_handle_bitmap_sz = mrioc->facts.max_devhandle / 8;
1167         if (mrioc->facts.max_devhandle % 8)
1168                 dev_handle_bitmap_sz++;
1169         if (dev_handle_bitmap_sz > mrioc->dev_handle_bitmap_sz) {
1170                 removepend_bitmap = krealloc(mrioc->removepend_bitmap,
1171                     dev_handle_bitmap_sz, GFP_KERNEL);
1172                 if (!removepend_bitmap) {
1173                         ioc_err(mrioc,
1174                             "failed to increase removepend_bitmap sz from: %d to %d\n",
1175                             mrioc->dev_handle_bitmap_sz, dev_handle_bitmap_sz);
1176                         return -EPERM;
1177                 }
1178                 memset(removepend_bitmap + mrioc->dev_handle_bitmap_sz, 0,
1179                     dev_handle_bitmap_sz - mrioc->dev_handle_bitmap_sz);
1180                 mrioc->removepend_bitmap = removepend_bitmap;
1181                 ioc_info(mrioc,
1182                     "increased dev_handle_bitmap_sz from %d to %d\n",
1183                     mrioc->dev_handle_bitmap_sz, dev_handle_bitmap_sz);
1184                 mrioc->dev_handle_bitmap_sz = dev_handle_bitmap_sz;
1185         }
1186
1187         return 0;
1188 }
1189
1190 /**
1191  * mpi3mr_bring_ioc_ready - Bring controller to ready state
1192  * @mrioc: Adapter instance reference
1193  *
1194  * Set Enable IOC bit in IOC configuration register and wait for
1195  * the controller to become ready.
1196  *
1197  * Return: 0 on success, appropriate error on failure.
1198  */
1199 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1200 {
1201         u32 ioc_config, ioc_status, timeout;
1202         int retval = 0;
1203         enum mpi3mr_iocstate ioc_state;
1204         u64 base_info;
1205
1206         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1207         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1208         base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1209         ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1210             ioc_status, ioc_config, base_info);
1211
1212         /*The timeout value is in 2sec unit, changing it to seconds*/
1213         mrioc->ready_timeout =
1214             ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1215             MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1216
1217         ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1218
1219         ioc_state = mpi3mr_get_iocstate(mrioc);
1220         ioc_info(mrioc, "controller is in %s state during detection\n",
1221             mpi3mr_iocstate_name(ioc_state));
1222
1223         if (ioc_state == MRIOC_STATE_BECOMING_READY ||
1224             ioc_state == MRIOC_STATE_RESET_REQUESTED) {
1225                 timeout = mrioc->ready_timeout * 10;
1226                 do {
1227                         msleep(100);
1228                 } while (--timeout);
1229
1230                 if (!pci_device_is_present(mrioc->pdev)) {
1231                         mrioc->unrecoverable = 1;
1232                         ioc_err(mrioc,
1233                             "controller is not present while waiting to reset\n");
1234                         retval = -1;
1235                         goto out_device_not_present;
1236                 }
1237
1238                 ioc_state = mpi3mr_get_iocstate(mrioc);
1239                 ioc_info(mrioc,
1240                     "controller is in %s state after waiting to reset\n",
1241                     mpi3mr_iocstate_name(ioc_state));
1242         }
1243
1244         if (ioc_state == MRIOC_STATE_READY) {
1245                 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1246                 retval = mpi3mr_issue_and_process_mur(mrioc,
1247                     MPI3MR_RESET_FROM_BRINGUP);
1248                 ioc_state = mpi3mr_get_iocstate(mrioc);
1249                 if (retval)
1250                         ioc_err(mrioc,
1251                             "message unit reset failed with error %d current state %s\n",
1252                             retval, mpi3mr_iocstate_name(ioc_state));
1253         }
1254         if (ioc_state != MRIOC_STATE_RESET) {
1255                 mpi3mr_print_fault_info(mrioc);
1256                 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1257                 retval = mpi3mr_issue_reset(mrioc,
1258                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1259                     MPI3MR_RESET_FROM_BRINGUP);
1260                 if (retval) {
1261                         ioc_err(mrioc,
1262                             "soft reset failed with error %d\n", retval);
1263                         goto out_failed;
1264                 }
1265         }
1266         ioc_state = mpi3mr_get_iocstate(mrioc);
1267         if (ioc_state != MRIOC_STATE_RESET) {
1268                 ioc_err(mrioc,
1269                     "cannot bring controller to reset state, current state: %s\n",
1270                     mpi3mr_iocstate_name(ioc_state));
1271                 goto out_failed;
1272         }
1273         mpi3mr_clear_reset_history(mrioc);
1274         retval = mpi3mr_setup_admin_qpair(mrioc);
1275         if (retval) {
1276                 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1277                     retval);
1278                 goto out_failed;
1279         }
1280
1281         ioc_info(mrioc, "bringing controller to ready state\n");
1282         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1283         ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1284         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1285
1286         timeout = mrioc->ready_timeout * 10;
1287         do {
1288                 ioc_state = mpi3mr_get_iocstate(mrioc);
1289                 if (ioc_state == MRIOC_STATE_READY) {
1290                         ioc_info(mrioc,
1291                             "successfully transitioned to %s state\n",
1292                             mpi3mr_iocstate_name(ioc_state));
1293                         return 0;
1294                 }
1295                 if (!pci_device_is_present(mrioc->pdev)) {
1296                         mrioc->unrecoverable = 1;
1297                         ioc_err(mrioc,
1298                             "controller is not present at the bringup\n");
1299                         retval = -1;
1300                         goto out_device_not_present;
1301                 }
1302                 msleep(100);
1303         } while (--timeout);
1304
1305 out_failed:
1306         ioc_state = mpi3mr_get_iocstate(mrioc);
1307         ioc_err(mrioc,
1308             "failed to bring to ready state,  current state: %s\n",
1309             mpi3mr_iocstate_name(ioc_state));
1310 out_device_not_present:
1311         return retval;
1312 }
1313
1314 /**
1315  * mpi3mr_soft_reset_success - Check softreset is success or not
1316  * @ioc_status: IOC status register value
1317  * @ioc_config: IOC config register value
1318  *
1319  * Check whether the soft reset is successful or not based on
1320  * IOC status and IOC config register values.
1321  *
1322  * Return: True when the soft reset is success, false otherwise.
1323  */
1324 static inline bool
1325 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1326 {
1327         if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1328             (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1329                 return true;
1330         return false;
1331 }
1332
1333 /**
1334  * mpi3mr_diagfault_success - Check diag fault is success or not
1335  * @mrioc: Adapter reference
1336  * @ioc_status: IOC status register value
1337  *
1338  * Check whether the controller hit diag reset fault code.
1339  *
1340  * Return: True when there is diag fault, false otherwise.
1341  */
1342 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1343         u32 ioc_status)
1344 {
1345         u32 fault;
1346
1347         if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1348                 return false;
1349         fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1350         if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1351                 mpi3mr_print_fault_info(mrioc);
1352                 return true;
1353         }
1354         return false;
1355 }
1356
1357 /**
1358  * mpi3mr_set_diagsave - Set diag save bit for snapdump
1359  * @mrioc: Adapter reference
1360  *
1361  * Set diag save bit in IOC configuration register to enable
1362  * snapdump.
1363  *
1364  * Return: Nothing.
1365  */
1366 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1367 {
1368         u32 ioc_config;
1369
1370         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1371         ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1372         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1373 }
1374
1375 /**
1376  * mpi3mr_issue_reset - Issue reset to the controller
1377  * @mrioc: Adapter reference
1378  * @reset_type: Reset type
1379  * @reset_reason: Reset reason code
1380  *
1381  * Unlock the host diagnostic registers and write the specific
1382  * reset type to that, wait for reset acknowledgment from the
1383  * controller, if the reset is not successful retry for the
1384  * predefined number of times.
1385  *
1386  * Return: 0 on success, non-zero on failure.
1387  */
1388 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1389         u32 reset_reason)
1390 {
1391         int retval = -1;
1392         u8 unlock_retry_count = 0;
1393         u32 host_diagnostic, ioc_status, ioc_config;
1394         u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1395
1396         if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1397             (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1398                 return retval;
1399         if (mrioc->unrecoverable)
1400                 return retval;
1401         if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1402                 retval = 0;
1403                 return retval;
1404         }
1405
1406         ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1407             mpi3mr_reset_type_name(reset_type),
1408             mpi3mr_reset_rc_name(reset_reason), reset_reason);
1409
1410         mpi3mr_clear_reset_history(mrioc);
1411         do {
1412                 ioc_info(mrioc,
1413                     "Write magic sequence to unlock host diag register (retry=%d)\n",
1414                     ++unlock_retry_count);
1415                 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1416                         ioc_err(mrioc,
1417                             "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1418                             mpi3mr_reset_type_name(reset_type),
1419                             host_diagnostic);
1420                         mrioc->unrecoverable = 1;
1421                         return retval;
1422                 }
1423
1424                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1425                     &mrioc->sysif_regs->write_sequence);
1426                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1427                     &mrioc->sysif_regs->write_sequence);
1428                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1429                     &mrioc->sysif_regs->write_sequence);
1430                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1431                     &mrioc->sysif_regs->write_sequence);
1432                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1433                     &mrioc->sysif_regs->write_sequence);
1434                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1435                     &mrioc->sysif_regs->write_sequence);
1436                 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1437                     &mrioc->sysif_regs->write_sequence);
1438                 usleep_range(1000, 1100);
1439                 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1440                 ioc_info(mrioc,
1441                     "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1442                     unlock_retry_count, host_diagnostic);
1443         } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1444
1445         writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1446         writel(host_diagnostic | reset_type,
1447             &mrioc->sysif_regs->host_diagnostic);
1448         switch (reset_type) {
1449         case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1450                 do {
1451                         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1452                         ioc_config =
1453                             readl(&mrioc->sysif_regs->ioc_configuration);
1454                         if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1455                             && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1456                             ) {
1457                                 mpi3mr_clear_reset_history(mrioc);
1458                                 retval = 0;
1459                                 break;
1460                         }
1461                         msleep(100);
1462                 } while (--timeout);
1463                 mpi3mr_print_fault_info(mrioc);
1464                 break;
1465         case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1466                 do {
1467                         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1468                         if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1469                                 retval = 0;
1470                                 break;
1471                         }
1472                         msleep(100);
1473                 } while (--timeout);
1474                 break;
1475         default:
1476                 break;
1477         }
1478
1479         writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1480             &mrioc->sysif_regs->write_sequence);
1481
1482         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1483         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1484         ioc_info(mrioc,
1485             "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1486             (!retval)?"successful":"failed", ioc_status,
1487             ioc_config);
1488         if (retval)
1489                 mrioc->unrecoverable = 1;
1490         return retval;
1491 }
1492
1493 /**
1494  * mpi3mr_admin_request_post - Post request to admin queue
1495  * @mrioc: Adapter reference
1496  * @admin_req: MPI3 request
1497  * @admin_req_sz: Request size
1498  * @ignore_reset: Ignore reset in process
1499  *
1500  * Post the MPI3 request into admin request queue and
1501  * inform the controller, if the queue is full return
1502  * appropriate error.
1503  *
1504  * Return: 0 on success, non-zero on failure.
1505  */
1506 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1507         u16 admin_req_sz, u8 ignore_reset)
1508 {
1509         u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1510         int retval = 0;
1511         unsigned long flags;
1512         u8 *areq_entry;
1513
1514         if (mrioc->unrecoverable) {
1515                 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1516                 return -EFAULT;
1517         }
1518
1519         spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1520         areq_pi = mrioc->admin_req_pi;
1521         areq_ci = mrioc->admin_req_ci;
1522         max_entries = mrioc->num_admin_req;
1523         if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1524             (areq_pi == (max_entries - 1)))) {
1525                 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1526                 retval = -EAGAIN;
1527                 goto out;
1528         }
1529         if (!ignore_reset && mrioc->reset_in_progress) {
1530                 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1531                 retval = -EAGAIN;
1532                 goto out;
1533         }
1534         areq_entry = (u8 *)mrioc->admin_req_base +
1535             (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1536         memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1537         memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1538
1539         if (++areq_pi == max_entries)
1540                 areq_pi = 0;
1541         mrioc->admin_req_pi = areq_pi;
1542
1543         writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1544
1545 out:
1546         spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1547
1548         return retval;
1549 }
1550
1551 /**
1552  * mpi3mr_free_op_req_q_segments - free request memory segments
1553  * @mrioc: Adapter instance reference
1554  * @q_idx: operational request queue index
1555  *
1556  * Free memory segments allocated for operational request queue
1557  *
1558  * Return: Nothing.
1559  */
1560 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1561 {
1562         u16 j;
1563         int size;
1564         struct segments *segments;
1565
1566         segments = mrioc->req_qinfo[q_idx].q_segments;
1567         if (!segments)
1568                 return;
1569
1570         if (mrioc->enable_segqueue) {
1571                 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1572                 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1573                         dma_free_coherent(&mrioc->pdev->dev,
1574                             MPI3MR_MAX_SEG_LIST_SIZE,
1575                             mrioc->req_qinfo[q_idx].q_segment_list,
1576                             mrioc->req_qinfo[q_idx].q_segment_list_dma);
1577                         mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1578                 }
1579         } else
1580                 size = mrioc->req_qinfo[q_idx].segment_qd *
1581                     mrioc->facts.op_req_sz;
1582
1583         for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1584                 if (!segments[j].segment)
1585                         continue;
1586                 dma_free_coherent(&mrioc->pdev->dev,
1587                     size, segments[j].segment, segments[j].segment_dma);
1588                 segments[j].segment = NULL;
1589         }
1590         kfree(mrioc->req_qinfo[q_idx].q_segments);
1591         mrioc->req_qinfo[q_idx].q_segments = NULL;
1592         mrioc->req_qinfo[q_idx].qid = 0;
1593 }
1594
1595 /**
1596  * mpi3mr_free_op_reply_q_segments - free reply memory segments
1597  * @mrioc: Adapter instance reference
1598  * @q_idx: operational reply queue index
1599  *
1600  * Free memory segments allocated for operational reply queue
1601  *
1602  * Return: Nothing.
1603  */
1604 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1605 {
1606         u16 j;
1607         int size;
1608         struct segments *segments;
1609
1610         segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1611         if (!segments)
1612                 return;
1613
1614         if (mrioc->enable_segqueue) {
1615                 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1616                 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1617                         dma_free_coherent(&mrioc->pdev->dev,
1618                             MPI3MR_MAX_SEG_LIST_SIZE,
1619                             mrioc->op_reply_qinfo[q_idx].q_segment_list,
1620                             mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1621                         mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1622                 }
1623         } else
1624                 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1625                     mrioc->op_reply_desc_sz;
1626
1627         for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1628                 if (!segments[j].segment)
1629                         continue;
1630                 dma_free_coherent(&mrioc->pdev->dev,
1631                     size, segments[j].segment, segments[j].segment_dma);
1632                 segments[j].segment = NULL;
1633         }
1634
1635         kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1636         mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1637         mrioc->op_reply_qinfo[q_idx].qid = 0;
1638 }
1639
1640 /**
1641  * mpi3mr_delete_op_reply_q - delete operational reply queue
1642  * @mrioc: Adapter instance reference
1643  * @qidx: operational reply queue index
1644  *
1645  * Delete operatinal reply queue by issuing MPI request
1646  * through admin queue.
1647  *
1648  * Return:  0 on success, non-zero on failure.
1649  */
1650 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1651 {
1652         struct mpi3_delete_reply_queue_request delq_req;
1653         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1654         int retval = 0;
1655         u16 reply_qid = 0, midx;
1656
1657         reply_qid = op_reply_q->qid;
1658
1659         midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1660
1661         if (!reply_qid) {
1662                 retval = -1;
1663                 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1664                 goto out;
1665         }
1666
1667         (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1668             mrioc->active_poll_qcount--;
1669
1670         memset(&delq_req, 0, sizeof(delq_req));
1671         mutex_lock(&mrioc->init_cmds.mutex);
1672         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1673                 retval = -1;
1674                 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1675                 mutex_unlock(&mrioc->init_cmds.mutex);
1676                 goto out;
1677         }
1678         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1679         mrioc->init_cmds.is_waiting = 1;
1680         mrioc->init_cmds.callback = NULL;
1681         delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1682         delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1683         delq_req.queue_id = cpu_to_le16(reply_qid);
1684
1685         init_completion(&mrioc->init_cmds.done);
1686         retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1687             1);
1688         if (retval) {
1689                 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1690                 goto out_unlock;
1691         }
1692         wait_for_completion_timeout(&mrioc->init_cmds.done,
1693             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1694         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1695                 ioc_err(mrioc, "delete reply queue timed out\n");
1696                 mpi3mr_check_rh_fault_ioc(mrioc,
1697                     MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1698                 retval = -1;
1699                 goto out_unlock;
1700         }
1701         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1702             != MPI3_IOCSTATUS_SUCCESS) {
1703                 ioc_err(mrioc,
1704                     "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1705                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1706                     mrioc->init_cmds.ioc_loginfo);
1707                 retval = -1;
1708                 goto out_unlock;
1709         }
1710         mrioc->intr_info[midx].op_reply_q = NULL;
1711
1712         mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1713 out_unlock:
1714         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1715         mutex_unlock(&mrioc->init_cmds.mutex);
1716 out:
1717
1718         return retval;
1719 }
1720
1721 /**
1722  * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1723  * @mrioc: Adapter instance reference
1724  * @qidx: request queue index
1725  *
1726  * Allocate segmented memory pools for operational reply
1727  * queue.
1728  *
1729  * Return: 0 on success, non-zero on failure.
1730  */
1731 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1732 {
1733         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1734         int i, size;
1735         u64 *q_segment_list_entry = NULL;
1736         struct segments *segments;
1737
1738         if (mrioc->enable_segqueue) {
1739                 op_reply_q->segment_qd =
1740                     MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1741
1742                 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1743
1744                 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1745                     MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1746                     GFP_KERNEL);
1747                 if (!op_reply_q->q_segment_list)
1748                         return -ENOMEM;
1749                 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1750         } else {
1751                 op_reply_q->segment_qd = op_reply_q->num_replies;
1752                 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1753         }
1754
1755         op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1756             op_reply_q->segment_qd);
1757
1758         op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
1759             sizeof(struct segments), GFP_KERNEL);
1760         if (!op_reply_q->q_segments)
1761                 return -ENOMEM;
1762
1763         segments = op_reply_q->q_segments;
1764         for (i = 0; i < op_reply_q->num_segments; i++) {
1765                 segments[i].segment =
1766                     dma_alloc_coherent(&mrioc->pdev->dev,
1767                     size, &segments[i].segment_dma, GFP_KERNEL);
1768                 if (!segments[i].segment)
1769                         return -ENOMEM;
1770                 if (mrioc->enable_segqueue)
1771                         q_segment_list_entry[i] =
1772                             (unsigned long)segments[i].segment_dma;
1773         }
1774
1775         return 0;
1776 }
1777
1778 /**
1779  * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
1780  * @mrioc: Adapter instance reference
1781  * @qidx: request queue index
1782  *
1783  * Allocate segmented memory pools for operational request
1784  * queue.
1785  *
1786  * Return: 0 on success, non-zero on failure.
1787  */
1788 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1789 {
1790         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
1791         int i, size;
1792         u64 *q_segment_list_entry = NULL;
1793         struct segments *segments;
1794
1795         if (mrioc->enable_segqueue) {
1796                 op_req_q->segment_qd =
1797                     MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
1798
1799                 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1800
1801                 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1802                     MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
1803                     GFP_KERNEL);
1804                 if (!op_req_q->q_segment_list)
1805                         return -ENOMEM;
1806                 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
1807
1808         } else {
1809                 op_req_q->segment_qd = op_req_q->num_requests;
1810                 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
1811         }
1812
1813         op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
1814             op_req_q->segment_qd);
1815
1816         op_req_q->q_segments = kcalloc(op_req_q->num_segments,
1817             sizeof(struct segments), GFP_KERNEL);
1818         if (!op_req_q->q_segments)
1819                 return -ENOMEM;
1820
1821         segments = op_req_q->q_segments;
1822         for (i = 0; i < op_req_q->num_segments; i++) {
1823                 segments[i].segment =
1824                     dma_alloc_coherent(&mrioc->pdev->dev,
1825                     size, &segments[i].segment_dma, GFP_KERNEL);
1826                 if (!segments[i].segment)
1827                         return -ENOMEM;
1828                 if (mrioc->enable_segqueue)
1829                         q_segment_list_entry[i] =
1830                             (unsigned long)segments[i].segment_dma;
1831         }
1832
1833         return 0;
1834 }
1835
1836 /**
1837  * mpi3mr_create_op_reply_q - create operational reply queue
1838  * @mrioc: Adapter instance reference
1839  * @qidx: operational reply queue index
1840  *
1841  * Create operatinal reply queue by issuing MPI request
1842  * through admin queue.
1843  *
1844  * Return:  0 on success, non-zero on failure.
1845  */
1846 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1847 {
1848         struct mpi3_create_reply_queue_request create_req;
1849         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1850         int retval = 0;
1851         u16 reply_qid = 0, midx;
1852
1853         reply_qid = op_reply_q->qid;
1854
1855         midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1856
1857         if (reply_qid) {
1858                 retval = -1;
1859                 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
1860                     reply_qid);
1861
1862                 return retval;
1863         }
1864
1865         reply_qid = qidx + 1;
1866         op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
1867         if (!mrioc->pdev->revision)
1868                 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
1869         op_reply_q->ci = 0;
1870         op_reply_q->ephase = 1;
1871         atomic_set(&op_reply_q->pend_ios, 0);
1872         atomic_set(&op_reply_q->in_use, 0);
1873         op_reply_q->enable_irq_poll = false;
1874
1875         if (!op_reply_q->q_segments) {
1876                 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
1877                 if (retval) {
1878                         mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1879                         goto out;
1880                 }
1881         }
1882
1883         memset(&create_req, 0, sizeof(create_req));
1884         mutex_lock(&mrioc->init_cmds.mutex);
1885         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1886                 retval = -1;
1887                 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
1888                 goto out_unlock;
1889         }
1890         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1891         mrioc->init_cmds.is_waiting = 1;
1892         mrioc->init_cmds.callback = NULL;
1893         create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1894         create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
1895         create_req.queue_id = cpu_to_le16(reply_qid);
1896
1897         if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
1898                 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
1899         else
1900                 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
1901
1902         if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
1903                 create_req.flags =
1904                         MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
1905                 create_req.msix_index =
1906                         cpu_to_le16(mrioc->intr_info[midx].msix_index);
1907         } else {
1908                 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
1909                 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
1910                         reply_qid, midx);
1911                 if (!mrioc->active_poll_qcount)
1912                         disable_irq_nosync(pci_irq_vector(mrioc->pdev,
1913                             mrioc->intr_info_count - 1));
1914         }
1915
1916         if (mrioc->enable_segqueue) {
1917                 create_req.flags |=
1918                     MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
1919                 create_req.base_address = cpu_to_le64(
1920                     op_reply_q->q_segment_list_dma);
1921         } else
1922                 create_req.base_address = cpu_to_le64(
1923                     op_reply_q->q_segments[0].segment_dma);
1924
1925         create_req.size = cpu_to_le16(op_reply_q->num_replies);
1926
1927         init_completion(&mrioc->init_cmds.done);
1928         retval = mpi3mr_admin_request_post(mrioc, &create_req,
1929             sizeof(create_req), 1);
1930         if (retval) {
1931                 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
1932                 goto out_unlock;
1933         }
1934         wait_for_completion_timeout(&mrioc->init_cmds.done,
1935             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1936         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1937                 ioc_err(mrioc, "create reply queue timed out\n");
1938                 mpi3mr_check_rh_fault_ioc(mrioc,
1939                     MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
1940                 retval = -1;
1941                 goto out_unlock;
1942         }
1943         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1944             != MPI3_IOCSTATUS_SUCCESS) {
1945                 ioc_err(mrioc,
1946                     "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1947                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1948                     mrioc->init_cmds.ioc_loginfo);
1949                 retval = -1;
1950                 goto out_unlock;
1951         }
1952         op_reply_q->qid = reply_qid;
1953         if (midx < mrioc->intr_info_count)
1954                 mrioc->intr_info[midx].op_reply_q = op_reply_q;
1955
1956         (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
1957             mrioc->active_poll_qcount++;
1958
1959 out_unlock:
1960         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1961         mutex_unlock(&mrioc->init_cmds.mutex);
1962 out:
1963
1964         return retval;
1965 }
1966
1967 /**
1968  * mpi3mr_create_op_req_q - create operational request queue
1969  * @mrioc: Adapter instance reference
1970  * @idx: operational request queue index
1971  * @reply_qid: Reply queue ID
1972  *
1973  * Create operatinal request queue by issuing MPI request
1974  * through admin queue.
1975  *
1976  * Return:  0 on success, non-zero on failure.
1977  */
1978 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
1979         u16 reply_qid)
1980 {
1981         struct mpi3_create_request_queue_request create_req;
1982         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
1983         int retval = 0;
1984         u16 req_qid = 0;
1985
1986         req_qid = op_req_q->qid;
1987
1988         if (req_qid) {
1989                 retval = -1;
1990                 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
1991                     req_qid);
1992
1993                 return retval;
1994         }
1995         req_qid = idx + 1;
1996
1997         op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
1998         op_req_q->ci = 0;
1999         op_req_q->pi = 0;
2000         op_req_q->reply_qid = reply_qid;
2001         spin_lock_init(&op_req_q->q_lock);
2002
2003         if (!op_req_q->q_segments) {
2004                 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2005                 if (retval) {
2006                         mpi3mr_free_op_req_q_segments(mrioc, idx);
2007                         goto out;
2008                 }
2009         }
2010
2011         memset(&create_req, 0, sizeof(create_req));
2012         mutex_lock(&mrioc->init_cmds.mutex);
2013         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2014                 retval = -1;
2015                 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2016                 goto out_unlock;
2017         }
2018         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2019         mrioc->init_cmds.is_waiting = 1;
2020         mrioc->init_cmds.callback = NULL;
2021         create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2022         create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2023         create_req.queue_id = cpu_to_le16(req_qid);
2024         if (mrioc->enable_segqueue) {
2025                 create_req.flags =
2026                     MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2027                 create_req.base_address = cpu_to_le64(
2028                     op_req_q->q_segment_list_dma);
2029         } else
2030                 create_req.base_address = cpu_to_le64(
2031                     op_req_q->q_segments[0].segment_dma);
2032         create_req.reply_queue_id = cpu_to_le16(reply_qid);
2033         create_req.size = cpu_to_le16(op_req_q->num_requests);
2034
2035         init_completion(&mrioc->init_cmds.done);
2036         retval = mpi3mr_admin_request_post(mrioc, &create_req,
2037             sizeof(create_req), 1);
2038         if (retval) {
2039                 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2040                 goto out_unlock;
2041         }
2042         wait_for_completion_timeout(&mrioc->init_cmds.done,
2043             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2044         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2045                 ioc_err(mrioc, "create request queue timed out\n");
2046                 mpi3mr_check_rh_fault_ioc(mrioc,
2047                     MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2048                 retval = -1;
2049                 goto out_unlock;
2050         }
2051         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2052             != MPI3_IOCSTATUS_SUCCESS) {
2053                 ioc_err(mrioc,
2054                     "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2055                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2056                     mrioc->init_cmds.ioc_loginfo);
2057                 retval = -1;
2058                 goto out_unlock;
2059         }
2060         op_req_q->qid = req_qid;
2061
2062 out_unlock:
2063         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2064         mutex_unlock(&mrioc->init_cmds.mutex);
2065 out:
2066
2067         return retval;
2068 }
2069
2070 /**
2071  * mpi3mr_create_op_queues - create operational queue pairs
2072  * @mrioc: Adapter instance reference
2073  *
2074  * Allocate memory for operational queue meta data and call
2075  * create request and reply queue functions.
2076  *
2077  * Return: 0 on success, non-zero on failures.
2078  */
2079 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2080 {
2081         int retval = 0;
2082         u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2083
2084         num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2085             mrioc->facts.max_op_req_q);
2086
2087         msix_count_op_q =
2088             mrioc->intr_info_count - mrioc->op_reply_q_offset;
2089         if (!mrioc->num_queues)
2090                 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2091         /*
2092          * During reset set the num_queues to the number of queues
2093          * that was set before the reset.
2094          */
2095         num_queues = mrioc->num_op_reply_q ?
2096             mrioc->num_op_reply_q : mrioc->num_queues;
2097         ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2098             num_queues);
2099
2100         if (!mrioc->req_qinfo) {
2101                 mrioc->req_qinfo = kcalloc(num_queues,
2102                     sizeof(struct op_req_qinfo), GFP_KERNEL);
2103                 if (!mrioc->req_qinfo) {
2104                         retval = -1;
2105                         goto out_failed;
2106                 }
2107
2108                 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2109                     num_queues, GFP_KERNEL);
2110                 if (!mrioc->op_reply_qinfo) {
2111                         retval = -1;
2112                         goto out_failed;
2113                 }
2114         }
2115
2116         if (mrioc->enable_segqueue)
2117                 ioc_info(mrioc,
2118                     "allocating operational queues through segmented queues\n");
2119
2120         for (i = 0; i < num_queues; i++) {
2121                 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2122                         ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2123                         break;
2124                 }
2125                 if (mpi3mr_create_op_req_q(mrioc, i,
2126                     mrioc->op_reply_qinfo[i].qid)) {
2127                         ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2128                         mpi3mr_delete_op_reply_q(mrioc, i);
2129                         break;
2130                 }
2131         }
2132
2133         if (i == 0) {
2134                 /* Not even one queue is created successfully*/
2135                 retval = -1;
2136                 goto out_failed;
2137         }
2138         mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2139         ioc_info(mrioc,
2140             "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2141             mrioc->num_op_reply_q, mrioc->default_qcount,
2142             mrioc->active_poll_qcount);
2143
2144         return retval;
2145 out_failed:
2146         kfree(mrioc->req_qinfo);
2147         mrioc->req_qinfo = NULL;
2148
2149         kfree(mrioc->op_reply_qinfo);
2150         mrioc->op_reply_qinfo = NULL;
2151
2152         return retval;
2153 }
2154
2155 /**
2156  * mpi3mr_op_request_post - Post request to operational queue
2157  * @mrioc: Adapter reference
2158  * @op_req_q: Operational request queue info
2159  * @req: MPI3 request
2160  *
2161  * Post the MPI3 request into operational request queue and
2162  * inform the controller, if the queue is full return
2163  * appropriate error.
2164  *
2165  * Return: 0 on success, non-zero on failure.
2166  */
2167 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2168         struct op_req_qinfo *op_req_q, u8 *req)
2169 {
2170         u16 pi = 0, max_entries, reply_qidx = 0, midx;
2171         int retval = 0;
2172         unsigned long flags;
2173         u8 *req_entry;
2174         void *segment_base_addr;
2175         u16 req_sz = mrioc->facts.op_req_sz;
2176         struct segments *segments = op_req_q->q_segments;
2177
2178         reply_qidx = op_req_q->reply_qid - 1;
2179
2180         if (mrioc->unrecoverable)
2181                 return -EFAULT;
2182
2183         spin_lock_irqsave(&op_req_q->q_lock, flags);
2184         pi = op_req_q->pi;
2185         max_entries = op_req_q->num_requests;
2186
2187         if (mpi3mr_check_req_qfull(op_req_q)) {
2188                 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2189                     reply_qidx, mrioc->op_reply_q_offset);
2190                 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2191
2192                 if (mpi3mr_check_req_qfull(op_req_q)) {
2193                         retval = -EAGAIN;
2194                         goto out;
2195                 }
2196         }
2197
2198         if (mrioc->reset_in_progress) {
2199                 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2200                 retval = -EAGAIN;
2201                 goto out;
2202         }
2203
2204         segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2205         req_entry = (u8 *)segment_base_addr +
2206             ((pi % op_req_q->segment_qd) * req_sz);
2207
2208         memset(req_entry, 0, req_sz);
2209         memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2210
2211         if (++pi == max_entries)
2212                 pi = 0;
2213         op_req_q->pi = pi;
2214
2215 #ifndef CONFIG_PREEMPT_RT
2216         if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2217             > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2218                 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2219 #else
2220         atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2221 #endif
2222
2223         writel(op_req_q->pi,
2224             &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2225
2226 out:
2227         spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2228         return retval;
2229 }
2230
2231 /**
2232  * mpi3mr_check_rh_fault_ioc - check reset history and fault
2233  * controller
2234  * @mrioc: Adapter instance reference
2235  * @reason_code: reason code for the fault.
2236  *
2237  * This routine will save snapdump and fault the controller with
2238  * the given reason code if it is not already in the fault or
2239  * not asynchronosuly reset. This will be used to handle
2240  * initilaization time faults/resets/timeout as in those cases
2241  * immediate soft reset invocation is not required.
2242  *
2243  * Return:  None.
2244  */
2245 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2246 {
2247         u32 ioc_status, host_diagnostic, timeout;
2248
2249         if (mrioc->unrecoverable) {
2250                 ioc_err(mrioc, "controller is unrecoverable\n");
2251                 return;
2252         }
2253
2254         if (!pci_device_is_present(mrioc->pdev)) {
2255                 mrioc->unrecoverable = 1;
2256                 ioc_err(mrioc, "controller is not present\n");
2257                 return;
2258         }
2259
2260         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2261         if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2262             (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
2263                 mpi3mr_print_fault_info(mrioc);
2264                 return;
2265         }
2266         mpi3mr_set_diagsave(mrioc);
2267         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2268             reason_code);
2269         timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2270         do {
2271                 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2272                 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2273                         break;
2274                 msleep(100);
2275         } while (--timeout);
2276 }
2277
2278 /**
2279  * mpi3mr_sync_timestamp - Issue time stamp sync request
2280  * @mrioc: Adapter reference
2281  *
2282  * Issue IO unit control MPI request to synchornize firmware
2283  * timestamp with host time.
2284  *
2285  * Return: 0 on success, non-zero on failure.
2286  */
2287 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2288 {
2289         ktime_t current_time;
2290         struct mpi3_iounit_control_request iou_ctrl;
2291         int retval = 0;
2292
2293         memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2294         mutex_lock(&mrioc->init_cmds.mutex);
2295         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2296                 retval = -1;
2297                 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2298                 mutex_unlock(&mrioc->init_cmds.mutex);
2299                 goto out;
2300         }
2301         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2302         mrioc->init_cmds.is_waiting = 1;
2303         mrioc->init_cmds.callback = NULL;
2304         iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2305         iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2306         iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2307         current_time = ktime_get_real();
2308         iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2309
2310         init_completion(&mrioc->init_cmds.done);
2311         retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2312             sizeof(iou_ctrl), 0);
2313         if (retval) {
2314                 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2315                 goto out_unlock;
2316         }
2317
2318         wait_for_completion_timeout(&mrioc->init_cmds.done,
2319             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2320         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2321                 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2322                 mrioc->init_cmds.is_waiting = 0;
2323                 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2324                         mpi3mr_soft_reset_handler(mrioc,
2325                             MPI3MR_RESET_FROM_TSU_TIMEOUT, 1);
2326                 retval = -1;
2327                 goto out_unlock;
2328         }
2329         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2330             != MPI3_IOCSTATUS_SUCCESS) {
2331                 ioc_err(mrioc,
2332                     "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2333                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2334                     mrioc->init_cmds.ioc_loginfo);
2335                 retval = -1;
2336                 goto out_unlock;
2337         }
2338
2339 out_unlock:
2340         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2341         mutex_unlock(&mrioc->init_cmds.mutex);
2342
2343 out:
2344         return retval;
2345 }
2346
2347 /**
2348  * mpi3mr_print_pkg_ver - display controller fw package version
2349  * @mrioc: Adapter reference
2350  *
2351  * Retrieve firmware package version from the component image
2352  * header of the controller flash and display it.
2353  *
2354  * Return: 0 on success and non-zero on failure.
2355  */
2356 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2357 {
2358         struct mpi3_ci_upload_request ci_upload;
2359         int retval = -1;
2360         void *data = NULL;
2361         dma_addr_t data_dma;
2362         struct mpi3_ci_manifest_mpi *manifest;
2363         u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2364         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2365
2366         data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2367             GFP_KERNEL);
2368         if (!data)
2369                 return -ENOMEM;
2370
2371         memset(&ci_upload, 0, sizeof(ci_upload));
2372         mutex_lock(&mrioc->init_cmds.mutex);
2373         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2374                 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2375                 mutex_unlock(&mrioc->init_cmds.mutex);
2376                 goto out;
2377         }
2378         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2379         mrioc->init_cmds.is_waiting = 1;
2380         mrioc->init_cmds.callback = NULL;
2381         ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2382         ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2383         ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2384         ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2385         ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2386         ci_upload.segment_size = cpu_to_le32(data_len);
2387
2388         mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2389             data_dma);
2390         init_completion(&mrioc->init_cmds.done);
2391         retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2392             sizeof(ci_upload), 1);
2393         if (retval) {
2394                 ioc_err(mrioc, "posting get package version failed\n");
2395                 goto out_unlock;
2396         }
2397         wait_for_completion_timeout(&mrioc->init_cmds.done,
2398             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2399         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2400                 ioc_err(mrioc, "get package version timed out\n");
2401                 mpi3mr_check_rh_fault_ioc(mrioc,
2402                     MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2403                 retval = -1;
2404                 goto out_unlock;
2405         }
2406         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2407             == MPI3_IOCSTATUS_SUCCESS) {
2408                 manifest = (struct mpi3_ci_manifest_mpi *) data;
2409                 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2410                         ioc_info(mrioc,
2411                             "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2412                             manifest->package_version.gen_major,
2413                             manifest->package_version.gen_minor,
2414                             manifest->package_version.phase_major,
2415                             manifest->package_version.phase_minor,
2416                             manifest->package_version.customer_id,
2417                             manifest->package_version.build_num);
2418                 }
2419         }
2420         retval = 0;
2421 out_unlock:
2422         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2423         mutex_unlock(&mrioc->init_cmds.mutex);
2424
2425 out:
2426         if (data)
2427                 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2428                     data_dma);
2429         return retval;
2430 }
2431
2432 /**
2433  * mpi3mr_watchdog_work - watchdog thread to monitor faults
2434  * @work: work struct
2435  *
2436  * Watch dog work periodically executed (1 second interval) to
2437  * monitor firmware fault and to issue periodic timer sync to
2438  * the firmware.
2439  *
2440  * Return: Nothing.
2441  */
2442 static void mpi3mr_watchdog_work(struct work_struct *work)
2443 {
2444         struct mpi3mr_ioc *mrioc =
2445             container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2446         unsigned long flags;
2447         enum mpi3mr_iocstate ioc_state;
2448         u32 fault, host_diagnostic, ioc_status;
2449         u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2450
2451         if (mrioc->reset_in_progress)
2452                 return;
2453
2454         if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2455                 ioc_err(mrioc, "watchdog could not detect the controller\n");
2456                 mrioc->unrecoverable = 1;
2457         }
2458
2459         if (mrioc->unrecoverable) {
2460                 ioc_err(mrioc,
2461                     "flush pending commands for unrecoverable controller\n");
2462                 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2463                 return;
2464         }
2465
2466         if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) {
2467                 mrioc->ts_update_counter = 0;
2468                 mpi3mr_sync_timestamp(mrioc);
2469         }
2470
2471         if ((mrioc->prepare_for_reset) &&
2472             ((mrioc->prepare_for_reset_timeout_counter++) >=
2473              MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2474                 mpi3mr_soft_reset_handler(mrioc,
2475                     MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2476                 return;
2477         }
2478
2479         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2480         if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2481                 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2482                 return;
2483         }
2484
2485         /*Check for fault state every one second and issue Soft reset*/
2486         ioc_state = mpi3mr_get_iocstate(mrioc);
2487         if (ioc_state != MRIOC_STATE_FAULT)
2488                 goto schedule_work;
2489
2490         fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2491         host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2492         if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2493                 if (!mrioc->diagsave_timeout) {
2494                         mpi3mr_print_fault_info(mrioc);
2495                         ioc_warn(mrioc, "diag save in progress\n");
2496                 }
2497                 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2498                         goto schedule_work;
2499         }
2500
2501         mpi3mr_print_fault_info(mrioc);
2502         mrioc->diagsave_timeout = 0;
2503
2504         switch (fault) {
2505         case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2506         case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2507                 ioc_warn(mrioc,
2508                     "controller requires system power cycle, marking controller as unrecoverable\n");
2509                 mrioc->unrecoverable = 1;
2510                 goto schedule_work;
2511         case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2512                 return;
2513         case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2514                 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2515                 break;
2516         default:
2517                 break;
2518         }
2519         mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2520         return;
2521
2522 schedule_work:
2523         spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2524         if (mrioc->watchdog_work_q)
2525                 queue_delayed_work(mrioc->watchdog_work_q,
2526                     &mrioc->watchdog_work,
2527                     msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2528         spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2529         return;
2530 }
2531
2532 /**
2533  * mpi3mr_start_watchdog - Start watchdog
2534  * @mrioc: Adapter instance reference
2535  *
2536  * Create and start the watchdog thread to monitor controller
2537  * faults.
2538  *
2539  * Return: Nothing.
2540  */
2541 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2542 {
2543         if (mrioc->watchdog_work_q)
2544                 return;
2545
2546         INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2547         snprintf(mrioc->watchdog_work_q_name,
2548             sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2549             mrioc->id);
2550         mrioc->watchdog_work_q =
2551             create_singlethread_workqueue(mrioc->watchdog_work_q_name);
2552         if (!mrioc->watchdog_work_q) {
2553                 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2554                 return;
2555         }
2556
2557         if (mrioc->watchdog_work_q)
2558                 queue_delayed_work(mrioc->watchdog_work_q,
2559                     &mrioc->watchdog_work,
2560                     msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2561 }
2562
2563 /**
2564  * mpi3mr_stop_watchdog - Stop watchdog
2565  * @mrioc: Adapter instance reference
2566  *
2567  * Stop the watchdog thread created to monitor controller
2568  * faults.
2569  *
2570  * Return: Nothing.
2571  */
2572 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2573 {
2574         unsigned long flags;
2575         struct workqueue_struct *wq;
2576
2577         spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2578         wq = mrioc->watchdog_work_q;
2579         mrioc->watchdog_work_q = NULL;
2580         spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2581         if (wq) {
2582                 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2583                         flush_workqueue(wq);
2584                 destroy_workqueue(wq);
2585         }
2586 }
2587
2588 /**
2589  * mpi3mr_setup_admin_qpair - Setup admin queue pair
2590  * @mrioc: Adapter instance reference
2591  *
2592  * Allocate memory for admin queue pair if required and register
2593  * the admin queue with the controller.
2594  *
2595  * Return: 0 on success, non-zero on failures.
2596  */
2597 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2598 {
2599         int retval = 0;
2600         u32 num_admin_entries = 0;
2601
2602         mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2603         mrioc->num_admin_req = mrioc->admin_req_q_sz /
2604             MPI3MR_ADMIN_REQ_FRAME_SZ;
2605         mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2606         mrioc->admin_req_base = NULL;
2607
2608         mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2609         mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2610             MPI3MR_ADMIN_REPLY_FRAME_SZ;
2611         mrioc->admin_reply_ci = 0;
2612         mrioc->admin_reply_ephase = 1;
2613         mrioc->admin_reply_base = NULL;
2614
2615         if (!mrioc->admin_req_base) {
2616                 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2617                     mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2618
2619                 if (!mrioc->admin_req_base) {
2620                         retval = -1;
2621                         goto out_failed;
2622                 }
2623
2624                 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2625                     mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2626                     GFP_KERNEL);
2627
2628                 if (!mrioc->admin_reply_base) {
2629                         retval = -1;
2630                         goto out_failed;
2631                 }
2632         }
2633
2634         num_admin_entries = (mrioc->num_admin_replies << 16) |
2635             (mrioc->num_admin_req);
2636         writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2637         mpi3mr_writeq(mrioc->admin_req_dma,
2638             &mrioc->sysif_regs->admin_request_queue_address);
2639         mpi3mr_writeq(mrioc->admin_reply_dma,
2640             &mrioc->sysif_regs->admin_reply_queue_address);
2641         writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2642         writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2643         return retval;
2644
2645 out_failed:
2646
2647         if (mrioc->admin_reply_base) {
2648                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2649                     mrioc->admin_reply_base, mrioc->admin_reply_dma);
2650                 mrioc->admin_reply_base = NULL;
2651         }
2652         if (mrioc->admin_req_base) {
2653                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2654                     mrioc->admin_req_base, mrioc->admin_req_dma);
2655                 mrioc->admin_req_base = NULL;
2656         }
2657         return retval;
2658 }
2659
2660 /**
2661  * mpi3mr_issue_iocfacts - Send IOC Facts
2662  * @mrioc: Adapter instance reference
2663  * @facts_data: Cached IOC facts data
2664  *
2665  * Issue IOC Facts MPI request through admin queue and wait for
2666  * the completion of it or time out.
2667  *
2668  * Return: 0 on success, non-zero on failures.
2669  */
2670 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2671         struct mpi3_ioc_facts_data *facts_data)
2672 {
2673         struct mpi3_ioc_facts_request iocfacts_req;
2674         void *data = NULL;
2675         dma_addr_t data_dma;
2676         u32 data_len = sizeof(*facts_data);
2677         int retval = 0;
2678         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2679
2680         data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2681             GFP_KERNEL);
2682
2683         if (!data) {
2684                 retval = -1;
2685                 goto out;
2686         }
2687
2688         memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2689         mutex_lock(&mrioc->init_cmds.mutex);
2690         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2691                 retval = -1;
2692                 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2693                 mutex_unlock(&mrioc->init_cmds.mutex);
2694                 goto out;
2695         }
2696         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2697         mrioc->init_cmds.is_waiting = 1;
2698         mrioc->init_cmds.callback = NULL;
2699         iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2700         iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2701
2702         mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2703             data_dma);
2704
2705         init_completion(&mrioc->init_cmds.done);
2706         retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2707             sizeof(iocfacts_req), 1);
2708         if (retval) {
2709                 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
2710                 goto out_unlock;
2711         }
2712         wait_for_completion_timeout(&mrioc->init_cmds.done,
2713             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2714         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2715                 ioc_err(mrioc, "ioc_facts timed out\n");
2716                 mpi3mr_check_rh_fault_ioc(mrioc,
2717                     MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2718                 retval = -1;
2719                 goto out_unlock;
2720         }
2721         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2722             != MPI3_IOCSTATUS_SUCCESS) {
2723                 ioc_err(mrioc,
2724                     "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2725                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2726                     mrioc->init_cmds.ioc_loginfo);
2727                 retval = -1;
2728                 goto out_unlock;
2729         }
2730         memcpy(facts_data, (u8 *)data, data_len);
2731         mpi3mr_process_factsdata(mrioc, facts_data);
2732 out_unlock:
2733         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2734         mutex_unlock(&mrioc->init_cmds.mutex);
2735
2736 out:
2737         if (data)
2738                 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
2739
2740         return retval;
2741 }
2742
2743 /**
2744  * mpi3mr_check_reset_dma_mask - Process IOC facts data
2745  * @mrioc: Adapter instance reference
2746  *
2747  * Check whether the new DMA mask requested through IOCFacts by
2748  * firmware needs to be set, if so set it .
2749  *
2750  * Return: 0 on success, non-zero on failure.
2751  */
2752 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
2753 {
2754         struct pci_dev *pdev = mrioc->pdev;
2755         int r;
2756         u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
2757
2758         if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
2759                 return 0;
2760
2761         ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
2762             mrioc->dma_mask, facts_dma_mask);
2763
2764         r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
2765         if (r) {
2766                 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
2767                     facts_dma_mask, r);
2768                 return r;
2769         }
2770         mrioc->dma_mask = facts_dma_mask;
2771         return r;
2772 }
2773
2774 /**
2775  * mpi3mr_process_factsdata - Process IOC facts data
2776  * @mrioc: Adapter instance reference
2777  * @facts_data: Cached IOC facts data
2778  *
2779  * Convert IOC facts data into cpu endianness and cache it in
2780  * the driver .
2781  *
2782  * Return: Nothing.
2783  */
2784 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
2785         struct mpi3_ioc_facts_data *facts_data)
2786 {
2787         u32 ioc_config, req_sz, facts_flags;
2788
2789         if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
2790             (sizeof(*facts_data) / 4)) {
2791                 ioc_warn(mrioc,
2792                     "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
2793                     sizeof(*facts_data),
2794                     le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
2795         }
2796
2797         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
2798         req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
2799             MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
2800         if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
2801                 ioc_err(mrioc,
2802                     "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
2803                     req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
2804         }
2805
2806         memset(&mrioc->facts, 0, sizeof(mrioc->facts));
2807
2808         facts_flags = le32_to_cpu(facts_data->flags);
2809         mrioc->facts.op_req_sz = req_sz;
2810         mrioc->op_reply_desc_sz = 1 << ((ioc_config &
2811             MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
2812             MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
2813
2814         mrioc->facts.ioc_num = facts_data->ioc_number;
2815         mrioc->facts.who_init = facts_data->who_init;
2816         mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
2817         mrioc->facts.personality = (facts_flags &
2818             MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
2819         mrioc->facts.dma_mask = (facts_flags &
2820             MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
2821             MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
2822         mrioc->facts.protocol_flags = facts_data->protocol_flags;
2823         mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
2824         mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
2825         mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
2826         mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
2827         mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
2828         mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
2829         mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
2830         mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
2831         mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
2832         mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
2833         mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
2834         mrioc->facts.max_pcie_switches =
2835             le16_to_cpu(facts_data->max_pcie_switches);
2836         mrioc->facts.max_sasexpanders =
2837             le16_to_cpu(facts_data->max_sas_expanders);
2838         mrioc->facts.max_sasinitiators =
2839             le16_to_cpu(facts_data->max_sas_initiators);
2840         mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
2841         mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
2842         mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
2843         mrioc->facts.max_op_req_q =
2844             le16_to_cpu(facts_data->max_operational_request_queues);
2845         mrioc->facts.max_op_reply_q =
2846             le16_to_cpu(facts_data->max_operational_reply_queues);
2847         mrioc->facts.ioc_capabilities =
2848             le32_to_cpu(facts_data->ioc_capabilities);
2849         mrioc->facts.fw_ver.build_num =
2850             le16_to_cpu(facts_data->fw_version.build_num);
2851         mrioc->facts.fw_ver.cust_id =
2852             le16_to_cpu(facts_data->fw_version.customer_id);
2853         mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
2854         mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
2855         mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
2856         mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
2857         mrioc->msix_count = min_t(int, mrioc->msix_count,
2858             mrioc->facts.max_msix_vectors);
2859         mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
2860         mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
2861         mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
2862         mrioc->facts.shutdown_timeout =
2863             le16_to_cpu(facts_data->shutdown_timeout);
2864
2865         mrioc->facts.max_dev_per_tg =
2866             facts_data->max_devices_per_throttle_group;
2867         mrioc->facts.io_throttle_data_length =
2868             le16_to_cpu(facts_data->io_throttle_data_length);
2869         mrioc->facts.max_io_throttle_group =
2870             le16_to_cpu(facts_data->max_io_throttle_group);
2871         mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
2872         mrioc->facts.io_throttle_high =
2873             le16_to_cpu(facts_data->io_throttle_high);
2874
2875         /* Store in 512b block count */
2876         if (mrioc->facts.io_throttle_data_length)
2877                 mrioc->io_throttle_data_length =
2878                     (mrioc->facts.io_throttle_data_length * 2 * 4);
2879         else
2880                 /* set the length to 1MB + 1K to disable throttle */
2881                 mrioc->io_throttle_data_length = MPI3MR_MAX_SECTORS + 2;
2882
2883         mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
2884         mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
2885
2886         ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
2887             mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
2888             mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
2889         ioc_info(mrioc,
2890             "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
2891             mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
2892             mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
2893         ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
2894             mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
2895             mrioc->facts.sge_mod_shift);
2896         ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n",
2897             mrioc->facts.dma_mask, (facts_flags &
2898             MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK));
2899         ioc_info(mrioc,
2900             "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
2901             mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
2902         ioc_info(mrioc,
2903            "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
2904            mrioc->facts.io_throttle_data_length * 4,
2905            mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
2906 }
2907
2908 /**
2909  * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
2910  * @mrioc: Adapter instance reference
2911  *
2912  * Allocate and initialize the reply free buffers, sense
2913  * buffers, reply free queue and sense buffer queue.
2914  *
2915  * Return: 0 on success, non-zero on failures.
2916  */
2917 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
2918 {
2919         int retval = 0;
2920         u32 sz, i;
2921
2922         if (mrioc->init_cmds.reply)
2923                 return retval;
2924
2925         mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2926         if (!mrioc->init_cmds.reply)
2927                 goto out_failed;
2928
2929         mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2930         if (!mrioc->bsg_cmds.reply)
2931                 goto out_failed;
2932
2933         mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2934         if (!mrioc->transport_cmds.reply)
2935                 goto out_failed;
2936
2937         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
2938                 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
2939                     GFP_KERNEL);
2940                 if (!mrioc->dev_rmhs_cmds[i].reply)
2941                         goto out_failed;
2942         }
2943
2944         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
2945                 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
2946                     GFP_KERNEL);
2947                 if (!mrioc->evtack_cmds[i].reply)
2948                         goto out_failed;
2949         }
2950
2951         mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2952         if (!mrioc->host_tm_cmds.reply)
2953                 goto out_failed;
2954
2955         mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2956         if (!mrioc->pel_cmds.reply)
2957                 goto out_failed;
2958
2959         mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2960         if (!mrioc->pel_abort_cmd.reply)
2961                 goto out_failed;
2962
2963         mrioc->dev_handle_bitmap_sz = mrioc->facts.max_devhandle / 8;
2964         if (mrioc->facts.max_devhandle % 8)
2965                 mrioc->dev_handle_bitmap_sz++;
2966         mrioc->removepend_bitmap = kzalloc(mrioc->dev_handle_bitmap_sz,
2967             GFP_KERNEL);
2968         if (!mrioc->removepend_bitmap)
2969                 goto out_failed;
2970
2971         mrioc->devrem_bitmap_sz = MPI3MR_NUM_DEVRMCMD / 8;
2972         if (MPI3MR_NUM_DEVRMCMD % 8)
2973                 mrioc->devrem_bitmap_sz++;
2974         mrioc->devrem_bitmap = kzalloc(mrioc->devrem_bitmap_sz,
2975             GFP_KERNEL);
2976         if (!mrioc->devrem_bitmap)
2977                 goto out_failed;
2978
2979         mrioc->evtack_cmds_bitmap_sz = MPI3MR_NUM_EVTACKCMD / 8;
2980         if (MPI3MR_NUM_EVTACKCMD % 8)
2981                 mrioc->evtack_cmds_bitmap_sz++;
2982         mrioc->evtack_cmds_bitmap = kzalloc(mrioc->evtack_cmds_bitmap_sz,
2983             GFP_KERNEL);
2984         if (!mrioc->evtack_cmds_bitmap)
2985                 goto out_failed;
2986
2987         mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
2988         mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
2989         mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
2990         mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
2991
2992         /* reply buffer pool, 16 byte align */
2993         sz = mrioc->num_reply_bufs * mrioc->reply_sz;
2994         mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
2995             &mrioc->pdev->dev, sz, 16, 0);
2996         if (!mrioc->reply_buf_pool) {
2997                 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
2998                 goto out_failed;
2999         }
3000
3001         mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3002             &mrioc->reply_buf_dma);
3003         if (!mrioc->reply_buf)
3004                 goto out_failed;
3005
3006         mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3007
3008         /* reply free queue, 8 byte align */
3009         sz = mrioc->reply_free_qsz * 8;
3010         mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3011             &mrioc->pdev->dev, sz, 8, 0);
3012         if (!mrioc->reply_free_q_pool) {
3013                 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3014                 goto out_failed;
3015         }
3016         mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3017             GFP_KERNEL, &mrioc->reply_free_q_dma);
3018         if (!mrioc->reply_free_q)
3019                 goto out_failed;
3020
3021         /* sense buffer pool,  4 byte align */
3022         sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3023         mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3024             &mrioc->pdev->dev, sz, 4, 0);
3025         if (!mrioc->sense_buf_pool) {
3026                 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3027                 goto out_failed;
3028         }
3029         mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3030             &mrioc->sense_buf_dma);
3031         if (!mrioc->sense_buf)
3032                 goto out_failed;
3033
3034         /* sense buffer queue, 8 byte align */
3035         sz = mrioc->sense_buf_q_sz * 8;
3036         mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3037             &mrioc->pdev->dev, sz, 8, 0);
3038         if (!mrioc->sense_buf_q_pool) {
3039                 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3040                 goto out_failed;
3041         }
3042         mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3043             GFP_KERNEL, &mrioc->sense_buf_q_dma);
3044         if (!mrioc->sense_buf_q)
3045                 goto out_failed;
3046
3047         return retval;
3048
3049 out_failed:
3050         retval = -1;
3051         return retval;
3052 }
3053
3054 /**
3055  * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3056  * buffers
3057  * @mrioc: Adapter instance reference
3058  *
3059  * Helper function to initialize reply and sense buffers along
3060  * with some debug prints.
3061  *
3062  * Return:  None.
3063  */
3064 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3065 {
3066         u32 sz, i;
3067         dma_addr_t phy_addr;
3068
3069         sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3070         ioc_info(mrioc,
3071             "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3072             mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3073             (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3074         sz = mrioc->reply_free_qsz * 8;
3075         ioc_info(mrioc,
3076             "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3077             mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3078             (unsigned long long)mrioc->reply_free_q_dma);
3079         sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3080         ioc_info(mrioc,
3081             "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3082             mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3083             (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3084         sz = mrioc->sense_buf_q_sz * 8;
3085         ioc_info(mrioc,
3086             "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3087             mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3088             (unsigned long long)mrioc->sense_buf_q_dma);
3089
3090         /* initialize Reply buffer Queue */
3091         for (i = 0, phy_addr = mrioc->reply_buf_dma;
3092             i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3093                 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3094         mrioc->reply_free_q[i] = cpu_to_le64(0);
3095
3096         /* initialize Sense Buffer Queue */
3097         for (i = 0, phy_addr = mrioc->sense_buf_dma;
3098             i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3099                 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3100         mrioc->sense_buf_q[i] = cpu_to_le64(0);
3101 }
3102
3103 /**
3104  * mpi3mr_issue_iocinit - Send IOC Init
3105  * @mrioc: Adapter instance reference
3106  *
3107  * Issue IOC Init MPI request through admin queue and wait for
3108  * the completion of it or time out.
3109  *
3110  * Return: 0 on success, non-zero on failures.
3111  */
3112 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3113 {
3114         struct mpi3_ioc_init_request iocinit_req;
3115         struct mpi3_driver_info_layout *drv_info;
3116         dma_addr_t data_dma;
3117         u32 data_len = sizeof(*drv_info);
3118         int retval = 0;
3119         ktime_t current_time;
3120
3121         drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3122             GFP_KERNEL);
3123         if (!drv_info) {
3124                 retval = -1;
3125                 goto out;
3126         }
3127         mpimr_initialize_reply_sbuf_queues(mrioc);
3128
3129         drv_info->information_length = cpu_to_le32(data_len);
3130         strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3131         strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3132         strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3133         strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3134         strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3135         strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3136             sizeof(drv_info->driver_release_date));
3137         drv_info->driver_capabilities = 0;
3138         memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3139             sizeof(mrioc->driver_info));
3140
3141         memset(&iocinit_req, 0, sizeof(iocinit_req));
3142         mutex_lock(&mrioc->init_cmds.mutex);
3143         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3144                 retval = -1;
3145                 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3146                 mutex_unlock(&mrioc->init_cmds.mutex);
3147                 goto out;
3148         }
3149         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3150         mrioc->init_cmds.is_waiting = 1;
3151         mrioc->init_cmds.callback = NULL;
3152         iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3153         iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3154         iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3155         iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3156         iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3157         iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3158         iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3159         iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3160         iocinit_req.reply_free_queue_address =
3161             cpu_to_le64(mrioc->reply_free_q_dma);
3162         iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3163         iocinit_req.sense_buffer_free_queue_depth =
3164             cpu_to_le16(mrioc->sense_buf_q_sz);
3165         iocinit_req.sense_buffer_free_queue_address =
3166             cpu_to_le64(mrioc->sense_buf_q_dma);
3167         iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3168
3169         current_time = ktime_get_real();
3170         iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3171
3172         init_completion(&mrioc->init_cmds.done);
3173         retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3174             sizeof(iocinit_req), 1);
3175         if (retval) {
3176                 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3177                 goto out_unlock;
3178         }
3179         wait_for_completion_timeout(&mrioc->init_cmds.done,
3180             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3181         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3182                 mpi3mr_check_rh_fault_ioc(mrioc,
3183                     MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3184                 ioc_err(mrioc, "ioc_init timed out\n");
3185                 retval = -1;
3186                 goto out_unlock;
3187         }
3188         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3189             != MPI3_IOCSTATUS_SUCCESS) {
3190                 ioc_err(mrioc,
3191                     "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3192                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3193                     mrioc->init_cmds.ioc_loginfo);
3194                 retval = -1;
3195                 goto out_unlock;
3196         }
3197
3198         mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3199         writel(mrioc->reply_free_queue_host_index,
3200             &mrioc->sysif_regs->reply_free_host_index);
3201
3202         mrioc->sbq_host_index = mrioc->num_sense_bufs;
3203         writel(mrioc->sbq_host_index,
3204             &mrioc->sysif_regs->sense_buffer_free_host_index);
3205 out_unlock:
3206         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3207         mutex_unlock(&mrioc->init_cmds.mutex);
3208
3209 out:
3210         if (drv_info)
3211                 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3212                     data_dma);
3213
3214         return retval;
3215 }
3216
3217 /**
3218  * mpi3mr_unmask_events - Unmask events in event mask bitmap
3219  * @mrioc: Adapter instance reference
3220  * @event: MPI event ID
3221  *
3222  * Un mask the specific event by resetting the event_mask
3223  * bitmap.
3224  *
3225  * Return: 0 on success, non-zero on failures.
3226  */
3227 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3228 {
3229         u32 desired_event;
3230         u8 word;
3231
3232         if (event >= 128)
3233                 return;
3234
3235         desired_event = (1 << (event % 32));
3236         word = event / 32;
3237
3238         mrioc->event_masks[word] &= ~desired_event;
3239 }
3240
3241 /**
3242  * mpi3mr_issue_event_notification - Send event notification
3243  * @mrioc: Adapter instance reference
3244  *
3245  * Issue event notification MPI request through admin queue and
3246  * wait for the completion of it or time out.
3247  *
3248  * Return: 0 on success, non-zero on failures.
3249  */
3250 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3251 {
3252         struct mpi3_event_notification_request evtnotify_req;
3253         int retval = 0;
3254         u8 i;
3255
3256         memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3257         mutex_lock(&mrioc->init_cmds.mutex);
3258         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3259                 retval = -1;
3260                 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3261                 mutex_unlock(&mrioc->init_cmds.mutex);
3262                 goto out;
3263         }
3264         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3265         mrioc->init_cmds.is_waiting = 1;
3266         mrioc->init_cmds.callback = NULL;
3267         evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3268         evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3269         for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3270                 evtnotify_req.event_masks[i] =
3271                     cpu_to_le32(mrioc->event_masks[i]);
3272         init_completion(&mrioc->init_cmds.done);
3273         retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3274             sizeof(evtnotify_req), 1);
3275         if (retval) {
3276                 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3277                 goto out_unlock;
3278         }
3279         wait_for_completion_timeout(&mrioc->init_cmds.done,
3280             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3281         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3282                 ioc_err(mrioc, "event notification timed out\n");
3283                 mpi3mr_check_rh_fault_ioc(mrioc,
3284                     MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3285                 retval = -1;
3286                 goto out_unlock;
3287         }
3288         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3289             != MPI3_IOCSTATUS_SUCCESS) {
3290                 ioc_err(mrioc,
3291                     "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3292                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3293                     mrioc->init_cmds.ioc_loginfo);
3294                 retval = -1;
3295                 goto out_unlock;
3296         }
3297
3298 out_unlock:
3299         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3300         mutex_unlock(&mrioc->init_cmds.mutex);
3301 out:
3302         return retval;
3303 }
3304
3305 /**
3306  * mpi3mr_process_event_ack - Process event acknowledgment
3307  * @mrioc: Adapter instance reference
3308  * @event: MPI3 event ID
3309  * @event_ctx: event context
3310  *
3311  * Send event acknowledgment through admin queue and wait for
3312  * it to complete.
3313  *
3314  * Return: 0 on success, non-zero on failures.
3315  */
3316 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3317         u32 event_ctx)
3318 {
3319         struct mpi3_event_ack_request evtack_req;
3320         int retval = 0;
3321
3322         memset(&evtack_req, 0, sizeof(evtack_req));
3323         mutex_lock(&mrioc->init_cmds.mutex);
3324         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3325                 retval = -1;
3326                 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3327                 mutex_unlock(&mrioc->init_cmds.mutex);
3328                 goto out;
3329         }
3330         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3331         mrioc->init_cmds.is_waiting = 1;
3332         mrioc->init_cmds.callback = NULL;
3333         evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3334         evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3335         evtack_req.event = event;
3336         evtack_req.event_context = cpu_to_le32(event_ctx);
3337
3338         init_completion(&mrioc->init_cmds.done);
3339         retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3340             sizeof(evtack_req), 1);
3341         if (retval) {
3342                 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3343                 goto out_unlock;
3344         }
3345         wait_for_completion_timeout(&mrioc->init_cmds.done,
3346             (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3347         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3348                 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3349                 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3350                         mpi3mr_soft_reset_handler(mrioc,
3351                             MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1);
3352                 retval = -1;
3353                 goto out_unlock;
3354         }
3355         if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3356             != MPI3_IOCSTATUS_SUCCESS) {
3357                 ioc_err(mrioc,
3358                     "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3359                     (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3360                     mrioc->init_cmds.ioc_loginfo);
3361                 retval = -1;
3362                 goto out_unlock;
3363         }
3364
3365 out_unlock:
3366         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3367         mutex_unlock(&mrioc->init_cmds.mutex);
3368 out:
3369         return retval;
3370 }
3371
3372 /**
3373  * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3374  * @mrioc: Adapter instance reference
3375  *
3376  * Allocate chain buffers and set a bitmap to indicate free
3377  * chain buffers. Chain buffers are used to pass the SGE
3378  * information along with MPI3 SCSI IO requests for host I/O.
3379  *
3380  * Return: 0 on success, non-zero on failure
3381  */
3382 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3383 {
3384         int retval = 0;
3385         u32 sz, i;
3386         u16 num_chains;
3387
3388         if (mrioc->chain_sgl_list)
3389                 return retval;
3390
3391         num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3392
3393         if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3394             | SHOST_DIX_TYPE1_PROTECTION
3395             | SHOST_DIX_TYPE2_PROTECTION
3396             | SHOST_DIX_TYPE3_PROTECTION))
3397                 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3398
3399         mrioc->chain_buf_count = num_chains;
3400         sz = sizeof(struct chain_element) * num_chains;
3401         mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3402         if (!mrioc->chain_sgl_list)
3403                 goto out_failed;
3404
3405         sz = MPI3MR_PAGE_SIZE_4K;
3406         mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3407             &mrioc->pdev->dev, sz, 16, 0);
3408         if (!mrioc->chain_buf_pool) {
3409                 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3410                 goto out_failed;
3411         }
3412
3413         for (i = 0; i < num_chains; i++) {
3414                 mrioc->chain_sgl_list[i].addr =
3415                     dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3416                     &mrioc->chain_sgl_list[i].dma_addr);
3417
3418                 if (!mrioc->chain_sgl_list[i].addr)
3419                         goto out_failed;
3420         }
3421         mrioc->chain_bitmap_sz = num_chains / 8;
3422         if (num_chains % 8)
3423                 mrioc->chain_bitmap_sz++;
3424         mrioc->chain_bitmap = kzalloc(mrioc->chain_bitmap_sz, GFP_KERNEL);
3425         if (!mrioc->chain_bitmap)
3426                 goto out_failed;
3427         return retval;
3428 out_failed:
3429         retval = -1;
3430         return retval;
3431 }
3432
3433 /**
3434  * mpi3mr_port_enable_complete - Mark port enable complete
3435  * @mrioc: Adapter instance reference
3436  * @drv_cmd: Internal command tracker
3437  *
3438  * Call back for asynchronous port enable request sets the
3439  * driver command to indicate port enable request is complete.
3440  *
3441  * Return: Nothing
3442  */
3443 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3444         struct mpi3mr_drv_cmd *drv_cmd)
3445 {
3446         drv_cmd->callback = NULL;
3447         mrioc->scan_started = 0;
3448         if (drv_cmd->state & MPI3MR_CMD_RESET)
3449                 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3450         else
3451                 mrioc->scan_failed = drv_cmd->ioc_status;
3452         drv_cmd->state = MPI3MR_CMD_NOTUSED;
3453 }
3454
3455 /**
3456  * mpi3mr_issue_port_enable - Issue Port Enable
3457  * @mrioc: Adapter instance reference
3458  * @async: Flag to wait for completion or not
3459  *
3460  * Issue Port Enable MPI request through admin queue and if the
3461  * async flag is not set wait for the completion of the port
3462  * enable or time out.
3463  *
3464  * Return: 0 on success, non-zero on failures.
3465  */
3466 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3467 {
3468         struct mpi3_port_enable_request pe_req;
3469         int retval = 0;
3470         u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3471
3472         memset(&pe_req, 0, sizeof(pe_req));
3473         mutex_lock(&mrioc->init_cmds.mutex);
3474         if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3475                 retval = -1;
3476                 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3477                 mutex_unlock(&mrioc->init_cmds.mutex);
3478                 goto out;
3479         }
3480         mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3481         if (async) {
3482                 mrioc->init_cmds.is_waiting = 0;
3483                 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3484         } else {
3485                 mrioc->init_cmds.is_waiting = 1;
3486                 mrioc->init_cmds.callback = NULL;
3487                 init_completion(&mrioc->init_cmds.done);
3488         }
3489         pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3490         pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3491
3492         retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3493         if (retval) {
3494                 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3495                 goto out_unlock;
3496         }
3497         if (async) {
3498                 mutex_unlock(&mrioc->init_cmds.mutex);
3499                 goto out;
3500         }
3501
3502         wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3503         if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3504                 ioc_err(mrioc, "port enable timed out\n");
3505                 retval = -1;
3506                 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3507                 goto out_unlock;
3508         }
3509         mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3510
3511 out_unlock:
3512         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3513         mutex_unlock(&mrioc->init_cmds.mutex);
3514 out:
3515         return retval;
3516 }
3517
3518 /* Protocol type to name mapper structure */
3519 static const struct {
3520         u8 protocol;
3521         char *name;
3522 } mpi3mr_protocols[] = {
3523         { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3524         { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3525         { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3526 };
3527
3528 /* Capability to name mapper structure*/
3529 static const struct {
3530         u32 capability;
3531         char *name;
3532 } mpi3mr_capabilities[] = {
3533         { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" },
3534         { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" },
3535 };
3536
3537 /**
3538  * mpi3mr_print_ioc_info - Display controller information
3539  * @mrioc: Adapter instance reference
3540  *
3541  * Display controller personalit, capability, supported
3542  * protocols etc.
3543  *
3544  * Return: Nothing
3545  */
3546 static void
3547 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3548 {
3549         int i = 0, bytes_written = 0;
3550         char personality[16];
3551         char protocol[50] = {0};
3552         char capabilities[100] = {0};
3553         struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3554
3555         switch (mrioc->facts.personality) {
3556         case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3557                 strncpy(personality, "Enhanced HBA", sizeof(personality));
3558                 break;
3559         case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3560                 strncpy(personality, "RAID", sizeof(personality));
3561                 break;
3562         default:
3563                 strncpy(personality, "Unknown", sizeof(personality));
3564                 break;
3565         }
3566
3567         ioc_info(mrioc, "Running in %s Personality", personality);
3568
3569         ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3570             fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3571             fwver->ph_minor, fwver->cust_id, fwver->build_num);
3572
3573         for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3574                 if (mrioc->facts.protocol_flags &
3575                     mpi3mr_protocols[i].protocol) {
3576                         bytes_written += scnprintf(protocol + bytes_written,
3577                                     sizeof(protocol) - bytes_written, "%s%s",
3578                                     bytes_written ? "," : "",
3579                                     mpi3mr_protocols[i].name);
3580                 }
3581         }
3582
3583         bytes_written = 0;
3584         for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3585                 if (mrioc->facts.protocol_flags &
3586                     mpi3mr_capabilities[i].capability) {
3587                         bytes_written += scnprintf(capabilities + bytes_written,
3588                                     sizeof(capabilities) - bytes_written, "%s%s",
3589                                     bytes_written ? "," : "",
3590                                     mpi3mr_capabilities[i].name);
3591                 }
3592         }
3593
3594         ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
3595                  protocol, capabilities);
3596 }
3597
3598 /**
3599  * mpi3mr_cleanup_resources - Free PCI resources
3600  * @mrioc: Adapter instance reference
3601  *
3602  * Unmap PCI device memory and disable PCI device.
3603  *
3604  * Return: 0 on success and non-zero on failure.
3605  */
3606 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
3607 {
3608         struct pci_dev *pdev = mrioc->pdev;
3609
3610         mpi3mr_cleanup_isr(mrioc);
3611
3612         if (mrioc->sysif_regs) {
3613                 iounmap((void __iomem *)mrioc->sysif_regs);
3614                 mrioc->sysif_regs = NULL;
3615         }
3616
3617         if (pci_is_enabled(pdev)) {
3618                 if (mrioc->bars)
3619                         pci_release_selected_regions(pdev, mrioc->bars);
3620                 pci_disable_device(pdev);
3621         }
3622 }
3623
3624 /**
3625  * mpi3mr_setup_resources - Enable PCI resources
3626  * @mrioc: Adapter instance reference
3627  *
3628  * Enable PCI device memory, MSI-x registers and set DMA mask.
3629  *
3630  * Return: 0 on success and non-zero on failure.
3631  */
3632 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
3633 {
3634         struct pci_dev *pdev = mrioc->pdev;
3635         u32 memap_sz = 0;
3636         int i, retval = 0, capb = 0;
3637         u16 message_control;
3638         u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
3639             (((dma_get_required_mask(&pdev->dev) > DMA_BIT_MASK(32)) &&
3640             (sizeof(dma_addr_t) > 4)) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
3641
3642         if (pci_enable_device_mem(pdev)) {
3643                 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
3644                 retval = -ENODEV;
3645                 goto out_failed;
3646         }
3647
3648         capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3649         if (!capb) {
3650                 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
3651                 retval = -ENODEV;
3652                 goto out_failed;
3653         }
3654         mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3655
3656         if (pci_request_selected_regions(pdev, mrioc->bars,
3657             mrioc->driver_name)) {
3658                 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
3659                 retval = -ENODEV;
3660                 goto out_failed;
3661         }
3662
3663         for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
3664                 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3665                         mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
3666                         memap_sz = pci_resource_len(pdev, i);
3667                         mrioc->sysif_regs =
3668                             ioremap(mrioc->sysif_regs_phys, memap_sz);
3669                         break;
3670                 }
3671         }
3672
3673         pci_set_master(pdev);
3674
3675         retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
3676         if (retval) {
3677                 if (dma_mask != DMA_BIT_MASK(32)) {
3678                         ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
3679                         dma_mask = DMA_BIT_MASK(32);
3680                         retval = dma_set_mask_and_coherent(&pdev->dev,
3681                             dma_mask);
3682                 }
3683                 if (retval) {
3684                         mrioc->dma_mask = 0;
3685                         ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
3686                         goto out_failed;
3687                 }
3688         }
3689         mrioc->dma_mask = dma_mask;
3690
3691         if (!mrioc->sysif_regs) {
3692                 ioc_err(mrioc,
3693                     "Unable to map adapter memory or resource not found\n");
3694                 retval = -EINVAL;
3695                 goto out_failed;
3696         }
3697
3698         pci_read_config_word(pdev, capb + 2, &message_control);
3699         mrioc->msix_count = (message_control & 0x3FF) + 1;
3700
3701         pci_save_state(pdev);
3702
3703         pci_set_drvdata(pdev, mrioc->shost);
3704
3705         mpi3mr_ioc_disable_intr(mrioc);
3706
3707         ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
3708             (unsigned long long)mrioc->sysif_regs_phys,
3709             mrioc->sysif_regs, memap_sz);
3710         ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
3711             mrioc->msix_count);
3712
3713         if (!reset_devices && poll_queues > 0)
3714                 mrioc->requested_poll_qcount = min_t(int, poll_queues,
3715                                 mrioc->msix_count - 2);
3716         return retval;
3717
3718 out_failed:
3719         mpi3mr_cleanup_resources(mrioc);
3720         return retval;
3721 }
3722
3723 /**
3724  * mpi3mr_enable_events - Enable required events
3725  * @mrioc: Adapter instance reference
3726  *
3727  * This routine unmasks the events required by the driver by
3728  * sennding appropriate event mask bitmapt through an event
3729  * notification request.
3730  *
3731  * Return: 0 on success and non-zero on failure.
3732  */
3733 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
3734 {
3735         int retval = 0;
3736         u32  i;
3737
3738         for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3739                 mrioc->event_masks[i] = -1;
3740
3741         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
3742         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
3743         mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
3744         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
3745         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
3746         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
3747         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
3748         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
3749         mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
3750         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
3751         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
3752         mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
3753         mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
3754         mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
3755
3756         retval = mpi3mr_issue_event_notification(mrioc);
3757         if (retval)
3758                 ioc_err(mrioc, "failed to issue event notification %d\n",
3759                     retval);
3760         return retval;
3761 }
3762
3763 /**
3764  * mpi3mr_init_ioc - Initialize the controller
3765  * @mrioc: Adapter instance reference
3766  *
3767  * This the controller initialization routine, executed either
3768  * after soft reset or from pci probe callback.
3769  * Setup the required resources, memory map the controller
3770  * registers, create admin and operational reply queue pairs,
3771  * allocate required memory for reply pool, sense buffer pool,
3772  * issue IOC init request to the firmware, unmask the events and
3773  * issue port enable to discover SAS/SATA/NVMe devies and RAID
3774  * volumes.
3775  *
3776  * Return: 0 on success and non-zero on failure.
3777  */
3778 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
3779 {
3780         int retval = 0;
3781         u8 retry = 0;
3782         struct mpi3_ioc_facts_data facts_data;
3783         u32 sz;
3784
3785 retry_init:
3786         retval = mpi3mr_bring_ioc_ready(mrioc);
3787         if (retval) {
3788                 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
3789                     retval);
3790                 goto out_failed_noretry;
3791         }
3792
3793         retval = mpi3mr_setup_isr(mrioc, 1);
3794         if (retval) {
3795                 ioc_err(mrioc, "Failed to setup ISR error %d\n",
3796                     retval);
3797                 goto out_failed_noretry;
3798         }
3799
3800         retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3801         if (retval) {
3802                 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
3803                     retval);
3804                 goto out_failed;
3805         }
3806
3807         mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
3808
3809         mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
3810         atomic_set(&mrioc->pend_large_data_sz, 0);
3811
3812         if (reset_devices)
3813                 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
3814                     MPI3MR_HOST_IOS_KDUMP);
3815
3816         if (!(mrioc->facts.ioc_capabilities &
3817             MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) {
3818                 mrioc->sas_transport_enabled = 1;
3819                 mrioc->scsi_device_channel = 1;
3820                 mrioc->shost->max_channel = 1;
3821                 mrioc->shost->transportt = mpi3mr_transport_template;
3822         }
3823
3824         mrioc->reply_sz = mrioc->facts.reply_sz;
3825
3826         retval = mpi3mr_check_reset_dma_mask(mrioc);
3827         if (retval) {
3828                 ioc_err(mrioc, "Resetting dma mask failed %d\n",
3829                     retval);
3830                 goto out_failed_noretry;
3831         }
3832
3833         mpi3mr_print_ioc_info(mrioc);
3834
3835         dprint_init(mrioc, "allocating config page buffers\n");
3836         mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev,
3837             MPI3MR_DEFAULT_CFG_PAGE_SZ, &mrioc->cfg_page_dma, GFP_KERNEL);
3838         if (!mrioc->cfg_page)
3839                 goto out_failed_noretry;
3840
3841         mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ;
3842
3843         retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
3844         if (retval) {
3845                 ioc_err(mrioc,
3846                     "%s :Failed to allocated reply sense buffers %d\n",
3847                     __func__, retval);
3848                 goto out_failed_noretry;
3849         }
3850
3851         retval = mpi3mr_alloc_chain_bufs(mrioc);
3852         if (retval) {
3853                 ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
3854                     retval);
3855                 goto out_failed_noretry;
3856         }
3857
3858         retval = mpi3mr_issue_iocinit(mrioc);
3859         if (retval) {
3860                 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
3861                     retval);
3862                 goto out_failed;
3863         }
3864
3865         retval = mpi3mr_print_pkg_ver(mrioc);
3866         if (retval) {
3867                 ioc_err(mrioc, "failed to get package version\n");
3868                 goto out_failed;
3869         }
3870
3871         retval = mpi3mr_setup_isr(mrioc, 0);
3872         if (retval) {
3873                 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
3874                     retval);
3875                 goto out_failed_noretry;
3876         }
3877
3878         retval = mpi3mr_create_op_queues(mrioc);
3879         if (retval) {
3880                 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
3881                     retval);
3882                 goto out_failed;
3883         }
3884
3885         if (!mrioc->pel_seqnum_virt) {
3886                 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
3887                 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
3888                 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
3889                     mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
3890                     GFP_KERNEL);
3891                 if (!mrioc->pel_seqnum_virt) {
3892                         retval = -ENOMEM;
3893                         goto out_failed_noretry;
3894                 }
3895         }
3896
3897         if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
3898                 dprint_init(mrioc, "allocating memory for throttle groups\n");
3899                 sz = sizeof(struct mpi3mr_throttle_group_info);
3900                 mrioc->throttle_groups = (struct mpi3mr_throttle_group_info *)
3901                     kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
3902                 if (!mrioc->throttle_groups)
3903                         goto out_failed_noretry;
3904         }
3905
3906         retval = mpi3mr_enable_events(mrioc);
3907         if (retval) {
3908                 ioc_err(mrioc, "failed to enable events %d\n",
3909                     retval);
3910                 goto out_failed;
3911         }
3912
3913         ioc_info(mrioc, "controller initialization completed successfully\n");
3914         return retval;
3915 out_failed:
3916         if (retry < 2) {
3917                 retry++;
3918                 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
3919                     retry);
3920                 mpi3mr_memset_buffers(mrioc);
3921                 goto retry_init;
3922         }
3923 out_failed_noretry:
3924         ioc_err(mrioc, "controller initialization failed\n");
3925         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
3926             MPI3MR_RESET_FROM_CTLR_CLEANUP);
3927         mrioc->unrecoverable = 1;
3928         return retval;
3929 }
3930
3931 /**
3932  * mpi3mr_reinit_ioc - Re-Initialize the controller
3933  * @mrioc: Adapter instance reference
3934  * @is_resume: Called from resume or reset path
3935  *
3936  * This the controller re-initialization routine, executed from
3937  * the soft reset handler or resume callback. Creates
3938  * operational reply queue pairs, allocate required memory for
3939  * reply pool, sense buffer pool, issue IOC init request to the
3940  * firmware, unmask the events and issue port enable to discover
3941  * SAS/SATA/NVMe devices and RAID volumes.
3942  *
3943  * Return: 0 on success and non-zero on failure.
3944  */
3945 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
3946 {
3947         int retval = 0;
3948         u8 retry = 0;
3949         struct mpi3_ioc_facts_data facts_data;
3950         u32 pe_timeout, ioc_status;
3951
3952 retry_init:
3953         pe_timeout =
3954             (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
3955
3956         dprint_reset(mrioc, "bringing up the controller to ready state\n");
3957         retval = mpi3mr_bring_ioc_ready(mrioc);
3958         if (retval) {
3959                 ioc_err(mrioc, "failed to bring to ready state\n");
3960                 goto out_failed_noretry;
3961         }
3962
3963         if (is_resume) {
3964                 dprint_reset(mrioc, "setting up single ISR\n");
3965                 retval = mpi3mr_setup_isr(mrioc, 1);
3966                 if (retval) {
3967                         ioc_err(mrioc, "failed to setup ISR\n");
3968                         goto out_failed_noretry;
3969                 }
3970         } else
3971                 mpi3mr_ioc_enable_intr(mrioc);
3972
3973         dprint_reset(mrioc, "getting ioc_facts\n");
3974         retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3975         if (retval) {
3976                 ioc_err(mrioc, "failed to get ioc_facts\n");
3977                 goto out_failed;
3978         }
3979
3980         dprint_reset(mrioc, "validating ioc_facts\n");
3981         retval = mpi3mr_revalidate_factsdata(mrioc);
3982         if (retval) {
3983                 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
3984                 goto out_failed_noretry;
3985         }
3986
3987         mpi3mr_print_ioc_info(mrioc);
3988
3989         dprint_reset(mrioc, "sending ioc_init\n");
3990         retval = mpi3mr_issue_iocinit(mrioc);
3991         if (retval) {
3992                 ioc_err(mrioc, "failed to send ioc_init\n");
3993                 goto out_failed;
3994         }
3995
3996         dprint_reset(mrioc, "getting package version\n");
3997         retval = mpi3mr_print_pkg_ver(mrioc);
3998         if (retval) {
3999                 ioc_err(mrioc, "failed to get package version\n");
4000                 goto out_failed;
4001         }
4002
4003         if (is_resume) {
4004                 dprint_reset(mrioc, "setting up multiple ISR\n");
4005                 retval = mpi3mr_setup_isr(mrioc, 0);
4006                 if (retval) {
4007                         ioc_err(mrioc, "failed to re-setup ISR\n");
4008                         goto out_failed_noretry;
4009                 }
4010         }
4011
4012         dprint_reset(mrioc, "creating operational queue pairs\n");
4013         retval = mpi3mr_create_op_queues(mrioc);
4014         if (retval) {
4015                 ioc_err(mrioc, "failed to create operational queue pairs\n");
4016                 goto out_failed;
4017         }
4018
4019         if (!mrioc->pel_seqnum_virt) {
4020                 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4021                 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4022                 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4023                     mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4024                     GFP_KERNEL);
4025                 if (!mrioc->pel_seqnum_virt) {
4026                         retval = -ENOMEM;
4027                         goto out_failed_noretry;
4028                 }
4029         }
4030
4031         if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4032                 ioc_err(mrioc,
4033                     "cannot create minimum number of operational queues expected:%d created:%d\n",
4034                     mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4035                 goto out_failed_noretry;
4036         }
4037
4038         dprint_reset(mrioc, "enabling events\n");
4039         retval = mpi3mr_enable_events(mrioc);
4040         if (retval) {
4041                 ioc_err(mrioc, "failed to enable events\n");
4042                 goto out_failed;
4043         }
4044
4045         if (!is_resume) {
4046                 mrioc->device_refresh_on = 1;
4047                 mpi3mr_add_event_wait_for_device_refresh(mrioc);
4048         }
4049
4050         ioc_info(mrioc, "sending port enable\n");
4051         retval = mpi3mr_issue_port_enable(mrioc, 1);
4052         if (retval) {
4053                 ioc_err(mrioc, "failed to issue port enable\n");
4054                 goto out_failed;
4055         }
4056         do {
4057                 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4058                 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4059                         break;
4060                 if (!pci_device_is_present(mrioc->pdev))
4061                         mrioc->unrecoverable = 1;
4062                 if (mrioc->unrecoverable) {
4063                         retval = -1;
4064                         goto out_failed_noretry;
4065                 }
4066                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4067                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4068                     (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4069                         mpi3mr_print_fault_info(mrioc);
4070                         mrioc->init_cmds.is_waiting = 0;
4071                         mrioc->init_cmds.callback = NULL;
4072                         mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4073                         goto out_failed;
4074                 }
4075         } while (--pe_timeout);
4076
4077         if (!pe_timeout) {
4078                 ioc_err(mrioc, "port enable timed out\n");
4079                 mpi3mr_check_rh_fault_ioc(mrioc,
4080                     MPI3MR_RESET_FROM_PE_TIMEOUT);
4081                 mrioc->init_cmds.is_waiting = 0;
4082                 mrioc->init_cmds.callback = NULL;
4083                 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4084                 goto out_failed;
4085         } else if (mrioc->scan_failed) {
4086                 ioc_err(mrioc,
4087                     "port enable failed with status=0x%04x\n",
4088                     mrioc->scan_failed);
4089         } else
4090                 ioc_info(mrioc, "port enable completed successfully\n");
4091
4092         ioc_info(mrioc, "controller %s completed successfully\n",
4093             (is_resume)?"resume":"re-initialization");
4094         return retval;
4095 out_failed:
4096         if (retry < 2) {
4097                 retry++;
4098                 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4099                     (is_resume)?"resume":"re-initialization", retry);
4100                 mpi3mr_memset_buffers(mrioc);
4101                 goto retry_init;
4102         }
4103 out_failed_noretry:
4104         ioc_err(mrioc, "controller %s is failed\n",
4105             (is_resume)?"resume":"re-initialization");
4106         mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4107             MPI3MR_RESET_FROM_CTLR_CLEANUP);
4108         mrioc->unrecoverable = 1;
4109         return retval;
4110 }
4111
4112 /**
4113  * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4114  *                                      segments
4115  * @mrioc: Adapter instance reference
4116  * @qidx: Operational reply queue index
4117  *
4118  * Return: Nothing.
4119  */
4120 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4121 {
4122         struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4123         struct segments *segments;
4124         int i, size;
4125
4126         if (!op_reply_q->q_segments)
4127                 return;
4128
4129         size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4130         segments = op_reply_q->q_segments;
4131         for (i = 0; i < op_reply_q->num_segments; i++)
4132                 memset(segments[i].segment, 0, size);
4133 }
4134
4135 /**
4136  * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4137  *                                      segments
4138  * @mrioc: Adapter instance reference
4139  * @qidx: Operational request queue index
4140  *
4141  * Return: Nothing.
4142  */
4143 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4144 {
4145         struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4146         struct segments *segments;
4147         int i, size;
4148
4149         if (!op_req_q->q_segments)
4150                 return;
4151
4152         size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4153         segments = op_req_q->q_segments;
4154         for (i = 0; i < op_req_q->num_segments; i++)
4155                 memset(segments[i].segment, 0, size);
4156 }
4157
4158 /**
4159  * mpi3mr_memset_buffers - memset memory for a controller
4160  * @mrioc: Adapter instance reference
4161  *
4162  * clear all the memory allocated for a controller, typically
4163  * called post reset to reuse the memory allocated during the
4164  * controller init.
4165  *
4166  * Return: Nothing.
4167  */
4168 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4169 {
4170         u16 i;
4171         struct mpi3mr_throttle_group_info *tg;
4172
4173         mrioc->change_count = 0;
4174         mrioc->active_poll_qcount = 0;
4175         mrioc->default_qcount = 0;
4176         if (mrioc->admin_req_base)
4177                 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4178         if (mrioc->admin_reply_base)
4179                 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4180
4181         if (mrioc->init_cmds.reply) {
4182                 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4183                 memset(mrioc->bsg_cmds.reply, 0,
4184                     sizeof(*mrioc->bsg_cmds.reply));
4185                 memset(mrioc->host_tm_cmds.reply, 0,
4186                     sizeof(*mrioc->host_tm_cmds.reply));
4187                 memset(mrioc->pel_cmds.reply, 0,
4188                     sizeof(*mrioc->pel_cmds.reply));
4189                 memset(mrioc->pel_abort_cmd.reply, 0,
4190                     sizeof(*mrioc->pel_abort_cmd.reply));
4191                 memset(mrioc->transport_cmds.reply, 0,
4192                     sizeof(*mrioc->transport_cmds.reply));
4193                 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4194                         memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4195                             sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4196                 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4197                         memset(mrioc->evtack_cmds[i].reply, 0,
4198                             sizeof(*mrioc->evtack_cmds[i].reply));
4199                 memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz);
4200                 memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz);
4201                 memset(mrioc->evtack_cmds_bitmap, 0,
4202                     mrioc->evtack_cmds_bitmap_sz);
4203         }
4204
4205         for (i = 0; i < mrioc->num_queues; i++) {
4206                 mrioc->op_reply_qinfo[i].qid = 0;
4207                 mrioc->op_reply_qinfo[i].ci = 0;
4208                 mrioc->op_reply_qinfo[i].num_replies = 0;
4209                 mrioc->op_reply_qinfo[i].ephase = 0;
4210                 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4211                 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4212                 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4213
4214                 mrioc->req_qinfo[i].ci = 0;
4215                 mrioc->req_qinfo[i].pi = 0;
4216                 mrioc->req_qinfo[i].num_requests = 0;
4217                 mrioc->req_qinfo[i].qid = 0;
4218                 mrioc->req_qinfo[i].reply_qid = 0;
4219                 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4220                 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4221         }
4222
4223         atomic_set(&mrioc->pend_large_data_sz, 0);
4224         if (mrioc->throttle_groups) {
4225                 tg = mrioc->throttle_groups;
4226                 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4227                         tg->id = 0;
4228                         tg->fw_qd = 0;
4229                         tg->modified_qd = 0;
4230                         tg->io_divert = 0;
4231                         tg->need_qd_reduction = 0;
4232                         tg->high = 0;
4233                         tg->low = 0;
4234                         tg->qd_reduction = 0;
4235                         atomic_set(&tg->pend_large_data_sz, 0);
4236                 }
4237         }
4238 }
4239
4240 /**
4241  * mpi3mr_free_mem - Free memory allocated for a controller
4242  * @mrioc: Adapter instance reference
4243  *
4244  * Free all the memory allocated for a controller.
4245  *
4246  * Return: Nothing.
4247  */
4248 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4249 {
4250         u16 i;
4251         struct mpi3mr_intr_info *intr_info;
4252
4253         mpi3mr_free_enclosure_list(mrioc);
4254
4255         if (mrioc->sense_buf_pool) {
4256                 if (mrioc->sense_buf)
4257                         dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4258                             mrioc->sense_buf_dma);
4259                 dma_pool_destroy(mrioc->sense_buf_pool);
4260                 mrioc->sense_buf = NULL;
4261                 mrioc->sense_buf_pool = NULL;
4262         }
4263         if (mrioc->sense_buf_q_pool) {
4264                 if (mrioc->sense_buf_q)
4265                         dma_pool_free(mrioc->sense_buf_q_pool,
4266                             mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4267                 dma_pool_destroy(mrioc->sense_buf_q_pool);
4268                 mrioc->sense_buf_q = NULL;
4269                 mrioc->sense_buf_q_pool = NULL;
4270         }
4271
4272         if (mrioc->reply_buf_pool) {
4273                 if (mrioc->reply_buf)
4274                         dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4275                             mrioc->reply_buf_dma);
4276                 dma_pool_destroy(mrioc->reply_buf_pool);
4277                 mrioc->reply_buf = NULL;
4278                 mrioc->reply_buf_pool = NULL;
4279         }
4280         if (mrioc->reply_free_q_pool) {
4281                 if (mrioc->reply_free_q)
4282                         dma_pool_free(mrioc->reply_free_q_pool,
4283                             mrioc->reply_free_q, mrioc->reply_free_q_dma);
4284                 dma_pool_destroy(mrioc->reply_free_q_pool);
4285                 mrioc->reply_free_q = NULL;
4286                 mrioc->reply_free_q_pool = NULL;
4287         }
4288
4289         for (i = 0; i < mrioc->num_op_req_q; i++)
4290                 mpi3mr_free_op_req_q_segments(mrioc, i);
4291
4292         for (i = 0; i < mrioc->num_op_reply_q; i++)
4293                 mpi3mr_free_op_reply_q_segments(mrioc, i);
4294
4295         for (i = 0; i < mrioc->intr_info_count; i++) {
4296                 intr_info = mrioc->intr_info + i;
4297                 intr_info->op_reply_q = NULL;
4298         }
4299
4300         kfree(mrioc->req_qinfo);
4301         mrioc->req_qinfo = NULL;
4302         mrioc->num_op_req_q = 0;
4303
4304         kfree(mrioc->op_reply_qinfo);
4305         mrioc->op_reply_qinfo = NULL;
4306         mrioc->num_op_reply_q = 0;
4307
4308         kfree(mrioc->init_cmds.reply);
4309         mrioc->init_cmds.reply = NULL;
4310
4311         kfree(mrioc->bsg_cmds.reply);
4312         mrioc->bsg_cmds.reply = NULL;
4313
4314         kfree(mrioc->host_tm_cmds.reply);
4315         mrioc->host_tm_cmds.reply = NULL;
4316
4317         kfree(mrioc->pel_cmds.reply);
4318         mrioc->pel_cmds.reply = NULL;
4319
4320         kfree(mrioc->pel_abort_cmd.reply);
4321         mrioc->pel_abort_cmd.reply = NULL;
4322
4323         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4324                 kfree(mrioc->evtack_cmds[i].reply);
4325                 mrioc->evtack_cmds[i].reply = NULL;
4326         }
4327
4328         kfree(mrioc->removepend_bitmap);
4329         mrioc->removepend_bitmap = NULL;
4330
4331         kfree(mrioc->devrem_bitmap);
4332         mrioc->devrem_bitmap = NULL;
4333
4334         kfree(mrioc->evtack_cmds_bitmap);
4335         mrioc->evtack_cmds_bitmap = NULL;
4336
4337         kfree(mrioc->chain_bitmap);
4338         mrioc->chain_bitmap = NULL;
4339
4340         kfree(mrioc->transport_cmds.reply);
4341         mrioc->transport_cmds.reply = NULL;
4342
4343         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4344                 kfree(mrioc->dev_rmhs_cmds[i].reply);
4345                 mrioc->dev_rmhs_cmds[i].reply = NULL;
4346         }
4347
4348         if (mrioc->chain_buf_pool) {
4349                 for (i = 0; i < mrioc->chain_buf_count; i++) {
4350                         if (mrioc->chain_sgl_list[i].addr) {
4351                                 dma_pool_free(mrioc->chain_buf_pool,
4352                                     mrioc->chain_sgl_list[i].addr,
4353                                     mrioc->chain_sgl_list[i].dma_addr);
4354                                 mrioc->chain_sgl_list[i].addr = NULL;
4355                         }
4356                 }
4357                 dma_pool_destroy(mrioc->chain_buf_pool);
4358                 mrioc->chain_buf_pool = NULL;
4359         }
4360
4361         kfree(mrioc->chain_sgl_list);
4362         mrioc->chain_sgl_list = NULL;
4363
4364         if (mrioc->admin_reply_base) {
4365                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4366                     mrioc->admin_reply_base, mrioc->admin_reply_dma);
4367                 mrioc->admin_reply_base = NULL;
4368         }
4369         if (mrioc->admin_req_base) {
4370                 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4371                     mrioc->admin_req_base, mrioc->admin_req_dma);
4372                 mrioc->admin_req_base = NULL;
4373         }
4374
4375         if (mrioc->pel_seqnum_virt) {
4376                 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4377                     mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4378                 mrioc->pel_seqnum_virt = NULL;
4379         }
4380
4381         kfree(mrioc->logdata_buf);
4382         mrioc->logdata_buf = NULL;
4383
4384 }
4385
4386 /**
4387  * mpi3mr_issue_ioc_shutdown - shutdown controller
4388  * @mrioc: Adapter instance reference
4389  *
4390  * Send shutodwn notification to the controller and wait for the
4391  * shutdown_timeout for it to be completed.
4392  *
4393  * Return: Nothing.
4394  */
4395 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4396 {
4397         u32 ioc_config, ioc_status;
4398         u8 retval = 1;
4399         u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4400
4401         ioc_info(mrioc, "Issuing shutdown Notification\n");
4402         if (mrioc->unrecoverable) {
4403                 ioc_warn(mrioc,
4404                     "IOC is unrecoverable shutdown is not issued\n");
4405                 return;
4406         }
4407         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4408         if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4409             == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4410                 ioc_info(mrioc, "shutdown already in progress\n");
4411                 return;
4412         }
4413
4414         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4415         ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4416         ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4417
4418         writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4419
4420         if (mrioc->facts.shutdown_timeout)
4421                 timeout = mrioc->facts.shutdown_timeout * 10;
4422
4423         do {
4424                 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4425                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4426                     == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4427                         retval = 0;
4428                         break;
4429                 }
4430                 msleep(100);
4431         } while (--timeout);
4432
4433         ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4434         ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4435
4436         if (retval) {
4437                 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4438                     == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4439                         ioc_warn(mrioc,
4440                             "shutdown still in progress after timeout\n");
4441         }
4442
4443         ioc_info(mrioc,
4444             "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
4445             (!retval) ? "successful" : "failed", ioc_status,
4446             ioc_config);
4447 }
4448
4449 /**
4450  * mpi3mr_cleanup_ioc - Cleanup controller
4451  * @mrioc: Adapter instance reference
4452  *
4453  * controller cleanup handler, Message unit reset or soft reset
4454  * and shutdown notification is issued to the controller.
4455  *
4456  * Return: Nothing.
4457  */
4458 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
4459 {
4460         enum mpi3mr_iocstate ioc_state;
4461
4462         dprint_exit(mrioc, "cleaning up the controller\n");
4463         mpi3mr_ioc_disable_intr(mrioc);
4464
4465         ioc_state = mpi3mr_get_iocstate(mrioc);
4466
4467         if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) &&
4468             (ioc_state == MRIOC_STATE_READY)) {
4469                 if (mpi3mr_issue_and_process_mur(mrioc,
4470                     MPI3MR_RESET_FROM_CTLR_CLEANUP))
4471                         mpi3mr_issue_reset(mrioc,
4472                             MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
4473                             MPI3MR_RESET_FROM_MUR_FAILURE);
4474                 mpi3mr_issue_ioc_shutdown(mrioc);
4475         }
4476         dprint_exit(mrioc, "controller cleanup completed\n");
4477 }
4478
4479 /**
4480  * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
4481  * @mrioc: Adapter instance reference
4482  * @cmdptr: Internal command tracker
4483  *
4484  * Complete an internal driver commands with state indicating it
4485  * is completed due to reset.
4486  *
4487  * Return: Nothing.
4488  */
4489 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
4490         struct mpi3mr_drv_cmd *cmdptr)
4491 {
4492         if (cmdptr->state & MPI3MR_CMD_PENDING) {
4493                 cmdptr->state |= MPI3MR_CMD_RESET;
4494                 cmdptr->state &= ~MPI3MR_CMD_PENDING;
4495                 if (cmdptr->is_waiting) {
4496                         complete(&cmdptr->done);
4497                         cmdptr->is_waiting = 0;
4498                 } else if (cmdptr->callback)
4499                         cmdptr->callback(mrioc, cmdptr);
4500         }
4501 }
4502
4503 /**
4504  * mpi3mr_flush_drv_cmds - Flush internaldriver commands
4505  * @mrioc: Adapter instance reference
4506  *
4507  * Flush all internal driver commands post reset
4508  *
4509  * Return: Nothing.
4510  */
4511 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
4512 {
4513         struct mpi3mr_drv_cmd *cmdptr;
4514         u8 i;
4515
4516         cmdptr = &mrioc->init_cmds;
4517         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4518
4519         cmdptr = &mrioc->cfg_cmds;
4520         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4521
4522         cmdptr = &mrioc->bsg_cmds;
4523         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4524         cmdptr = &mrioc->host_tm_cmds;
4525         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4526
4527         for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4528                 cmdptr = &mrioc->dev_rmhs_cmds[i];
4529                 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4530         }
4531
4532         for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4533                 cmdptr = &mrioc->evtack_cmds[i];
4534                 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4535         }
4536
4537         cmdptr = &mrioc->pel_cmds;
4538         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4539
4540         cmdptr = &mrioc->pel_abort_cmd;
4541         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4542
4543         cmdptr = &mrioc->transport_cmds;
4544         mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4545 }
4546
4547 /**
4548  * mpi3mr_pel_wait_post - Issue PEL Wait
4549  * @mrioc: Adapter instance reference
4550  * @drv_cmd: Internal command tracker
4551  *
4552  * Issue PEL Wait MPI request through admin queue and return.
4553  *
4554  * Return: Nothing.
4555  */
4556 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
4557         struct mpi3mr_drv_cmd *drv_cmd)
4558 {
4559         struct mpi3_pel_req_action_wait pel_wait;
4560
4561         mrioc->pel_abort_requested = false;
4562
4563         memset(&pel_wait, 0, sizeof(pel_wait));
4564         drv_cmd->state = MPI3MR_CMD_PENDING;
4565         drv_cmd->is_waiting = 0;
4566         drv_cmd->callback = mpi3mr_pel_wait_complete;
4567         drv_cmd->ioc_status = 0;
4568         drv_cmd->ioc_loginfo = 0;
4569         pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4570         pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4571         pel_wait.action = MPI3_PEL_ACTION_WAIT;
4572         pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
4573         pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
4574         pel_wait.class = cpu_to_le16(mrioc->pel_class);
4575         pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
4576         dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
4577             mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
4578
4579         if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
4580                 dprint_bsg_err(mrioc,
4581                             "Issuing PELWait: Admin post failed\n");
4582                 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4583                 drv_cmd->callback = NULL;
4584                 drv_cmd->retry_count = 0;
4585                 mrioc->pel_enabled = false;
4586         }
4587 }
4588
4589 /**
4590  * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
4591  * @mrioc: Adapter instance reference
4592  * @drv_cmd: Internal command tracker
4593  *
4594  * Issue PEL get sequence number MPI request through admin queue
4595  * and return.
4596  *
4597  * Return: 0 on success, non-zero on failure.
4598  */
4599 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
4600         struct mpi3mr_drv_cmd *drv_cmd)
4601 {
4602         struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
4603         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
4604         int retval = 0;
4605
4606         memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
4607         mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
4608         mrioc->pel_cmds.is_waiting = 0;
4609         mrioc->pel_cmds.ioc_status = 0;
4610         mrioc->pel_cmds.ioc_loginfo = 0;
4611         mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
4612         pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4613         pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4614         pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
4615         mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
4616             mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
4617
4618         retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
4619                         sizeof(pel_getseq_req), 0);
4620         if (retval) {
4621                 if (drv_cmd) {
4622                         drv_cmd->state = MPI3MR_CMD_NOTUSED;
4623                         drv_cmd->callback = NULL;
4624                         drv_cmd->retry_count = 0;
4625                 }
4626                 mrioc->pel_enabled = false;
4627         }
4628
4629         return retval;
4630 }
4631
4632 /**
4633  * mpi3mr_pel_wait_complete - PELWait Completion callback
4634  * @mrioc: Adapter instance reference
4635  * @drv_cmd: Internal command tracker
4636  *
4637  * This is a callback handler for the PELWait request and
4638  * firmware completes a PELWait request when it is aborted or a
4639  * new PEL entry is available. This sends AEN to the application
4640  * and if the PELwait completion is not due to PELAbort then
4641  * this will send a request for new PEL Sequence number
4642  *
4643  * Return: Nothing.
4644  */
4645 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
4646         struct mpi3mr_drv_cmd *drv_cmd)
4647 {
4648         struct mpi3_pel_reply *pel_reply = NULL;
4649         u16 ioc_status, pe_log_status;
4650         bool do_retry = false;
4651
4652         if (drv_cmd->state & MPI3MR_CMD_RESET)
4653                 goto cleanup_drv_cmd;
4654
4655         ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4656         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4657                 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
4658                         __func__, ioc_status, drv_cmd->ioc_loginfo);
4659                 dprint_bsg_err(mrioc,
4660                     "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4661                     ioc_status, drv_cmd->ioc_loginfo);
4662                 do_retry = true;
4663         }
4664
4665         if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4666                 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4667
4668         if (!pel_reply) {
4669                 dprint_bsg_err(mrioc,
4670                     "pel_wait: failed due to no reply\n");
4671                 goto out_failed;
4672         }
4673
4674         pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
4675         if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
4676             (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
4677                 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
4678                         __func__, pe_log_status);
4679                 dprint_bsg_err(mrioc,
4680                     "pel_wait: failed due to pel_log_status(0x%04x)\n",
4681                     pe_log_status);
4682                 do_retry = true;
4683         }
4684
4685         if (do_retry) {
4686                 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4687                         drv_cmd->retry_count++;
4688                         dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
4689                             drv_cmd->retry_count);
4690                         mpi3mr_pel_wait_post(mrioc, drv_cmd);
4691                         return;
4692                 }
4693                 dprint_bsg_err(mrioc,
4694                     "pel_wait: failed after all retries(%d)\n",
4695                     drv_cmd->retry_count);
4696                 goto out_failed;
4697         }
4698         atomic64_inc(&event_counter);
4699         if (!mrioc->pel_abort_requested) {
4700                 mrioc->pel_cmds.retry_count = 0;
4701                 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
4702         }
4703
4704         return;
4705 out_failed:
4706         mrioc->pel_enabled = false;
4707 cleanup_drv_cmd:
4708         drv_cmd->state = MPI3MR_CMD_NOTUSED;
4709         drv_cmd->callback = NULL;
4710         drv_cmd->retry_count = 0;
4711 }
4712
4713 /**
4714  * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
4715  * @mrioc: Adapter instance reference
4716  * @drv_cmd: Internal command tracker
4717  *
4718  * This is a callback handler for the PEL get sequence number
4719  * request and a new PEL wait request will be issued to the
4720  * firmware from this
4721  *
4722  * Return: Nothing.
4723  */
4724 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
4725         struct mpi3mr_drv_cmd *drv_cmd)
4726 {
4727         struct mpi3_pel_reply *pel_reply = NULL;
4728         struct mpi3_pel_seq *pel_seqnum_virt;
4729         u16 ioc_status;
4730         bool do_retry = false;
4731
4732         pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
4733
4734         if (drv_cmd->state & MPI3MR_CMD_RESET)
4735                 goto cleanup_drv_cmd;
4736
4737         ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4738         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4739                 dprint_bsg_err(mrioc,
4740                     "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4741                     ioc_status, drv_cmd->ioc_loginfo);
4742                 do_retry = true;
4743         }
4744
4745         if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4746                 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4747         if (!pel_reply) {
4748                 dprint_bsg_err(mrioc,
4749                     "pel_get_seqnum: failed due to no reply\n");
4750                 goto out_failed;
4751         }
4752
4753         if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
4754                 dprint_bsg_err(mrioc,
4755                     "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
4756                     le16_to_cpu(pel_reply->pe_log_status));
4757                 do_retry = true;
4758         }
4759
4760         if (do_retry) {
4761                 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4762                         drv_cmd->retry_count++;
4763                         dprint_bsg_err(mrioc,
4764                             "pel_get_seqnum: retrying(%d)\n",
4765                             drv_cmd->retry_count);
4766                         mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
4767                         return;
4768                 }
4769
4770                 dprint_bsg_err(mrioc,
4771                     "pel_get_seqnum: failed after all retries(%d)\n",
4772                     drv_cmd->retry_count);
4773                 goto out_failed;
4774         }
4775         mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
4776         drv_cmd->retry_count = 0;
4777         mpi3mr_pel_wait_post(mrioc, drv_cmd);
4778
4779         return;
4780 out_failed:
4781         mrioc->pel_enabled = false;
4782 cleanup_drv_cmd:
4783         drv_cmd->state = MPI3MR_CMD_NOTUSED;
4784         drv_cmd->callback = NULL;
4785         drv_cmd->retry_count = 0;
4786 }
4787
4788 /**
4789  * mpi3mr_soft_reset_handler - Reset the controller
4790  * @mrioc: Adapter instance reference
4791  * @reset_reason: Reset reason code
4792  * @snapdump: Flag to generate snapdump in firmware or not
4793  *
4794  * This is an handler for recovering controller by issuing soft
4795  * reset are diag fault reset.  This is a blocking function and
4796  * when one reset is executed if any other resets they will be
4797  * blocked. All BSG requests will be blocked during the reset. If
4798  * controller reset is successful then the controller will be
4799  * reinitalized, otherwise the controller will be marked as not
4800  * recoverable
4801  *
4802  * In snapdump bit is set, the controller is issued with diag
4803  * fault reset so that the firmware can create a snap dump and
4804  * post that the firmware will result in F000 fault and the
4805  * driver will issue soft reset to recover from that.
4806  *
4807  * Return: 0 on success, non-zero on failure.
4808  */
4809 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
4810         u32 reset_reason, u8 snapdump)
4811 {
4812         int retval = 0, i;
4813         unsigned long flags;
4814         u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
4815
4816         /* Block the reset handler until diag save in progress*/
4817         dprint_reset(mrioc,
4818             "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
4819             mrioc->diagsave_timeout);
4820         while (mrioc->diagsave_timeout)
4821                 ssleep(1);
4822         /*
4823          * Block new resets until the currently executing one is finished and
4824          * return the status of the existing reset for all blocked resets
4825          */
4826         dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
4827         if (!mutex_trylock(&mrioc->reset_mutex)) {
4828                 ioc_info(mrioc,
4829                     "controller reset triggered by %s is blocked due to another reset in progress\n",
4830                     mpi3mr_reset_rc_name(reset_reason));
4831                 do {
4832                         ssleep(1);
4833                 } while (mrioc->reset_in_progress == 1);
4834                 ioc_info(mrioc,
4835                     "returning previous reset result(%d) for the reset triggered by %s\n",
4836                     mrioc->prev_reset_result,
4837                     mpi3mr_reset_rc_name(reset_reason));
4838                 return mrioc->prev_reset_result;
4839         }
4840         ioc_info(mrioc, "controller reset is triggered by %s\n",
4841             mpi3mr_reset_rc_name(reset_reason));
4842
4843         mrioc->device_refresh_on = 0;
4844         mrioc->reset_in_progress = 1;
4845         mrioc->stop_bsgs = 1;
4846         mrioc->prev_reset_result = -1;
4847
4848         if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
4849             (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
4850             (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
4851                 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4852                         mrioc->event_masks[i] = -1;
4853
4854                 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
4855                 mpi3mr_issue_event_notification(mrioc);
4856         }
4857
4858         mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
4859
4860         mpi3mr_ioc_disable_intr(mrioc);
4861
4862         if (snapdump) {
4863                 mpi3mr_set_diagsave(mrioc);
4864                 retval = mpi3mr_issue_reset(mrioc,
4865                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4866                 if (!retval) {
4867                         do {
4868                                 host_diagnostic =
4869                                     readl(&mrioc->sysif_regs->host_diagnostic);
4870                                 if (!(host_diagnostic &
4871                                     MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
4872                                         break;
4873                                 msleep(100);
4874                         } while (--timeout);
4875                 }
4876         }
4877
4878         retval = mpi3mr_issue_reset(mrioc,
4879             MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
4880         if (retval) {
4881                 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
4882                 goto out;
4883         }
4884         if (mrioc->num_io_throttle_group !=
4885             mrioc->facts.max_io_throttle_group) {
4886                 ioc_err(mrioc,
4887                     "max io throttle group doesn't match old(%d), new(%d)\n",
4888                     mrioc->num_io_throttle_group,
4889                     mrioc->facts.max_io_throttle_group);
4890                 retval = -EPERM;
4891                 goto out;
4892         }
4893
4894         mpi3mr_flush_delayed_cmd_lists(mrioc);
4895         mpi3mr_flush_drv_cmds(mrioc);
4896         memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz);
4897         memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz);
4898         memset(mrioc->evtack_cmds_bitmap, 0, mrioc->evtack_cmds_bitmap_sz);
4899         mpi3mr_flush_host_io(mrioc);
4900         mpi3mr_cleanup_fwevt_list(mrioc);
4901         mpi3mr_invalidate_devhandles(mrioc);
4902         mpi3mr_free_enclosure_list(mrioc);
4903
4904         if (mrioc->prepare_for_reset) {
4905                 mrioc->prepare_for_reset = 0;
4906                 mrioc->prepare_for_reset_timeout_counter = 0;
4907         }
4908         mpi3mr_memset_buffers(mrioc);
4909         retval = mpi3mr_reinit_ioc(mrioc, 0);
4910         if (retval) {
4911                 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
4912                     mrioc->name, reset_reason);
4913                 goto out;
4914         }
4915         ssleep(10);
4916
4917 out:
4918         if (!retval) {
4919                 mrioc->diagsave_timeout = 0;
4920                 mrioc->reset_in_progress = 0;
4921                 mrioc->pel_abort_requested = 0;
4922                 if (mrioc->pel_enabled) {
4923                         mrioc->pel_cmds.retry_count = 0;
4924                         mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
4925                 }
4926
4927                 mrioc->device_refresh_on = 0;
4928
4929                 mrioc->ts_update_counter = 0;
4930                 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
4931                 if (mrioc->watchdog_work_q)
4932                         queue_delayed_work(mrioc->watchdog_work_q,
4933                             &mrioc->watchdog_work,
4934                             msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
4935                 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
4936                 mrioc->stop_bsgs = 0;
4937                 if (mrioc->pel_enabled)
4938                         atomic64_inc(&event_counter);
4939         } else {
4940                 mpi3mr_issue_reset(mrioc,
4941                     MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4942                 mrioc->device_refresh_on = 0;
4943                 mrioc->unrecoverable = 1;
4944                 mrioc->reset_in_progress = 0;
4945                 retval = -1;
4946                 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
4947         }
4948         mrioc->prev_reset_result = retval;
4949         mutex_unlock(&mrioc->reset_mutex);
4950         ioc_info(mrioc, "controller reset is %s\n",
4951             ((retval == 0) ? "successful" : "failed"));
4952         return retval;
4953 }
4954
4955
4956 /**
4957  * mpi3mr_free_config_dma_memory - free memory for config page
4958  * @mrioc: Adapter instance reference
4959  * @mem_desc: memory descriptor structure
4960  *
4961  * Check whether the size of the buffer specified by the memory
4962  * descriptor is greater than the default page size if so then
4963  * free the memory pointed by the descriptor.
4964  *
4965  * Return: Nothing.
4966  */
4967 static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc,
4968         struct dma_memory_desc *mem_desc)
4969 {
4970         if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) {
4971                 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
4972                     mem_desc->addr, mem_desc->dma_addr);
4973                 mem_desc->addr = NULL;
4974         }
4975 }
4976
4977 /**
4978  * mpi3mr_alloc_config_dma_memory - Alloc memory for config page
4979  * @mrioc: Adapter instance reference
4980  * @mem_desc: Memory descriptor to hold dma memory info
4981  *
4982  * This function allocates new dmaable memory or provides the
4983  * default config page dmaable memory based on the memory size
4984  * described by the descriptor.
4985  *
4986  * Return: 0 on success, non-zero on failure.
4987  */
4988 static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc,
4989         struct dma_memory_desc *mem_desc)
4990 {
4991         if (mem_desc->size > mrioc->cfg_page_sz) {
4992                 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
4993                     mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL);
4994                 if (!mem_desc->addr)
4995                         return -ENOMEM;
4996         } else {
4997                 mem_desc->addr = mrioc->cfg_page;
4998                 mem_desc->dma_addr = mrioc->cfg_page_dma;
4999                 memset(mem_desc->addr, 0, mrioc->cfg_page_sz);
5000         }
5001         return 0;
5002 }
5003
5004 /**
5005  * mpi3mr_post_cfg_req - Issue config requests and wait
5006  * @mrioc: Adapter instance reference
5007  * @cfg_req: Configuration request
5008  * @timeout: Timeout in seconds
5009  * @ioc_status: Pointer to return ioc status
5010  *
5011  * A generic function for posting MPI3 configuration request to
5012  * the firmware. This blocks for the completion of request for
5013  * timeout seconds and if the request times out this function
5014  * faults the controller with proper reason code.
5015  *
5016  * On successful completion of the request this function returns
5017  * appropriate ioc status from the firmware back to the caller.
5018  *
5019  * Return: 0 on success, non-zero on failure.
5020  */
5021 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5022         struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5023 {
5024         int retval = 0;
5025
5026         mutex_lock(&mrioc->cfg_cmds.mutex);
5027         if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5028                 retval = -1;
5029                 ioc_err(mrioc, "sending config request failed due to command in use\n");
5030                 mutex_unlock(&mrioc->cfg_cmds.mutex);
5031                 goto out;
5032         }
5033         mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5034         mrioc->cfg_cmds.is_waiting = 1;
5035         mrioc->cfg_cmds.callback = NULL;
5036         mrioc->cfg_cmds.ioc_status = 0;
5037         mrioc->cfg_cmds.ioc_loginfo = 0;
5038
5039         cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5040         cfg_req->function = MPI3_FUNCTION_CONFIG;
5041
5042         init_completion(&mrioc->cfg_cmds.done);
5043         dprint_cfg_info(mrioc, "posting config request\n");
5044         if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5045                 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5046                     "mpi3_cfg_req");
5047         retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5048         if (retval) {
5049                 ioc_err(mrioc, "posting config request failed\n");
5050                 goto out_unlock;
5051         }
5052         wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5053         if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5054                 mpi3mr_check_rh_fault_ioc(mrioc,
5055                     MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5056                 ioc_err(mrioc, "config request timed out\n");
5057                 retval = -1;
5058                 goto out_unlock;
5059         }
5060         *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5061         if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5062                 dprint_cfg_err(mrioc,
5063                     "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5064                     *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5065
5066 out_unlock:
5067         mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5068         mutex_unlock(&mrioc->cfg_cmds.mutex);
5069
5070 out:
5071         return retval;
5072 }
5073
5074 /**
5075  * mpi3mr_process_cfg_req - config page request processor
5076  * @mrioc: Adapter instance reference
5077  * @cfg_req: Configuration request
5078  * @cfg_hdr: Configuration page header
5079  * @timeout: Timeout in seconds
5080  * @ioc_status: Pointer to return ioc status
5081  * @cfg_buf: Memory pointer to copy config page or header
5082  * @cfg_buf_sz: Size of the memory to get config page or header
5083  *
5084  * This is handler for config page read, write and config page
5085  * header read operations.
5086  *
5087  * This function expects the cfg_req to be populated with page
5088  * type, page number, action for the header read and with page
5089  * address for all other operations.
5090  *
5091  * The cfg_hdr can be passed as null for reading required header
5092  * details for read/write pages the cfg_hdr should point valid
5093  * configuration page header.
5094  *
5095  * This allocates dmaable memory based on the size of the config
5096  * buffer and set the SGE of the cfg_req.
5097  *
5098  * For write actions, the config page data has to be passed in
5099  * the cfg_buf and size of the data has to be mentioned in the
5100  * cfg_buf_sz.
5101  *
5102  * For read/header actions, on successful completion of the
5103  * request with successful ioc_status the data will be copied
5104  * into the cfg_buf limited to a minimum of actual page size and
5105  * cfg_buf_sz
5106  *
5107  *
5108  * Return: 0 on success, non-zero on failure.
5109  */
5110 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5111         struct mpi3_config_request *cfg_req,
5112         struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5113         void *cfg_buf, u32 cfg_buf_sz)
5114 {
5115         struct dma_memory_desc mem_desc;
5116         int retval = -1;
5117         u8 invalid_action = 0;
5118         u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5119
5120         memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5121
5122         if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5123                 mem_desc.size = sizeof(struct mpi3_config_page_header);
5124         else {
5125                 if (!cfg_hdr) {
5126                         ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5127                             cfg_req->action, cfg_req->page_type,
5128                             cfg_req->page_number);
5129                         goto out;
5130                 }
5131                 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5132                 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5133                         if (cfg_req->action
5134                             != MPI3_CONFIG_ACTION_READ_CURRENT)
5135                                 invalid_action = 1;
5136                         break;
5137                 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5138                         if ((cfg_req->action ==
5139                              MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5140                             (cfg_req->action ==
5141                              MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5142                                 invalid_action = 1;
5143                         break;
5144                 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5145                 default:
5146                         break;
5147                 }
5148                 if (invalid_action) {
5149                         ioc_err(mrioc,
5150                             "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5151                             cfg_req->action, cfg_req->page_type,
5152                             cfg_req->page_number, cfg_hdr->page_attribute);
5153                         goto out;
5154                 }
5155                 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5156                 cfg_req->page_length = cfg_hdr->page_length;
5157                 cfg_req->page_version = cfg_hdr->page_version;
5158         }
5159         if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc))
5160                 goto out;
5161
5162         mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5163             mem_desc.dma_addr);
5164
5165         if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5166             (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5167                 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5168                     cfg_buf_sz));
5169                 dprint_cfg_info(mrioc, "config buffer to be written\n");
5170                 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5171                         dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5172         }
5173
5174         if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5175                 goto out;
5176
5177         retval = 0;
5178         if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5179             (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5180             (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5181                 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5182                     cfg_buf_sz));
5183                 dprint_cfg_info(mrioc, "config buffer read\n");
5184                 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5185                         dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5186         }
5187
5188 out:
5189         mpi3mr_free_config_dma_memory(mrioc, &mem_desc);
5190         return retval;
5191 }
5192
5193 /**
5194  * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5195  * @mrioc: Adapter instance reference
5196  * @ioc_status: Pointer to return ioc status
5197  * @dev_pg0: Pointer to return device page 0
5198  * @pg_sz: Size of the memory allocated to the page pointer
5199  * @form: The form to be used for addressing the page
5200  * @form_spec: Form specific information like device handle
5201  *
5202  * This is handler for config page read for a specific device
5203  * page0. The ioc_status has the controller returned ioc_status.
5204  * This routine doesn't check ioc_status to decide whether the
5205  * page read is success or not and it is the callers
5206  * responsibility.
5207  *
5208  * Return: 0 on success, non-zero on failure.
5209  */
5210 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5211         struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5212 {
5213         struct mpi3_config_page_header cfg_hdr;
5214         struct mpi3_config_request cfg_req;
5215         u32 page_address;
5216
5217         memset(dev_pg0, 0, pg_sz);
5218         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5219         memset(&cfg_req, 0, sizeof(cfg_req));
5220
5221         cfg_req.function = MPI3_FUNCTION_CONFIG;
5222         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5223         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5224         cfg_req.page_number = 0;
5225         cfg_req.page_address = 0;
5226
5227         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5228             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5229                 ioc_err(mrioc, "device page0 header read failed\n");
5230                 goto out_failed;
5231         }
5232         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5233                 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5234                     *ioc_status);
5235                 goto out_failed;
5236         }
5237         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5238         page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5239             (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5240         cfg_req.page_address = cpu_to_le32(page_address);
5241         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5242             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5243                 ioc_err(mrioc, "device page0 read failed\n");
5244                 goto out_failed;
5245         }
5246         return 0;
5247 out_failed:
5248         return -1;
5249 }
5250
5251
5252 /**
5253  * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5254  * @mrioc: Adapter instance reference
5255  * @ioc_status: Pointer to return ioc status
5256  * @phy_pg0: Pointer to return SAS Phy page 0
5257  * @pg_sz: Size of the memory allocated to the page pointer
5258  * @form: The form to be used for addressing the page
5259  * @form_spec: Form specific information like phy number
5260  *
5261  * This is handler for config page read for a specific SAS Phy
5262  * page0. The ioc_status has the controller returned ioc_status.
5263  * This routine doesn't check ioc_status to decide whether the
5264  * page read is success or not and it is the callers
5265  * responsibility.
5266  *
5267  * Return: 0 on success, non-zero on failure.
5268  */
5269 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5270         struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5271         u32 form_spec)
5272 {
5273         struct mpi3_config_page_header cfg_hdr;
5274         struct mpi3_config_request cfg_req;
5275         u32 page_address;
5276
5277         memset(phy_pg0, 0, pg_sz);
5278         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5279         memset(&cfg_req, 0, sizeof(cfg_req));
5280
5281         cfg_req.function = MPI3_FUNCTION_CONFIG;
5282         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5283         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5284         cfg_req.page_number = 0;
5285         cfg_req.page_address = 0;
5286
5287         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5288             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5289                 ioc_err(mrioc, "sas phy page0 header read failed\n");
5290                 goto out_failed;
5291         }
5292         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5293                 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5294                     *ioc_status);
5295                 goto out_failed;
5296         }
5297         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5298         page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5299             (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5300         cfg_req.page_address = cpu_to_le32(page_address);
5301         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5302             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5303                 ioc_err(mrioc, "sas phy page0 read failed\n");
5304                 goto out_failed;
5305         }
5306         return 0;
5307 out_failed:
5308         return -1;
5309 }
5310
5311 /**
5312  * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5313  * @mrioc: Adapter instance reference
5314  * @ioc_status: Pointer to return ioc status
5315  * @phy_pg1: Pointer to return SAS Phy page 1
5316  * @pg_sz: Size of the memory allocated to the page pointer
5317  * @form: The form to be used for addressing the page
5318  * @form_spec: Form specific information like phy number
5319  *
5320  * This is handler for config page read for a specific SAS Phy
5321  * page1. The ioc_status has the controller returned ioc_status.
5322  * This routine doesn't check ioc_status to decide whether the
5323  * page read is success or not and it is the callers
5324  * responsibility.
5325  *
5326  * Return: 0 on success, non-zero on failure.
5327  */
5328 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5329         struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5330         u32 form_spec)
5331 {
5332         struct mpi3_config_page_header cfg_hdr;
5333         struct mpi3_config_request cfg_req;
5334         u32 page_address;
5335
5336         memset(phy_pg1, 0, pg_sz);
5337         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5338         memset(&cfg_req, 0, sizeof(cfg_req));
5339
5340         cfg_req.function = MPI3_FUNCTION_CONFIG;
5341         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5342         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5343         cfg_req.page_number = 1;
5344         cfg_req.page_address = 0;
5345
5346         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5347             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5348                 ioc_err(mrioc, "sas phy page1 header read failed\n");
5349                 goto out_failed;
5350         }
5351         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5352                 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5353                     *ioc_status);
5354                 goto out_failed;
5355         }
5356         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5357         page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5358             (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5359         cfg_req.page_address = cpu_to_le32(page_address);
5360         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5361             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5362                 ioc_err(mrioc, "sas phy page1 read failed\n");
5363                 goto out_failed;
5364         }
5365         return 0;
5366 out_failed:
5367         return -1;
5368 }
5369
5370
5371 /**
5372  * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5373  * @mrioc: Adapter instance reference
5374  * @ioc_status: Pointer to return ioc status
5375  * @exp_pg0: Pointer to return SAS Expander page 0
5376  * @pg_sz: Size of the memory allocated to the page pointer
5377  * @form: The form to be used for addressing the page
5378  * @form_spec: Form specific information like device handle
5379  *
5380  * This is handler for config page read for a specific SAS
5381  * Expander page0. The ioc_status has the controller returned
5382  * ioc_status. This routine doesn't check ioc_status to decide
5383  * whether the page read is success or not and it is the callers
5384  * responsibility.
5385  *
5386  * Return: 0 on success, non-zero on failure.
5387  */
5388 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5389         struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5390         u32 form_spec)
5391 {
5392         struct mpi3_config_page_header cfg_hdr;
5393         struct mpi3_config_request cfg_req;
5394         u32 page_address;
5395
5396         memset(exp_pg0, 0, pg_sz);
5397         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5398         memset(&cfg_req, 0, sizeof(cfg_req));
5399
5400         cfg_req.function = MPI3_FUNCTION_CONFIG;
5401         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5402         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5403         cfg_req.page_number = 0;
5404         cfg_req.page_address = 0;
5405
5406         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5407             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5408                 ioc_err(mrioc, "expander page0 header read failed\n");
5409                 goto out_failed;
5410         }
5411         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5412                 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
5413                     *ioc_status);
5414                 goto out_failed;
5415         }
5416         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5417         page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5418             (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5419             MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5420         cfg_req.page_address = cpu_to_le32(page_address);
5421         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5422             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
5423                 ioc_err(mrioc, "expander page0 read failed\n");
5424                 goto out_failed;
5425         }
5426         return 0;
5427 out_failed:
5428         return -1;
5429 }
5430
5431 /**
5432  * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
5433  * @mrioc: Adapter instance reference
5434  * @ioc_status: Pointer to return ioc status
5435  * @exp_pg1: Pointer to return SAS Expander page 1
5436  * @pg_sz: Size of the memory allocated to the page pointer
5437  * @form: The form to be used for addressing the page
5438  * @form_spec: Form specific information like phy number
5439  *
5440  * This is handler for config page read for a specific SAS
5441  * Expander page1. The ioc_status has the controller returned
5442  * ioc_status. This routine doesn't check ioc_status to decide
5443  * whether the page read is success or not and it is the callers
5444  * responsibility.
5445  *
5446  * Return: 0 on success, non-zero on failure.
5447  */
5448 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5449         struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
5450         u32 form_spec)
5451 {
5452         struct mpi3_config_page_header cfg_hdr;
5453         struct mpi3_config_request cfg_req;
5454         u32 page_address;
5455
5456         memset(exp_pg1, 0, pg_sz);
5457         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5458         memset(&cfg_req, 0, sizeof(cfg_req));
5459
5460         cfg_req.function = MPI3_FUNCTION_CONFIG;
5461         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5462         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5463         cfg_req.page_number = 1;
5464         cfg_req.page_address = 0;
5465
5466         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5467             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5468                 ioc_err(mrioc, "expander page1 header read failed\n");
5469                 goto out_failed;
5470         }
5471         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5472                 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
5473                     *ioc_status);
5474                 goto out_failed;
5475         }
5476         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5477         page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5478             (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5479             MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5480         cfg_req.page_address = cpu_to_le32(page_address);
5481         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5482             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
5483                 ioc_err(mrioc, "expander page1 read failed\n");
5484                 goto out_failed;
5485         }
5486         return 0;
5487 out_failed:
5488         return -1;
5489 }
5490
5491 /**
5492  * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
5493  * @mrioc: Adapter instance reference
5494  * @ioc_status: Pointer to return ioc status
5495  * @encl_pg0: Pointer to return Enclosure page 0
5496  * @pg_sz: Size of the memory allocated to the page pointer
5497  * @form: The form to be used for addressing the page
5498  * @form_spec: Form specific information like device handle
5499  *
5500  * This is handler for config page read for a specific Enclosure
5501  * page0. The ioc_status has the controller returned ioc_status.
5502  * This routine doesn't check ioc_status to decide whether the
5503  * page read is success or not and it is the callers
5504  * responsibility.
5505  *
5506  * Return: 0 on success, non-zero on failure.
5507  */
5508 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5509         struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
5510         u32 form_spec)
5511 {
5512         struct mpi3_config_page_header cfg_hdr;
5513         struct mpi3_config_request cfg_req;
5514         u32 page_address;
5515
5516         memset(encl_pg0, 0, pg_sz);
5517         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5518         memset(&cfg_req, 0, sizeof(cfg_req));
5519
5520         cfg_req.function = MPI3_FUNCTION_CONFIG;
5521         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5522         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
5523         cfg_req.page_number = 0;
5524         cfg_req.page_address = 0;
5525
5526         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5527             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5528                 ioc_err(mrioc, "enclosure page0 header read failed\n");
5529                 goto out_failed;
5530         }
5531         if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5532                 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
5533                     *ioc_status);
5534                 goto out_failed;
5535         }
5536         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5537         page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
5538             (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
5539         cfg_req.page_address = cpu_to_le32(page_address);
5540         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5541             MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
5542                 ioc_err(mrioc, "enclosure page0 read failed\n");
5543                 goto out_failed;
5544         }
5545         return 0;
5546 out_failed:
5547         return -1;
5548 }
5549
5550
5551 /**
5552  * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
5553  * @mrioc: Adapter instance reference
5554  * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
5555  * @pg_sz: Size of the memory allocated to the page pointer
5556  *
5557  * This is handler for config page read for the SAS IO Unit
5558  * page0. This routine checks ioc_status to decide whether the
5559  * page read is success or not.
5560  *
5561  * Return: 0 on success, non-zero on failure.
5562  */
5563 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
5564         struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
5565 {
5566         struct mpi3_config_page_header cfg_hdr;
5567         struct mpi3_config_request cfg_req;
5568         u16 ioc_status = 0;
5569
5570         memset(sas_io_unit_pg0, 0, pg_sz);
5571         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5572         memset(&cfg_req, 0, sizeof(cfg_req));
5573
5574         cfg_req.function = MPI3_FUNCTION_CONFIG;
5575         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5576         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5577         cfg_req.page_number = 0;
5578         cfg_req.page_address = 0;
5579
5580         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5581             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5582                 ioc_err(mrioc, "sas io unit page0 header read failed\n");
5583                 goto out_failed;
5584         }
5585         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5586                 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
5587                     ioc_status);
5588                 goto out_failed;
5589         }
5590         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5591
5592         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5593             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
5594                 ioc_err(mrioc, "sas io unit page0 read failed\n");
5595                 goto out_failed;
5596         }
5597         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5598                 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
5599                     ioc_status);
5600                 goto out_failed;
5601         }
5602         return 0;
5603 out_failed:
5604         return -1;
5605 }
5606
5607 /**
5608  * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
5609  * @mrioc: Adapter instance reference
5610  * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
5611  * @pg_sz: Size of the memory allocated to the page pointer
5612  *
5613  * This is handler for config page read for the SAS IO Unit
5614  * page1. This routine checks ioc_status to decide whether the
5615  * page read is success or not.
5616  *
5617  * Return: 0 on success, non-zero on failure.
5618  */
5619 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5620         struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5621 {
5622         struct mpi3_config_page_header cfg_hdr;
5623         struct mpi3_config_request cfg_req;
5624         u16 ioc_status = 0;
5625
5626         memset(sas_io_unit_pg1, 0, pg_sz);
5627         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5628         memset(&cfg_req, 0, sizeof(cfg_req));
5629
5630         cfg_req.function = MPI3_FUNCTION_CONFIG;
5631         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5632         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5633         cfg_req.page_number = 1;
5634         cfg_req.page_address = 0;
5635
5636         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5637             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5638                 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5639                 goto out_failed;
5640         }
5641         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5642                 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5643                     ioc_status);
5644                 goto out_failed;
5645         }
5646         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5647
5648         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5649             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5650                 ioc_err(mrioc, "sas io unit page1 read failed\n");
5651                 goto out_failed;
5652         }
5653         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5654                 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
5655                     ioc_status);
5656                 goto out_failed;
5657         }
5658         return 0;
5659 out_failed:
5660         return -1;
5661 }
5662
5663 /**
5664  * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
5665  * @mrioc: Adapter instance reference
5666  * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
5667  * @pg_sz: Size of the memory allocated to the page pointer
5668  *
5669  * This is handler for config page write for the SAS IO Unit
5670  * page1. This routine checks ioc_status to decide whether the
5671  * page read is success or not. This will modify both current
5672  * and persistent page.
5673  *
5674  * Return: 0 on success, non-zero on failure.
5675  */
5676 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5677         struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5678 {
5679         struct mpi3_config_page_header cfg_hdr;
5680         struct mpi3_config_request cfg_req;
5681         u16 ioc_status = 0;
5682
5683         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5684         memset(&cfg_req, 0, sizeof(cfg_req));
5685
5686         cfg_req.function = MPI3_FUNCTION_CONFIG;
5687         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5688         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5689         cfg_req.page_number = 1;
5690         cfg_req.page_address = 0;
5691
5692         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5693             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5694                 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5695                 goto out_failed;
5696         }
5697         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5698                 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5699                     ioc_status);
5700                 goto out_failed;
5701         }
5702         cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
5703
5704         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5705             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5706                 ioc_err(mrioc, "sas io unit page1 write current failed\n");
5707                 goto out_failed;
5708         }
5709         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5710                 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
5711                     ioc_status);
5712                 goto out_failed;
5713         }
5714
5715         cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
5716
5717         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5718             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5719                 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
5720                 goto out_failed;
5721         }
5722         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5723                 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
5724                     ioc_status);
5725                 goto out_failed;
5726         }
5727         return 0;
5728 out_failed:
5729         return -1;
5730 }
5731
5732 /**
5733  * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
5734  * @mrioc: Adapter instance reference
5735  * @driver_pg1: Pointer to return Driver page 1
5736  * @pg_sz: Size of the memory allocated to the page pointer
5737  *
5738  * This is handler for config page read for the Driver page1.
5739  * This routine checks ioc_status to decide whether the page
5740  * read is success or not.
5741  *
5742  * Return: 0 on success, non-zero on failure.
5743  */
5744 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
5745         struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
5746 {
5747         struct mpi3_config_page_header cfg_hdr;
5748         struct mpi3_config_request cfg_req;
5749         u16 ioc_status = 0;
5750
5751         memset(driver_pg1, 0, pg_sz);
5752         memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5753         memset(&cfg_req, 0, sizeof(cfg_req));
5754
5755         cfg_req.function = MPI3_FUNCTION_CONFIG;
5756         cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5757         cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
5758         cfg_req.page_number = 1;
5759         cfg_req.page_address = 0;
5760
5761         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5762             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5763                 ioc_err(mrioc, "driver page1 header read failed\n");
5764                 goto out_failed;
5765         }
5766         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5767                 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
5768                     ioc_status);
5769                 goto out_failed;
5770         }
5771         cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5772
5773         if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5774             MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
5775                 ioc_err(mrioc, "driver page1 read failed\n");
5776                 goto out_failed;
5777         }
5778         if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5779                 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
5780                     ioc_status);
5781                 goto out_failed;
5782         }
5783         return 0;
5784 out_failed:
5785         return -1;
5786 }