1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Driver for Broadcom MPI3 Storage Controllers
5 * Copyright (C) 2017-2021 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
10 #ifndef MPI3MR_H_INCLUDED
11 #define MPI3MR_H_INCLUDED
13 #include <linux/blkdev.h>
14 #include <linux/blk-mq.h>
15 #include <linux/blk-mq-pci.h>
16 #include <linux/delay.h>
17 #include <linux/dmapool.h>
18 #include <linux/errno.h>
19 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/miscdevice.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/poll.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/types.h>
30 #include <linux/uaccess.h>
31 #include <linux/utsname.h>
32 #include <linux/version.h>
33 #include <linux/workqueue.h>
34 #include <asm/unaligned.h>
35 #include <scsi/scsi.h>
36 #include <scsi/scsi_cmnd.h>
37 #include <scsi/scsi_dbg.h>
38 #include <scsi/scsi_device.h>
39 #include <scsi/scsi_host.h>
40 #include <scsi/scsi_tcq.h>
42 #include "mpi/mpi30_transport.h"
43 #include "mpi/mpi30_cnfg.h"
44 #include "mpi/mpi30_image.h"
45 #include "mpi/mpi30_init.h"
46 #include "mpi/mpi30_ioc.h"
47 #include "mpi/mpi30_sas.h"
48 #include "mpi/mpi30_pci.h"
49 #include "mpi3mr_debug.h"
51 /* Global list and lock for storing multiple adapters managed by the driver */
52 extern spinlock_t mrioc_list_lock;
53 extern struct list_head mrioc_list;
56 #define MPI3MR_DRIVER_VERSION "00.255.45.01"
57 #define MPI3MR_DRIVER_RELDATE "12-December-2020"
59 #define MPI3MR_DRIVER_NAME "mpi3mr"
60 #define MPI3MR_DRIVER_LICENSE "GPL"
61 #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
62 #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver"
64 #define MPI3MR_NAME_LENGTH 32
65 #define IOCNAME "%s: "
67 /* Definitions for internal SGL and Chain SGL buffers */
68 #define MPI3MR_PAGE_SIZE_4K 4096
69 #define MPI3MR_SG_DEPTH (MPI3MR_PAGE_SIZE_4K / sizeof(struct mpi3_sge_common))
71 /* Definitions for MAX values for shost */
72 #define MPI3MR_MAX_CMDS_LUN 7
73 #define MPI3MR_MAX_CDB_LENGTH 32
75 /* Admin queue management definitions */
76 #define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K)
77 #define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K)
78 #define MPI3MR_ADMIN_REQ_FRAME_SZ 128
79 #define MPI3MR_ADMIN_REPLY_FRAME_SZ 16
81 /* Operational queue management definitions */
82 #define MPI3MR_OP_REQ_Q_QD 512
83 #define MPI3MR_OP_REP_Q_QD 4096
84 #define MPI3MR_OP_REQ_Q_SEG_SIZE 4096
85 #define MPI3MR_OP_REP_Q_SEG_SIZE 4096
86 #define MPI3MR_MAX_SEG_LIST_SIZE 4096
88 /* Reserved Host Tag definitions */
89 #define MPI3MR_HOSTTAG_INVALID 0xFFFF
90 #define MPI3MR_HOSTTAG_INITCMDS 1
91 #define MPI3MR_HOSTTAG_IOCTLCMDS 2
92 #define MPI3MR_HOSTTAG_BLK_TMS 5
94 #define MPI3MR_NUM_DEVRMCMD 16
95 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_BLK_TMS + 1)
96 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
97 MPI3MR_NUM_DEVRMCMD - 1)
99 #define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX
100 #define MPI3MR_NUM_EVTACKCMD 4
101 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
102 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
103 MPI3MR_NUM_EVTACKCMD - 1)
105 /* Reduced resource count definition for crash kernel */
106 #define MPI3MR_HOST_IOS_KDUMP 128
108 /* command/controller interaction timeout definitions in seconds */
109 #define MPI3MR_INTADMCMD_TIMEOUT 60
110 #define MPI3MR_PORTENABLE_TIMEOUT 300
111 #define MPI3MR_ABORTTM_TIMEOUT 60
112 #define MPI3MR_RESETTM_TIMEOUT 60
113 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5
114 #define MPI3MR_TSUPDATE_INTERVAL 900
115 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120
116 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
117 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180
118 #define MPI3MR_RESET_ACK_TIMEOUT 30
120 #define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */
122 /* Internal admin command state definitions*/
123 #define MPI3MR_CMD_NOTUSED 0x8000
124 #define MPI3MR_CMD_COMPLETE 0x0001
125 #define MPI3MR_CMD_PENDING 0x0002
126 #define MPI3MR_CMD_REPLY_VALID 0x0004
127 #define MPI3MR_CMD_RESET 0x0008
129 /* Definitions for Event replies and sense buffer allocated per controller */
130 #define MPI3MR_NUM_EVT_REPLIES 64
131 #define MPI3MR_SENSE_BUF_SZ 256
132 #define MPI3MR_SENSEBUF_FACTOR 3
133 #define MPI3MR_CHAINBUF_FACTOR 3
134 #define MPI3MR_CHAINBUFDIX_FACTOR 2
136 /* Invalid target device handle */
137 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF
139 /* Controller Reset related definitions */
140 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5
141 #define MPI3MR_MAX_RESET_RETRY_COUNT 3
143 /* ResponseCode definitions */
144 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF)
145 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \
146 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
148 #define MPI3MR_DEFAULT_MDTS (128 * 1024)
149 #define MPI3MR_DEFAULT_PGSZEXP (12)
150 /* Command retry count definitions */
151 #define MPI3MR_DEV_RMHS_RETRY_COUNT 3
153 /* Default target device queue depth */
154 #define MPI3MR_DEFAULT_SDEV_QD 32
156 /* Definitions for Threaded IRQ poll*/
157 #define MPI3MR_IRQ_POLL_SLEEP 2
158 #define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8
160 /* Definitions for the controller security status*/
161 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C
162 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02
164 #define MPI3MR_INVALID_DEVICE 0x00
165 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04
166 #define MPI3MR_HARD_SECURE_DEVICE 0x08
167 #define MPI3MR_TAMPERED_DEVICE 0x0C
169 /* SGE Flag definition */
170 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
171 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
172 MPI3_SGE_FLAGS_END_OF_LIST)
174 /* MSI Index from Reply Queue Index */
175 #define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset)
177 /* IOC State definitions */
178 enum mpi3mr_iocstate {
179 MRIOC_STATE_READY = 1,
182 MRIOC_STATE_BECOMING_READY,
183 MRIOC_STATE_RESET_REQUESTED,
184 MRIOC_STATE_UNRECOVERABLE,
187 /* Reset reason code definitions*/
188 enum mpi3mr_reset_reason {
189 MPI3MR_RESET_FROM_BRINGUP = 1,
190 MPI3MR_RESET_FROM_FAULT_WATCH = 2,
191 MPI3MR_RESET_FROM_IOCTL = 3,
192 MPI3MR_RESET_FROM_EH_HOS = 4,
193 MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
194 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6,
195 MPI3MR_RESET_FROM_MUR_FAILURE = 7,
196 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
197 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
198 MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
199 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
200 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
201 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
202 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
203 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
204 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
205 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
206 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
207 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
208 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
209 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
210 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
211 MPI3MR_RESET_FROM_SYSFS = 23,
212 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
213 MPI3MR_RESET_FROM_FIRMWARE = 27,
216 /* Queue type definitions */
218 MPI3MR_DEFAULT_QUEUE = 0,
223 * struct mpi3mr_compimg_ver - replica of component image
224 * version defined in mpi30_image.h in host endianness
227 struct mpi3mr_compimg_ver {
237 * struct mpi3mr_ioc_facs - replica of component image version
238 * defined in mpi30_ioc.h in host endianness
241 struct mpi3mr_ioc_facts {
242 u32 ioc_capabilities;
243 struct mpi3mr_compimg_ver fw_ver;
252 u16 max_sasexpanders;
253 u16 max_sasinitiators;
255 u16 max_pcie_switches;
265 u16 shutdown_timeout;
268 u16 max_msix_vectors;
278 * struct segments - memory descriptor structure to store
279 * virtual and dma addresses for operational queue segments.
281 * @segment: virtual address
282 * @segment_dma: dma address
286 dma_addr_t segment_dma;
290 * struct op_req_qinfo - Operational Request Queue Information
292 * @ci: consumer index
293 * @pi: producer index
294 * @num_request: Maximum number of entries in the queue
295 * @qid: Queue Id starting from 1
296 * @reply_qid: Associated reply queue Id
297 * @num_segments: Number of discontiguous memory segments
298 * @segment_qd: Depth of each segments
299 * @q_lock: Concurrent queue access lock
300 * @q_segments: Segment descriptor pointer
301 * @q_segment_list: Segment list base virtual address
302 * @q_segment_list_dma: Segment list base DMA address
304 struct op_req_qinfo {
313 struct segments *q_segments;
314 void *q_segment_list;
315 dma_addr_t q_segment_list_dma;
319 * struct op_reply_qinfo - Operational Reply Queue Information
321 * @ci: consumer index
322 * @qid: Queue Id starting from 1
323 * @num_replies: Maximum number of entries in the queue
324 * @num_segments: Number of discontiguous memory segments
325 * @segment_qd: Depth of each segments
326 * @q_segments: Segment descriptor pointer
327 * @q_segment_list: Segment list base virtual address
328 * @q_segment_list_dma: Segment list base DMA address
329 * @ephase: Expected phased identifier for the reply queue
330 * @pend_ios: Number of IOs pending in HW for this queue
331 * @enable_irq_poll: Flag to indicate polling is enabled
332 * @in_use: Queue is handled by poll/ISR
333 * @qtype: Type of queue (types defined in enum queue_type)
335 struct op_reply_qinfo {
341 struct segments *q_segments;
342 void *q_segment_list;
343 dma_addr_t q_segment_list_dma;
346 bool enable_irq_poll;
348 enum queue_type qtype;
352 * struct mpi3mr_intr_info - Interrupt cookie information
354 * @mrioc: Adapter instance reference
355 * @msix_index: MSIx index
356 * @op_reply_q: Associated operational reply queue
357 * @name: Dev name for the irq claiming device
359 struct mpi3mr_intr_info {
360 struct mpi3mr_ioc *mrioc;
362 struct op_reply_qinfo *op_reply_q;
363 char name[MPI3MR_NAME_LENGTH];
367 * struct tgt_dev_sas_sata - SAS/SATA device specific
368 * information cached from firmware given data
370 * @sas_address: World wide unique SAS address
371 * @dev_info: Device information bits
373 struct tgt_dev_sas_sata {
379 * struct tgt_dev_pcie - PCIe device specific information cached
380 * from firmware given data
382 * @mdts: Maximum data transfer size
383 * @capb: Device capabilities
384 * @pgsz: Device page size
385 * @abort_to: Timeout for abort TM
386 * @reset_to: Timeout for Target/LUN reset TM
387 * @dev_info: Device information bits
389 struct tgt_dev_pcie {
399 * struct tgt_dev_volume - virtual device specific information
400 * cached from firmware given data
402 * @state: State of the VD
404 struct tgt_dev_volume {
409 * union _form_spec_inf - union of device specific information
411 union _form_spec_inf {
412 struct tgt_dev_sas_sata sas_sata_inf;
413 struct tgt_dev_pcie pcie_inf;
414 struct tgt_dev_volume vol_inf;
420 * struct mpi3mr_tgt_dev - target device data structure
422 * @list: List pointer
423 * @starget: Scsi_target pointer
424 * @dev_handle: FW device handle
425 * @parent_handle: FW parent device handle
427 * @encl_handle: FW enclosure handle
428 * @perst_id: FW assigned Persistent ID
429 * @dev_type: SAS/SATA/PCIE device type
430 * @is_hidden: Should be exposed to upper layers or not
431 * @host_exposed: Already exposed to host or not
432 * @q_depth: Device specific Queue Depth
433 * @wwid: World wide ID
434 * @dev_spec: Device type specific information
435 * @ref_count: Reference count
437 struct mpi3mr_tgt_dev {
438 struct list_head list;
439 struct scsi_target *starget;
450 union _form_spec_inf dev_spec;
451 struct kref ref_count;
455 * mpi3mr_tgtdev_get - k reference incrementor
456 * @s: Target device reference
458 * Increment target device reference count.
460 static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
462 kref_get(&s->ref_count);
466 * mpi3mr_free_tgtdev - target device memory dealloctor
467 * @r: k reference pointer of the target device
469 * Free target device memory when no reference.
471 static inline void mpi3mr_free_tgtdev(struct kref *r)
473 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
477 * mpi3mr_tgtdev_put - k reference decrementor
478 * @s: Target device reference
480 * Decrement target device reference count.
482 static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
484 kref_put(&s->ref_count, mpi3mr_free_tgtdev);
489 * struct mpi3mr_stgt_priv_data - SCSI target private structure
491 * @starget: Scsi_target pointer
492 * @dev_handle: FW device handle
493 * @perst_id: FW assigned Persistent ID
494 * @num_luns: Number of Logical Units
495 * @block_io: I/O blocked to the device or not
496 * @dev_removed: Device removed in the Firmware
497 * @dev_removedelay: Device is waiting to be removed in FW
498 * @dev_type: Device type
499 * @tgt_dev: Internal target device pointer
501 struct mpi3mr_stgt_priv_data {
502 struct scsi_target *starget;
510 struct mpi3mr_tgt_dev *tgt_dev;
514 * struct mpi3mr_stgt_priv_data - SCSI device private structure
516 * @tgt_priv_data: Scsi_target private data pointer
517 * @lun_id: LUN ID of the device
518 * @ncq_prio_enable: NCQ priority enable for SATA device
520 struct mpi3mr_sdev_priv_data {
521 struct mpi3mr_stgt_priv_data *tgt_priv_data;
527 * struct mpi3mr_drv_cmd - Internal command tracker
529 * @mutex: Command mutex
530 * @done: Completeor for wakeup
531 * @reply: Firmware reply for internal commands
532 * @sensebuf: Sensebuf for SCSI IO commands
533 * @iou_rc: IO Unit control reason code
534 * @state: Command State
535 * @dev_handle: Firmware handle for device specific commands
536 * @ioc_status: IOC status from the firmware
537 * @ioc_loginfo:IOC log info from the firmware
538 * @is_waiting: Is the command issued in block mode
539 * @retry_count: Retry count for retriable commands
540 * @host_tag: Host tag used by the command
541 * @callback: Callback for non blocking commands
543 struct mpi3mr_drv_cmd {
545 struct completion done;
557 void (*callback)(struct mpi3mr_ioc *mrioc,
558 struct mpi3mr_drv_cmd *drv_cmd);
563 * struct chain_element - memory descriptor structure to store
564 * virtual and dma addresses for chain elements.
566 * @addr: virtual address
567 * @dma_addr: dma address
569 struct chain_element {
575 * struct scmd_priv - SCSI command private data
577 * @host_tag: Host tag specific to operational queue
578 * @in_lld_scope: Command in LLD scope or not
579 * @meta_sg_valid: DIX command with meta data SGL or not
580 * @scmd: SCSI Command pointer
581 * @req_q_idx: Operational request queue index
582 * @chain_idx: Chain frame index
583 * @meta_chain_idx: Chain frame index of meta data SGL
584 * @mpi3mr_scsiio_req: MPI SCSI IO request
590 struct scsi_cmnd *scmd;
594 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
598 * struct mpi3mr_ioc - Adapter anchor structure stored in shost
601 * @list: List pointer
602 * @pdev: PCI device pointer
603 * @shost: Scsi_Host pointer
605 * @cpu_count: Number of online CPUs
606 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
607 * @name: Controller ASCII name
608 * @driver_name: Driver ASCII name
609 * @sysif_regs: System interface registers virtual address
610 * @sysif_regs_phys: System interface registers physical address
612 * @dma_mask: DMA mask
613 * @msix_count: Number of MSIX vectors used
614 * @intr_enabled: Is interrupts enabled
615 * @num_admin_req: Number of admin requests
616 * @admin_req_q_sz: Admin request queue size
617 * @admin_req_pi: Admin request queue producer index
618 * @admin_req_ci: Admin request queue consumer index
619 * @admin_req_base: Admin request queue base virtual address
620 * @admin_req_dma: Admin request queue base dma address
621 * @admin_req_lock: Admin queue access lock
622 * @num_admin_replies: Number of admin replies
623 * @admin_reply_q_sz: Admin reply queue size
624 * @admin_reply_ci: Admin reply queue consumer index
625 * @admin_reply_ephase:Admin reply queue expected phase
626 * @admin_reply_base: Admin reply queue base virtual address
627 * @admin_reply_dma: Admin reply queue base dma address
628 * @ready_timeout: Controller ready timeout
629 * @intr_info: Interrupt cookie pointer
630 * @intr_info_count: Number of interrupt cookies
631 * @is_intr_info_set: Flag to indicate intr info is setup
632 * @num_queues: Number of operational queues
633 * @num_op_req_q: Number of operational request queues
634 * @req_qinfo: Operational request queue info pointer
635 * @num_op_reply_q: Number of operational reply queues
636 * @op_reply_qinfo: Operational reply queue info pointer
637 * @init_cmds: Command tracker for initialization commands
638 * @facts: Cached IOC facts data
639 * @op_reply_desc_sz: Operational reply descriptor size
640 * @num_reply_bufs: Number of reply buffers allocated
641 * @reply_buf_pool: Reply buffer pool
642 * @reply_buf: Reply buffer base virtual address
643 * @reply_buf_dma: Reply buffer DMA address
644 * @reply_buf_dma_max_address: Reply DMA address max limit
645 * @reply_free_qsz: Reply free queue size
646 * @reply_free_q_pool: Reply free queue pool
647 * @reply_free_q: Reply free queue base virtual address
648 * @reply_free_q_dma: Reply free queue base DMA address
649 * @reply_free_queue_lock: Reply free queue lock
650 * @reply_free_queue_host_index: Reply free queue host index
651 * @num_sense_bufs: Number of sense buffers
652 * @sense_buf_pool: Sense buffer pool
653 * @sense_buf: Sense buffer base virtual address
654 * @sense_buf_dma: Sense buffer base DMA address
655 * @sense_buf_q_sz: Sense buffer queue size
656 * @sense_buf_q_pool: Sense buffer queue pool
657 * @sense_buf_q: Sense buffer queue virtual address
658 * @sense_buf_q_dma: Sense buffer queue DMA address
659 * @sbq_lock: Sense buffer queue lock
660 * @sbq_host_index: Sense buffer queuehost index
661 * @event_masks: Event mask bitmap
662 * @fwevt_worker_name: Firmware event worker thread name
663 * @fwevt_worker_thread: Firmware event worker thread
664 * @fwevt_lock: Firmware event lock
665 * @fwevt_list: Firmware event list
666 * @watchdog_work_q_name: Fault watchdog worker thread name
667 * @watchdog_work_q: Fault watchdog worker thread
668 * @watchdog_work: Fault watchdog work
669 * @watchdog_lock: Fault watchdog lock
670 * @is_driver_loading: Is driver still loading
671 * @scan_started: Async scan started
672 * @scan_failed: Asycn scan failed
673 * @stop_drv_processing: Stop all command processing
674 * @max_host_ios: Maximum host I/O count
675 * @chain_buf_count: Chain buffer count
676 * @chain_buf_pool: Chain buffer pool
677 * @chain_sgl_list: Chain SGL list
678 * @chain_bitmap_sz: Chain buffer allocator bitmap size
679 * @chain_bitmap: Chain buffer allocator bitmap
680 * @chain_buf_lock: Chain buffer list lock
681 * @host_tm_cmds: Command tracker for task management commands
682 * @dev_rmhs_cmds: Command tracker for device removal commands
683 * @evtack_cmds: Command tracker for event ack commands
684 * @devrem_bitmap_sz: Device removal bitmap size
685 * @devrem_bitmap: Device removal bitmap
686 * @dev_handle_bitmap_sz: Device handle bitmap size
687 * @removepend_bitmap: Remove pending bitmap
688 * @delayed_rmhs_list: Delayed device removal list
689 * @evtack_cmds_bitmap_sz: Event Ack bitmap size
690 * @evtack_cmds_bitmap: Event Ack bitmap
691 * @delayed_evtack_cmds_list: Delayed event acknowledgment list
692 * @ts_update_counter: Timestamp update counter
693 * @reset_in_progress: Reset in progress flag
694 * @unrecoverable: Controller unrecoverable flag
695 * @prev_reset_result: Result of previous reset
696 * @reset_mutex: Controller reset mutex
697 * @reset_waitq: Controller reset wait queue
698 * @prepare_for_reset: Prepare for reset event received
699 * @prepare_for_reset_timeout_counter: Prepare for reset timeout
700 * @diagsave_timeout: Diagnostic information save timeout
701 * @logging_level: Controller debug logging level
702 * @flush_io_count: I/O count to flush after reset
703 * @current_event: Firmware event currently in process
704 * @driver_info: Driver, Kernel, OS information to firmware
705 * @change_count: Topology change count
706 * @op_reply_q_offset: Operational reply queue offset with MSIx
707 * @default_qcount: Total Default queues
708 * @active_poll_qcount: Currently active poll queue count
709 * @requested_poll_qcount: User requested poll queue count
712 struct list_head list;
713 struct pci_dev *pdev;
714 struct Scsi_Host *shost;
717 bool enable_segqueue;
720 char name[MPI3MR_NAME_LENGTH];
721 char driver_name[MPI3MR_NAME_LENGTH];
723 volatile struct mpi3_sysif_registers __iomem *sysif_regs;
724 resource_size_t sysif_regs_phys;
735 void *admin_req_base;
736 dma_addr_t admin_req_dma;
737 spinlock_t admin_req_lock;
739 u16 num_admin_replies;
740 u32 admin_reply_q_sz;
742 u8 admin_reply_ephase;
743 void *admin_reply_base;
744 dma_addr_t admin_reply_dma;
748 struct mpi3mr_intr_info *intr_info;
750 bool is_intr_info_set;
754 struct op_req_qinfo *req_qinfo;
757 struct op_reply_qinfo *op_reply_qinfo;
759 struct mpi3mr_drv_cmd init_cmds;
760 struct mpi3mr_ioc_facts facts;
761 u16 op_reply_desc_sz;
764 struct dma_pool *reply_buf_pool;
766 dma_addr_t reply_buf_dma;
767 dma_addr_t reply_buf_dma_max_address;
771 struct dma_pool *reply_free_q_pool;
772 __le64 *reply_free_q;
773 dma_addr_t reply_free_q_dma;
774 spinlock_t reply_free_queue_lock;
775 u32 reply_free_queue_host_index;
778 struct dma_pool *sense_buf_pool;
780 dma_addr_t sense_buf_dma;
783 struct dma_pool *sense_buf_q_pool;
785 dma_addr_t sense_buf_q_dma;
788 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
790 char fwevt_worker_name[MPI3MR_NAME_LENGTH];
791 struct workqueue_struct *fwevt_worker_thread;
792 spinlock_t fwevt_lock;
793 struct list_head fwevt_list;
795 char watchdog_work_q_name[20];
796 struct workqueue_struct *watchdog_work_q;
797 struct delayed_work watchdog_work;
798 spinlock_t watchdog_lock;
800 u8 is_driver_loading;
803 u8 stop_drv_processing;
806 spinlock_t tgtdev_lock;
807 struct list_head tgtdev_list;
810 struct dma_pool *chain_buf_pool;
811 struct chain_element *chain_sgl_list;
814 spinlock_t chain_buf_lock;
816 struct mpi3mr_drv_cmd host_tm_cmds;
817 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
818 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
819 u16 devrem_bitmap_sz;
821 u16 dev_handle_bitmap_sz;
822 void *removepend_bitmap;
823 struct list_head delayed_rmhs_list;
824 u16 evtack_cmds_bitmap_sz;
825 void *evtack_cmds_bitmap;
826 struct list_head delayed_evtack_cmds_list;
828 u32 ts_update_counter;
829 u8 reset_in_progress;
831 int prev_reset_result;
832 struct mutex reset_mutex;
833 wait_queue_head_t reset_waitq;
835 u8 prepare_for_reset;
836 u16 prepare_for_reset_timeout_counter;
838 u16 diagsave_timeout;
842 struct mpi3mr_fwevt *current_event;
843 struct mpi3_driver_info_layout driver_info;
845 u16 op_reply_q_offset;
848 u16 active_poll_qcount;
849 u16 requested_poll_qcount;
853 * struct mpi3mr_fwevt - Firmware event structure.
856 * @work: Work structure
857 * @mrioc: Adapter instance reference
858 * @event_id: MPI3 firmware event ID
859 * @send_ack: Event acknowledgment required or not
860 * @process_evt: Bottomhalf processing required or not
861 * @evt_ctx: Event context to send in Ack
862 * @ref_count: kref count
863 * @event_data: Actual MPI3 event data
865 struct mpi3mr_fwevt {
866 struct list_head list;
867 struct work_struct work;
868 struct mpi3mr_ioc *mrioc;
873 struct kref ref_count;
874 char event_data[0] __aligned(4);
879 * struct delayed_dev_rmhs_node - Delayed device removal node
882 * @handle: Device handle
883 * @iou_rc: IO Unit Control Reason Code
885 struct delayed_dev_rmhs_node {
886 struct list_head list;
892 * struct delayed_evt_ack_node - Delayed event ack node
894 * @event: MPI3 event ID
895 * @event_ctx: event context
897 struct delayed_evt_ack_node {
898 struct list_head list;
903 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
904 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
905 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc);
906 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume);
907 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc);
908 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
909 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
910 u16 admin_req_sz, u8 ignore_reset);
911 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
912 struct op_req_qinfo *opreqq, u8 *req);
913 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
914 dma_addr_t dma_addr);
915 void mpi3mr_build_zero_len_sge(void *paddr);
916 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
917 dma_addr_t phys_addr);
918 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
919 dma_addr_t phys_addr);
920 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
923 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);
924 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc);
925 void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
926 struct mpi3_event_notification_reply *event_reply);
927 void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
928 struct mpi3_default_reply_descriptor *reply_desc,
929 u64 *reply_dma, u16 qidx);
930 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
931 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
933 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
934 u32 reset_reason, u8 snapdump);
935 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
936 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
938 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
939 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
942 void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
943 void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
944 void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
945 void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
946 void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc);
947 void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
948 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
949 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
950 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
951 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
952 struct op_reply_qinfo *op_reply_q);
953 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
955 #endif /*MPI3MR_H_INCLUDED*/