drivers/scsi/lpfc/lpfc_hw4.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2017-2021 Broadcom. All Rights Reserved. The term *
   5  * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.  *
   6  * Copyright (C) 2009-2016 Emulex.  All rights reserved.           *
   7  * EMULEX and SLI are trademarks of Emulex.                        *
   8  * www.broadcom.com                                                *
   9  *                                                                 *
  10  * This program is free software; you can redistribute it and/or   *
  11  * modify it under the terms of version 2 of the GNU General       *
  12  * Public License as published by the Free Software Foundation.    *
  13  * This program is distributed in the hope that it will be useful. *
  14  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  15  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  16  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  17  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  18  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  19  * more details, a copy of which can be found in the file COPYING  *
  20  * included with this package.                                     *
  21  *******************************************************************/
  22
  23 #include <uapi/scsi/fc/fc_fs.h>
  24 #include <uapi/scsi/fc/fc_els.h>
  25
  26 /* Macros to deal with bit fields. Each bit field must have 3 #defines
  27  * associated with it (_SHIFT, _MASK, and _WORD).
  28  * EG. For a bit field that is in the 7th bit of the "field4" field of a
  29  * structure and is 2 bits in size the following #defines must exist:
  30  *      struct temp {
  31  *              uint32_t        field1;
  32  *              uint32_t        field2;
  33  *              uint32_t        field3;
  34  *              uint32_t        field4;
  35  *      #define example_bit_field_SHIFT         7
  36  *      #define example_bit_field_MASK          0x03
  37  *      #define example_bit_field_WORD          field4
  38  *              uint32_t        field5;
  39  *      };
  40  * Then the macros below may be used to get or set the value of that field.
  41  * EG. To get the value of the bit field from the above example:
  42  *      struct temp t1;
  43  *      value = bf_get(example_bit_field, &t1);
  44  * And then to set that bit field:
  45  *      bf_set(example_bit_field, &t1, 2);
  46  * Or clear that bit field:
  47  *      bf_set(example_bit_field, &t1, 0);
  48  */
  49 #define bf_get_be32(name, ptr) \
  50         ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  51 #define bf_get_le32(name, ptr) \
  52         ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  53 #define bf_get(name, ptr) \
  54         (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
  55 #define bf_set_le32(name, ptr, value) \
  56         ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
  57         name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
  58         ~(name##_MASK << name##_SHIFT)))))
  59 #define bf_set(name, ptr, value) \
  60         ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
  61                  ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
  62
  63 struct dma_address {
  64         uint32_t addr_lo;
  65         uint32_t addr_hi;
  66 };
  67
  68 struct lpfc_sli_intf {
  69         uint32_t word0;
  70 #define lpfc_sli_intf_valid_SHIFT               29
  71 #define lpfc_sli_intf_valid_MASK                0x00000007
  72 #define lpfc_sli_intf_valid_WORD                word0
  73 #define LPFC_SLI_INTF_VALID             6
  74 #define lpfc_sli_intf_sli_hint2_SHIFT           24
  75 #define lpfc_sli_intf_sli_hint2_MASK            0x0000001F
  76 #define lpfc_sli_intf_sli_hint2_WORD            word0
  77 #define LPFC_SLI_INTF_SLI_HINT2_NONE    0
  78 #define lpfc_sli_intf_sli_hint1_SHIFT           16
  79 #define lpfc_sli_intf_sli_hint1_MASK            0x000000FF
  80 #define lpfc_sli_intf_sli_hint1_WORD            word0
  81 #define LPFC_SLI_INTF_SLI_HINT1_NONE    0
  82 #define LPFC_SLI_INTF_SLI_HINT1_1       1
  83 #define LPFC_SLI_INTF_SLI_HINT1_2       2
  84 #define lpfc_sli_intf_if_type_SHIFT             12
  85 #define lpfc_sli_intf_if_type_MASK              0x0000000F
  86 #define lpfc_sli_intf_if_type_WORD              word0
  87 #define LPFC_SLI_INTF_IF_TYPE_0         0
  88 #define LPFC_SLI_INTF_IF_TYPE_1         1
  89 #define LPFC_SLI_INTF_IF_TYPE_2         2
  90 #define LPFC_SLI_INTF_IF_TYPE_6         6
  91 #define lpfc_sli_intf_sli_family_SHIFT          8
  92 #define lpfc_sli_intf_sli_family_MASK           0x0000000F
  93 #define lpfc_sli_intf_sli_family_WORD           word0
  94 #define LPFC_SLI_INTF_FAMILY_BE2        0x0
  95 #define LPFC_SLI_INTF_FAMILY_BE3        0x1
  96 #define LPFC_SLI_INTF_FAMILY_LNCR_A0    0xa
  97 #define LPFC_SLI_INTF_FAMILY_LNCR_B0    0xb
  98 #define LPFC_SLI_INTF_FAMILY_G6         0xc
  99 #define LPFC_SLI_INTF_FAMILY_G7         0xd
 100 #define LPFC_SLI_INTF_FAMILY_G7P        0xe
 101 #define lpfc_sli_intf_slirev_SHIFT              4
 102 #define lpfc_sli_intf_slirev_MASK               0x0000000F
 103 #define lpfc_sli_intf_slirev_WORD               word0
 104 #define LPFC_SLI_INTF_REV_SLI3          3
 105 #define LPFC_SLI_INTF_REV_SLI4          4
 106 #define lpfc_sli_intf_func_type_SHIFT           0
 107 #define lpfc_sli_intf_func_type_MASK            0x00000001
 108 #define lpfc_sli_intf_func_type_WORD            word0
 109 #define LPFC_SLI_INTF_IF_TYPE_PHYS      0
 110 #define LPFC_SLI_INTF_IF_TYPE_VIRT      1
 111 };
 112
 113 #define LPFC_SLI4_MBX_EMBED     true
 114 #define LPFC_SLI4_MBX_NEMBED    false
 115
 116 #define LPFC_SLI4_MB_WORD_COUNT         64
 117 #define LPFC_MAX_MQ_PAGE                8
 118 #define LPFC_MAX_WQ_PAGE_V0             4
 119 #define LPFC_MAX_WQ_PAGE                8
 120 #define LPFC_MAX_RQ_PAGE                8
 121 #define LPFC_MAX_CQ_PAGE                4
 122 #define LPFC_MAX_EQ_PAGE                8
 123
 124 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
 125 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
 126 #define LPFC_VFR_PAGE_SIZE      0x1000 /* 4KB BAR2 per-VF register page size */
 127
 128 /* Define SLI4 Alignment requirements. */
 129 #define LPFC_ALIGN_16_BYTE      16
 130 #define LPFC_ALIGN_64_BYTE      64
 131 #define SLI4_PAGE_SIZE          4096
 132
 133 /* Define SLI4 specific definitions. */
 134 #define LPFC_MQ_CQE_BYTE_OFFSET 256
 135 #define LPFC_MBX_CMD_HDR_LENGTH 16
 136 #define LPFC_MBX_ERROR_RANGE    0x4000
 137 #define LPFC_BMBX_BIT1_ADDR_HI  0x2
 138 #define LPFC_BMBX_BIT1_ADDR_LO  0
 139 #define LPFC_RPI_HDR_COUNT      64
 140 #define LPFC_HDR_TEMPLATE_SIZE  4096
 141 #define LPFC_RPI_ALLOC_ERROR    0xFFFF
 142 #define LPFC_FCF_RECORD_WD_CNT  132
 143 #define LPFC_ENTIRE_FCF_DATABASE 0
 144 #define LPFC_DFLT_FCF_INDEX      0
 145
 146 /* Virtual function numbers */
 147 #define LPFC_VF0                0
 148 #define LPFC_VF1                1
 149 #define LPFC_VF2                2
 150 #define LPFC_VF3                3
 151 #define LPFC_VF4                4
 152 #define LPFC_VF5                5
 153 #define LPFC_VF6                6
 154 #define LPFC_VF7                7
 155 #define LPFC_VF8                8
 156 #define LPFC_VF9                9
 157 #define LPFC_VF10               10
 158 #define LPFC_VF11               11
 159 #define LPFC_VF12               12
 160 #define LPFC_VF13               13
 161 #define LPFC_VF14               14
 162 #define LPFC_VF15               15
 163 #define LPFC_VF16               16
 164 #define LPFC_VF17               17
 165 #define LPFC_VF18               18
 166 #define LPFC_VF19               19
 167 #define LPFC_VF20               20
 168 #define LPFC_VF21               21
 169 #define LPFC_VF22               22
 170 #define LPFC_VF23               23
 171 #define LPFC_VF24               24
 172 #define LPFC_VF25               25
 173 #define LPFC_VF26               26
 174 #define LPFC_VF27               27
 175 #define LPFC_VF28               28
 176 #define LPFC_VF29               29
 177 #define LPFC_VF30               30
 178 #define LPFC_VF31               31
 179
 180 /* PCI function numbers */
 181 #define LPFC_PCI_FUNC0          0
 182 #define LPFC_PCI_FUNC1          1
 183 #define LPFC_PCI_FUNC2          2
 184 #define LPFC_PCI_FUNC3          3
 185 #define LPFC_PCI_FUNC4          4
 186
 187 /* SLI4 interface type-2 PDEV_CTL register */
 188 #define LPFC_CTL_PDEV_CTL_OFFSET        0x414
 189 #define LPFC_CTL_PDEV_CTL_DRST          0x00000001
 190 #define LPFC_CTL_PDEV_CTL_FRST          0x00000002
 191 #define LPFC_CTL_PDEV_CTL_DD            0x00000004
 192 #define LPFC_CTL_PDEV_CTL_LC            0x00000008
 193 #define LPFC_CTL_PDEV_CTL_FRL_ALL       0x00
 194 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE   0x10
 195 #define LPFC_CTL_PDEV_CTL_FRL_NIC       0x20
 196 #define LPFC_CTL_PDEV_CTL_DDL_RAS       0x1000000
 197
 198 #define LPFC_FW_DUMP_REQUEST    (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
 199
 200 /* Active interrupt test count */
 201 #define LPFC_ACT_INTR_CNT       4
 202
 203 /* Algrithmns for scheduling FCP commands to WQs */
 204 #define LPFC_FCP_SCHED_BY_HDWQ          0
 205 #define LPFC_FCP_SCHED_BY_CPU           1
 206
 207 /* Algrithmns for NameServer Query after RSCN */
 208 #define LPFC_NS_QUERY_GID_FT    0
 209 #define LPFC_NS_QUERY_GID_PT    1
 210
 211 /* Delay Multiplier constant */
 212 #define LPFC_DMULT_CONST       651042
 213 #define LPFC_DMULT_MAX         1023
 214
 215 /* Configuration of Interrupts / sec for entire HBA port */
 216 #define LPFC_MIN_IMAX          5000
 217 #define LPFC_MAX_IMAX          5000000
 218 #define LPFC_DEF_IMAX          0
 219
 220 #define LPFC_MAX_AUTO_EQ_DELAY 120
 221 #define LPFC_EQ_DELAY_STEP     15
 222 #define LPFC_EQD_ISR_TRIGGER   20000
 223 /* 1s intervals */
 224 #define LPFC_EQ_DELAY_MSECS    1000
 225
 226 #define LPFC_MIN_CPU_MAP       0
 227 #define LPFC_MAX_CPU_MAP       1
 228 #define LPFC_HBA_CPU_MAP       1
 229
 230 /* PORT_CAPABILITIES constants. */
 231 #define LPFC_MAX_SUPPORTED_PAGES        8
 232
 233 struct ulp_bde64 {
 234         union ULP_BDE_TUS {
 235                 uint32_t w;
 236                 struct {
 237 #ifdef __BIG_ENDIAN_BITFIELD
 238                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 239                                                    VALUE !! */
 240                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 241 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 242                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 243                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 244                                                    VALUE !! */
 245 #endif
 246 #define BUFF_TYPE_BDE_64    0x00        /* BDE (Host_resident) */
 247 #define BUFF_TYPE_BDE_IMMED 0x01        /* Immediate Data BDE */
 248 #define BUFF_TYPE_BDE_64P   0x02        /* BDE (Port-resident) */
 249 #define BUFF_TYPE_BDE_64I   0x08        /* Input BDE (Host-resident) */
 250 #define BUFF_TYPE_BDE_64IP  0x0A        /* Input BDE (Port-resident) */
 251 #define BUFF_TYPE_BLP_64    0x40        /* BLP (Host-resident) */
 252 #define BUFF_TYPE_BLP_64P   0x42        /* BLP (Port-resident) */
 253                 } f;
 254         } tus;
 255         uint32_t addrLow;
 256         uint32_t addrHigh;
 257 };
 258
 259 /* Maximun size of immediate data that can fit into a 128 byte WQE */
 260 #define LPFC_MAX_BDE_IMM_SIZE   64
 261
 262 struct lpfc_sli4_flags {
 263         uint32_t word0;
 264 #define lpfc_idx_rsrc_rdy_SHIFT         0
 265 #define lpfc_idx_rsrc_rdy_MASK          0x00000001
 266 #define lpfc_idx_rsrc_rdy_WORD          word0
 267 #define LPFC_IDX_RSRC_RDY               1
 268 #define lpfc_rpi_rsrc_rdy_SHIFT         1
 269 #define lpfc_rpi_rsrc_rdy_MASK          0x00000001
 270 #define lpfc_rpi_rsrc_rdy_WORD          word0
 271 #define LPFC_RPI_RSRC_RDY               1
 272 #define lpfc_vpi_rsrc_rdy_SHIFT         2
 273 #define lpfc_vpi_rsrc_rdy_MASK          0x00000001
 274 #define lpfc_vpi_rsrc_rdy_WORD          word0
 275 #define LPFC_VPI_RSRC_RDY               1
 276 #define lpfc_vfi_rsrc_rdy_SHIFT         3
 277 #define lpfc_vfi_rsrc_rdy_MASK          0x00000001
 278 #define lpfc_vfi_rsrc_rdy_WORD          word0
 279 #define LPFC_VFI_RSRC_RDY               1
 280 #define lpfc_ftr_ashdr_SHIFT            4
 281 #define lpfc_ftr_ashdr_MASK             0x00000001
 282 #define lpfc_ftr_ashdr_WORD             word0
 283 };
 284
 285 struct sli4_bls_rsp {
 286         uint32_t word0_rsvd;      /* Word0 must be reserved */
 287         uint32_t word1;
 288 #define lpfc_abts_orig_SHIFT      0
 289 #define lpfc_abts_orig_MASK       0x00000001
 290 #define lpfc_abts_orig_WORD       word1
 291 #define LPFC_ABTS_UNSOL_RSP       1
 292 #define LPFC_ABTS_UNSOL_INT       0
 293         uint32_t word2;
 294 #define lpfc_abts_rxid_SHIFT      0
 295 #define lpfc_abts_rxid_MASK       0x0000FFFF
 296 #define lpfc_abts_rxid_WORD       word2
 297 #define lpfc_abts_oxid_SHIFT      16
 298 #define lpfc_abts_oxid_MASK       0x0000FFFF
 299 #define lpfc_abts_oxid_WORD       word2
 300         uint32_t word3;
 301 #define lpfc_vndr_code_SHIFT    0
 302 #define lpfc_vndr_code_MASK     0x000000FF
 303 #define lpfc_vndr_code_WORD     word3
 304 #define lpfc_rsn_expln_SHIFT    8
 305 #define lpfc_rsn_expln_MASK     0x000000FF
 306 #define lpfc_rsn_expln_WORD     word3
 307 #define lpfc_rsn_code_SHIFT     16
 308 #define lpfc_rsn_code_MASK      0x000000FF
 309 #define lpfc_rsn_code_WORD      word3
 310
 311         uint32_t word4;
 312         uint32_t word5_rsvd;    /* Word5 must be reserved */
 313 };
 314
 315 /* event queue entry structure */
 316 struct lpfc_eqe {
 317         uint32_t word0;
 318 #define lpfc_eqe_resource_id_SHIFT      16
 319 #define lpfc_eqe_resource_id_MASK       0x0000FFFF
 320 #define lpfc_eqe_resource_id_WORD       word0
 321 #define lpfc_eqe_minor_code_SHIFT       4
 322 #define lpfc_eqe_minor_code_MASK        0x00000FFF
 323 #define lpfc_eqe_minor_code_WORD        word0
 324 #define lpfc_eqe_major_code_SHIFT       1
 325 #define lpfc_eqe_major_code_MASK        0x00000007
 326 #define lpfc_eqe_major_code_WORD        word0
 327 #define lpfc_eqe_valid_SHIFT            0
 328 #define lpfc_eqe_valid_MASK             0x00000001
 329 #define lpfc_eqe_valid_WORD             word0
 330 };
 331
 332 /* completion queue entry structure (common fields for all cqe types) */
 333 struct lpfc_cqe {
 334         uint32_t reserved0;
 335         uint32_t reserved1;
 336         uint32_t reserved2;
 337         uint32_t word3;
 338 #define lpfc_cqe_valid_SHIFT            31
 339 #define lpfc_cqe_valid_MASK             0x00000001
 340 #define lpfc_cqe_valid_WORD             word3
 341 #define lpfc_cqe_code_SHIFT             16
 342 #define lpfc_cqe_code_MASK              0x000000FF
 343 #define lpfc_cqe_code_WORD              word3
 344 };
 345
 346 /* Completion Queue Entry Status Codes */
 347 #define CQE_STATUS_SUCCESS              0x0
 348 #define CQE_STATUS_FCP_RSP_FAILURE      0x1
 349 #define CQE_STATUS_REMOTE_STOP          0x2
 350 #define CQE_STATUS_LOCAL_REJECT         0x3
 351 #define CQE_STATUS_NPORT_RJT            0x4
 352 #define CQE_STATUS_FABRIC_RJT           0x5
 353 #define CQE_STATUS_NPORT_BSY            0x6
 354 #define CQE_STATUS_FABRIC_BSY           0x7
 355 #define CQE_STATUS_INTERMED_RSP         0x8
 356 #define CQE_STATUS_LS_RJT               0x9
 357 #define CQE_STATUS_CMD_REJECT           0xb
 358 #define CQE_STATUS_FCP_TGT_LENCHECK     0xc
 359 #define CQE_STATUS_NEED_BUFF_ENTRY      0xf
 360 #define CQE_STATUS_DI_ERROR             0x16
 361
 362 /* Used when mapping CQE status to IOCB */
 363 #define LPFC_IOCB_STATUS_MASK           0xf
 364
 365 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
 366 #define CQE_HW_STATUS_NO_ERR            0x0
 367 #define CQE_HW_STATUS_UNDERRUN          0x1
 368 #define CQE_HW_STATUS_OVERRUN           0x2
 369
 370 /* Completion Queue Entry Codes */
 371 #define CQE_CODE_COMPL_WQE              0x1
 372 #define CQE_CODE_RELEASE_WQE            0x2
 373 #define CQE_CODE_RECEIVE                0x4
 374 #define CQE_CODE_XRI_ABORTED            0x5
 375 #define CQE_CODE_RECEIVE_V1             0x9
 376 #define CQE_CODE_NVME_ERSP              0xd
 377
 378 /*
 379  * Define mask value for xri_aborted and wcqe completed CQE extended status.
 380  * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
 381  */
 382 #define WCQE_PARAM_MASK         0x1FF
 383
 384 /* completion queue entry for wqe completions */
 385 struct lpfc_wcqe_complete {
 386         uint32_t word0;
 387 #define lpfc_wcqe_c_request_tag_SHIFT   16
 388 #define lpfc_wcqe_c_request_tag_MASK    0x0000FFFF
 389 #define lpfc_wcqe_c_request_tag_WORD    word0
 390 #define lpfc_wcqe_c_status_SHIFT        8
 391 #define lpfc_wcqe_c_status_MASK         0x000000FF
 392 #define lpfc_wcqe_c_status_WORD         word0
 393 #define lpfc_wcqe_c_hw_status_SHIFT     0
 394 #define lpfc_wcqe_c_hw_status_MASK      0x000000FF
 395 #define lpfc_wcqe_c_hw_status_WORD      word0
 396 #define lpfc_wcqe_c_ersp0_SHIFT         0
 397 #define lpfc_wcqe_c_ersp0_MASK          0x0000FFFF
 398 #define lpfc_wcqe_c_ersp0_WORD          word0
 399         uint32_t total_data_placed;
 400 #define lpfc_wcqe_c_cmf_cg_SHIFT        31
 401 #define lpfc_wcqe_c_cmf_cg_MASK         0x00000001
 402 #define lpfc_wcqe_c_cmf_cg_WORD         total_data_placed
 403 #define lpfc_wcqe_c_cmf_bw_SHIFT        0
 404 #define lpfc_wcqe_c_cmf_bw_MASK         0x0FFFFFFF
 405 #define lpfc_wcqe_c_cmf_bw_WORD         total_data_placed
 406         uint32_t parameter;
 407 #define lpfc_wcqe_c_bg_edir_SHIFT       5
 408 #define lpfc_wcqe_c_bg_edir_MASK        0x00000001
 409 #define lpfc_wcqe_c_bg_edir_WORD        parameter
 410 #define lpfc_wcqe_c_bg_tdpv_SHIFT       3
 411 #define lpfc_wcqe_c_bg_tdpv_MASK        0x00000001
 412 #define lpfc_wcqe_c_bg_tdpv_WORD        parameter
 413 #define lpfc_wcqe_c_bg_re_SHIFT         2
 414 #define lpfc_wcqe_c_bg_re_MASK          0x00000001
 415 #define lpfc_wcqe_c_bg_re_WORD          parameter
 416 #define lpfc_wcqe_c_bg_ae_SHIFT         1
 417 #define lpfc_wcqe_c_bg_ae_MASK          0x00000001
 418 #define lpfc_wcqe_c_bg_ae_WORD          parameter
 419 #define lpfc_wcqe_c_bg_ge_SHIFT         0
 420 #define lpfc_wcqe_c_bg_ge_MASK          0x00000001
 421 #define lpfc_wcqe_c_bg_ge_WORD          parameter
 422         uint32_t word3;
 423 #define lpfc_wcqe_c_valid_SHIFT         lpfc_cqe_valid_SHIFT
 424 #define lpfc_wcqe_c_valid_MASK          lpfc_cqe_valid_MASK
 425 #define lpfc_wcqe_c_valid_WORD          lpfc_cqe_valid_WORD
 426 #define lpfc_wcqe_c_xb_SHIFT            28
 427 #define lpfc_wcqe_c_xb_MASK             0x00000001
 428 #define lpfc_wcqe_c_xb_WORD             word3
 429 #define lpfc_wcqe_c_pv_SHIFT            27
 430 #define lpfc_wcqe_c_pv_MASK             0x00000001
 431 #define lpfc_wcqe_c_pv_WORD             word3
 432 #define lpfc_wcqe_c_priority_SHIFT      24
 433 #define lpfc_wcqe_c_priority_MASK       0x00000007
 434 #define lpfc_wcqe_c_priority_WORD       word3
 435 #define lpfc_wcqe_c_code_SHIFT          lpfc_cqe_code_SHIFT
 436 #define lpfc_wcqe_c_code_MASK           lpfc_cqe_code_MASK
 437 #define lpfc_wcqe_c_code_WORD           lpfc_cqe_code_WORD
 438 #define lpfc_wcqe_c_sqhead_SHIFT        0
 439 #define lpfc_wcqe_c_sqhead_MASK         0x0000FFFF
 440 #define lpfc_wcqe_c_sqhead_WORD         word3
 441 };
 442
 443 /* completion queue entry for wqe release */
 444 struct lpfc_wcqe_release {
 445         uint32_t reserved0;
 446         uint32_t reserved1;
 447         uint32_t word2;
 448 #define lpfc_wcqe_r_wq_id_SHIFT         16
 449 #define lpfc_wcqe_r_wq_id_MASK          0x0000FFFF
 450 #define lpfc_wcqe_r_wq_id_WORD          word2
 451 #define lpfc_wcqe_r_wqe_index_SHIFT     0
 452 #define lpfc_wcqe_r_wqe_index_MASK      0x0000FFFF
 453 #define lpfc_wcqe_r_wqe_index_WORD      word2
 454         uint32_t word3;
 455 #define lpfc_wcqe_r_valid_SHIFT         lpfc_cqe_valid_SHIFT
 456 #define lpfc_wcqe_r_valid_MASK          lpfc_cqe_valid_MASK
 457 #define lpfc_wcqe_r_valid_WORD          lpfc_cqe_valid_WORD
 458 #define lpfc_wcqe_r_code_SHIFT          lpfc_cqe_code_SHIFT
 459 #define lpfc_wcqe_r_code_MASK           lpfc_cqe_code_MASK
 460 #define lpfc_wcqe_r_code_WORD           lpfc_cqe_code_WORD
 461 };
 462
 463 struct sli4_wcqe_xri_aborted {
 464         uint32_t word0;
 465 #define lpfc_wcqe_xa_status_SHIFT               8
 466 #define lpfc_wcqe_xa_status_MASK                0x000000FF
 467 #define lpfc_wcqe_xa_status_WORD                word0
 468         uint32_t parameter;
 469         uint32_t word2;
 470 #define lpfc_wcqe_xa_remote_xid_SHIFT   16
 471 #define lpfc_wcqe_xa_remote_xid_MASK    0x0000FFFF
 472 #define lpfc_wcqe_xa_remote_xid_WORD    word2
 473 #define lpfc_wcqe_xa_xri_SHIFT          0
 474 #define lpfc_wcqe_xa_xri_MASK           0x0000FFFF
 475 #define lpfc_wcqe_xa_xri_WORD           word2
 476         uint32_t word3;
 477 #define lpfc_wcqe_xa_valid_SHIFT        lpfc_cqe_valid_SHIFT
 478 #define lpfc_wcqe_xa_valid_MASK         lpfc_cqe_valid_MASK
 479 #define lpfc_wcqe_xa_valid_WORD         lpfc_cqe_valid_WORD
 480 #define lpfc_wcqe_xa_ia_SHIFT           30
 481 #define lpfc_wcqe_xa_ia_MASK            0x00000001
 482 #define lpfc_wcqe_xa_ia_WORD            word3
 483 #define CQE_XRI_ABORTED_IA_REMOTE       0
 484 #define CQE_XRI_ABORTED_IA_LOCAL        1
 485 #define lpfc_wcqe_xa_br_SHIFT           29
 486 #define lpfc_wcqe_xa_br_MASK            0x00000001
 487 #define lpfc_wcqe_xa_br_WORD            word3
 488 #define CQE_XRI_ABORTED_BR_BA_ACC       0
 489 #define CQE_XRI_ABORTED_BR_BA_RJT       1
 490 #define lpfc_wcqe_xa_eo_SHIFT           28
 491 #define lpfc_wcqe_xa_eo_MASK            0x00000001
 492 #define lpfc_wcqe_xa_eo_WORD            word3
 493 #define CQE_XRI_ABORTED_EO_REMOTE       0
 494 #define CQE_XRI_ABORTED_EO_LOCAL        1
 495 #define lpfc_wcqe_xa_code_SHIFT         lpfc_cqe_code_SHIFT
 496 #define lpfc_wcqe_xa_code_MASK          lpfc_cqe_code_MASK
 497 #define lpfc_wcqe_xa_code_WORD          lpfc_cqe_code_WORD
 498 };
 499
 500 /* completion queue entry structure for rqe completion */
 501 struct lpfc_rcqe {
 502         uint32_t word0;
 503 #define lpfc_rcqe_bindex_SHIFT          16
 504 #define lpfc_rcqe_bindex_MASK           0x0000FFF
 505 #define lpfc_rcqe_bindex_WORD           word0
 506 #define lpfc_rcqe_status_SHIFT          8
 507 #define lpfc_rcqe_status_MASK           0x000000FF
 508 #define lpfc_rcqe_status_WORD           word0
 509 #define FC_STATUS_RQ_SUCCESS            0x10 /* Async receive successful */
 510 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED   0x11 /* payload truncated */
 511 #define FC_STATUS_INSUFF_BUF_NEED_BUF   0x12 /* Insufficient buffers */
 512 #define FC_STATUS_INSUFF_BUF_FRM_DISC   0x13 /* Frame Discard */
 513         uint32_t word1;
 514 #define lpfc_rcqe_fcf_id_v1_SHIFT       0
 515 #define lpfc_rcqe_fcf_id_v1_MASK        0x0000003F
 516 #define lpfc_rcqe_fcf_id_v1_WORD        word1
 517         uint32_t word2;
 518 #define lpfc_rcqe_length_SHIFT          16
 519 #define lpfc_rcqe_length_MASK           0x0000FFFF
 520 #define lpfc_rcqe_length_WORD           word2
 521 #define lpfc_rcqe_rq_id_SHIFT           6
 522 #define lpfc_rcqe_rq_id_MASK            0x000003FF
 523 #define lpfc_rcqe_rq_id_WORD            word2
 524 #define lpfc_rcqe_fcf_id_SHIFT          0
 525 #define lpfc_rcqe_fcf_id_MASK           0x0000003F
 526 #define lpfc_rcqe_fcf_id_WORD           word2
 527 #define lpfc_rcqe_rq_id_v1_SHIFT        0
 528 #define lpfc_rcqe_rq_id_v1_MASK         0x0000FFFF
 529 #define lpfc_rcqe_rq_id_v1_WORD         word2
 530         uint32_t word3;
 531 #define lpfc_rcqe_valid_SHIFT           lpfc_cqe_valid_SHIFT
 532 #define lpfc_rcqe_valid_MASK            lpfc_cqe_valid_MASK
 533 #define lpfc_rcqe_valid_WORD            lpfc_cqe_valid_WORD
 534 #define lpfc_rcqe_port_SHIFT            30
 535 #define lpfc_rcqe_port_MASK             0x00000001
 536 #define lpfc_rcqe_port_WORD             word3
 537 #define lpfc_rcqe_hdr_length_SHIFT      24
 538 #define lpfc_rcqe_hdr_length_MASK       0x0000001F
 539 #define lpfc_rcqe_hdr_length_WORD       word3
 540 #define lpfc_rcqe_code_SHIFT            lpfc_cqe_code_SHIFT
 541 #define lpfc_rcqe_code_MASK             lpfc_cqe_code_MASK
 542 #define lpfc_rcqe_code_WORD             lpfc_cqe_code_WORD
 543 #define lpfc_rcqe_eof_SHIFT             8
 544 #define lpfc_rcqe_eof_MASK              0x000000FF
 545 #define lpfc_rcqe_eof_WORD              word3
 546 #define FCOE_EOFn       0x41
 547 #define FCOE_EOFt       0x42
 548 #define FCOE_EOFni      0x49
 549 #define FCOE_EOFa       0x50
 550 #define lpfc_rcqe_sof_SHIFT             0
 551 #define lpfc_rcqe_sof_MASK              0x000000FF
 552 #define lpfc_rcqe_sof_WORD              word3
 553 #define FCOE_SOFi2      0x2d
 554 #define FCOE_SOFi3      0x2e
 555 #define FCOE_SOFn2      0x35
 556 #define FCOE_SOFn3      0x36
 557 };
 558
 559 struct lpfc_rqe {
 560         uint32_t address_hi;
 561         uint32_t address_lo;
 562 };
 563
 564 /* buffer descriptors */
 565 struct lpfc_bde4 {
 566         uint32_t addr_hi;
 567         uint32_t addr_lo;
 568         uint32_t word2;
 569 #define lpfc_bde4_last_SHIFT            31
 570 #define lpfc_bde4_last_MASK             0x00000001
 571 #define lpfc_bde4_last_WORD             word2
 572 #define lpfc_bde4_sge_offset_SHIFT      0
 573 #define lpfc_bde4_sge_offset_MASK       0x000003FF
 574 #define lpfc_bde4_sge_offset_WORD       word2
 575         uint32_t word3;
 576 #define lpfc_bde4_length_SHIFT          0
 577 #define lpfc_bde4_length_MASK           0x000000FF
 578 #define lpfc_bde4_length_WORD           word3
 579 };
 580
 581 struct lpfc_register {
 582         uint32_t word0;
 583 };
 584
 585 #define LPFC_PORT_SEM_UE_RECOVERABLE    0xE000
 586 #define LPFC_PORT_SEM_MASK              0xF000
 587 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
 588 #define LPFC_UERR_STATUS_HI             0x00A4
 589 #define LPFC_UERR_STATUS_LO             0x00A0
 590 #define LPFC_UE_MASK_HI                 0x00AC
 591 #define LPFC_UE_MASK_LO                 0x00A8
 592
 593 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
 594 #define LPFC_SLI_INTF                   0x0058
 595 #define LPFC_SLI_ASIC_VER               0x009C
 596
 597 #define LPFC_CTL_PORT_SEM_OFFSET        0x400
 598 #define lpfc_port_smphr_perr_SHIFT      31
 599 #define lpfc_port_smphr_perr_MASK       0x1
 600 #define lpfc_port_smphr_perr_WORD       word0
 601 #define lpfc_port_smphr_sfi_SHIFT       30
 602 #define lpfc_port_smphr_sfi_MASK        0x1
 603 #define lpfc_port_smphr_sfi_WORD        word0
 604 #define lpfc_port_smphr_nip_SHIFT       29
 605 #define lpfc_port_smphr_nip_MASK        0x1
 606 #define lpfc_port_smphr_nip_WORD        word0
 607 #define lpfc_port_smphr_ipc_SHIFT       28
 608 #define lpfc_port_smphr_ipc_MASK        0x1
 609 #define lpfc_port_smphr_ipc_WORD        word0
 610 #define lpfc_port_smphr_scr1_SHIFT      27
 611 #define lpfc_port_smphr_scr1_MASK       0x1
 612 #define lpfc_port_smphr_scr1_WORD       word0
 613 #define lpfc_port_smphr_scr2_SHIFT      26
 614 #define lpfc_port_smphr_scr2_MASK       0x1
 615 #define lpfc_port_smphr_scr2_WORD       word0
 616 #define lpfc_port_smphr_host_scratch_SHIFT      16
 617 #define lpfc_port_smphr_host_scratch_MASK       0xFF
 618 #define lpfc_port_smphr_host_scratch_WORD       word0
 619 #define lpfc_port_smphr_port_status_SHIFT       0
 620 #define lpfc_port_smphr_port_status_MASK        0xFFFF
 621 #define lpfc_port_smphr_port_status_WORD        word0
 622
 623 #define LPFC_POST_STAGE_POWER_ON_RESET                  0x0000
 624 #define LPFC_POST_STAGE_AWAITING_HOST_RDY               0x0001
 625 #define LPFC_POST_STAGE_HOST_RDY                        0x0002
 626 #define LPFC_POST_STAGE_BE_RESET                        0x0003
 627 #define LPFC_POST_STAGE_SEEPROM_CS_START                0x0100
 628 #define LPFC_POST_STAGE_SEEPROM_CS_DONE                 0x0101
 629 #define LPFC_POST_STAGE_DDR_CONFIG_START                0x0200
 630 #define LPFC_POST_STAGE_DDR_CONFIG_DONE                 0x0201
 631 #define LPFC_POST_STAGE_DDR_CALIBRATE_START             0x0300
 632 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE              0x0301
 633 #define LPFC_POST_STAGE_DDR_TEST_START                  0x0400
 634 #define LPFC_POST_STAGE_DDR_TEST_DONE                   0x0401
 635 #define LPFC_POST_STAGE_REDBOOT_INIT_START              0x0600
 636 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE               0x0601
 637 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START             0x0700
 638 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE              0x0701
 639 #define LPFC_POST_STAGE_ARMFW_START                     0x0800
 640 #define LPFC_POST_STAGE_DHCP_QUERY_START                0x0900
 641 #define LPFC_POST_STAGE_DHCP_QUERY_DONE                 0x0901
 642 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START     0x0A00
 643 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE      0x0A01
 644 #define LPFC_POST_STAGE_RC_OPTION_SET                   0x0B00
 645 #define LPFC_POST_STAGE_SWITCH_LINK                     0x0B01
 646 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE               0x0B02
 647 #define LPFC_POST_STAGE_PERFROM_TFTP                    0x0B03
 648 #define LPFC_POST_STAGE_PARSE_XML                       0x0B04
 649 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE                  0x0B05
 650 #define LPFC_POST_STAGE_FLASH_IMAGE                     0x0B06
 651 #define LPFC_POST_STAGE_RC_DONE                         0x0B07
 652 #define LPFC_POST_STAGE_REBOOT_SYSTEM                   0x0B08
 653 #define LPFC_POST_STAGE_MAC_ADDRESS                     0x0C00
 654 #define LPFC_POST_STAGE_PORT_READY                      0xC000
 655 #define LPFC_POST_STAGE_PORT_UE                         0xF000
 656
 657 #define LPFC_CTL_PORT_STA_OFFSET        0x404
 658 #define lpfc_sliport_status_err_SHIFT   31
 659 #define lpfc_sliport_status_err_MASK    0x1
 660 #define lpfc_sliport_status_err_WORD    word0
 661 #define lpfc_sliport_status_end_SHIFT   30
 662 #define lpfc_sliport_status_end_MASK    0x1
 663 #define lpfc_sliport_status_end_WORD    word0
 664 #define lpfc_sliport_status_oti_SHIFT   29
 665 #define lpfc_sliport_status_oti_MASK    0x1
 666 #define lpfc_sliport_status_oti_WORD    word0
 667 #define lpfc_sliport_status_dip_SHIFT   25
 668 #define lpfc_sliport_status_dip_MASK    0x1
 669 #define lpfc_sliport_status_dip_WORD    word0
 670 #define lpfc_sliport_status_rn_SHIFT    24
 671 #define lpfc_sliport_status_rn_MASK     0x1
 672 #define lpfc_sliport_status_rn_WORD     word0
 673 #define lpfc_sliport_status_rdy_SHIFT   23
 674 #define lpfc_sliport_status_rdy_MASK    0x1
 675 #define lpfc_sliport_status_rdy_WORD    word0
 676 #define MAX_IF_TYPE_2_RESETS            6
 677
 678 #define LPFC_CTL_PORT_CTL_OFFSET        0x408
 679 #define lpfc_sliport_ctrl_end_SHIFT     30
 680 #define lpfc_sliport_ctrl_end_MASK      0x1
 681 #define lpfc_sliport_ctrl_end_WORD      word0
 682 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
 683 #define LPFC_SLIPORT_BIG_ENDIAN    1
 684 #define lpfc_sliport_ctrl_ip_SHIFT      27
 685 #define lpfc_sliport_ctrl_ip_MASK       0x1
 686 #define lpfc_sliport_ctrl_ip_WORD       word0
 687 #define LPFC_SLIPORT_INIT_PORT  1
 688
 689 #define LPFC_CTL_PORT_ER1_OFFSET        0x40C
 690 #define LPFC_CTL_PORT_ER2_OFFSET        0x410
 691
 692 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET   0x418
 693 #define lpfc_sliport_eqdelay_delay_SHIFT 16
 694 #define lpfc_sliport_eqdelay_delay_MASK 0xffff
 695 #define lpfc_sliport_eqdelay_delay_WORD word0
 696 #define lpfc_sliport_eqdelay_id_SHIFT   0
 697 #define lpfc_sliport_eqdelay_id_MASK    0xfff
 698 #define lpfc_sliport_eqdelay_id_WORD    word0
 699 #define LPFC_SEC_TO_USEC                1000000
 700 #define LPFC_SEC_TO_MSEC                1000
 701
 702 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
 703  * reside in BAR 2.
 704  */
 705 #define LPFC_SLIPORT_IF0_SMPHR  0x00AC
 706
 707 #define LPFC_IMR_MASK_ALL       0xFFFFFFFF
 708 #define LPFC_ISCR_CLEAR_ALL     0xFFFFFFFF
 709
 710 #define LPFC_HST_ISR0           0x0C18
 711 #define LPFC_HST_ISR1           0x0C1C
 712 #define LPFC_HST_ISR2           0x0C20
 713 #define LPFC_HST_ISR3           0x0C24
 714 #define LPFC_HST_ISR4           0x0C28
 715
 716 #define LPFC_HST_IMR0           0x0C48
 717 #define LPFC_HST_IMR1           0x0C4C
 718 #define LPFC_HST_IMR2           0x0C50
 719 #define LPFC_HST_IMR3           0x0C54
 720 #define LPFC_HST_IMR4           0x0C58
 721
 722 #define LPFC_HST_ISCR0          0x0C78
 723 #define LPFC_HST_ISCR1          0x0C7C
 724 #define LPFC_HST_ISCR2          0x0C80
 725 #define LPFC_HST_ISCR3          0x0C84
 726 #define LPFC_HST_ISCR4          0x0C88
 727
 728 #define LPFC_SLI4_INTR0                 BIT0
 729 #define LPFC_SLI4_INTR1                 BIT1
 730 #define LPFC_SLI4_INTR2                 BIT2
 731 #define LPFC_SLI4_INTR3                 BIT3
 732 #define LPFC_SLI4_INTR4                 BIT4
 733 #define LPFC_SLI4_INTR5                 BIT5
 734 #define LPFC_SLI4_INTR6                 BIT6
 735 #define LPFC_SLI4_INTR7                 BIT7
 736 #define LPFC_SLI4_INTR8                 BIT8
 737 #define LPFC_SLI4_INTR9                 BIT9
 738 #define LPFC_SLI4_INTR10                BIT10
 739 #define LPFC_SLI4_INTR11                BIT11
 740 #define LPFC_SLI4_INTR12                BIT12
 741 #define LPFC_SLI4_INTR13                BIT13
 742 #define LPFC_SLI4_INTR14                BIT14
 743 #define LPFC_SLI4_INTR15                BIT15
 744 #define LPFC_SLI4_INTR16                BIT16
 745 #define LPFC_SLI4_INTR17                BIT17
 746 #define LPFC_SLI4_INTR18                BIT18
 747 #define LPFC_SLI4_INTR19                BIT19
 748 #define LPFC_SLI4_INTR20                BIT20
 749 #define LPFC_SLI4_INTR21                BIT21
 750 #define LPFC_SLI4_INTR22                BIT22
 751 #define LPFC_SLI4_INTR23                BIT23
 752 #define LPFC_SLI4_INTR24                BIT24
 753 #define LPFC_SLI4_INTR25                BIT25
 754 #define LPFC_SLI4_INTR26                BIT26
 755 #define LPFC_SLI4_INTR27                BIT27
 756 #define LPFC_SLI4_INTR28                BIT28
 757 #define LPFC_SLI4_INTR29                BIT29
 758 #define LPFC_SLI4_INTR30                BIT30
 759 #define LPFC_SLI4_INTR31                BIT31
 760
 761 /*
 762  * The Doorbell registers defined here exist in different BAR
 763  * register sets depending on the UCNA Port's reported if_type
 764  * value.  For UCNA ports running SLI4 and if_type 0, they reside in
 765  * BAR4.  For UCNA ports running SLI4 and if_type 2, they reside in
 766  * BAR0.  For FC ports running SLI4 and if_type 6, they reside in
 767  * BAR2. The offsets and base address are different,  so the driver
 768  * has to compute the register addresses accordingly
 769  */
 770 #define LPFC_ULP0_RQ_DOORBELL           0x00A0
 771 #define LPFC_ULP1_RQ_DOORBELL           0x00C0
 772 #define LPFC_IF6_RQ_DOORBELL            0x0080
 773 #define lpfc_rq_db_list_fm_num_posted_SHIFT     24
 774 #define lpfc_rq_db_list_fm_num_posted_MASK      0x00FF
 775 #define lpfc_rq_db_list_fm_num_posted_WORD      word0
 776 #define lpfc_rq_db_list_fm_index_SHIFT          16
 777 #define lpfc_rq_db_list_fm_index_MASK           0x00FF
 778 #define lpfc_rq_db_list_fm_index_WORD           word0
 779 #define lpfc_rq_db_list_fm_id_SHIFT             0
 780 #define lpfc_rq_db_list_fm_id_MASK              0xFFFF
 781 #define lpfc_rq_db_list_fm_id_WORD              word0
 782 #define lpfc_rq_db_ring_fm_num_posted_SHIFT     16
 783 #define lpfc_rq_db_ring_fm_num_posted_MASK      0x3FFF
 784 #define lpfc_rq_db_ring_fm_num_posted_WORD      word0
 785 #define lpfc_rq_db_ring_fm_id_SHIFT             0
 786 #define lpfc_rq_db_ring_fm_id_MASK              0xFFFF
 787 #define lpfc_rq_db_ring_fm_id_WORD              word0
 788
 789 #define LPFC_ULP0_WQ_DOORBELL           0x0040
 790 #define LPFC_ULP1_WQ_DOORBELL           0x0060
 791 #define lpfc_wq_db_list_fm_num_posted_SHIFT     24
 792 #define lpfc_wq_db_list_fm_num_posted_MASK      0x00FF
 793 #define lpfc_wq_db_list_fm_num_posted_WORD      word0
 794 #define lpfc_wq_db_list_fm_index_SHIFT          16
 795 #define lpfc_wq_db_list_fm_index_MASK           0x00FF
 796 #define lpfc_wq_db_list_fm_index_WORD           word0
 797 #define lpfc_wq_db_list_fm_id_SHIFT             0
 798 #define lpfc_wq_db_list_fm_id_MASK              0xFFFF
 799 #define lpfc_wq_db_list_fm_id_WORD              word0
 800 #define lpfc_wq_db_ring_fm_num_posted_SHIFT     16
 801 #define lpfc_wq_db_ring_fm_num_posted_MASK      0x3FFF
 802 #define lpfc_wq_db_ring_fm_num_posted_WORD      word0
 803 #define lpfc_wq_db_ring_fm_id_SHIFT             0
 804 #define lpfc_wq_db_ring_fm_id_MASK              0xFFFF
 805 #define lpfc_wq_db_ring_fm_id_WORD              word0
 806
 807 #define LPFC_IF6_WQ_DOORBELL            0x0040
 808 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24
 809 #define lpfc_if6_wq_db_list_fm_num_posted_MASK  0x00FF
 810 #define lpfc_if6_wq_db_list_fm_num_posted_WORD  word0
 811 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT        23
 812 #define lpfc_if6_wq_db_list_fm_dpp_MASK         0x0001
 813 #define lpfc_if6_wq_db_list_fm_dpp_WORD         word0
 814 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT     16
 815 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK      0x001F
 816 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD      word0
 817 #define lpfc_if6_wq_db_list_fm_id_SHIFT         0
 818 #define lpfc_if6_wq_db_list_fm_id_MASK          0xFFFF
 819 #define lpfc_if6_wq_db_list_fm_id_WORD          word0
 820
 821 #define LPFC_EQCQ_DOORBELL              0x0120
 822 #define lpfc_eqcq_doorbell_se_SHIFT             31
 823 #define lpfc_eqcq_doorbell_se_MASK              0x0001
 824 #define lpfc_eqcq_doorbell_se_WORD              word0
 825 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF    0
 826 #define LPFC_EQCQ_SOLICIT_ENABLE_ON     1
 827 #define lpfc_eqcq_doorbell_arm_SHIFT            29
 828 #define lpfc_eqcq_doorbell_arm_MASK             0x0001
 829 #define lpfc_eqcq_doorbell_arm_WORD             word0
 830 #define lpfc_eqcq_doorbell_num_released_SHIFT   16
 831 #define lpfc_eqcq_doorbell_num_released_MASK    0x1FFF
 832 #define lpfc_eqcq_doorbell_num_released_WORD    word0
 833 #define lpfc_eqcq_doorbell_qt_SHIFT             10
 834 #define lpfc_eqcq_doorbell_qt_MASK              0x0001
 835 #define lpfc_eqcq_doorbell_qt_WORD              word0
 836 #define LPFC_QUEUE_TYPE_COMPLETION      0
 837 #define LPFC_QUEUE_TYPE_EVENT           1
 838 #define lpfc_eqcq_doorbell_eqci_SHIFT           9
 839 #define lpfc_eqcq_doorbell_eqci_MASK            0x0001
 840 #define lpfc_eqcq_doorbell_eqci_WORD            word0
 841 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT        0
 842 #define lpfc_eqcq_doorbell_cqid_lo_MASK         0x03FF
 843 #define lpfc_eqcq_doorbell_cqid_lo_WORD         word0
 844 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT        11
 845 #define lpfc_eqcq_doorbell_cqid_hi_MASK         0x001F
 846 #define lpfc_eqcq_doorbell_cqid_hi_WORD         word0
 847 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT        0
 848 #define lpfc_eqcq_doorbell_eqid_lo_MASK         0x01FF
 849 #define lpfc_eqcq_doorbell_eqid_lo_WORD         word0
 850 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT        11
 851 #define lpfc_eqcq_doorbell_eqid_hi_MASK         0x001F
 852 #define lpfc_eqcq_doorbell_eqid_hi_WORD         word0
 853 #define LPFC_CQID_HI_FIELD_SHIFT                10
 854 #define LPFC_EQID_HI_FIELD_SHIFT                9
 855
 856 #define LPFC_IF6_CQ_DOORBELL                    0x00C0
 857 #define lpfc_if6_cq_doorbell_se_SHIFT           31
 858 #define lpfc_if6_cq_doorbell_se_MASK            0x0001
 859 #define lpfc_if6_cq_doorbell_se_WORD            word0
 860 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF          0
 861 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON           1
 862 #define lpfc_if6_cq_doorbell_arm_SHIFT          29
 863 #define lpfc_if6_cq_doorbell_arm_MASK           0x0001
 864 #define lpfc_if6_cq_doorbell_arm_WORD           word0
 865 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16
 866 #define lpfc_if6_cq_doorbell_num_released_MASK  0x1FFF
 867 #define lpfc_if6_cq_doorbell_num_released_WORD  word0
 868 #define lpfc_if6_cq_doorbell_cqid_SHIFT         0
 869 #define lpfc_if6_cq_doorbell_cqid_MASK          0xFFFF
 870 #define lpfc_if6_cq_doorbell_cqid_WORD          word0
 871
 872 #define LPFC_IF6_EQ_DOORBELL                    0x0120
 873 #define lpfc_if6_eq_doorbell_io_SHIFT           31
 874 #define lpfc_if6_eq_doorbell_io_MASK            0x0001
 875 #define lpfc_if6_eq_doorbell_io_WORD            word0
 876 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF           0
 877 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON            1
 878 #define lpfc_if6_eq_doorbell_arm_SHIFT          29
 879 #define lpfc_if6_eq_doorbell_arm_MASK           0x0001
 880 #define lpfc_if6_eq_doorbell_arm_WORD           word0
 881 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16
 882 #define lpfc_if6_eq_doorbell_num_released_MASK  0x1FFF
 883 #define lpfc_if6_eq_doorbell_num_released_WORD  word0
 884 #define lpfc_if6_eq_doorbell_eqid_SHIFT         0
 885 #define lpfc_if6_eq_doorbell_eqid_MASK          0x0FFF
 886 #define lpfc_if6_eq_doorbell_eqid_WORD          word0
 887
 888 #define LPFC_BMBX                       0x0160
 889 #define lpfc_bmbx_addr_SHIFT            2
 890 #define lpfc_bmbx_addr_MASK             0x3FFFFFFF
 891 #define lpfc_bmbx_addr_WORD             word0
 892 #define lpfc_bmbx_hi_SHIFT              1
 893 #define lpfc_bmbx_hi_MASK               0x0001
 894 #define lpfc_bmbx_hi_WORD               word0
 895 #define lpfc_bmbx_rdy_SHIFT             0
 896 #define lpfc_bmbx_rdy_MASK              0x0001
 897 #define lpfc_bmbx_rdy_WORD              word0
 898
 899 #define LPFC_MQ_DOORBELL                        0x0140
 900 #define LPFC_IF6_MQ_DOORBELL                    0x0160
 901 #define lpfc_mq_doorbell_num_posted_SHIFT       16
 902 #define lpfc_mq_doorbell_num_posted_MASK        0x3FFF
 903 #define lpfc_mq_doorbell_num_posted_WORD        word0
 904 #define lpfc_mq_doorbell_id_SHIFT               0
 905 #define lpfc_mq_doorbell_id_MASK                0xFFFF
 906 #define lpfc_mq_doorbell_id_WORD                word0
 907
 908 struct lpfc_sli4_cfg_mhdr {
 909         uint32_t word1;
 910 #define lpfc_mbox_hdr_emb_SHIFT         0
 911 #define lpfc_mbox_hdr_emb_MASK          0x00000001
 912 #define lpfc_mbox_hdr_emb_WORD          word1
 913 #define lpfc_mbox_hdr_sge_cnt_SHIFT     3
 914 #define lpfc_mbox_hdr_sge_cnt_MASK      0x0000001F
 915 #define lpfc_mbox_hdr_sge_cnt_WORD      word1
 916         uint32_t payload_length;
 917         uint32_t tag_lo;
 918         uint32_t tag_hi;
 919         uint32_t reserved5;
 920 };
 921
 922 union lpfc_sli4_cfg_shdr {
 923         struct {
 924                 uint32_t word6;
 925 #define lpfc_mbox_hdr_opcode_SHIFT      0
 926 #define lpfc_mbox_hdr_opcode_MASK       0x000000FF
 927 #define lpfc_mbox_hdr_opcode_WORD       word6
 928 #define lpfc_mbox_hdr_subsystem_SHIFT   8
 929 #define lpfc_mbox_hdr_subsystem_MASK    0x000000FF
 930 #define lpfc_mbox_hdr_subsystem_WORD    word6
 931 #define lpfc_mbox_hdr_port_number_SHIFT 16
 932 #define lpfc_mbox_hdr_port_number_MASK  0x000000FF
 933 #define lpfc_mbox_hdr_port_number_WORD  word6
 934 #define lpfc_mbox_hdr_domain_SHIFT      24
 935 #define lpfc_mbox_hdr_domain_MASK       0x000000FF
 936 #define lpfc_mbox_hdr_domain_WORD       word6
 937                 uint32_t timeout;
 938                 uint32_t request_length;
 939                 uint32_t word9;
 940 #define lpfc_mbox_hdr_version_SHIFT     0
 941 #define lpfc_mbox_hdr_version_MASK      0x000000FF
 942 #define lpfc_mbox_hdr_version_WORD      word9
 943 #define lpfc_mbox_hdr_pf_num_SHIFT      16
 944 #define lpfc_mbox_hdr_pf_num_MASK       0x000000FF
 945 #define lpfc_mbox_hdr_pf_num_WORD       word9
 946 #define lpfc_mbox_hdr_vh_num_SHIFT      24
 947 #define lpfc_mbox_hdr_vh_num_MASK       0x000000FF
 948 #define lpfc_mbox_hdr_vh_num_WORD       word9
 949 #define LPFC_Q_CREATE_VERSION_2 2
 950 #define LPFC_Q_CREATE_VERSION_1 1
 951 #define LPFC_Q_CREATE_VERSION_0 0
 952 #define LPFC_OPCODE_VERSION_0   0
 953 #define LPFC_OPCODE_VERSION_1   1
 954         } request;
 955         struct {
 956                 uint32_t word6;
 957 #define lpfc_mbox_hdr_opcode_SHIFT              0
 958 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 959 #define lpfc_mbox_hdr_opcode_WORD               word6
 960 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 961 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 962 #define lpfc_mbox_hdr_subsystem_WORD            word6
 963 #define lpfc_mbox_hdr_domain_SHIFT              24
 964 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 965 #define lpfc_mbox_hdr_domain_WORD               word6
 966                 uint32_t word7;
 967 #define lpfc_mbox_hdr_status_SHIFT              0
 968 #define lpfc_mbox_hdr_status_MASK               0x000000FF
 969 #define lpfc_mbox_hdr_status_WORD               word7
 970 #define lpfc_mbox_hdr_add_status_SHIFT          8
 971 #define lpfc_mbox_hdr_add_status_MASK           0x000000FF
 972 #define lpfc_mbox_hdr_add_status_WORD           word7
 973 #define LPFC_ADD_STATUS_INCOMPAT_OBJ            0xA2
 974 #define lpfc_mbox_hdr_add_status_2_SHIFT        16
 975 #define lpfc_mbox_hdr_add_status_2_MASK         0x000000FF
 976 #define lpfc_mbox_hdr_add_status_2_WORD         word7
 977 #define LPFC_ADD_STATUS_2_INCOMPAT_FLASH        0x01
 978 #define LPFC_ADD_STATUS_2_INCORRECT_ASIC        0x02
 979                 uint32_t response_length;
 980                 uint32_t actual_response_length;
 981         } response;
 982 };
 983
 984 /* Mailbox Header structures.
 985  * struct mbox_header is defined for first generation SLI4_CFG mailbox
 986  * calls deployed for BE-based ports.
 987  *
 988  * struct sli4_mbox_header is defined for second generation SLI4
 989  * ports that don't deploy the SLI4_CFG mechanism.
 990  */
 991 struct mbox_header {
 992         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 993         union  lpfc_sli4_cfg_shdr cfg_shdr;
 994 };
 995
 996 #define LPFC_EXTENT_LOCAL               0
 997 #define LPFC_TIMEOUT_DEFAULT            0
 998 #define LPFC_EXTENT_VERSION_DEFAULT     0
 999
1000 /* Subsystem Definitions */
1001 #define LPFC_MBOX_SUBSYSTEM_NA          0x0
1002 #define LPFC_MBOX_SUBSYSTEM_COMMON      0x1
1003 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL    0xB
1004 #define LPFC_MBOX_SUBSYSTEM_FCOE        0xC
1005
1006 /* Device Specific Definitions */
1007
1008 /* The HOST ENDIAN defines are in Big Endian format. */
1009 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
1010 #define HOST_ENDIAN_HIGH_WORD1  0xFF7856FF
1011
1012 /* Common Opcodes */
1013 #define LPFC_MBOX_OPCODE_NA                             0x00
1014 #define LPFC_MBOX_OPCODE_CQ_CREATE                      0x0C
1015 #define LPFC_MBOX_OPCODE_EQ_CREATE                      0x0D
1016 #define LPFC_MBOX_OPCODE_MQ_CREATE                      0x15
1017 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES            0x20
1018 #define LPFC_MBOX_OPCODE_NOP                            0x21
1019 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY                0x29
1020 #define LPFC_MBOX_OPCODE_MQ_DESTROY                     0x35
1021 #define LPFC_MBOX_OPCODE_CQ_DESTROY                     0x36
1022 #define LPFC_MBOX_OPCODE_EQ_DESTROY                     0x37
1023 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG                   0x3A
1024 #define LPFC_MBOX_OPCODE_FUNCTION_RESET                 0x3D
1025 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG       0x3E
1026 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG                0x43
1027 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG              0x45
1028 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG              0x46
1029 #define LPFC_MBOX_OPCODE_GET_PORT_NAME                  0x4D
1030 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT                  0x5A
1031 #define LPFC_MBOX_OPCODE_GET_VPD_DATA                   0x5B
1032 #define LPFC_MBOX_OPCODE_SET_HOST_DATA                  0x5D
1033 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION                0x73
1034 #define LPFC_MBOX_OPCODE_RESET_LICENSES                 0x74
1035 #define LPFC_MBOX_OPCODE_REG_CONGESTION_BUF             0x8E
1036 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO           0x9A
1037 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT          0x9B
1038 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT              0x9C
1039 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT            0x9D
1040 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG            0xA0
1041 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES         0xA1
1042 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG             0xA4
1043 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG             0xA5
1044 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST               0xA6
1045 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE                0xA8
1046 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG     0xA9
1047 #define LPFC_MBOX_OPCODE_READ_OBJECT                    0xAB
1048 #define LPFC_MBOX_OPCODE_WRITE_OBJECT                   0xAC
1049 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST               0xAD
1050 #define LPFC_MBOX_OPCODE_DELETE_OBJECT                  0xAE
1051 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS            0xB5
1052 #define LPFC_MBOX_OPCODE_SET_FEATURES                   0xBF
1053
1054 /* FCoE Opcodes */
1055 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE                 0x01
1056 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY                0x02
1057 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES            0x03
1058 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES          0x04
1059 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE                 0x05
1060 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY                0x06
1061 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE            0x08
1062 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF                   0x09
1063 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF                0x0A
1064 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE         0x0B
1065 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF            0x10
1066 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET             0x1D
1067 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS       0x21
1068 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE           0x22
1069 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK        0x23
1070 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE         0x42
1071
1072 /* Low level Opcodes */
1073 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION            0x37
1074
1075 /* Mailbox command structures */
1076 struct eq_context {
1077         uint32_t word0;
1078 #define lpfc_eq_context_size_SHIFT      31
1079 #define lpfc_eq_context_size_MASK       0x00000001
1080 #define lpfc_eq_context_size_WORD       word0
1081 #define LPFC_EQE_SIZE_4                 0x0
1082 #define LPFC_EQE_SIZE_16                0x1
1083 #define lpfc_eq_context_valid_SHIFT     29
1084 #define lpfc_eq_context_valid_MASK      0x00000001
1085 #define lpfc_eq_context_valid_WORD      word0
1086 #define lpfc_eq_context_autovalid_SHIFT 28
1087 #define lpfc_eq_context_autovalid_MASK  0x00000001
1088 #define lpfc_eq_context_autovalid_WORD  word0
1089         uint32_t word1;
1090 #define lpfc_eq_context_count_SHIFT     26
1091 #define lpfc_eq_context_count_MASK      0x00000003
1092 #define lpfc_eq_context_count_WORD      word1
1093 #define LPFC_EQ_CNT_256         0x0
1094 #define LPFC_EQ_CNT_512         0x1
1095 #define LPFC_EQ_CNT_1024        0x2
1096 #define LPFC_EQ_CNT_2048        0x3
1097 #define LPFC_EQ_CNT_4096        0x4
1098         uint32_t word2;
1099 #define lpfc_eq_context_delay_multi_SHIFT       13
1100 #define lpfc_eq_context_delay_multi_MASK        0x000003FF
1101 #define lpfc_eq_context_delay_multi_WORD        word2
1102         uint32_t reserved3;
1103 };
1104
1105 struct eq_delay_info {
1106         uint32_t eq_id;
1107         uint32_t phase;
1108         uint32_t delay_multi;
1109 };
1110 #define LPFC_MAX_EQ_DELAY_EQID_CNT      8
1111
1112 struct sgl_page_pairs {
1113         uint32_t sgl_pg0_addr_lo;
1114         uint32_t sgl_pg0_addr_hi;
1115         uint32_t sgl_pg1_addr_lo;
1116         uint32_t sgl_pg1_addr_hi;
1117 };
1118
1119 struct lpfc_mbx_post_sgl_pages {
1120         struct mbox_header header;
1121         uint32_t word0;
1122 #define lpfc_post_sgl_pages_xri_SHIFT   0
1123 #define lpfc_post_sgl_pages_xri_MASK    0x0000FFFF
1124 #define lpfc_post_sgl_pages_xri_WORD    word0
1125 #define lpfc_post_sgl_pages_xricnt_SHIFT        16
1126 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1127 #define lpfc_post_sgl_pages_xricnt_WORD word0
1128         struct sgl_page_pairs  sgl_pg_pairs[1];
1129 };
1130
1131 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
1132 struct lpfc_mbx_post_uembed_sgl_page1 {
1133         union  lpfc_sli4_cfg_shdr cfg_shdr;
1134         uint32_t word0;
1135         struct sgl_page_pairs sgl_pg_pairs;
1136 };
1137
1138 struct lpfc_mbx_sge {
1139         uint32_t pa_lo;
1140         uint32_t pa_hi;
1141         uint32_t length;
1142 };
1143
1144 struct lpfc_mbx_host_buf {
1145         uint32_t length;
1146         uint32_t pa_lo;
1147         uint32_t pa_hi;
1148 };
1149
1150 struct lpfc_mbx_nembed_cmd {
1151         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1152 #define LPFC_SLI4_MBX_SGE_MAX_PAGES     19
1153         struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1154 };
1155
1156 struct lpfc_mbx_nembed_sge_virt {
1157         void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1158 };
1159
1160 #define LPFC_MBX_OBJECT_NAME_LEN_DW     26
1161 struct lpfc_mbx_read_object {  /* Version 0 */
1162         struct mbox_header header;
1163         union {
1164                 struct {
1165                         uint32_t word0;
1166 #define lpfc_mbx_rd_object_rlen_SHIFT   0
1167 #define lpfc_mbx_rd_object_rlen_MASK    0x00FFFFFF
1168 #define lpfc_mbx_rd_object_rlen_WORD    word0
1169                         uint32_t rd_object_offset;
1170                         uint32_t rd_object_name[LPFC_MBX_OBJECT_NAME_LEN_DW];
1171 #define LPFC_OBJ_NAME_SZ 104   /* 26 x sizeof(uint32_t) is 104. */
1172                         uint32_t rd_object_cnt;
1173                         struct lpfc_mbx_host_buf rd_object_hbuf[4];
1174                 } request;
1175                 struct {
1176                         uint32_t rd_object_actual_rlen;
1177                         uint32_t word1;
1178 #define lpfc_mbx_rd_object_eof_SHIFT    31
1179 #define lpfc_mbx_rd_object_eof_MASK     0x1
1180 #define lpfc_mbx_rd_object_eof_WORD     word1
1181                 } response;
1182         } u;
1183 };
1184
1185 struct lpfc_mbx_eq_create {
1186         struct mbox_header header;
1187         union {
1188                 struct {
1189                         uint32_t word0;
1190 #define lpfc_mbx_eq_create_num_pages_SHIFT      0
1191 #define lpfc_mbx_eq_create_num_pages_MASK       0x0000FFFF
1192 #define lpfc_mbx_eq_create_num_pages_WORD       word0
1193                         struct eq_context context;
1194                         struct dma_address page[LPFC_MAX_EQ_PAGE];
1195                 } request;
1196                 struct {
1197                         uint32_t word0;
1198 #define lpfc_mbx_eq_create_q_id_SHIFT   0
1199 #define lpfc_mbx_eq_create_q_id_MASK    0x0000FFFF
1200 #define lpfc_mbx_eq_create_q_id_WORD    word0
1201                 } response;
1202         } u;
1203 };
1204
1205 struct lpfc_mbx_modify_eq_delay {
1206         struct mbox_header header;
1207         union {
1208                 struct {
1209                         uint32_t num_eq;
1210                         struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT];
1211                 } request;
1212                 struct {
1213                         uint32_t word0;
1214                 } response;
1215         } u;
1216 };
1217
1218 struct lpfc_mbx_eq_destroy {
1219         struct mbox_header header;
1220         union {
1221                 struct {
1222                         uint32_t word0;
1223 #define lpfc_mbx_eq_destroy_q_id_SHIFT  0
1224 #define lpfc_mbx_eq_destroy_q_id_MASK   0x0000FFFF
1225 #define lpfc_mbx_eq_destroy_q_id_WORD   word0
1226                 } request;
1227                 struct {
1228                         uint32_t word0;
1229                 } response;
1230         } u;
1231 };
1232
1233 struct lpfc_mbx_nop {
1234         struct mbox_header header;
1235         uint32_t context[2];
1236 };
1237
1238
1239
1240 struct lpfc_mbx_set_ras_fwlog {
1241         struct mbox_header header;
1242         union {
1243                 struct {
1244                         uint32_t word4;
1245 #define lpfc_fwlog_enable_SHIFT         0
1246 #define lpfc_fwlog_enable_MASK          0x00000001
1247 #define lpfc_fwlog_enable_WORD          word4
1248 #define lpfc_fwlog_loglvl_SHIFT         8
1249 #define lpfc_fwlog_loglvl_MASK          0x0000000F
1250 #define lpfc_fwlog_loglvl_WORD          word4
1251 #define lpfc_fwlog_ra_SHIFT             15
1252 #define lpfc_fwlog_ra_WORD              0x00000008
1253 #define lpfc_fwlog_buffcnt_SHIFT        16
1254 #define lpfc_fwlog_buffcnt_MASK         0x000000FF
1255 #define lpfc_fwlog_buffcnt_WORD         word4
1256 #define lpfc_fwlog_buffsz_SHIFT         24
1257 #define lpfc_fwlog_buffsz_MASK          0x000000FF
1258 #define lpfc_fwlog_buffsz_WORD          word4
1259                         uint32_t word5;
1260 #define lpfc_fwlog_acqe_SHIFT           0
1261 #define lpfc_fwlog_acqe_MASK            0x0000FFFF
1262 #define lpfc_fwlog_acqe_WORD            word5
1263 #define lpfc_fwlog_cqid_SHIFT           16
1264 #define lpfc_fwlog_cqid_MASK            0x0000FFFF
1265 #define lpfc_fwlog_cqid_WORD            word5
1266 #define LPFC_MAX_FWLOG_PAGE     16
1267                         struct dma_address lwpd;
1268                         struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE];
1269                 } request;
1270                 struct {
1271                         uint32_t word0;
1272                 } response;
1273         } u;
1274 };
1275
1276
1277 struct cq_context {
1278         uint32_t word0;
1279 #define lpfc_cq_context_event_SHIFT     31
1280 #define lpfc_cq_context_event_MASK      0x00000001
1281 #define lpfc_cq_context_event_WORD      word0
1282 #define lpfc_cq_context_valid_SHIFT     29
1283 #define lpfc_cq_context_valid_MASK      0x00000001
1284 #define lpfc_cq_context_valid_WORD      word0
1285 #define lpfc_cq_context_count_SHIFT     27
1286 #define lpfc_cq_context_count_MASK      0x00000003
1287 #define lpfc_cq_context_count_WORD      word0
1288 #define LPFC_CQ_CNT_256         0x0
1289 #define LPFC_CQ_CNT_512         0x1
1290 #define LPFC_CQ_CNT_1024        0x2
1291 #define LPFC_CQ_CNT_WORD7       0x3
1292 #define lpfc_cq_context_autovalid_SHIFT 15
1293 #define lpfc_cq_context_autovalid_MASK  0x00000001
1294 #define lpfc_cq_context_autovalid_WORD  word0
1295         uint32_t word1;
1296 #define lpfc_cq_eq_id_SHIFT             22      /* Version 0 Only */
1297 #define lpfc_cq_eq_id_MASK              0x000000FF
1298 #define lpfc_cq_eq_id_WORD              word1
1299 #define lpfc_cq_eq_id_2_SHIFT           0       /* Version 2 Only */
1300 #define lpfc_cq_eq_id_2_MASK            0x0000FFFF
1301 #define lpfc_cq_eq_id_2_WORD            word1
1302         uint32_t lpfc_cq_context_count;         /* Version 2 Only */
1303         uint32_t reserved1;
1304 };
1305
1306 struct lpfc_mbx_cq_create {
1307         struct mbox_header header;
1308         union {
1309                 struct {
1310                         uint32_t word0;
1311 #define lpfc_mbx_cq_create_page_size_SHIFT      16      /* Version 2 Only */
1312 #define lpfc_mbx_cq_create_page_size_MASK       0x000000FF
1313 #define lpfc_mbx_cq_create_page_size_WORD       word0
1314 #define lpfc_mbx_cq_create_num_pages_SHIFT      0
1315 #define lpfc_mbx_cq_create_num_pages_MASK       0x0000FFFF
1316 #define lpfc_mbx_cq_create_num_pages_WORD       word0
1317                         struct cq_context context;
1318                         struct dma_address page[LPFC_MAX_CQ_PAGE];
1319                 } request;
1320                 struct {
1321                         uint32_t word0;
1322 #define lpfc_mbx_cq_create_q_id_SHIFT   0
1323 #define lpfc_mbx_cq_create_q_id_MASK    0x0000FFFF
1324 #define lpfc_mbx_cq_create_q_id_WORD    word0
1325                 } response;
1326         } u;
1327 };
1328
1329 struct lpfc_mbx_cq_create_set {
1330         union  lpfc_sli4_cfg_shdr cfg_shdr;
1331         union {
1332                 struct {
1333                         uint32_t word0;
1334 #define lpfc_mbx_cq_create_set_page_size_SHIFT  16      /* Version 2 Only */
1335 #define lpfc_mbx_cq_create_set_page_size_MASK   0x000000FF
1336 #define lpfc_mbx_cq_create_set_page_size_WORD   word0
1337 #define lpfc_mbx_cq_create_set_num_pages_SHIFT  0
1338 #define lpfc_mbx_cq_create_set_num_pages_MASK   0x0000FFFF
1339 #define lpfc_mbx_cq_create_set_num_pages_WORD   word0
1340                         uint32_t word1;
1341 #define lpfc_mbx_cq_create_set_evt_SHIFT        31
1342 #define lpfc_mbx_cq_create_set_evt_MASK         0x00000001
1343 #define lpfc_mbx_cq_create_set_evt_WORD         word1
1344 #define lpfc_mbx_cq_create_set_valid_SHIFT      29
1345 #define lpfc_mbx_cq_create_set_valid_MASK       0x00000001
1346 #define lpfc_mbx_cq_create_set_valid_WORD       word1
1347 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT    27
1348 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK     0x00000003
1349 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD     word1
1350 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT   25
1351 #define lpfc_mbx_cq_create_set_cqe_size_MASK    0x00000003
1352 #define lpfc_mbx_cq_create_set_cqe_size_WORD    word1
1353 #define lpfc_mbx_cq_create_set_autovalid_SHIFT  15
1354 #define lpfc_mbx_cq_create_set_autovalid_MASK   0x0000001
1355 #define lpfc_mbx_cq_create_set_autovalid_WORD   word1
1356 #define lpfc_mbx_cq_create_set_nodelay_SHIFT    14
1357 #define lpfc_mbx_cq_create_set_nodelay_MASK     0x00000001
1358 #define lpfc_mbx_cq_create_set_nodelay_WORD     word1
1359 #define lpfc_mbx_cq_create_set_clswm_SHIFT      12
1360 #define lpfc_mbx_cq_create_set_clswm_MASK       0x00000003
1361 #define lpfc_mbx_cq_create_set_clswm_WORD       word1
1362                         uint32_t word2;
1363 #define lpfc_mbx_cq_create_set_arm_SHIFT        31
1364 #define lpfc_mbx_cq_create_set_arm_MASK         0x00000001
1365 #define lpfc_mbx_cq_create_set_arm_WORD         word2
1366 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT     16
1367 #define lpfc_mbx_cq_create_set_cq_cnt_MASK      0x00007FFF
1368 #define lpfc_mbx_cq_create_set_cq_cnt_WORD      word2
1369 #define lpfc_mbx_cq_create_set_num_cq_SHIFT     0
1370 #define lpfc_mbx_cq_create_set_num_cq_MASK      0x0000FFFF
1371 #define lpfc_mbx_cq_create_set_num_cq_WORD      word2
1372                         uint32_t word3;
1373 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT     16
1374 #define lpfc_mbx_cq_create_set_eq_id1_MASK      0x0000FFFF
1375 #define lpfc_mbx_cq_create_set_eq_id1_WORD      word3
1376 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT     0
1377 #define lpfc_mbx_cq_create_set_eq_id0_MASK      0x0000FFFF
1378 #define lpfc_mbx_cq_create_set_eq_id0_WORD      word3
1379                         uint32_t word4;
1380 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT     16
1381 #define lpfc_mbx_cq_create_set_eq_id3_MASK      0x0000FFFF
1382 #define lpfc_mbx_cq_create_set_eq_id3_WORD      word4
1383 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT     0
1384 #define lpfc_mbx_cq_create_set_eq_id2_MASK      0x0000FFFF
1385 #define lpfc_mbx_cq_create_set_eq_id2_WORD      word4
1386                         uint32_t word5;
1387 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT     16
1388 #define lpfc_mbx_cq_create_set_eq_id5_MASK      0x0000FFFF
1389 #define lpfc_mbx_cq_create_set_eq_id5_WORD      word5
1390 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT     0
1391 #define lpfc_mbx_cq_create_set_eq_id4_MASK      0x0000FFFF
1392 #define lpfc_mbx_cq_create_set_eq_id4_WORD      word5
1393                         uint32_t word6;
1394 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT     16
1395 #define lpfc_mbx_cq_create_set_eq_id7_MASK      0x0000FFFF
1396 #define lpfc_mbx_cq_create_set_eq_id7_WORD      word6
1397 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT     0
1398 #define lpfc_mbx_cq_create_set_eq_id6_MASK      0x0000FFFF
1399 #define lpfc_mbx_cq_create_set_eq_id6_WORD      word6
1400                         uint32_t word7;
1401 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT     16
1402 #define lpfc_mbx_cq_create_set_eq_id9_MASK      0x0000FFFF
1403 #define lpfc_mbx_cq_create_set_eq_id9_WORD      word7
1404 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT     0
1405 #define lpfc_mbx_cq_create_set_eq_id8_MASK      0x0000FFFF
1406 #define lpfc_mbx_cq_create_set_eq_id8_WORD      word7
1407                         uint32_t word8;
1408 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT    16
1409 #define lpfc_mbx_cq_create_set_eq_id11_MASK     0x0000FFFF
1410 #define lpfc_mbx_cq_create_set_eq_id11_WORD     word8
1411 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT    0
1412 #define lpfc_mbx_cq_create_set_eq_id10_MASK     0x0000FFFF
1413 #define lpfc_mbx_cq_create_set_eq_id10_WORD     word8
1414                         uint32_t word9;
1415 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT    16
1416 #define lpfc_mbx_cq_create_set_eq_id13_MASK     0x0000FFFF
1417 #define lpfc_mbx_cq_create_set_eq_id13_WORD     word9
1418 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT    0
1419 #define lpfc_mbx_cq_create_set_eq_id12_MASK     0x0000FFFF
1420 #define lpfc_mbx_cq_create_set_eq_id12_WORD     word9
1421                         uint32_t word10;
1422 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT    16
1423 #define lpfc_mbx_cq_create_set_eq_id15_MASK     0x0000FFFF
1424 #define lpfc_mbx_cq_create_set_eq_id15_WORD     word10
1425 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT    0
1426 #define lpfc_mbx_cq_create_set_eq_id14_MASK     0x0000FFFF
1427 #define lpfc_mbx_cq_create_set_eq_id14_WORD     word10
1428                         struct dma_address page[1];
1429                 } request;
1430                 struct {
1431                         uint32_t word0;
1432 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT  16
1433 #define lpfc_mbx_cq_create_set_num_alloc_MASK   0x0000FFFF
1434 #define lpfc_mbx_cq_create_set_num_alloc_WORD   word0
1435 #define lpfc_mbx_cq_create_set_base_id_SHIFT    0
1436 #define lpfc_mbx_cq_create_set_base_id_MASK     0x0000FFFF
1437 #define lpfc_mbx_cq_create_set_base_id_WORD     word0
1438                 } response;
1439         } u;
1440 };
1441
1442 struct lpfc_mbx_cq_destroy {
1443         struct mbox_header header;
1444         union {
1445                 struct {
1446                         uint32_t word0;
1447 #define lpfc_mbx_cq_destroy_q_id_SHIFT  0
1448 #define lpfc_mbx_cq_destroy_q_id_MASK   0x0000FFFF
1449 #define lpfc_mbx_cq_destroy_q_id_WORD   word0
1450                 } request;
1451                 struct {
1452                         uint32_t word0;
1453                 } response;
1454         } u;
1455 };
1456
1457 struct wq_context {
1458         uint32_t reserved0;
1459         uint32_t reserved1;
1460         uint32_t reserved2;
1461         uint32_t reserved3;
1462 };
1463
1464 struct lpfc_mbx_wq_create {
1465         struct mbox_header header;
1466         union {
1467                 struct {        /* Version 0 Request */
1468                         uint32_t word0;
1469 #define lpfc_mbx_wq_create_num_pages_SHIFT      0
1470 #define lpfc_mbx_wq_create_num_pages_MASK       0x000000FF
1471 #define lpfc_mbx_wq_create_num_pages_WORD       word0
1472 #define lpfc_mbx_wq_create_dua_SHIFT            8
1473 #define lpfc_mbx_wq_create_dua_MASK             0x00000001
1474 #define lpfc_mbx_wq_create_dua_WORD             word0
1475 #define lpfc_mbx_wq_create_cq_id_SHIFT          16
1476 #define lpfc_mbx_wq_create_cq_id_MASK           0x0000FFFF
1477 #define lpfc_mbx_wq_create_cq_id_WORD           word0
1478                         struct dma_address page[LPFC_MAX_WQ_PAGE_V0];
1479                         uint32_t word9;
1480 #define lpfc_mbx_wq_create_bua_SHIFT            0
1481 #define lpfc_mbx_wq_create_bua_MASK             0x00000001
1482 #define lpfc_mbx_wq_create_bua_WORD             word9
1483 #define lpfc_mbx_wq_create_ulp_num_SHIFT        8
1484 #define lpfc_mbx_wq_create_ulp_num_MASK         0x000000FF
1485 #define lpfc_mbx_wq_create_ulp_num_WORD         word9
1486                 } request;
1487                 struct {        /* Version 1 Request */
1488                         uint32_t word0; /* Word 0 is the same as in v0 */
1489                         uint32_t word1;
1490 #define lpfc_mbx_wq_create_page_size_SHIFT      0
1491 #define lpfc_mbx_wq_create_page_size_MASK       0x000000FF
1492 #define lpfc_mbx_wq_create_page_size_WORD       word1
1493 #define LPFC_WQ_PAGE_SIZE_4096  0x1
1494 #define lpfc_mbx_wq_create_dpp_req_SHIFT        15
1495 #define lpfc_mbx_wq_create_dpp_req_MASK         0x00000001
1496 #define lpfc_mbx_wq_create_dpp_req_WORD         word1
1497 #define lpfc_mbx_wq_create_doe_SHIFT            14
1498 #define lpfc_mbx_wq_create_doe_MASK             0x00000001
1499 #define lpfc_mbx_wq_create_doe_WORD             word1
1500 #define lpfc_mbx_wq_create_toe_SHIFT            13
1501 #define lpfc_mbx_wq_create_toe_MASK             0x00000001
1502 #define lpfc_mbx_wq_create_toe_WORD             word1
1503 #define lpfc_mbx_wq_create_wqe_size_SHIFT       8
1504 #define lpfc_mbx_wq_create_wqe_size_MASK        0x0000000F
1505 #define lpfc_mbx_wq_create_wqe_size_WORD        word1
1506 #define LPFC_WQ_WQE_SIZE_64     0x5
1507 #define LPFC_WQ_WQE_SIZE_128    0x6
1508 #define lpfc_mbx_wq_create_wqe_count_SHIFT      16
1509 #define lpfc_mbx_wq_create_wqe_count_MASK       0x0000FFFF
1510 #define lpfc_mbx_wq_create_wqe_count_WORD       word1
1511                         uint32_t word2;
1512                         struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1513                 } request_1;
1514                 struct {
1515                         uint32_t word0;
1516 #define lpfc_mbx_wq_create_q_id_SHIFT   0
1517 #define lpfc_mbx_wq_create_q_id_MASK    0x0000FFFF
1518 #define lpfc_mbx_wq_create_q_id_WORD    word0
1519                         uint32_t doorbell_offset;
1520                         uint32_t word2;
1521 #define lpfc_mbx_wq_create_bar_set_SHIFT        0
1522 #define lpfc_mbx_wq_create_bar_set_MASK         0x0000FFFF
1523 #define lpfc_mbx_wq_create_bar_set_WORD         word2
1524 #define WQ_PCI_BAR_0_AND_1      0x00
1525 #define WQ_PCI_BAR_2_AND_3      0x01
1526 #define WQ_PCI_BAR_4_AND_5      0x02
1527 #define lpfc_mbx_wq_create_db_format_SHIFT      16
1528 #define lpfc_mbx_wq_create_db_format_MASK       0x0000FFFF
1529 #define lpfc_mbx_wq_create_db_format_WORD       word2
1530                 } response;
1531                 struct {
1532                         uint32_t word0;
1533 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT        31
1534 #define lpfc_mbx_wq_create_dpp_rsp_MASK         0x00000001
1535 #define lpfc_mbx_wq_create_dpp_rsp_WORD         word0
1536 #define lpfc_mbx_wq_create_v1_q_id_SHIFT        0
1537 #define lpfc_mbx_wq_create_v1_q_id_MASK         0x0000FFFF
1538 #define lpfc_mbx_wq_create_v1_q_id_WORD         word0
1539                         uint32_t word1;
1540 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT     0
1541 #define lpfc_mbx_wq_create_v1_bar_set_MASK      0x0000000F
1542 #define lpfc_mbx_wq_create_v1_bar_set_WORD      word1
1543                         uint32_t doorbell_offset;
1544                         uint32_t word3;
1545 #define lpfc_mbx_wq_create_dpp_id_SHIFT         16
1546 #define lpfc_mbx_wq_create_dpp_id_MASK          0x0000001F
1547 #define lpfc_mbx_wq_create_dpp_id_WORD          word3
1548 #define lpfc_mbx_wq_create_dpp_bar_SHIFT        0
1549 #define lpfc_mbx_wq_create_dpp_bar_MASK         0x0000000F
1550 #define lpfc_mbx_wq_create_dpp_bar_WORD         word3
1551                         uint32_t dpp_offset;
1552                 } response_1;
1553         } u;
1554 };
1555
1556 struct lpfc_mbx_wq_destroy {
1557         struct mbox_header header;
1558         union {
1559                 struct {
1560                         uint32_t word0;
1561 #define lpfc_mbx_wq_destroy_q_id_SHIFT  0
1562 #define lpfc_mbx_wq_destroy_q_id_MASK   0x0000FFFF
1563 #define lpfc_mbx_wq_destroy_q_id_WORD   word0
1564                 } request;
1565                 struct {
1566                         uint32_t word0;
1567                 } response;
1568         } u;
1569 };
1570
1571 #define LPFC_HDR_BUF_SIZE 128
1572 #define LPFC_DATA_BUF_SIZE 2048
1573 #define LPFC_NVMET_DATA_BUF_SIZE 128
1574 struct rq_context {
1575         uint32_t word0;
1576 #define lpfc_rq_context_rqe_count_SHIFT 16      /* Version 0 Only */
1577 #define lpfc_rq_context_rqe_count_MASK  0x0000000F
1578 #define lpfc_rq_context_rqe_count_WORD  word0
1579 #define LPFC_RQ_RING_SIZE_512           9       /* 512 entries */
1580 #define LPFC_RQ_RING_SIZE_1024          10      /* 1024 entries */
1581 #define LPFC_RQ_RING_SIZE_2048          11      /* 2048 entries */
1582 #define LPFC_RQ_RING_SIZE_4096          12      /* 4096 entries */
1583 #define lpfc_rq_context_rqe_count_1_SHIFT       16      /* Version 1-2 Only */
1584 #define lpfc_rq_context_rqe_count_1_MASK        0x0000FFFF
1585 #define lpfc_rq_context_rqe_count_1_WORD        word0
1586 #define lpfc_rq_context_rqe_size_SHIFT  8               /* Version 1-2 Only */
1587 #define lpfc_rq_context_rqe_size_MASK   0x0000000F
1588 #define lpfc_rq_context_rqe_size_WORD   word0
1589 #define LPFC_RQE_SIZE_8         2
1590 #define LPFC_RQE_SIZE_16        3
1591 #define LPFC_RQE_SIZE_32        4
1592 #define LPFC_RQE_SIZE_64        5
1593 #define LPFC_RQE_SIZE_128       6
1594 #define lpfc_rq_context_page_size_SHIFT 0               /* Version 1 Only */
1595 #define lpfc_rq_context_page_size_MASK  0x000000FF
1596 #define lpfc_rq_context_page_size_WORD  word0
1597 #define LPFC_RQ_PAGE_SIZE_4096  0x1
1598         uint32_t word1;
1599 #define lpfc_rq_context_data_size_SHIFT 16              /* Version 2 Only */
1600 #define lpfc_rq_context_data_size_MASK  0x0000FFFF
1601 #define lpfc_rq_context_data_size_WORD  word1
1602 #define lpfc_rq_context_hdr_size_SHIFT  0               /* Version 2 Only */
1603 #define lpfc_rq_context_hdr_size_MASK   0x0000FFFF
1604 #define lpfc_rq_context_hdr_size_WORD   word1
1605         uint32_t word2;
1606 #define lpfc_rq_context_cq_id_SHIFT     16
1607 #define lpfc_rq_context_cq_id_MASK      0x0000FFFF
1608 #define lpfc_rq_context_cq_id_WORD      word2
1609 #define lpfc_rq_context_buf_size_SHIFT  0
1610 #define lpfc_rq_context_buf_size_MASK   0x0000FFFF
1611 #define lpfc_rq_context_buf_size_WORD   word2
1612 #define lpfc_rq_context_base_cq_SHIFT   0               /* Version 2 Only */
1613 #define lpfc_rq_context_base_cq_MASK    0x0000FFFF
1614 #define lpfc_rq_context_base_cq_WORD    word2
1615         uint32_t buffer_size;                           /* Version 1 Only */
1616 };
1617
1618 struct lpfc_mbx_rq_create {
1619         struct mbox_header header;
1620         union {
1621                 struct {
1622                         uint32_t word0;
1623 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1624 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1625 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1626 #define lpfc_mbx_rq_create_dua_SHIFT            16
1627 #define lpfc_mbx_rq_create_dua_MASK             0x00000001
1628 #define lpfc_mbx_rq_create_dua_WORD             word0
1629 #define lpfc_mbx_rq_create_bqu_SHIFT            17
1630 #define lpfc_mbx_rq_create_bqu_MASK             0x00000001
1631 #define lpfc_mbx_rq_create_bqu_WORD             word0
1632 #define lpfc_mbx_rq_create_ulp_num_SHIFT        24
1633 #define lpfc_mbx_rq_create_ulp_num_MASK         0x000000FF
1634 #define lpfc_mbx_rq_create_ulp_num_WORD         word0
1635                         struct rq_context context;
1636                         struct dma_address page[LPFC_MAX_RQ_PAGE];
1637                 } request;
1638                 struct {
1639                         uint32_t word0;
1640 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT       16
1641 #define lpfc_mbx_rq_create_q_cnt_v2_MASK        0x0000FFFF
1642 #define lpfc_mbx_rq_create_q_cnt_v2_WORD        word0
1643 #define lpfc_mbx_rq_create_q_id_SHIFT           0
1644 #define lpfc_mbx_rq_create_q_id_MASK            0x0000FFFF
1645 #define lpfc_mbx_rq_create_q_id_WORD            word0
1646                         uint32_t doorbell_offset;
1647                         uint32_t word2;
1648 #define lpfc_mbx_rq_create_bar_set_SHIFT        0
1649 #define lpfc_mbx_rq_create_bar_set_MASK         0x0000FFFF
1650 #define lpfc_mbx_rq_create_bar_set_WORD         word2
1651 #define lpfc_mbx_rq_create_db_format_SHIFT      16
1652 #define lpfc_mbx_rq_create_db_format_MASK       0x0000FFFF
1653 #define lpfc_mbx_rq_create_db_format_WORD       word2
1654                 } response;
1655         } u;
1656 };
1657
1658 struct lpfc_mbx_rq_create_v2 {
1659         union  lpfc_sli4_cfg_shdr cfg_shdr;
1660         union {
1661                 struct {
1662                         uint32_t word0;
1663 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1664 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1665 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1666 #define lpfc_mbx_rq_create_rq_cnt_SHIFT         16
1667 #define lpfc_mbx_rq_create_rq_cnt_MASK          0x000000FF
1668 #define lpfc_mbx_rq_create_rq_cnt_WORD          word0
1669 #define lpfc_mbx_rq_create_dua_SHIFT            16
1670 #define lpfc_mbx_rq_create_dua_MASK             0x00000001
1671 #define lpfc_mbx_rq_create_dua_WORD             word0
1672 #define lpfc_mbx_rq_create_bqu_SHIFT            17
1673 #define lpfc_mbx_rq_create_bqu_MASK             0x00000001
1674 #define lpfc_mbx_rq_create_bqu_WORD             word0
1675 #define lpfc_mbx_rq_create_ulp_num_SHIFT        24
1676 #define lpfc_mbx_rq_create_ulp_num_MASK         0x000000FF
1677 #define lpfc_mbx_rq_create_ulp_num_WORD         word0
1678 #define lpfc_mbx_rq_create_dim_SHIFT            29
1679 #define lpfc_mbx_rq_create_dim_MASK             0x00000001
1680 #define lpfc_mbx_rq_create_dim_WORD             word0
1681 #define lpfc_mbx_rq_create_dfd_SHIFT            30
1682 #define lpfc_mbx_rq_create_dfd_MASK             0x00000001
1683 #define lpfc_mbx_rq_create_dfd_WORD             word0
1684 #define lpfc_mbx_rq_create_dnb_SHIFT            31
1685 #define lpfc_mbx_rq_create_dnb_MASK             0x00000001
1686 #define lpfc_mbx_rq_create_dnb_WORD             word0
1687                         struct rq_context context;
1688                         struct dma_address page[1];
1689                 } request;
1690                 struct {
1691                         uint32_t word0;
1692 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT       16
1693 #define lpfc_mbx_rq_create_q_cnt_v2_MASK        0x0000FFFF
1694 #define lpfc_mbx_rq_create_q_cnt_v2_WORD        word0
1695 #define lpfc_mbx_rq_create_q_id_SHIFT           0
1696 #define lpfc_mbx_rq_create_q_id_MASK            0x0000FFFF
1697 #define lpfc_mbx_rq_create_q_id_WORD            word0
1698                         uint32_t doorbell_offset;
1699                         uint32_t word2;
1700 #define lpfc_mbx_rq_create_bar_set_SHIFT        0
1701 #define lpfc_mbx_rq_create_bar_set_MASK         0x0000FFFF
1702 #define lpfc_mbx_rq_create_bar_set_WORD         word2
1703 #define lpfc_mbx_rq_create_db_format_SHIFT      16
1704 #define lpfc_mbx_rq_create_db_format_MASK       0x0000FFFF
1705 #define lpfc_mbx_rq_create_db_format_WORD       word2
1706                 } response;
1707         } u;
1708 };
1709
1710 struct lpfc_mbx_rq_destroy {
1711         struct mbox_header header;
1712         union {
1713                 struct {
1714                         uint32_t word0;
1715 #define lpfc_mbx_rq_destroy_q_id_SHIFT  0
1716 #define lpfc_mbx_rq_destroy_q_id_MASK   0x0000FFFF
1717 #define lpfc_mbx_rq_destroy_q_id_WORD   word0
1718                 } request;
1719                 struct {
1720                         uint32_t word0;
1721                 } response;
1722         } u;
1723 };
1724
1725 struct mq_context {
1726         uint32_t word0;
1727 #define lpfc_mq_context_cq_id_SHIFT     22      /* Version 0 Only */
1728 #define lpfc_mq_context_cq_id_MASK      0x000003FF
1729 #define lpfc_mq_context_cq_id_WORD      word0
1730 #define lpfc_mq_context_ring_size_SHIFT 16
1731 #define lpfc_mq_context_ring_size_MASK  0x0000000F
1732 #define lpfc_mq_context_ring_size_WORD  word0
1733 #define LPFC_MQ_RING_SIZE_16            0x5
1734 #define LPFC_MQ_RING_SIZE_32            0x6
1735 #define LPFC_MQ_RING_SIZE_64            0x7
1736 #define LPFC_MQ_RING_SIZE_128           0x8
1737         uint32_t word1;
1738 #define lpfc_mq_context_valid_SHIFT     31
1739 #define lpfc_mq_context_valid_MASK      0x00000001
1740 #define lpfc_mq_context_valid_WORD      word1
1741         uint32_t reserved2;
1742         uint32_t reserved3;
1743 };
1744
1745 struct lpfc_mbx_mq_create {
1746         struct mbox_header header;
1747         union {
1748                 struct {
1749                         uint32_t word0;
1750 #define lpfc_mbx_mq_create_num_pages_SHIFT      0
1751 #define lpfc_mbx_mq_create_num_pages_MASK       0x0000FFFF
1752 #define lpfc_mbx_mq_create_num_pages_WORD       word0
1753                         struct mq_context context;
1754                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1755                 } request;
1756                 struct {
1757                         uint32_t word0;
1758 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1759 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1760 #define lpfc_mbx_mq_create_q_id_WORD    word0
1761                 } response;
1762         } u;
1763 };
1764
1765 struct lpfc_mbx_mq_create_ext {
1766         struct mbox_header header;
1767         union {
1768                 struct {
1769                         uint32_t word0;
1770 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT  0
1771 #define lpfc_mbx_mq_create_ext_num_pages_MASK   0x0000FFFF
1772 #define lpfc_mbx_mq_create_ext_num_pages_WORD   word0
1773 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT      16      /* Version 1 Only */
1774 #define lpfc_mbx_mq_create_ext_cq_id_MASK       0x0000FFFF
1775 #define lpfc_mbx_mq_create_ext_cq_id_WORD       word0
1776                         uint32_t async_evt_bmap;
1777 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT     LPFC_TRAILER_CODE_LINK
1778 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK      0x00000001
1779 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD      async_evt_bmap
1780 #define LPFC_EVT_CODE_LINK_NO_LINK      0x0
1781 #define LPFC_EVT_CODE_LINK_10_MBIT      0x1
1782 #define LPFC_EVT_CODE_LINK_100_MBIT     0x2
1783 #define LPFC_EVT_CODE_LINK_1_GBIT       0x3
1784 #define LPFC_EVT_CODE_LINK_10_GBIT      0x4
1785 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT      LPFC_TRAILER_CODE_FCOE
1786 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK       0x00000001
1787 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD       async_evt_bmap
1788 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT   LPFC_TRAILER_CODE_GRP5
1789 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK    0x00000001
1790 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD    async_evt_bmap
1791 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT       LPFC_TRAILER_CODE_FC
1792 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK        0x00000001
1793 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD        async_evt_bmap
1794 #define LPFC_EVT_CODE_FC_NO_LINK        0x0
1795 #define LPFC_EVT_CODE_FC_1_GBAUD        0x1
1796 #define LPFC_EVT_CODE_FC_2_GBAUD        0x2
1797 #define LPFC_EVT_CODE_FC_4_GBAUD        0x4
1798 #define LPFC_EVT_CODE_FC_8_GBAUD        0x8
1799 #define LPFC_EVT_CODE_FC_10_GBAUD       0xA
1800 #define LPFC_EVT_CODE_FC_16_GBAUD       0x10
1801 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT      LPFC_TRAILER_CODE_SLI
1802 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK       0x00000001
1803 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD       async_evt_bmap
1804                         struct mq_context context;
1805                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1806                 } request;
1807                 struct {
1808                         uint32_t word0;
1809 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1810 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1811 #define lpfc_mbx_mq_create_q_id_WORD    word0
1812                 } response;
1813         } u;
1814 #define LPFC_ASYNC_EVENT_LINK_STATE     0x2
1815 #define LPFC_ASYNC_EVENT_FCF_STATE      0x4
1816 #define LPFC_ASYNC_EVENT_GROUP5         0x20
1817 };
1818
1819 struct lpfc_mbx_mq_destroy {
1820         struct mbox_header header;
1821         union {
1822                 struct {
1823                         uint32_t word0;
1824 #define lpfc_mbx_mq_destroy_q_id_SHIFT  0
1825 #define lpfc_mbx_mq_destroy_q_id_MASK   0x0000FFFF
1826 #define lpfc_mbx_mq_destroy_q_id_WORD   word0
1827                 } request;
1828                 struct {
1829                         uint32_t word0;
1830                 } response;
1831         } u;
1832 };
1833
1834 /* Start Gen 2 SLI4 Mailbox definitions: */
1835
1836 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1837 #define LPFC_RSC_TYPE_FCOE_VFI  0x20
1838 #define LPFC_RSC_TYPE_FCOE_VPI  0x21
1839 #define LPFC_RSC_TYPE_FCOE_RPI  0x22
1840 #define LPFC_RSC_TYPE_FCOE_XRI  0x23
1841
1842 struct lpfc_mbx_get_rsrc_extent_info {
1843         struct mbox_header header;
1844         union {
1845                 struct {
1846                         uint32_t word4;
1847 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT        0
1848 #define lpfc_mbx_get_rsrc_extent_info_type_MASK         0x0000FFFF
1849 #define lpfc_mbx_get_rsrc_extent_info_type_WORD         word4
1850                 } req;
1851                 struct {
1852                         uint32_t word4;
1853 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT         0
1854 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK          0x0000FFFF
1855 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD          word4
1856 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT        16
1857 #define lpfc_mbx_get_rsrc_extent_info_size_MASK         0x0000FFFF
1858 #define lpfc_mbx_get_rsrc_extent_info_size_WORD         word4
1859                 } rsp;
1860         } u;
1861 };
1862
1863 struct lpfc_mbx_query_fw_config {
1864         struct mbox_header header;
1865         struct {
1866                 uint32_t config_number;
1867 #define LPFC_FC_FCOE            0x00000007
1868                 uint32_t asic_revision;
1869                 uint32_t physical_port;
1870                 uint32_t function_mode;
1871 #define LPFC_FCOE_INI_MODE      0x00000040
1872 #define LPFC_FCOE_TGT_MODE      0x00000080
1873 #define LPFC_DUA_MODE           0x00000800
1874                 uint32_t ulp0_mode;
1875 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1876 #define LPFC_ULP_FCOE_TGT_MODE  0x00000080
1877                 uint32_t ulp0_nap_words[12];
1878                 uint32_t ulp1_mode;
1879                 uint32_t ulp1_nap_words[12];
1880                 uint32_t function_capabilities;
1881                 uint32_t cqid_base;
1882                 uint32_t cqid_tot;
1883                 uint32_t eqid_base;
1884                 uint32_t eqid_tot;
1885                 uint32_t ulp0_nap2_words[2];
1886                 uint32_t ulp1_nap2_words[2];
1887         } rsp;
1888 };
1889
1890 struct lpfc_mbx_set_beacon_config {
1891         struct mbox_header header;
1892         uint32_t word4;
1893 #define lpfc_mbx_set_beacon_port_num_SHIFT              0
1894 #define lpfc_mbx_set_beacon_port_num_MASK               0x0000003F
1895 #define lpfc_mbx_set_beacon_port_num_WORD               word4
1896 #define lpfc_mbx_set_beacon_port_type_SHIFT             6
1897 #define lpfc_mbx_set_beacon_port_type_MASK              0x00000003
1898 #define lpfc_mbx_set_beacon_port_type_WORD              word4
1899 #define lpfc_mbx_set_beacon_state_SHIFT                 8
1900 #define lpfc_mbx_set_beacon_state_MASK                  0x000000FF
1901 #define lpfc_mbx_set_beacon_state_WORD                  word4
1902 #define lpfc_mbx_set_beacon_duration_SHIFT              16
1903 #define lpfc_mbx_set_beacon_duration_MASK               0x000000FF
1904 #define lpfc_mbx_set_beacon_duration_WORD               word4
1905
1906 /* COMMON_SET_BEACON_CONFIG_V1 */
1907 #define lpfc_mbx_set_beacon_duration_v1_SHIFT           16
1908 #define lpfc_mbx_set_beacon_duration_v1_MASK            0x0000FFFF
1909 #define lpfc_mbx_set_beacon_duration_v1_WORD            word4
1910         uint32_t word5;  /* RESERVED  */
1911 };
1912
1913 struct lpfc_id_range {
1914         uint32_t word5;
1915 #define lpfc_mbx_rsrc_id_word4_0_SHIFT  0
1916 #define lpfc_mbx_rsrc_id_word4_0_MASK   0x0000FFFF
1917 #define lpfc_mbx_rsrc_id_word4_0_WORD   word5
1918 #define lpfc_mbx_rsrc_id_word4_1_SHIFT  16
1919 #define lpfc_mbx_rsrc_id_word4_1_MASK   0x0000FFFF
1920 #define lpfc_mbx_rsrc_id_word4_1_WORD   word5
1921 };
1922
1923 struct lpfc_mbx_set_link_diag_state {
1924         struct mbox_header header;
1925         union {
1926                 struct {
1927                         uint32_t word0;
1928 #define lpfc_mbx_set_diag_state_diag_SHIFT      0
1929 #define lpfc_mbx_set_diag_state_diag_MASK       0x00000001
1930 #define lpfc_mbx_set_diag_state_diag_WORD       word0
1931 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT    2
1932 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK     0x00000001
1933 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD     word0
1934 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE        0
1935 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE           1
1936 #define lpfc_mbx_set_diag_state_link_num_SHIFT  16
1937 #define lpfc_mbx_set_diag_state_link_num_MASK   0x0000003F
1938 #define lpfc_mbx_set_diag_state_link_num_WORD   word0
1939 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1940 #define lpfc_mbx_set_diag_state_link_type_MASK  0x00000003
1941 #define lpfc_mbx_set_diag_state_link_type_WORD  word0
1942                 } req;
1943                 struct {
1944                         uint32_t word0;
1945                 } rsp;
1946         } u;
1947 };
1948
1949 struct lpfc_mbx_set_link_diag_loopback {
1950         struct mbox_header header;
1951         union {
1952                 struct {
1953                         uint32_t word0;
1954 #define lpfc_mbx_set_diag_lpbk_type_SHIFT               0
1955 #define lpfc_mbx_set_diag_lpbk_type_MASK                0x00000003
1956 #define lpfc_mbx_set_diag_lpbk_type_WORD                word0
1957 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE                 0x0
1958 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL                0x1
1959 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES                  0x2
1960 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED        0x3
1961 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT           16
1962 #define lpfc_mbx_set_diag_lpbk_link_num_MASK            0x0000003F
1963 #define lpfc_mbx_set_diag_lpbk_link_num_WORD            word0
1964 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT          22
1965 #define lpfc_mbx_set_diag_lpbk_link_type_MASK           0x00000003
1966 #define lpfc_mbx_set_diag_lpbk_link_type_WORD           word0
1967                 } req;
1968                 struct {
1969                         uint32_t word0;
1970                 } rsp;
1971         } u;
1972 };
1973
1974 struct lpfc_mbx_run_link_diag_test {
1975         struct mbox_header header;
1976         union {
1977                 struct {
1978                         uint32_t word0;
1979 #define lpfc_mbx_run_diag_test_link_num_SHIFT   16
1980 #define lpfc_mbx_run_diag_test_link_num_MASK    0x0000003F
1981 #define lpfc_mbx_run_diag_test_link_num_WORD    word0
1982 #define lpfc_mbx_run_diag_test_link_type_SHIFT  22
1983 #define lpfc_mbx_run_diag_test_link_type_MASK   0x00000003
1984 #define lpfc_mbx_run_diag_test_link_type_WORD   word0
1985                         uint32_t word1;
1986 #define lpfc_mbx_run_diag_test_test_id_SHIFT    0
1987 #define lpfc_mbx_run_diag_test_test_id_MASK     0x0000FFFF
1988 #define lpfc_mbx_run_diag_test_test_id_WORD     word1
1989 #define lpfc_mbx_run_diag_test_loops_SHIFT      16
1990 #define lpfc_mbx_run_diag_test_loops_MASK       0x0000FFFF
1991 #define lpfc_mbx_run_diag_test_loops_WORD       word1
1992                         uint32_t word2;
1993 #define lpfc_mbx_run_diag_test_test_ver_SHIFT   0
1994 #define lpfc_mbx_run_diag_test_test_ver_MASK    0x0000FFFF
1995 #define lpfc_mbx_run_diag_test_test_ver_WORD    word2
1996 #define lpfc_mbx_run_diag_test_err_act_SHIFT    16
1997 #define lpfc_mbx_run_diag_test_err_act_MASK     0x000000FF
1998 #define lpfc_mbx_run_diag_test_err_act_WORD     word2
1999                 } req;
2000                 struct {
2001                         uint32_t word0;
2002                 } rsp;
2003         } u;
2004 };
2005
2006 /*
2007  * struct lpfc_mbx_alloc_rsrc_extents:
2008  * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
2009  * 6 words of header + 4 words of shared subcommand header +
2010  * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
2011  *
2012  * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
2013  * for extents payload.
2014  *
2015  * 212/2 (bytes per extent) = 106 extents.
2016  * 106/2 (extents per word) = 53 words.
2017  * lpfc_id_range id is statically size to 53.
2018  *
2019  * This mailbox definition is used for ALLOC or GET_ALLOCATED
2020  * extent ranges.  For ALLOC, the type and cnt are required.
2021  * For GET_ALLOCATED, only the type is required.
2022  */
2023 struct lpfc_mbx_alloc_rsrc_extents {
2024         struct mbox_header header;
2025         union {
2026                 struct {
2027                         uint32_t word4;
2028 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT  0
2029 #define lpfc_mbx_alloc_rsrc_extents_type_MASK   0x0000FFFF
2030 #define lpfc_mbx_alloc_rsrc_extents_type_WORD   word4
2031 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT   16
2032 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK    0x0000FFFF
2033 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD    word4
2034                 } req;
2035                 struct {
2036                         uint32_t word4;
2037 #define lpfc_mbx_rsrc_cnt_SHIFT 0
2038 #define lpfc_mbx_rsrc_cnt_MASK  0x0000FFFF
2039 #define lpfc_mbx_rsrc_cnt_WORD  word4
2040                         struct lpfc_id_range id[53];
2041                 } rsp;
2042         } u;
2043 };
2044
2045 /*
2046  * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
2047  * structure shares the same SHIFT/MASK/WORD defines provided in the
2048  * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
2049  * the structures defined above.  This non-embedded structure provides for the
2050  * maximum number of extents supported by the port.
2051  */
2052 struct lpfc_mbx_nembed_rsrc_extent {
2053         union  lpfc_sli4_cfg_shdr cfg_shdr;
2054         uint32_t word4;
2055         struct lpfc_id_range id;
2056 };
2057
2058 struct lpfc_mbx_dealloc_rsrc_extents {
2059         struct mbox_header header;
2060         struct {
2061                 uint32_t word4;
2062 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT        0
2063 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK         0x0000FFFF
2064 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD         word4
2065         } req;
2066
2067 };
2068
2069 /* Start SLI4 FCoE specific mbox structures. */
2070
2071 struct lpfc_mbx_post_hdr_tmpl {
2072         struct mbox_header header;
2073         uint32_t word10;
2074 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
2075 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
2076 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
2077 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
2078 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
2079 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
2080         uint32_t rpi_paddr_lo;
2081         uint32_t rpi_paddr_hi;
2082 };
2083
2084 struct sli4_sge {       /* SLI-4 */
2085         uint32_t addr_hi;
2086         uint32_t addr_lo;
2087
2088         uint32_t word2;
2089 #define lpfc_sli4_sge_offset_SHIFT      0
2090 #define lpfc_sli4_sge_offset_MASK       0x07FFFFFF
2091 #define lpfc_sli4_sge_offset_WORD       word2
2092 #define lpfc_sli4_sge_type_SHIFT        27
2093 #define lpfc_sli4_sge_type_MASK         0x0000000F
2094 #define lpfc_sli4_sge_type_WORD         word2
2095 #define LPFC_SGE_TYPE_DATA              0x0
2096 #define LPFC_SGE_TYPE_DIF               0x4
2097 #define LPFC_SGE_TYPE_LSP               0x5
2098 #define LPFC_SGE_TYPE_PEDIF             0x6
2099 #define LPFC_SGE_TYPE_PESEED            0x7
2100 #define LPFC_SGE_TYPE_DISEED            0x8
2101 #define LPFC_SGE_TYPE_ENC               0x9
2102 #define LPFC_SGE_TYPE_ATM               0xA
2103 #define LPFC_SGE_TYPE_SKIP              0xC
2104 #define lpfc_sli4_sge_last_SHIFT        31 /* Last SEG in the SGL sets it */
2105 #define lpfc_sli4_sge_last_MASK         0x00000001
2106 #define lpfc_sli4_sge_last_WORD         word2
2107         uint32_t sge_len;
2108 };
2109
2110 struct sli4_hybrid_sgl {
2111         struct list_head list_node;
2112         struct sli4_sge *dma_sgl;
2113         dma_addr_t dma_phys_sgl;
2114 };
2115
2116 struct fcp_cmd_rsp_buf {
2117         struct list_head list_node;
2118
2119         /* for storing cmd/rsp dma alloc'ed virt_addr */
2120         struct fcp_cmnd *fcp_cmnd;
2121         struct fcp_rsp *fcp_rsp;
2122
2123         /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */
2124         dma_addr_t fcp_cmd_rsp_dma_handle;
2125 };
2126
2127 struct sli4_sge_diseed {        /* SLI-4 */
2128         uint32_t ref_tag;
2129         uint32_t ref_tag_tran;
2130
2131         uint32_t word2;
2132 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
2133 #define lpfc_sli4_sge_dif_apptran_MASK  0x0000FFFF
2134 #define lpfc_sli4_sge_dif_apptran_WORD  word2
2135 #define lpfc_sli4_sge_dif_af_SHIFT      24
2136 #define lpfc_sli4_sge_dif_af_MASK       0x00000001
2137 #define lpfc_sli4_sge_dif_af_WORD       word2
2138 #define lpfc_sli4_sge_dif_na_SHIFT      25
2139 #define lpfc_sli4_sge_dif_na_MASK       0x00000001
2140 #define lpfc_sli4_sge_dif_na_WORD       word2
2141 #define lpfc_sli4_sge_dif_hi_SHIFT      26
2142 #define lpfc_sli4_sge_dif_hi_MASK       0x00000001
2143 #define lpfc_sli4_sge_dif_hi_WORD       word2
2144 #define lpfc_sli4_sge_dif_type_SHIFT    27
2145 #define lpfc_sli4_sge_dif_type_MASK     0x0000000F
2146 #define lpfc_sli4_sge_dif_type_WORD     word2
2147 #define lpfc_sli4_sge_dif_last_SHIFT    31 /* Last SEG in the SGL sets it */
2148 #define lpfc_sli4_sge_dif_last_MASK     0x00000001
2149 #define lpfc_sli4_sge_dif_last_WORD     word2
2150         uint32_t word3;
2151 #define lpfc_sli4_sge_dif_apptag_SHIFT  0
2152 #define lpfc_sli4_sge_dif_apptag_MASK   0x0000FFFF
2153 #define lpfc_sli4_sge_dif_apptag_WORD   word3
2154 #define lpfc_sli4_sge_dif_bs_SHIFT      16
2155 #define lpfc_sli4_sge_dif_bs_MASK       0x00000007
2156 #define lpfc_sli4_sge_dif_bs_WORD       word3
2157 #define lpfc_sli4_sge_dif_ai_SHIFT      19
2158 #define lpfc_sli4_sge_dif_ai_MASK       0x00000001
2159 #define lpfc_sli4_sge_dif_ai_WORD       word3
2160 #define lpfc_sli4_sge_dif_me_SHIFT      20
2161 #define lpfc_sli4_sge_dif_me_MASK       0x00000001
2162 #define lpfc_sli4_sge_dif_me_WORD       word3
2163 #define lpfc_sli4_sge_dif_re_SHIFT      21
2164 #define lpfc_sli4_sge_dif_re_MASK       0x00000001
2165 #define lpfc_sli4_sge_dif_re_WORD       word3
2166 #define lpfc_sli4_sge_dif_ce_SHIFT      22
2167 #define lpfc_sli4_sge_dif_ce_MASK       0x00000001
2168 #define lpfc_sli4_sge_dif_ce_WORD       word3
2169 #define lpfc_sli4_sge_dif_nr_SHIFT      23
2170 #define lpfc_sli4_sge_dif_nr_MASK       0x00000001
2171 #define lpfc_sli4_sge_dif_nr_WORD       word3
2172 #define lpfc_sli4_sge_dif_oprx_SHIFT    24
2173 #define lpfc_sli4_sge_dif_oprx_MASK     0x0000000F
2174 #define lpfc_sli4_sge_dif_oprx_WORD     word3
2175 #define lpfc_sli4_sge_dif_optx_SHIFT    28
2176 #define lpfc_sli4_sge_dif_optx_MASK     0x0000000F
2177 #define lpfc_sli4_sge_dif_optx_WORD     word3
2178 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
2179 };
2180
2181 struct fcf_record {
2182         uint32_t max_rcv_size;
2183         uint32_t fka_adv_period;
2184         uint32_t fip_priority;
2185         uint32_t word3;
2186 #define lpfc_fcf_record_mac_0_SHIFT             0
2187 #define lpfc_fcf_record_mac_0_MASK              0x000000FF
2188 #define lpfc_fcf_record_mac_0_WORD              word3
2189 #define lpfc_fcf_record_mac_1_SHIFT             8
2190 #define lpfc_fcf_record_mac_1_MASK              0x000000FF
2191 #define lpfc_fcf_record_mac_1_WORD              word3
2192 #define lpfc_fcf_record_mac_2_SHIFT             16
2193 #define lpfc_fcf_record_mac_2_MASK              0x000000FF
2194 #define lpfc_fcf_record_mac_2_WORD              word3
2195 #define lpfc_fcf_record_mac_3_SHIFT             24
2196 #define lpfc_fcf_record_mac_3_MASK              0x000000FF
2197 #define lpfc_fcf_record_mac_3_WORD              word3
2198         uint32_t word4;
2199 #define lpfc_fcf_record_mac_4_SHIFT             0
2200 #define lpfc_fcf_record_mac_4_MASK              0x000000FF
2201 #define lpfc_fcf_record_mac_4_WORD              word4
2202 #define lpfc_fcf_record_mac_5_SHIFT             8
2203 #define lpfc_fcf_record_mac_5_MASK              0x000000FF
2204 #define lpfc_fcf_record_mac_5_WORD              word4
2205 #define lpfc_fcf_record_fcf_avail_SHIFT         16
2206 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
2207 #define lpfc_fcf_record_fcf_avail_WORD          word4
2208 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
2209 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
2210 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
2211 #define LPFC_FCF_FPMA           1       /* Fabric Provided MAC Address */
2212 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
2213         uint32_t word5;
2214 #define lpfc_fcf_record_fab_name_0_SHIFT        0
2215 #define lpfc_fcf_record_fab_name_0_MASK         0x000000FF
2216 #define lpfc_fcf_record_fab_name_0_WORD         word5
2217 #define lpfc_fcf_record_fab_name_1_SHIFT        8
2218 #define lpfc_fcf_record_fab_name_1_MASK         0x000000FF
2219 #define lpfc_fcf_record_fab_name_1_WORD         word5
2220 #define lpfc_fcf_record_fab_name_2_SHIFT        16
2221 #define lpfc_fcf_record_fab_name_2_MASK         0x000000FF
2222 #define lpfc_fcf_record_fab_name_2_WORD         word5
2223 #define lpfc_fcf_record_fab_name_3_SHIFT        24
2224 #define lpfc_fcf_record_fab_name_3_MASK         0x000000FF
2225 #define lpfc_fcf_record_fab_name_3_WORD         word5
2226         uint32_t word6;
2227 #define lpfc_fcf_record_fab_name_4_SHIFT        0
2228 #define lpfc_fcf_record_fab_name_4_MASK         0x000000FF
2229 #define lpfc_fcf_record_fab_name_4_WORD         word6
2230 #define lpfc_fcf_record_fab_name_5_SHIFT        8
2231 #define lpfc_fcf_record_fab_name_5_MASK         0x000000FF
2232 #define lpfc_fcf_record_fab_name_5_WORD         word6
2233 #define lpfc_fcf_record_fab_name_6_SHIFT        16
2234 #define lpfc_fcf_record_fab_name_6_MASK         0x000000FF
2235 #define lpfc_fcf_record_fab_name_6_WORD         word6
2236 #define lpfc_fcf_record_fab_name_7_SHIFT        24
2237 #define lpfc_fcf_record_fab_name_7_MASK         0x000000FF
2238 #define lpfc_fcf_record_fab_name_7_WORD         word6
2239         uint32_t word7;
2240 #define lpfc_fcf_record_fc_map_0_SHIFT          0
2241 #define lpfc_fcf_record_fc_map_0_MASK           0x000000FF
2242 #define lpfc_fcf_record_fc_map_0_WORD           word7
2243 #define lpfc_fcf_record_fc_map_1_SHIFT          8
2244 #define lpfc_fcf_record_fc_map_1_MASK           0x000000FF
2245 #define lpfc_fcf_record_fc_map_1_WORD           word7
2246 #define lpfc_fcf_record_fc_map_2_SHIFT          16
2247 #define lpfc_fcf_record_fc_map_2_MASK           0x000000FF
2248 #define lpfc_fcf_record_fc_map_2_WORD           word7
2249 #define lpfc_fcf_record_fcf_valid_SHIFT         24
2250 #define lpfc_fcf_record_fcf_valid_MASK          0x00000001
2251 #define lpfc_fcf_record_fcf_valid_WORD          word7
2252 #define lpfc_fcf_record_fcf_fc_SHIFT            25
2253 #define lpfc_fcf_record_fcf_fc_MASK             0x00000001
2254 #define lpfc_fcf_record_fcf_fc_WORD             word7
2255 #define lpfc_fcf_record_fcf_sol_SHIFT           31
2256 #define lpfc_fcf_record_fcf_sol_MASK            0x00000001
2257 #define lpfc_fcf_record_fcf_sol_WORD            word7
2258         uint32_t word8;
2259 #define lpfc_fcf_record_fcf_index_SHIFT         0
2260 #define lpfc_fcf_record_fcf_index_MASK          0x0000FFFF
2261 #define lpfc_fcf_record_fcf_index_WORD          word8
2262 #define lpfc_fcf_record_fcf_state_SHIFT         16
2263 #define lpfc_fcf_record_fcf_state_MASK          0x0000FFFF
2264 #define lpfc_fcf_record_fcf_state_WORD          word8
2265         uint8_t vlan_bitmap[512];
2266         uint32_t word137;
2267 #define lpfc_fcf_record_switch_name_0_SHIFT     0
2268 #define lpfc_fcf_record_switch_name_0_MASK      0x000000FF
2269 #define lpfc_fcf_record_switch_name_0_WORD      word137
2270 #define lpfc_fcf_record_switch_name_1_SHIFT     8
2271 #define lpfc_fcf_record_switch_name_1_MASK      0x000000FF
2272 #define lpfc_fcf_record_switch_name_1_WORD      word137
2273 #define lpfc_fcf_record_switch_name_2_SHIFT     16
2274 #define lpfc_fcf_record_switch_name_2_MASK      0x000000FF
2275 #define lpfc_fcf_record_switch_name_2_WORD      word137
2276 #define lpfc_fcf_record_switch_name_3_SHIFT     24
2277 #define lpfc_fcf_record_switch_name_3_MASK      0x000000FF
2278 #define lpfc_fcf_record_switch_name_3_WORD      word137
2279         uint32_t word138;
2280 #define lpfc_fcf_record_switch_name_4_SHIFT     0
2281 #define lpfc_fcf_record_switch_name_4_MASK      0x000000FF
2282 #define lpfc_fcf_record_switch_name_4_WORD      word138
2283 #define lpfc_fcf_record_switch_name_5_SHIFT     8
2284 #define lpfc_fcf_record_switch_name_5_MASK      0x000000FF
2285 #define lpfc_fcf_record_switch_name_5_WORD      word138
2286 #define lpfc_fcf_record_switch_name_6_SHIFT     16
2287 #define lpfc_fcf_record_switch_name_6_MASK      0x000000FF
2288 #define lpfc_fcf_record_switch_name_6_WORD      word138
2289 #define lpfc_fcf_record_switch_name_7_SHIFT     24
2290 #define lpfc_fcf_record_switch_name_7_MASK      0x000000FF
2291 #define lpfc_fcf_record_switch_name_7_WORD      word138
2292 };
2293
2294 struct lpfc_mbx_read_fcf_tbl {
2295         union lpfc_sli4_cfg_shdr cfg_shdr;
2296         union {
2297                 struct {
2298                         uint32_t word10;
2299 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT        0
2300 #define lpfc_mbx_read_fcf_tbl_indx_MASK         0x0000FFFF
2301 #define lpfc_mbx_read_fcf_tbl_indx_WORD         word10
2302                 } request;
2303                 struct {
2304                         uint32_t eventag;
2305                 } response;
2306         } u;
2307         uint32_t word11;
2308 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT   0
2309 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK    0x0000FFFF
2310 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD    word11
2311 };
2312
2313 struct lpfc_mbx_add_fcf_tbl_entry {
2314         union lpfc_sli4_cfg_shdr cfg_shdr;
2315         uint32_t word10;
2316 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
2317 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
2318 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
2319         struct lpfc_mbx_sge fcf_sge;
2320 };
2321
2322 struct lpfc_mbx_del_fcf_tbl_entry {
2323         struct mbox_header header;
2324         uint32_t word10;
2325 #define lpfc_mbx_del_fcf_tbl_count_SHIFT        0
2326 #define lpfc_mbx_del_fcf_tbl_count_MASK         0x0000FFFF
2327 #define lpfc_mbx_del_fcf_tbl_count_WORD         word10
2328 #define lpfc_mbx_del_fcf_tbl_index_SHIFT        16
2329 #define lpfc_mbx_del_fcf_tbl_index_MASK         0x0000FFFF
2330 #define lpfc_mbx_del_fcf_tbl_index_WORD         word10
2331 };
2332
2333 struct lpfc_mbx_redisc_fcf_tbl {
2334         struct mbox_header header;
2335         uint32_t word10;
2336 #define lpfc_mbx_redisc_fcf_count_SHIFT         0
2337 #define lpfc_mbx_redisc_fcf_count_MASK          0x0000FFFF
2338 #define lpfc_mbx_redisc_fcf_count_WORD          word10
2339         uint32_t resvd;
2340         uint32_t word12;
2341 #define lpfc_mbx_redisc_fcf_index_SHIFT         0
2342 #define lpfc_mbx_redisc_fcf_index_MASK          0x0000FFFF
2343 #define lpfc_mbx_redisc_fcf_index_WORD          word12
2344 };
2345
2346 /* Status field for embedded SLI_CONFIG mailbox command */
2347 #define STATUS_SUCCESS                                  0x0
2348 #define STATUS_FAILED                                   0x1
2349 #define STATUS_ILLEGAL_REQUEST                          0x2
2350 #define STATUS_ILLEGAL_FIELD                            0x3
2351 #define STATUS_INSUFFICIENT_BUFFER                      0x4
2352 #define STATUS_UNAUTHORIZED_REQUEST                     0x5
2353 #define STATUS_FLASHROM_SAVE_FAILED                     0x17
2354 #define STATUS_FLASHROM_RESTORE_FAILED                  0x18
2355 #define STATUS_ICCBINDEX_ALLOC_FAILED                   0x1a
2356 #define STATUS_IOCTLHANDLE_ALLOC_FAILED                 0x1b
2357 #define STATUS_INVALID_PHY_ADDR_FROM_OSM                0x1c
2358 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM            0x1d
2359 #define STATUS_ASSERT_FAILED                            0x1e
2360 #define STATUS_INVALID_SESSION                          0x1f
2361 #define STATUS_INVALID_CONNECTION                       0x20
2362 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT               0x21
2363 #define STATUS_BTL_NO_FREE_SLOT_PATH                    0x24
2364 #define STATUS_BTL_NO_FREE_SLOT_TGTID                   0x25
2365 #define STATUS_OSM_DEVSLOT_NOT_FOUND                    0x26
2366 #define STATUS_FLASHROM_READ_FAILED                     0x27
2367 #define STATUS_POLL_IOCTL_TIMEOUT                       0x28
2368 #define STATUS_ERROR_ACITMAIN                           0x2a
2369 #define STATUS_REBOOT_REQUIRED                          0x2c
2370 #define STATUS_FCF_IN_USE                               0x3a
2371 #define STATUS_FCF_TABLE_EMPTY                          0x43
2372
2373 /*
2374  * Additional status field for embedded SLI_CONFIG mailbox
2375  * command.
2376  */
2377 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE             0x67
2378 #define ADD_STATUS_FW_NOT_SUPPORTED                     0xEB
2379 #define ADD_STATUS_INVALID_REQUEST                      0x4B
2380 #define ADD_STATUS_INVALID_OBJECT_NAME                  0xA0
2381 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED              0x58
2382
2383 struct lpfc_mbx_sli4_config {
2384         struct mbox_header header;
2385 };
2386
2387 struct lpfc_mbx_init_vfi {
2388         uint32_t word1;
2389 #define lpfc_init_vfi_vr_SHIFT          31
2390 #define lpfc_init_vfi_vr_MASK           0x00000001
2391 #define lpfc_init_vfi_vr_WORD           word1
2392 #define lpfc_init_vfi_vt_SHIFT          30
2393 #define lpfc_init_vfi_vt_MASK           0x00000001
2394 #define lpfc_init_vfi_vt_WORD           word1
2395 #define lpfc_init_vfi_vf_SHIFT          29
2396 #define lpfc_init_vfi_vf_MASK           0x00000001
2397 #define lpfc_init_vfi_vf_WORD           word1
2398 #define lpfc_init_vfi_vp_SHIFT          28
2399 #define lpfc_init_vfi_vp_MASK           0x00000001
2400 #define lpfc_init_vfi_vp_WORD           word1
2401 #define lpfc_init_vfi_vfi_SHIFT         0
2402 #define lpfc_init_vfi_vfi_MASK          0x0000FFFF
2403 #define lpfc_init_vfi_vfi_WORD          word1
2404         uint32_t word2;
2405 #define lpfc_init_vfi_vpi_SHIFT         16
2406 #define lpfc_init_vfi_vpi_MASK          0x0000FFFF
2407 #define lpfc_init_vfi_vpi_WORD          word2
2408 #define lpfc_init_vfi_fcfi_SHIFT        0
2409 #define lpfc_init_vfi_fcfi_MASK         0x0000FFFF
2410 #define lpfc_init_vfi_fcfi_WORD         word2
2411         uint32_t word3;
2412 #define lpfc_init_vfi_pri_SHIFT         13
2413 #define lpfc_init_vfi_pri_MASK          0x00000007
2414 #define lpfc_init_vfi_pri_WORD          word3
2415 #define lpfc_init_vfi_vf_id_SHIFT       1
2416 #define lpfc_init_vfi_vf_id_MASK        0x00000FFF
2417 #define lpfc_init_vfi_vf_id_WORD        word3
2418         uint32_t word4;
2419 #define lpfc_init_vfi_hop_count_SHIFT   24
2420 #define lpfc_init_vfi_hop_count_MASK    0x000000FF
2421 #define lpfc_init_vfi_hop_count_WORD    word4
2422 };
2423 #define MBX_VFI_IN_USE                  0x9F02
2424
2425
2426 struct lpfc_mbx_reg_vfi {
2427         uint32_t word1;
2428 #define lpfc_reg_vfi_upd_SHIFT          29
2429 #define lpfc_reg_vfi_upd_MASK           0x00000001
2430 #define lpfc_reg_vfi_upd_WORD           word1
2431 #define lpfc_reg_vfi_vp_SHIFT           28
2432 #define lpfc_reg_vfi_vp_MASK            0x00000001
2433 #define lpfc_reg_vfi_vp_WORD            word1
2434 #define lpfc_reg_vfi_vfi_SHIFT          0
2435 #define lpfc_reg_vfi_vfi_MASK           0x0000FFFF
2436 #define lpfc_reg_vfi_vfi_WORD           word1
2437         uint32_t word2;
2438 #define lpfc_reg_vfi_vpi_SHIFT          16
2439 #define lpfc_reg_vfi_vpi_MASK           0x0000FFFF
2440 #define lpfc_reg_vfi_vpi_WORD           word2
2441 #define lpfc_reg_vfi_fcfi_SHIFT         0
2442 #define lpfc_reg_vfi_fcfi_MASK          0x0000FFFF
2443 #define lpfc_reg_vfi_fcfi_WORD          word2
2444         uint32_t wwn[2];
2445         struct ulp_bde64 bde;
2446         uint32_t e_d_tov;
2447         uint32_t r_a_tov;
2448         uint32_t word10;
2449 #define lpfc_reg_vfi_nport_id_SHIFT     0
2450 #define lpfc_reg_vfi_nport_id_MASK      0x00FFFFFF
2451 #define lpfc_reg_vfi_nport_id_WORD      word10
2452 #define lpfc_reg_vfi_bbcr_SHIFT         27
2453 #define lpfc_reg_vfi_bbcr_MASK          0x00000001
2454 #define lpfc_reg_vfi_bbcr_WORD          word10
2455 #define lpfc_reg_vfi_bbscn_SHIFT        28
2456 #define lpfc_reg_vfi_bbscn_MASK         0x0000000F
2457 #define lpfc_reg_vfi_bbscn_WORD         word10
2458 };
2459
2460 struct lpfc_mbx_init_vpi {
2461         uint32_t word1;
2462 #define lpfc_init_vpi_vfi_SHIFT         16
2463 #define lpfc_init_vpi_vfi_MASK          0x0000FFFF
2464 #define lpfc_init_vpi_vfi_WORD          word1
2465 #define lpfc_init_vpi_vpi_SHIFT         0
2466 #define lpfc_init_vpi_vpi_MASK          0x0000FFFF
2467 #define lpfc_init_vpi_vpi_WORD          word1
2468 };
2469
2470 struct lpfc_mbx_read_vpi {
2471         uint32_t word1_rsvd;
2472         uint32_t word2;
2473 #define lpfc_mbx_read_vpi_vnportid_SHIFT        0
2474 #define lpfc_mbx_read_vpi_vnportid_MASK         0x00FFFFFF
2475 #define lpfc_mbx_read_vpi_vnportid_WORD         word2
2476         uint32_t word3_rsvd;
2477         uint32_t word4;
2478 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT        0
2479 #define lpfc_mbx_read_vpi_acq_alpa_MASK         0x000000FF
2480 #define lpfc_mbx_read_vpi_acq_alpa_WORD         word4
2481 #define lpfc_mbx_read_vpi_pb_SHIFT              15
2482 #define lpfc_mbx_read_vpi_pb_MASK               0x00000001
2483 #define lpfc_mbx_read_vpi_pb_WORD               word4
2484 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT       16
2485 #define lpfc_mbx_read_vpi_spec_alpa_MASK        0x000000FF
2486 #define lpfc_mbx_read_vpi_spec_alpa_WORD        word4
2487 #define lpfc_mbx_read_vpi_ns_SHIFT              30
2488 #define lpfc_mbx_read_vpi_ns_MASK               0x00000001
2489 #define lpfc_mbx_read_vpi_ns_WORD               word4
2490 #define lpfc_mbx_read_vpi_hl_SHIFT              31
2491 #define lpfc_mbx_read_vpi_hl_MASK               0x00000001
2492 #define lpfc_mbx_read_vpi_hl_WORD               word4
2493         uint32_t word5_rsvd;
2494         uint32_t word6;
2495 #define lpfc_mbx_read_vpi_vpi_SHIFT             0
2496 #define lpfc_mbx_read_vpi_vpi_MASK              0x0000FFFF
2497 #define lpfc_mbx_read_vpi_vpi_WORD              word6
2498         uint32_t word7;
2499 #define lpfc_mbx_read_vpi_mac_0_SHIFT           0
2500 #define lpfc_mbx_read_vpi_mac_0_MASK            0x000000FF
2501 #define lpfc_mbx_read_vpi_mac_0_WORD            word7
2502 #define lpfc_mbx_read_vpi_mac_1_SHIFT           8
2503 #define lpfc_mbx_read_vpi_mac_1_MASK            0x000000FF
2504 #define lpfc_mbx_read_vpi_mac_1_WORD            word7
2505 #define lpfc_mbx_read_vpi_mac_2_SHIFT           16
2506 #define lpfc_mbx_read_vpi_mac_2_MASK            0x000000FF
2507 #define lpfc_mbx_read_vpi_mac_2_WORD            word7
2508 #define lpfc_mbx_read_vpi_mac_3_SHIFT           24
2509 #define lpfc_mbx_read_vpi_mac_3_MASK            0x000000FF
2510 #define lpfc_mbx_read_vpi_mac_3_WORD            word7
2511         uint32_t word8;
2512 #define lpfc_mbx_read_vpi_mac_4_SHIFT           0
2513 #define lpfc_mbx_read_vpi_mac_4_MASK            0x000000FF
2514 #define lpfc_mbx_read_vpi_mac_4_WORD            word8
2515 #define lpfc_mbx_read_vpi_mac_5_SHIFT           8
2516 #define lpfc_mbx_read_vpi_mac_5_MASK            0x000000FF
2517 #define lpfc_mbx_read_vpi_mac_5_WORD            word8
2518 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT        16
2519 #define lpfc_mbx_read_vpi_vlan_tag_MASK         0x00000FFF
2520 #define lpfc_mbx_read_vpi_vlan_tag_WORD         word8
2521 #define lpfc_mbx_read_vpi_vv_SHIFT              28
2522 #define lpfc_mbx_read_vpi_vv_MASK               0x0000001
2523 #define lpfc_mbx_read_vpi_vv_WORD               word8
2524 };
2525
2526 struct lpfc_mbx_unreg_vfi {
2527         uint32_t word1_rsvd;
2528         uint32_t word2;
2529 #define lpfc_unreg_vfi_vfi_SHIFT        0
2530 #define lpfc_unreg_vfi_vfi_MASK         0x0000FFFF
2531 #define lpfc_unreg_vfi_vfi_WORD         word2
2532 };
2533
2534 struct lpfc_mbx_resume_rpi {
2535         uint32_t word1;
2536 #define lpfc_resume_rpi_index_SHIFT     0
2537 #define lpfc_resume_rpi_index_MASK      0x0000FFFF
2538 #define lpfc_resume_rpi_index_WORD      word1
2539 #define lpfc_resume_rpi_ii_SHIFT        30
2540 #define lpfc_resume_rpi_ii_MASK         0x00000003
2541 #define lpfc_resume_rpi_ii_WORD         word1
2542 #define RESUME_INDEX_RPI                0
2543 #define RESUME_INDEX_VPI                1
2544 #define RESUME_INDEX_VFI                2
2545 #define RESUME_INDEX_FCFI               3
2546         uint32_t event_tag;
2547 };
2548
2549 #define REG_FCF_INVALID_QID     0xFFFF
2550 struct lpfc_mbx_reg_fcfi {
2551         uint32_t word1;
2552 #define lpfc_reg_fcfi_info_index_SHIFT  0
2553 #define lpfc_reg_fcfi_info_index_MASK   0x0000FFFF
2554 #define lpfc_reg_fcfi_info_index_WORD   word1
2555 #define lpfc_reg_fcfi_fcfi_SHIFT        16
2556 #define lpfc_reg_fcfi_fcfi_MASK         0x0000FFFF
2557 #define lpfc_reg_fcfi_fcfi_WORD         word1
2558         uint32_t word2;
2559 #define lpfc_reg_fcfi_rq_id1_SHIFT      0
2560 #define lpfc_reg_fcfi_rq_id1_MASK       0x0000FFFF
2561 #define lpfc_reg_fcfi_rq_id1_WORD       word2
2562 #define lpfc_reg_fcfi_rq_id0_SHIFT      16
2563 #define lpfc_reg_fcfi_rq_id0_MASK       0x0000FFFF
2564 #define lpfc_reg_fcfi_rq_id0_WORD       word2
2565         uint32_t word3;
2566 #define lpfc_reg_fcfi_rq_id3_SHIFT      0
2567 #define lpfc_reg_fcfi_rq_id3_MASK       0x0000FFFF
2568 #define lpfc_reg_fcfi_rq_id3_WORD       word3
2569 #define lpfc_reg_fcfi_rq_id2_SHIFT      16
2570 #define lpfc_reg_fcfi_rq_id2_MASK       0x0000FFFF
2571 #define lpfc_reg_fcfi_rq_id2_WORD       word3
2572         uint32_t word4;
2573 #define lpfc_reg_fcfi_type_match0_SHIFT 24
2574 #define lpfc_reg_fcfi_type_match0_MASK  0x000000FF
2575 #define lpfc_reg_fcfi_type_match0_WORD  word4
2576 #define lpfc_reg_fcfi_type_mask0_SHIFT  16
2577 #define lpfc_reg_fcfi_type_mask0_MASK   0x000000FF
2578 #define lpfc_reg_fcfi_type_mask0_WORD   word4
2579 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2580 #define lpfc_reg_fcfi_rctl_match0_MASK  0x000000FF
2581 #define lpfc_reg_fcfi_rctl_match0_WORD  word4
2582 #define lpfc_reg_fcfi_rctl_mask0_SHIFT  0
2583 #define lpfc_reg_fcfi_rctl_mask0_MASK   0x000000FF
2584 #define lpfc_reg_fcfi_rctl_mask0_WORD   word4
2585         uint32_t word5;
2586 #define lpfc_reg_fcfi_type_match1_SHIFT 24
2587 #define lpfc_reg_fcfi_type_match1_MASK  0x000000FF
2588 #define lpfc_reg_fcfi_type_match1_WORD  word5
2589 #define lpfc_reg_fcfi_type_mask1_SHIFT  16
2590 #define lpfc_reg_fcfi_type_mask1_MASK   0x000000FF
2591 #define lpfc_reg_fcfi_type_mask1_WORD   word5
2592 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2593 #define lpfc_reg_fcfi_rctl_match1_MASK  0x000000FF
2594 #define lpfc_reg_fcfi_rctl_match1_WORD  word5
2595 #define lpfc_reg_fcfi_rctl_mask1_SHIFT  0
2596 #define lpfc_reg_fcfi_rctl_mask1_MASK   0x000000FF
2597 #define lpfc_reg_fcfi_rctl_mask1_WORD   word5
2598         uint32_t word6;
2599 #define lpfc_reg_fcfi_type_match2_SHIFT 24
2600 #define lpfc_reg_fcfi_type_match2_MASK  0x000000FF
2601 #define lpfc_reg_fcfi_type_match2_WORD  word6
2602 #define lpfc_reg_fcfi_type_mask2_SHIFT  16
2603 #define lpfc_reg_fcfi_type_mask2_MASK   0x000000FF
2604 #define lpfc_reg_fcfi_type_mask2_WORD   word6
2605 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2606 #define lpfc_reg_fcfi_rctl_match2_MASK  0x000000FF
2607 #define lpfc_reg_fcfi_rctl_match2_WORD  word6
2608 #define lpfc_reg_fcfi_rctl_mask2_SHIFT  0
2609 #define lpfc_reg_fcfi_rctl_mask2_MASK   0x000000FF
2610 #define lpfc_reg_fcfi_rctl_mask2_WORD   word6
2611         uint32_t word7;
2612 #define lpfc_reg_fcfi_type_match3_SHIFT 24
2613 #define lpfc_reg_fcfi_type_match3_MASK  0x000000FF
2614 #define lpfc_reg_fcfi_type_match3_WORD  word7
2615 #define lpfc_reg_fcfi_type_mask3_SHIFT  16
2616 #define lpfc_reg_fcfi_type_mask3_MASK   0x000000FF
2617 #define lpfc_reg_fcfi_type_mask3_WORD   word7
2618 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2619 #define lpfc_reg_fcfi_rctl_match3_MASK  0x000000FF
2620 #define lpfc_reg_fcfi_rctl_match3_WORD  word7
2621 #define lpfc_reg_fcfi_rctl_mask3_SHIFT  0
2622 #define lpfc_reg_fcfi_rctl_mask3_MASK   0x000000FF
2623 #define lpfc_reg_fcfi_rctl_mask3_WORD   word7
2624         uint32_t word8;
2625 #define lpfc_reg_fcfi_mam_SHIFT         13
2626 #define lpfc_reg_fcfi_mam_MASK          0x00000003
2627 #define lpfc_reg_fcfi_mam_WORD          word8
2628 #define LPFC_MAM_BOTH           0       /* Both SPMA and FPMA */
2629 #define LPFC_MAM_SPMA           1       /* Server Provided MAC Address */
2630 #define LPFC_MAM_FPMA           2       /* Fabric Provided MAC Address */
2631 #define lpfc_reg_fcfi_vv_SHIFT          12
2632 #define lpfc_reg_fcfi_vv_MASK           0x00000001
2633 #define lpfc_reg_fcfi_vv_WORD           word8
2634 #define lpfc_reg_fcfi_vlan_tag_SHIFT    0
2635 #define lpfc_reg_fcfi_vlan_tag_MASK     0x00000FFF
2636 #define lpfc_reg_fcfi_vlan_tag_WORD     word8
2637 };
2638
2639 struct lpfc_mbx_reg_fcfi_mrq {
2640         uint32_t word1;
2641 #define lpfc_reg_fcfi_mrq_info_index_SHIFT      0
2642 #define lpfc_reg_fcfi_mrq_info_index_MASK       0x0000FFFF
2643 #define lpfc_reg_fcfi_mrq_info_index_WORD       word1
2644 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT            16
2645 #define lpfc_reg_fcfi_mrq_fcfi_MASK             0x0000FFFF
2646 #define lpfc_reg_fcfi_mrq_fcfi_WORD             word1
2647         uint32_t word2;
2648 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT          0
2649 #define lpfc_reg_fcfi_mrq_rq_id1_MASK           0x0000FFFF
2650 #define lpfc_reg_fcfi_mrq_rq_id1_WORD           word2
2651 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT          16
2652 #define lpfc_reg_fcfi_mrq_rq_id0_MASK           0x0000FFFF
2653 #define lpfc_reg_fcfi_mrq_rq_id0_WORD           word2
2654         uint32_t word3;
2655 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT          0
2656 #define lpfc_reg_fcfi_mrq_rq_id3_MASK           0x0000FFFF
2657 #define lpfc_reg_fcfi_mrq_rq_id3_WORD           word3
2658 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT          16
2659 #define lpfc_reg_fcfi_mrq_rq_id2_MASK           0x0000FFFF
2660 #define lpfc_reg_fcfi_mrq_rq_id2_WORD           word3
2661         uint32_t word4;
2662 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT     24
2663 #define lpfc_reg_fcfi_mrq_type_match0_MASK      0x000000FF
2664 #define lpfc_reg_fcfi_mrq_type_match0_WORD      word4
2665 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT      16
2666 #define lpfc_reg_fcfi_mrq_type_mask0_MASK       0x000000FF
2667 #define lpfc_reg_fcfi_mrq_type_mask0_WORD       word4
2668 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT     8
2669 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK      0x000000FF
2670 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD      word4
2671 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT      0
2672 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK       0x000000FF
2673 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD       word4
2674         uint32_t word5;
2675 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT     24
2676 #define lpfc_reg_fcfi_mrq_type_match1_MASK      0x000000FF
2677 #define lpfc_reg_fcfi_mrq_type_match1_WORD      word5
2678 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT      16
2679 #define lpfc_reg_fcfi_mrq_type_mask1_MASK       0x000000FF
2680 #define lpfc_reg_fcfi_mrq_type_mask1_WORD       word5
2681 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT     8
2682 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK      0x000000FF
2683 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD      word5
2684 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT      0
2685 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK       0x000000FF
2686 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD       word5
2687         uint32_t word6;
2688 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT     24
2689 #define lpfc_reg_fcfi_mrq_type_match2_MASK      0x000000FF
2690 #define lpfc_reg_fcfi_mrq_type_match2_WORD      word6
2691 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT      16
2692 #define lpfc_reg_fcfi_mrq_type_mask2_MASK       0x000000FF
2693 #define lpfc_reg_fcfi_mrq_type_mask2_WORD       word6
2694 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT     8
2695 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK      0x000000FF
2696 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD      word6
2697 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT      0
2698 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK       0x000000FF
2699 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD       word6
2700         uint32_t word7;
2701 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT     24
2702 #define lpfc_reg_fcfi_mrq_type_match3_MASK      0x000000FF
2703 #define lpfc_reg_fcfi_mrq_type_match3_WORD      word7
2704 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT      16
2705 #define lpfc_reg_fcfi_mrq_type_mask3_MASK       0x000000FF
2706 #define lpfc_reg_fcfi_mrq_type_mask3_WORD       word7
2707 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT     8
2708 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK      0x000000FF
2709 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD      word7
2710 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT      0
2711 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK       0x000000FF
2712 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD       word7
2713         uint32_t word8;
2714 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT            31
2715 #define lpfc_reg_fcfi_mrq_ptc7_MASK             0x00000001
2716 #define lpfc_reg_fcfi_mrq_ptc7_WORD             word8
2717 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT            30
2718 #define lpfc_reg_fcfi_mrq_ptc6_MASK             0x00000001
2719 #define lpfc_reg_fcfi_mrq_ptc6_WORD             word8
2720 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT            29
2721 #define lpfc_reg_fcfi_mrq_ptc5_MASK             0x00000001
2722 #define lpfc_reg_fcfi_mrq_ptc5_WORD             word8
2723 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT            28
2724 #define lpfc_reg_fcfi_mrq_ptc4_MASK             0x00000001
2725 #define lpfc_reg_fcfi_mrq_ptc4_WORD             word8
2726 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT            27
2727 #define lpfc_reg_fcfi_mrq_ptc3_MASK             0x00000001
2728 #define lpfc_reg_fcfi_mrq_ptc3_WORD             word8
2729 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT            26
2730 #define lpfc_reg_fcfi_mrq_ptc2_MASK             0x00000001
2731 #define lpfc_reg_fcfi_mrq_ptc2_WORD             word8
2732 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT            25
2733 #define lpfc_reg_fcfi_mrq_ptc1_MASK             0x00000001
2734 #define lpfc_reg_fcfi_mrq_ptc1_WORD             word8
2735 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT            24
2736 #define lpfc_reg_fcfi_mrq_ptc0_MASK             0x00000001
2737 #define lpfc_reg_fcfi_mrq_ptc0_WORD             word8
2738 #define lpfc_reg_fcfi_mrq_pt7_SHIFT             23
2739 #define lpfc_reg_fcfi_mrq_pt7_MASK              0x00000001
2740 #define lpfc_reg_fcfi_mrq_pt7_WORD              word8
2741 #define lpfc_reg_fcfi_mrq_pt6_SHIFT             22
2742 #define lpfc_reg_fcfi_mrq_pt6_MASK              0x00000001
2743 #define lpfc_reg_fcfi_mrq_pt6_WORD              word8
2744 #define lpfc_reg_fcfi_mrq_pt5_SHIFT             21
2745 #define lpfc_reg_fcfi_mrq_pt5_MASK              0x00000001
2746 #define lpfc_reg_fcfi_mrq_pt5_WORD              word8
2747 #define lpfc_reg_fcfi_mrq_pt4_SHIFT             20
2748 #define lpfc_reg_fcfi_mrq_pt4_MASK              0x00000001
2749 #define lpfc_reg_fcfi_mrq_pt4_WORD              word8
2750 #define lpfc_reg_fcfi_mrq_pt3_SHIFT             19
2751 #define lpfc_reg_fcfi_mrq_pt3_MASK              0x00000001
2752 #define lpfc_reg_fcfi_mrq_pt3_WORD              word8
2753 #define lpfc_reg_fcfi_mrq_pt2_SHIFT             18
2754 #define lpfc_reg_fcfi_mrq_pt2_MASK              0x00000001
2755 #define lpfc_reg_fcfi_mrq_pt2_WORD              word8
2756 #define lpfc_reg_fcfi_mrq_pt1_SHIFT             17
2757 #define lpfc_reg_fcfi_mrq_pt1_MASK              0x00000001
2758 #define lpfc_reg_fcfi_mrq_pt1_WORD              word8
2759 #define lpfc_reg_fcfi_mrq_pt0_SHIFT             16
2760 #define lpfc_reg_fcfi_mrq_pt0_MASK              0x00000001
2761 #define lpfc_reg_fcfi_mrq_pt0_WORD              word8
2762 #define lpfc_reg_fcfi_mrq_xmv_SHIFT             15
2763 #define lpfc_reg_fcfi_mrq_xmv_MASK              0x00000001
2764 #define lpfc_reg_fcfi_mrq_xmv_WORD              word8
2765 #define lpfc_reg_fcfi_mrq_mode_SHIFT            13
2766 #define lpfc_reg_fcfi_mrq_mode_MASK             0x00000001
2767 #define lpfc_reg_fcfi_mrq_mode_WORD             word8
2768 #define lpfc_reg_fcfi_mrq_vv_SHIFT              12
2769 #define lpfc_reg_fcfi_mrq_vv_MASK               0x00000001
2770 #define lpfc_reg_fcfi_mrq_vv_WORD               word8
2771 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT        0
2772 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK         0x00000FFF
2773 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD         word8
2774         uint32_t word9;
2775 #define lpfc_reg_fcfi_mrq_policy_SHIFT          12
2776 #define lpfc_reg_fcfi_mrq_policy_MASK           0x0000000F
2777 #define lpfc_reg_fcfi_mrq_policy_WORD           word9
2778 #define lpfc_reg_fcfi_mrq_filter_SHIFT          8
2779 #define lpfc_reg_fcfi_mrq_filter_MASK           0x0000000F
2780 #define lpfc_reg_fcfi_mrq_filter_WORD           word9
2781 #define lpfc_reg_fcfi_mrq_npairs_SHIFT          0
2782 #define lpfc_reg_fcfi_mrq_npairs_MASK           0x000000FF
2783 #define lpfc_reg_fcfi_mrq_npairs_WORD           word9
2784         uint32_t word10;
2785         uint32_t word11;
2786         uint32_t word12;
2787         uint32_t word13;
2788         uint32_t word14;
2789         uint32_t word15;
2790         uint32_t word16;
2791 };
2792
2793 struct lpfc_mbx_unreg_fcfi {
2794         uint32_t word1_rsv;
2795         uint32_t word2;
2796 #define lpfc_unreg_fcfi_SHIFT           0
2797 #define lpfc_unreg_fcfi_MASK            0x0000FFFF
2798 #define lpfc_unreg_fcfi_WORD            word2
2799 };
2800
2801 struct lpfc_mbx_read_rev {
2802         uint32_t word1;
2803 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT           16
2804 #define lpfc_mbx_rd_rev_sli_lvl_MASK            0x0000000F
2805 #define lpfc_mbx_rd_rev_sli_lvl_WORD            word1
2806 #define lpfc_mbx_rd_rev_fcoe_SHIFT              20
2807 #define lpfc_mbx_rd_rev_fcoe_MASK               0x00000001
2808 #define lpfc_mbx_rd_rev_fcoe_WORD               word1
2809 #define lpfc_mbx_rd_rev_cee_ver_SHIFT           21
2810 #define lpfc_mbx_rd_rev_cee_ver_MASK            0x00000003
2811 #define lpfc_mbx_rd_rev_cee_ver_WORD            word1
2812 #define LPFC_PREDCBX_CEE_MODE   0
2813 #define LPFC_DCBX_CEE_MODE      1
2814 #define lpfc_mbx_rd_rev_vpd_SHIFT               29
2815 #define lpfc_mbx_rd_rev_vpd_MASK                0x00000001
2816 #define lpfc_mbx_rd_rev_vpd_WORD                word1
2817         uint32_t first_hw_rev;
2818 #define LPFC_G7_ASIC_1                          0xd
2819         uint32_t second_hw_rev;
2820         uint32_t word4_rsvd;
2821         uint32_t third_hw_rev;
2822         uint32_t word6;
2823 #define lpfc_mbx_rd_rev_fcph_low_SHIFT          0
2824 #define lpfc_mbx_rd_rev_fcph_low_MASK           0x000000FF
2825 #define lpfc_mbx_rd_rev_fcph_low_WORD           word6
2826 #define lpfc_mbx_rd_rev_fcph_high_SHIFT         8
2827 #define lpfc_mbx_rd_rev_fcph_high_MASK          0x000000FF
2828 #define lpfc_mbx_rd_rev_fcph_high_WORD          word6
2829 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT       16
2830 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK        0x000000FF
2831 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD        word6
2832 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT      24
2833 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK       0x000000FF
2834 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD       word6
2835         uint32_t word7_rsvd;
2836         uint32_t fw_id_rev;
2837         uint8_t  fw_name[16];
2838         uint32_t ulp_fw_id_rev;
2839         uint8_t  ulp_fw_name[16];
2840         uint32_t word18_47_rsvd[30];
2841         uint32_t word48;
2842 #define lpfc_mbx_rd_rev_avail_len_SHIFT         0
2843 #define lpfc_mbx_rd_rev_avail_len_MASK          0x00FFFFFF
2844 #define lpfc_mbx_rd_rev_avail_len_WORD          word48
2845         uint32_t vpd_paddr_low;
2846         uint32_t vpd_paddr_high;
2847         uint32_t avail_vpd_len;
2848         uint32_t rsvd_52_63[12];
2849 };
2850
2851 struct lpfc_mbx_read_config {
2852         uint32_t word1;
2853 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT     31
2854 #define lpfc_mbx_rd_conf_extnts_inuse_MASK      0x00000001
2855 #define lpfc_mbx_rd_conf_extnts_inuse_WORD      word1
2856 #define lpfc_mbx_rd_conf_wcs_SHIFT              28      /* warning signaling */
2857 #define lpfc_mbx_rd_conf_wcs_MASK               0x00000001
2858 #define lpfc_mbx_rd_conf_wcs_WORD               word1
2859 #define lpfc_mbx_rd_conf_acs_SHIFT              27      /* alarm signaling */
2860 #define lpfc_mbx_rd_conf_acs_MASK               0x00000001
2861 #define lpfc_mbx_rd_conf_acs_WORD               word1
2862         uint32_t word2;
2863 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT         0
2864 #define lpfc_mbx_rd_conf_lnk_numb_MASK          0x0000003F
2865 #define lpfc_mbx_rd_conf_lnk_numb_WORD          word2
2866 #define lpfc_mbx_rd_conf_lnk_type_SHIFT         6
2867 #define lpfc_mbx_rd_conf_lnk_type_MASK          0x00000003
2868 #define lpfc_mbx_rd_conf_lnk_type_WORD          word2
2869 #define LPFC_LNK_TYPE_GE        0
2870 #define LPFC_LNK_TYPE_FC        1
2871 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT          8
2872 #define lpfc_mbx_rd_conf_lnk_ldv_MASK           0x00000001
2873 #define lpfc_mbx_rd_conf_lnk_ldv_WORD           word2
2874 #define lpfc_mbx_rd_conf_trunk_SHIFT            12
2875 #define lpfc_mbx_rd_conf_trunk_MASK             0x0000000F
2876 #define lpfc_mbx_rd_conf_trunk_WORD             word2
2877 #define lpfc_mbx_rd_conf_pt_SHIFT               20
2878 #define lpfc_mbx_rd_conf_pt_MASK                0x00000003
2879 #define lpfc_mbx_rd_conf_pt_WORD                word2
2880 #define lpfc_mbx_rd_conf_tf_SHIFT               22
2881 #define lpfc_mbx_rd_conf_tf_MASK                0x00000001
2882 #define lpfc_mbx_rd_conf_tf_WORD                word2
2883 #define lpfc_mbx_rd_conf_ptv_SHIFT              23
2884 #define lpfc_mbx_rd_conf_ptv_MASK               0x00000001
2885 #define lpfc_mbx_rd_conf_ptv_WORD               word2
2886 #define lpfc_mbx_rd_conf_topology_SHIFT         24
2887 #define lpfc_mbx_rd_conf_topology_MASK          0x000000FF
2888 #define lpfc_mbx_rd_conf_topology_WORD          word2
2889         uint32_t rsvd_3;
2890         uint32_t word4;
2891 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT          0
2892 #define lpfc_mbx_rd_conf_e_d_tov_MASK           0x0000FFFF
2893 #define lpfc_mbx_rd_conf_e_d_tov_WORD           word4
2894         uint32_t rsvd_5;
2895         uint32_t word6;
2896 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT          0
2897 #define lpfc_mbx_rd_conf_r_a_tov_MASK           0x0000FFFF
2898 #define lpfc_mbx_rd_conf_r_a_tov_WORD           word6
2899 #define lpfc_mbx_rd_conf_link_speed_SHIFT       16
2900 #define lpfc_mbx_rd_conf_link_speed_MASK        0x0000FFFF
2901 #define lpfc_mbx_rd_conf_link_speed_WORD        word6
2902         uint32_t rsvd_7;
2903         uint32_t word8;
2904 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT        0
2905 #define lpfc_mbx_rd_conf_bbscn_min_MASK         0x0000000F
2906 #define lpfc_mbx_rd_conf_bbscn_min_WORD         word8
2907 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT        4
2908 #define lpfc_mbx_rd_conf_bbscn_max_MASK         0x0000000F
2909 #define lpfc_mbx_rd_conf_bbscn_max_WORD         word8
2910 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT        8
2911 #define lpfc_mbx_rd_conf_bbscn_def_MASK         0x0000000F
2912 #define lpfc_mbx_rd_conf_bbscn_def_WORD         word8
2913         uint32_t word9;
2914 #define lpfc_mbx_rd_conf_lmt_SHIFT              0
2915 #define lpfc_mbx_rd_conf_lmt_MASK               0x0000FFFF
2916 #define lpfc_mbx_rd_conf_lmt_WORD               word9
2917         uint32_t rsvd_10;
2918         uint32_t rsvd_11;
2919         uint32_t word12;
2920 #define lpfc_mbx_rd_conf_xri_base_SHIFT         0
2921 #define lpfc_mbx_rd_conf_xri_base_MASK          0x0000FFFF
2922 #define lpfc_mbx_rd_conf_xri_base_WORD          word12
2923 #define lpfc_mbx_rd_conf_xri_count_SHIFT        16
2924 #define lpfc_mbx_rd_conf_xri_count_MASK         0x0000FFFF
2925 #define lpfc_mbx_rd_conf_xri_count_WORD         word12
2926         uint32_t word13;
2927 #define lpfc_mbx_rd_conf_rpi_base_SHIFT         0
2928 #define lpfc_mbx_rd_conf_rpi_base_MASK          0x0000FFFF
2929 #define lpfc_mbx_rd_conf_rpi_base_WORD          word13
2930 #define lpfc_mbx_rd_conf_rpi_count_SHIFT        16
2931 #define lpfc_mbx_rd_conf_rpi_count_MASK         0x0000FFFF
2932 #define lpfc_mbx_rd_conf_rpi_count_WORD         word13
2933         uint32_t word14;
2934 #define lpfc_mbx_rd_conf_vpi_base_SHIFT         0
2935 #define lpfc_mbx_rd_conf_vpi_base_MASK          0x0000FFFF
2936 #define lpfc_mbx_rd_conf_vpi_base_WORD          word14
2937 #define lpfc_mbx_rd_conf_vpi_count_SHIFT        16
2938 #define lpfc_mbx_rd_conf_vpi_count_MASK         0x0000FFFF
2939 #define lpfc_mbx_rd_conf_vpi_count_WORD         word14
2940         uint32_t word15;
2941 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
2942 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
2943 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
2944 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
2945 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
2946 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
2947         uint32_t word16;
2948 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT       16
2949 #define lpfc_mbx_rd_conf_fcfi_count_MASK        0x0000FFFF
2950 #define lpfc_mbx_rd_conf_fcfi_count_WORD        word16
2951         uint32_t word17;
2952 #define lpfc_mbx_rd_conf_rq_count_SHIFT         0
2953 #define lpfc_mbx_rd_conf_rq_count_MASK          0x0000FFFF
2954 #define lpfc_mbx_rd_conf_rq_count_WORD          word17
2955 #define lpfc_mbx_rd_conf_eq_count_SHIFT         16
2956 #define lpfc_mbx_rd_conf_eq_count_MASK          0x0000FFFF
2957 #define lpfc_mbx_rd_conf_eq_count_WORD          word17
2958         uint32_t word18;
2959 #define lpfc_mbx_rd_conf_wq_count_SHIFT         0
2960 #define lpfc_mbx_rd_conf_wq_count_MASK          0x0000FFFF
2961 #define lpfc_mbx_rd_conf_wq_count_WORD          word18
2962 #define lpfc_mbx_rd_conf_cq_count_SHIFT         16
2963 #define lpfc_mbx_rd_conf_cq_count_MASK          0x0000FFFF
2964 #define lpfc_mbx_rd_conf_cq_count_WORD          word18
2965 };
2966
2967 struct lpfc_mbx_request_features {
2968         uint32_t word1;
2969 #define lpfc_mbx_rq_ftr_qry_SHIFT               0
2970 #define lpfc_mbx_rq_ftr_qry_MASK                0x00000001
2971 #define lpfc_mbx_rq_ftr_qry_WORD                word1
2972         uint32_t word2;
2973 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT           0
2974 #define lpfc_mbx_rq_ftr_rq_iaab_MASK            0x00000001
2975 #define lpfc_mbx_rq_ftr_rq_iaab_WORD            word2
2976 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT           1
2977 #define lpfc_mbx_rq_ftr_rq_npiv_MASK            0x00000001
2978 #define lpfc_mbx_rq_ftr_rq_npiv_WORD            word2
2979 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT            2
2980 #define lpfc_mbx_rq_ftr_rq_dif_MASK             0x00000001
2981 #define lpfc_mbx_rq_ftr_rq_dif_WORD             word2
2982 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT             3
2983 #define lpfc_mbx_rq_ftr_rq_vf_MASK              0x00000001
2984 #define lpfc_mbx_rq_ftr_rq_vf_WORD              word2
2985 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT           4
2986 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK            0x00000001
2987 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD            word2
2988 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT           5
2989 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK            0x00000001
2990 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD            word2
2991 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT           6
2992 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK            0x00000001
2993 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD            word2
2994 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT           7
2995 #define lpfc_mbx_rq_ftr_rq_ifip_MASK            0x00000001
2996 #define lpfc_mbx_rq_ftr_rq_ifip_WORD            word2
2997 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT           9
2998 #define lpfc_mbx_rq_ftr_rq_iaar_MASK            0x00000001
2999 #define lpfc_mbx_rq_ftr_rq_iaar_WORD            word2
3000 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT          11
3001 #define lpfc_mbx_rq_ftr_rq_perfh_MASK           0x00000001
3002 #define lpfc_mbx_rq_ftr_rq_perfh_WORD           word2
3003 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT           16
3004 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK            0x00000001
3005 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD            word2
3006 #define lpfc_mbx_rq_ftr_rq_ashdr_SHIFT          17
3007 #define lpfc_mbx_rq_ftr_rq_ashdr_MASK           0x00000001
3008 #define lpfc_mbx_rq_ftr_rq_ashdr_WORD           word2
3009         uint32_t word3;
3010 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT          0
3011 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK           0x00000001
3012 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD           word3
3013 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT          1
3014 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK           0x00000001
3015 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD           word3
3016 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT           2
3017 #define lpfc_mbx_rq_ftr_rsp_dif_MASK            0x00000001
3018 #define lpfc_mbx_rq_ftr_rsp_dif_WORD            word3
3019 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT            3
3020 #define lpfc_mbx_rq_ftr_rsp_vf__MASK            0x00000001
3021 #define lpfc_mbx_rq_ftr_rsp_vf_WORD             word3
3022 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT          4
3023 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK           0x00000001
3024 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD           word3
3025 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT          5
3026 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK           0x00000001
3027 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD           word3
3028 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT          6
3029 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK           0x00000001
3030 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD           word3
3031 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT          7
3032 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK           0x00000001
3033 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD           word3
3034 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT         11
3035 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK          0x00000001
3036 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD          word3
3037 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT          16
3038 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK           0x00000001
3039 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD           word3
3040 #define lpfc_mbx_rq_ftr_rsp_ashdr_SHIFT         17
3041 #define lpfc_mbx_rq_ftr_rsp_ashdr_MASK          0x00000001
3042 #define lpfc_mbx_rq_ftr_rsp_ashdr_WORD          word3
3043 };
3044
3045 struct lpfc_mbx_memory_dump_type3 {
3046         uint32_t word1;
3047 #define lpfc_mbx_memory_dump_type3_type_SHIFT    0
3048 #define lpfc_mbx_memory_dump_type3_type_MASK     0x0000000f
3049 #define lpfc_mbx_memory_dump_type3_type_WORD     word1
3050 #define lpfc_mbx_memory_dump_type3_link_SHIFT    24
3051 #define lpfc_mbx_memory_dump_type3_link_MASK     0x000000ff
3052 #define lpfc_mbx_memory_dump_type3_link_WORD     word1
3053         uint32_t word2;
3054 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT  0
3055 #define lpfc_mbx_memory_dump_type3_page_no_MASK   0x0000ffff
3056 #define lpfc_mbx_memory_dump_type3_page_no_WORD   word2
3057 #define lpfc_mbx_memory_dump_type3_offset_SHIFT   16
3058 #define lpfc_mbx_memory_dump_type3_offset_MASK    0x0000ffff
3059 #define lpfc_mbx_memory_dump_type3_offset_WORD    word2
3060         uint32_t word3;
3061 #define lpfc_mbx_memory_dump_type3_length_SHIFT  0
3062 #define lpfc_mbx_memory_dump_type3_length_MASK   0x00ffffff
3063 #define lpfc_mbx_memory_dump_type3_length_WORD   word3
3064         uint32_t addr_lo;
3065         uint32_t addr_hi;
3066         uint32_t return_len;
3067 };
3068
3069 #define DMP_PAGE_A0             0xa0
3070 #define DMP_PAGE_A2             0xa2
3071 #define DMP_SFF_PAGE_A0_SIZE    256
3072 #define DMP_SFF_PAGE_A2_SIZE    256
3073
3074 #define SFP_WAVELENGTH_LC1310   1310
3075 #define SFP_WAVELENGTH_LL1550   1550
3076
3077
3078 /*
3079  *  * SFF-8472 TABLE 3.4
3080  *   */
3081 #define  SFF_PG0_CONNECTOR_UNKNOWN    0x00   /* Unknown  */
3082 #define  SFF_PG0_CONNECTOR_SC         0x01   /* SC       */
3083 #define  SFF_PG0_CONNECTOR_FC_COPPER1 0x02   /* FC style 1 copper connector */
3084 #define  SFF_PG0_CONNECTOR_FC_COPPER2 0x03   /* FC style 2 copper connector */
3085 #define  SFF_PG0_CONNECTOR_BNC        0x04   /* BNC / TNC */
3086 #define  SFF_PG0_CONNECTOR__FC_COAX   0x05   /* FC coaxial headers */
3087 #define  SFF_PG0_CONNECTOR_FIBERJACK  0x06   /* FiberJack */
3088 #define  SFF_PG0_CONNECTOR_LC         0x07   /* LC        */
3089 #define  SFF_PG0_CONNECTOR_MT         0x08   /* MT - RJ   */
3090 #define  SFF_PG0_CONNECTOR_MU         0x09   /* MU        */
3091 #define  SFF_PG0_CONNECTOR_SF         0x0A   /* SG        */
3092 #define  SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
3093 #define  SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
3094 #define  SFF_PG0_CONNECTOR_HSSDC_II   0x20   /* HSSDC II */
3095 #define  SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
3096 #define  SFF_PG0_CONNECTOR_RJ45       0x22  /* RJ45 */
3097
3098 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */
3099
3100 #define SSF_IDENTIFIER                  0
3101 #define SSF_EXT_IDENTIFIER              1
3102 #define SSF_CONNECTOR                   2
3103 #define SSF_TRANSCEIVER_CODE_B0         3
3104 #define SSF_TRANSCEIVER_CODE_B1         4
3105 #define SSF_TRANSCEIVER_CODE_B2         5
3106 #define SSF_TRANSCEIVER_CODE_B3         6
3107 #define SSF_TRANSCEIVER_CODE_B4         7
3108 #define SSF_TRANSCEIVER_CODE_B5         8
3109 #define SSF_TRANSCEIVER_CODE_B6         9
3110 #define SSF_TRANSCEIVER_CODE_B7         10
3111 #define SSF_ENCODING                    11
3112 #define SSF_BR_NOMINAL                  12
3113 #define SSF_RATE_IDENTIFIER             13
3114 #define SSF_LENGTH_9UM_KM               14
3115 #define SSF_LENGTH_9UM                  15
3116 #define SSF_LENGTH_50UM_OM2             16
3117 #define SSF_LENGTH_62UM_OM1             17
3118 #define SFF_LENGTH_COPPER               18
3119 #define SSF_LENGTH_50UM_OM3             19
3120 #define SSF_VENDOR_NAME                 20
3121 #define SSF_VENDOR_OUI                  36
3122 #define SSF_VENDOR_PN                   40
3123 #define SSF_VENDOR_REV                  56
3124 #define SSF_WAVELENGTH_B1               60
3125 #define SSF_WAVELENGTH_B0               61
3126 #define SSF_CC_BASE                     63
3127 #define SSF_OPTIONS_B1                  64
3128 #define SSF_OPTIONS_B0                  65
3129 #define SSF_BR_MAX                      66
3130 #define SSF_BR_MIN                      67
3131 #define SSF_VENDOR_SN                   68
3132 #define SSF_DATE_CODE                   84
3133 #define SSF_MONITORING_TYPEDIAGNOSTIC   92
3134 #define SSF_ENHANCED_OPTIONS            93
3135 #define SFF_8472_COMPLIANCE             94
3136 #define SSF_CC_EXT                      95
3137 #define SSF_A0_VENDOR_SPECIFIC          96
3138
3139 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */
3140
3141 #define SSF_TEMP_HIGH_ALARM             0
3142 #define SSF_TEMP_LOW_ALARM              2
3143 #define SSF_TEMP_HIGH_WARNING           4
3144 #define SSF_TEMP_LOW_WARNING            6
3145 #define SSF_VOLTAGE_HIGH_ALARM          8
3146 #define SSF_VOLTAGE_LOW_ALARM           10
3147 #define SSF_VOLTAGE_HIGH_WARNING        12
3148 #define SSF_VOLTAGE_LOW_WARNING         14
3149 #define SSF_BIAS_HIGH_ALARM             16
3150 #define SSF_BIAS_LOW_ALARM              18
3151 #define SSF_BIAS_HIGH_WARNING           20
3152 #define SSF_BIAS_LOW_WARNING            22
3153 #define SSF_TXPOWER_HIGH_ALARM          24
3154 #define SSF_TXPOWER_LOW_ALARM           26
3155 #define SSF_TXPOWER_HIGH_WARNING        28
3156 #define SSF_TXPOWER_LOW_WARNING         30
3157 #define SSF_RXPOWER_HIGH_ALARM          32
3158 #define SSF_RXPOWER_LOW_ALARM           34
3159 #define SSF_RXPOWER_HIGH_WARNING        36
3160 #define SSF_RXPOWER_LOW_WARNING         38
3161 #define SSF_EXT_CAL_CONSTANTS           56
3162 #define SSF_CC_DMI                      95
3163 #define SFF_TEMPERATURE_B1              96
3164 #define SFF_TEMPERATURE_B0              97
3165 #define SFF_VCC_B1                      98
3166 #define SFF_VCC_B0                      99
3167 #define SFF_TX_BIAS_CURRENT_B1          100
3168 #define SFF_TX_BIAS_CURRENT_B0          101
3169 #define SFF_TXPOWER_B1                  102
3170 #define SFF_TXPOWER_B0                  103
3171 #define SFF_RXPOWER_B1                  104
3172 #define SFF_RXPOWER_B0                  105
3173 #define SSF_STATUS_CONTROL              110
3174 #define SSF_ALARM_FLAGS                 112
3175 #define SSF_WARNING_FLAGS               116
3176 #define SSF_EXT_TATUS_CONTROL_B1        118
3177 #define SSF_EXT_TATUS_CONTROL_B0        119
3178 #define SSF_A2_VENDOR_SPECIFIC          120
3179 #define SSF_USER_EEPROM                 128
3180 #define SSF_VENDOR_CONTROL              148
3181
3182
3183 /*
3184  * Tranceiver codes Fibre Channel SFF-8472
3185  * Table 3.5.
3186  */
3187
3188 struct sff_trasnceiver_codes_byte0 {
3189         uint8_t inifiband:4;
3190         uint8_t teng_ethernet:4;
3191 };
3192
3193 struct sff_trasnceiver_codes_byte1 {
3194         uint8_t  sonet:6;
3195         uint8_t  escon:2;
3196 };
3197
3198 struct sff_trasnceiver_codes_byte2 {
3199         uint8_t  soNet:8;
3200 };
3201
3202 struct sff_trasnceiver_codes_byte3 {
3203         uint8_t ethernet:8;
3204 };
3205
3206 struct sff_trasnceiver_codes_byte4 {
3207         uint8_t fc_el_lo:1;
3208         uint8_t fc_lw_laser:1;
3209         uint8_t fc_sw_laser:1;
3210         uint8_t fc_md_distance:1;
3211         uint8_t fc_lg_distance:1;
3212         uint8_t fc_int_distance:1;
3213         uint8_t fc_short_distance:1;
3214         uint8_t fc_vld_distance:1;
3215 };
3216
3217 struct sff_trasnceiver_codes_byte5 {
3218         uint8_t reserved1:1;
3219         uint8_t reserved2:1;
3220         uint8_t fc_sfp_active:1;  /* Active cable   */
3221         uint8_t fc_sfp_passive:1; /* Passive cable  */
3222         uint8_t fc_lw_laser:1;     /* Longwave laser */
3223         uint8_t fc_sw_laser_sl:1;
3224         uint8_t fc_sw_laser_sn:1;
3225         uint8_t fc_el_hi:1;        /* Electrical enclosure high bit */
3226 };
3227
3228 struct sff_trasnceiver_codes_byte6 {
3229         uint8_t fc_tm_sm:1;      /* Single Mode */
3230         uint8_t reserved:1;
3231         uint8_t fc_tm_m6:1;       /* Multimode, 62.5um (M6) */
3232         uint8_t fc_tm_tv:1;      /* Video Coax (TV) */
3233         uint8_t fc_tm_mi:1;      /* Miniature Coax (MI) */
3234         uint8_t fc_tm_tp:1;      /* Twisted Pair (TP) */
3235         uint8_t fc_tm_tw:1;      /* Twin Axial Pair  */
3236 };
3237
3238 struct sff_trasnceiver_codes_byte7 {
3239         uint8_t fc_sp_100MB:1;   /*  100 MB/sec */
3240         uint8_t reserve:1;
3241         uint8_t fc_sp_200mb:1;   /*  200 MB/sec */
3242         uint8_t fc_sp_3200MB:1;  /* 3200 MB/sec */
3243         uint8_t fc_sp_400MB:1;   /*  400 MB/sec */
3244         uint8_t fc_sp_1600MB:1;  /* 1600 MB/sec */
3245         uint8_t fc_sp_800MB:1;   /*  800 MB/sec */
3246         uint8_t fc_sp_1200MB:1;  /* 1200 MB/sec */
3247 };
3248
3249 /* User writable non-volatile memory, SFF-8472 Table 3.20 */
3250 struct user_eeprom {
3251         uint8_t vendor_name[16];
3252         uint8_t vendor_oui[3];
3253         uint8_t vendor_pn[816];
3254         uint8_t vendor_rev[4];
3255         uint8_t vendor_sn[16];
3256         uint8_t datecode[6];
3257         uint8_t lot_code[2];
3258         uint8_t reserved191[57];
3259 };
3260
3261 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
3262                                &(~((SLI4_PAGE_SIZE)-1)))
3263
3264 struct lpfc_sli4_parameters {
3265         uint32_t word0;
3266 #define cfg_prot_type_SHIFT                     0
3267 #define cfg_prot_type_MASK                      0x000000FF
3268 #define cfg_prot_type_WORD                      word0
3269         uint32_t word1;
3270 #define cfg_ft_SHIFT                            0
3271 #define cfg_ft_MASK                             0x00000001
3272 #define cfg_ft_WORD                             word1
3273 #define cfg_sli_rev_SHIFT                       4
3274 #define cfg_sli_rev_MASK                        0x0000000f
3275 #define cfg_sli_rev_WORD                        word1
3276 #define cfg_sli_family_SHIFT                    8
3277 #define cfg_sli_family_MASK                     0x0000000f
3278 #define cfg_sli_family_WORD                     word1
3279 #define cfg_if_type_SHIFT                       12
3280 #define cfg_if_type_MASK                        0x0000000f
3281 #define cfg_if_type_WORD                        word1
3282 #define cfg_sli_hint_1_SHIFT                    16
3283 #define cfg_sli_hint_1_MASK                     0x000000ff
3284 #define cfg_sli_hint_1_WORD                     word1
3285 #define cfg_sli_hint_2_SHIFT                    24
3286 #define cfg_sli_hint_2_MASK                     0x0000001f
3287 #define cfg_sli_hint_2_WORD                     word1
3288         uint32_t word2;
3289 #define cfg_eqav_SHIFT                          31
3290 #define cfg_eqav_MASK                           0x00000001
3291 #define cfg_eqav_WORD                           word2
3292         uint32_t word3;
3293         uint32_t word4;
3294 #define cfg_cqv_SHIFT                           14
3295 #define cfg_cqv_MASK                            0x00000003
3296 #define cfg_cqv_WORD                            word4
3297 #define cfg_cqpsize_SHIFT                       16
3298 #define cfg_cqpsize_MASK                        0x000000ff
3299 #define cfg_cqpsize_WORD                        word4
3300 #define cfg_cqav_SHIFT                          31
3301 #define cfg_cqav_MASK                           0x00000001
3302 #define cfg_cqav_WORD                           word4
3303         uint32_t word5;
3304         uint32_t word6;
3305 #define cfg_mqv_SHIFT                           14
3306 #define cfg_mqv_MASK                            0x00000003
3307 #define cfg_mqv_WORD                            word6
3308         uint32_t word7;
3309         uint32_t word8;
3310 #define cfg_wqpcnt_SHIFT                        0
3311 #define cfg_wqpcnt_MASK                         0x0000000f
3312 #define cfg_wqpcnt_WORD                         word8
3313 #define cfg_wqsize_SHIFT                        8
3314 #define cfg_wqsize_MASK                         0x0000000f
3315 #define cfg_wqsize_WORD                         word8
3316 #define cfg_wqv_SHIFT                           14
3317 #define cfg_wqv_MASK                            0x00000003
3318 #define cfg_wqv_WORD                            word8
3319 #define cfg_wqpsize_SHIFT                       16
3320 #define cfg_wqpsize_MASK                        0x000000ff
3321 #define cfg_wqpsize_WORD                        word8
3322         uint32_t word9;
3323         uint32_t word10;
3324 #define cfg_rqv_SHIFT                           14
3325 #define cfg_rqv_MASK                            0x00000003
3326 #define cfg_rqv_WORD                            word10
3327         uint32_t word11;
3328 #define cfg_rq_db_window_SHIFT                  28
3329 #define cfg_rq_db_window_MASK                   0x0000000f
3330 #define cfg_rq_db_window_WORD                   word11
3331         uint32_t word12;
3332 #define cfg_fcoe_SHIFT                          0
3333 #define cfg_fcoe_MASK                           0x00000001
3334 #define cfg_fcoe_WORD                           word12
3335 #define cfg_ext_SHIFT                           1
3336 #define cfg_ext_MASK                            0x00000001
3337 #define cfg_ext_WORD                            word12
3338 #define cfg_hdrr_SHIFT                          2
3339 #define cfg_hdrr_MASK                           0x00000001
3340 #define cfg_hdrr_WORD                           word12
3341 #define cfg_phwq_SHIFT                          15
3342 #define cfg_phwq_MASK                           0x00000001
3343 #define cfg_phwq_WORD                           word12
3344 #define cfg_oas_SHIFT                           25
3345 #define cfg_oas_MASK                            0x00000001
3346 #define cfg_oas_WORD                            word12
3347 #define cfg_loopbk_scope_SHIFT                  28
3348 #define cfg_loopbk_scope_MASK                   0x0000000f
3349 #define cfg_loopbk_scope_WORD                   word12
3350         uint32_t sge_supp_len;
3351         uint32_t word14;
3352 #define cfg_sgl_page_cnt_SHIFT                  0
3353 #define cfg_sgl_page_cnt_MASK                   0x0000000f
3354 #define cfg_sgl_page_cnt_WORD                   word14
3355 #define cfg_sgl_page_size_SHIFT                 8
3356 #define cfg_sgl_page_size_MASK                  0x000000ff
3357 #define cfg_sgl_page_size_WORD                  word14
3358 #define cfg_sgl_pp_align_SHIFT                  16
3359 #define cfg_sgl_pp_align_MASK                   0x000000ff
3360 #define cfg_sgl_pp_align_WORD                   word14
3361         uint32_t word15;
3362         uint32_t word16;
3363         uint32_t word17;
3364         uint32_t word18;
3365         uint32_t word19;
3366 #define cfg_ext_embed_cb_SHIFT                  0
3367 #define cfg_ext_embed_cb_MASK                   0x00000001
3368 #define cfg_ext_embed_cb_WORD                   word19
3369 #define cfg_mds_diags_SHIFT                     1
3370 #define cfg_mds_diags_MASK                      0x00000001
3371 #define cfg_mds_diags_WORD                      word19
3372 #define cfg_nvme_SHIFT                          3
3373 #define cfg_nvme_MASK                           0x00000001
3374 #define cfg_nvme_WORD                           word19
3375 #define cfg_xib_SHIFT                           4
3376 #define cfg_xib_MASK                            0x00000001
3377 #define cfg_xib_WORD                            word19
3378 #define cfg_xpsgl_SHIFT                         6
3379 #define cfg_xpsgl_MASK                          0x00000001
3380 #define cfg_xpsgl_WORD                          word19
3381 #define cfg_eqdr_SHIFT                          8
3382 #define cfg_eqdr_MASK                           0x00000001
3383 #define cfg_eqdr_WORD                           word19
3384 #define cfg_nosr_SHIFT                          9
3385 #define cfg_nosr_MASK                           0x00000001
3386 #define cfg_nosr_WORD                           word19
3387 #define cfg_bv1s_SHIFT                          10
3388 #define cfg_bv1s_MASK                           0x00000001
3389 #define cfg_bv1s_WORD                           word19
3390
3391 #define cfg_nsler_SHIFT                         12
3392 #define cfg_nsler_MASK                          0x00000001
3393 #define cfg_nsler_WORD                          word19
3394 #define cfg_pvl_SHIFT                           13
3395 #define cfg_pvl_MASK                            0x00000001
3396 #define cfg_pvl_WORD                            word19
3397
3398 #define cfg_pbde_SHIFT                          20
3399 #define cfg_pbde_MASK                           0x00000001
3400 #define cfg_pbde_WORD                           word19
3401
3402         uint32_t word20;
3403 #define cfg_max_tow_xri_SHIFT                   0
3404 #define cfg_max_tow_xri_MASK                    0x0000ffff
3405 #define cfg_max_tow_xri_WORD                    word20
3406
3407         uint32_t word21;
3408 #define cfg_mi_ver_SHIFT                        0
3409 #define cfg_mi_ver_MASK                         0x0000ffff
3410 #define cfg_mi_ver_WORD                         word21
3411 #define cfg_cmf_SHIFT                           24
3412 #define cfg_cmf_MASK                            0x000000ff
3413 #define cfg_cmf_WORD                            word21
3414
3415         uint32_t mib_size;
3416         uint32_t word23;                        /* RESERVED */
3417
3418         uint32_t word24;
3419 #define cfg_frag_field_offset_SHIFT             0
3420 #define cfg_frag_field_offset_MASK              0x0000ffff
3421 #define cfg_frag_field_offset_WORD              word24
3422
3423 #define cfg_frag_field_size_SHIFT               16
3424 #define cfg_frag_field_size_MASK                0x0000ffff
3425 #define cfg_frag_field_size_WORD                word24
3426
3427         uint32_t word25;
3428 #define cfg_sgl_field_offset_SHIFT              0
3429 #define cfg_sgl_field_offset_MASK               0x0000ffff
3430 #define cfg_sgl_field_offset_WORD               word25
3431
3432 #define cfg_sgl_field_size_SHIFT                16
3433 #define cfg_sgl_field_size_MASK                 0x0000ffff
3434 #define cfg_sgl_field_size_WORD                 word25
3435
3436         uint32_t word26;        /* Chain SGE initial value LOW  */
3437         uint32_t word27;        /* Chain SGE initial value HIGH */
3438 #define LPFC_NODELAY_MAX_IO                     32
3439 };
3440
3441 #define LPFC_SET_UE_RECOVERY            0x10
3442 #define LPFC_SET_MDS_DIAGS              0x12
3443 #define LPFC_SET_CGN_SIGNAL             0x1f
3444 #define LPFC_SET_DUAL_DUMP              0x1e
3445 #define LPFC_SET_ENABLE_MI              0x21
3446 #define LPFC_SET_ENABLE_CMF             0x24
3447 struct lpfc_mbx_set_feature {
3448         struct mbox_header header;
3449         uint32_t feature;
3450         uint32_t param_len;
3451         uint32_t word6;
3452 #define lpfc_mbx_set_feature_UER_SHIFT  0
3453 #define lpfc_mbx_set_feature_UER_MASK   0x00000001
3454 #define lpfc_mbx_set_feature_UER_WORD   word6
3455 #define lpfc_mbx_set_feature_mds_SHIFT  2
3456 #define lpfc_mbx_set_feature_mds_MASK   0x00000001
3457 #define lpfc_mbx_set_feature_mds_WORD   word6
3458 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT  1
3459 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK   0x00000001
3460 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD   word6
3461 #define lpfc_mbx_set_feature_CGN_warn_freq_SHIFT 0
3462 #define lpfc_mbx_set_feature_CGN_warn_freq_MASK  0x0000ffff
3463 #define lpfc_mbx_set_feature_CGN_warn_freq_WORD  word6
3464 #define lpfc_mbx_set_feature_dd_SHIFT           0
3465 #define lpfc_mbx_set_feature_dd_MASK            0x00000001
3466 #define lpfc_mbx_set_feature_dd_WORD            word6
3467 #define lpfc_mbx_set_feature_ddquery_SHIFT      1
3468 #define lpfc_mbx_set_feature_ddquery_MASK       0x00000001
3469 #define lpfc_mbx_set_feature_ddquery_WORD       word6
3470 #define LPFC_DISABLE_DUAL_DUMP          0
3471 #define LPFC_ENABLE_DUAL_DUMP           1
3472 #define LPFC_QUERY_OP_DUAL_DUMP         2
3473 #define lpfc_mbx_set_feature_cmf_SHIFT          0
3474 #define lpfc_mbx_set_feature_cmf_MASK           0x00000001
3475 #define lpfc_mbx_set_feature_cmf_WORD           word6
3476 #define lpfc_mbx_set_feature_mi_SHIFT           0
3477 #define lpfc_mbx_set_feature_mi_MASK            0x0000ffff
3478 #define lpfc_mbx_set_feature_mi_WORD            word6
3479 #define lpfc_mbx_set_feature_milunq_SHIFT       16
3480 #define lpfc_mbx_set_feature_milunq_MASK        0x0000ffff
3481 #define lpfc_mbx_set_feature_milunq_WORD        word6
3482         uint32_t word7;
3483 #define lpfc_mbx_set_feature_UERP_SHIFT 0
3484 #define lpfc_mbx_set_feature_UERP_MASK  0x0000ffff
3485 #define lpfc_mbx_set_feature_UERP_WORD  word7
3486 #define lpfc_mbx_set_feature_UESR_SHIFT 16
3487 #define lpfc_mbx_set_feature_UESR_MASK  0x0000ffff
3488 #define lpfc_mbx_set_feature_UESR_WORD  word7
3489 #define lpfc_mbx_set_feature_CGN_alarm_freq_SHIFT 0
3490 #define lpfc_mbx_set_feature_CGN_alarm_freq_MASK  0x0000ffff
3491 #define lpfc_mbx_set_feature_CGN_alarm_freq_WORD  word7
3492         u32 word8;
3493 #define lpfc_mbx_set_feature_CGN_acqe_freq_SHIFT 0
3494 #define lpfc_mbx_set_feature_CGN_acqe_freq_MASK  0x000000ff
3495 #define lpfc_mbx_set_feature_CGN_acqe_freq_WORD  word8
3496 };
3497
3498
3499 #define LPFC_SET_HOST_OS_DRIVER_VERSION    0x2
3500 #define LPFC_SET_HOST_DATE_TIME            0x4
3501
3502 struct lpfc_mbx_set_host_date_time {
3503         uint32_t word6;
3504 #define lpfc_mbx_set_host_month_WORD    word6
3505 #define lpfc_mbx_set_host_month_SHIFT   16
3506 #define lpfc_mbx_set_host_month_MASK    0xFF
3507 #define lpfc_mbx_set_host_day_WORD      word6
3508 #define lpfc_mbx_set_host_day_SHIFT     8
3509 #define lpfc_mbx_set_host_day_MASK      0xFF
3510 #define lpfc_mbx_set_host_year_WORD     word6
3511 #define lpfc_mbx_set_host_year_SHIFT    0
3512 #define lpfc_mbx_set_host_year_MASK     0xFF
3513         uint32_t word7;
3514 #define lpfc_mbx_set_host_hour_WORD     word7
3515 #define lpfc_mbx_set_host_hour_SHIFT    16
3516 #define lpfc_mbx_set_host_hour_MASK     0xFF
3517 #define lpfc_mbx_set_host_min_WORD      word7
3518 #define lpfc_mbx_set_host_min_SHIFT     8
3519 #define lpfc_mbx_set_host_min_MASK      0xFF
3520 #define lpfc_mbx_set_host_sec_WORD      word7
3521 #define lpfc_mbx_set_host_sec_SHIFT     0
3522 #define lpfc_mbx_set_host_sec_MASK      0xFF
3523 };
3524
3525 struct lpfc_mbx_set_host_data {
3526 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE   48
3527         struct mbox_header header;
3528         uint32_t param_id;
3529         uint32_t param_len;
3530         union {
3531                 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE];
3532                 struct  lpfc_mbx_set_host_date_time tm;
3533         } un;
3534 };
3535
3536 struct lpfc_mbx_set_trunk_mode {
3537         struct mbox_header header;
3538         uint32_t word0;
3539 #define lpfc_mbx_set_trunk_mode_WORD      word0
3540 #define lpfc_mbx_set_trunk_mode_SHIFT     0
3541 #define lpfc_mbx_set_trunk_mode_MASK      0xFF
3542         uint32_t word1;
3543         uint32_t word2;
3544 };
3545
3546 struct lpfc_mbx_get_sli4_parameters {
3547         struct mbox_header header;
3548         struct lpfc_sli4_parameters sli4_parameters;
3549 };
3550
3551 struct lpfc_mbx_reg_congestion_buf {
3552         struct mbox_header header;
3553         uint32_t word0;
3554 #define lpfc_mbx_reg_cgn_buf_type_WORD          word0
3555 #define lpfc_mbx_reg_cgn_buf_type_SHIFT         0
3556 #define lpfc_mbx_reg_cgn_buf_type_MASK          0xFF
3557 #define lpfc_mbx_reg_cgn_buf_cnt_WORD           word0
3558 #define lpfc_mbx_reg_cgn_buf_cnt_SHIFT          16
3559 #define lpfc_mbx_reg_cgn_buf_cnt_MASK           0xFF
3560         uint32_t word1;
3561         uint32_t length;
3562         uint32_t addr_lo;
3563         uint32_t addr_hi;
3564 };
3565
3566 struct lpfc_rscr_desc_generic {
3567 #define LPFC_RSRC_DESC_WSIZE                    22
3568         uint32_t desc[LPFC_RSRC_DESC_WSIZE];
3569 };
3570
3571 struct lpfc_rsrc_desc_pcie {
3572         uint32_t word0;
3573 #define lpfc_rsrc_desc_pcie_type_SHIFT          0
3574 #define lpfc_rsrc_desc_pcie_type_MASK           0x000000ff
3575 #define lpfc_rsrc_desc_pcie_type_WORD           word0
3576 #define LPFC_RSRC_DESC_TYPE_PCIE                0x40
3577 #define lpfc_rsrc_desc_pcie_length_SHIFT        8
3578 #define lpfc_rsrc_desc_pcie_length_MASK         0x000000ff
3579 #define lpfc_rsrc_desc_pcie_length_WORD         word0
3580         uint32_t word1;
3581 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT         0
3582 #define lpfc_rsrc_desc_pcie_pfnum_MASK          0x000000ff
3583 #define lpfc_rsrc_desc_pcie_pfnum_WORD          word1
3584         uint32_t reserved;
3585         uint32_t word3;
3586 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT     0
3587 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK      0x000000ff
3588 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD      word3
3589 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT        8
3590 #define lpfc_rsrc_desc_pcie_pf_sta_MASK         0x000000ff
3591 #define lpfc_rsrc_desc_pcie_pf_sta_WORD         word3
3592 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT       16
3593 #define lpfc_rsrc_desc_pcie_pf_type_MASK        0x000000ff
3594 #define lpfc_rsrc_desc_pcie_pf_type_WORD        word3
3595         uint32_t word4;
3596 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT     0
3597 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK      0x0000ffff
3598 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD      word4
3599 };
3600
3601 struct lpfc_rsrc_desc_fcfcoe {
3602         uint32_t word0;
3603 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT        0
3604 #define lpfc_rsrc_desc_fcfcoe_type_MASK         0x000000ff
3605 #define lpfc_rsrc_desc_fcfcoe_type_WORD         word0
3606 #define LPFC_RSRC_DESC_TYPE_FCFCOE              0x43
3607 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT      8
3608 #define lpfc_rsrc_desc_fcfcoe_length_MASK       0x000000ff
3609 #define lpfc_rsrc_desc_fcfcoe_length_WORD       word0
3610 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD      0
3611 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH    72
3612 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH    88
3613         uint32_t word1;
3614 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT       0
3615 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK        0x000000ff
3616 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD        word1
3617 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT       16
3618 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK        0x000007ff
3619 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD        word1
3620         uint32_t word2;
3621 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT     0
3622 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK      0x0000ffff
3623 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD      word2
3624 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT     16
3625 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK      0x0000ffff
3626 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD      word2
3627         uint32_t word3;
3628 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT      0
3629 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK       0x0000ffff
3630 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD       word3
3631 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT      16
3632 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK       0x0000ffff
3633 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD       word3
3634         uint32_t word4;
3635 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT      0
3636 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK       0x0000ffff
3637 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD       word4
3638 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT     16
3639 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK      0x0000ffff
3640 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD      word4
3641         uint32_t word5;
3642 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT    0
3643 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK     0x0000ffff
3644 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD     word5
3645 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT     16
3646 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK      0x0000ffff
3647 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD      word5
3648         uint32_t word6;
3649         uint32_t word7;
3650         uint32_t word8;
3651         uint32_t word9;
3652         uint32_t word10;
3653         uint32_t word11;
3654         uint32_t word12;
3655         uint32_t word13;
3656 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT      0
3657 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK       0x0000003f
3658 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD       word13
3659 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT      6
3660 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK       0x00000003
3661 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD       word13
3662 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT         8
3663 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK          0x00000001
3664 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD          word13
3665 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT         9
3666 #define lpfc_rsrc_desc_fcfcoe_lld_MASK          0x00000001
3667 #define lpfc_rsrc_desc_fcfcoe_lld_WORD          word13
3668 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT      16
3669 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK       0x0000ffff
3670 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD       word13
3671 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */
3672         uint32_t bw_min;
3673         uint32_t bw_max;
3674         uint32_t iops_min;
3675         uint32_t iops_max;
3676         uint32_t reserved[4];
3677 };
3678
3679 struct lpfc_func_cfg {
3680 #define LPFC_RSRC_DESC_MAX_NUM                  2
3681         uint32_t rsrc_desc_count;
3682         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3683 };
3684
3685 struct lpfc_mbx_get_func_cfg {
3686         struct mbox_header header;
3687 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
3688 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
3689 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
3690         struct lpfc_func_cfg func_cfg;
3691 };
3692
3693 struct lpfc_prof_cfg {
3694 #define LPFC_RSRC_DESC_MAX_NUM                  2
3695         uint32_t rsrc_desc_count;
3696         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3697 };
3698
3699 struct lpfc_mbx_get_prof_cfg {
3700         struct mbox_header header;
3701 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
3702 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
3703 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
3704         union {
3705                 struct {
3706                         uint32_t word10;
3707 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT     0
3708 #define lpfc_mbx_get_prof_cfg_prof_id_MASK      0x000000ff
3709 #define lpfc_mbx_get_prof_cfg_prof_id_WORD      word10
3710 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT     8
3711 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK      0x00000003
3712 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD      word10
3713                 } request;
3714                 struct {
3715                         struct lpfc_prof_cfg prof_cfg;
3716                 } response;
3717         } u;
3718 };
3719
3720 struct lpfc_controller_attribute {
3721         uint32_t version_string[8];
3722         uint32_t manufacturer_name[8];
3723         uint32_t supported_modes;
3724         uint32_t word17;
3725 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT       0
3726 #define lpfc_cntl_attr_eprom_ver_lo_MASK        0x000000ff
3727 #define lpfc_cntl_attr_eprom_ver_lo_WORD        word17
3728 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT       8
3729 #define lpfc_cntl_attr_eprom_ver_hi_MASK        0x000000ff
3730 #define lpfc_cntl_attr_eprom_ver_hi_WORD        word17
3731 #define lpfc_cntl_attr_flash_id_SHIFT           16
3732 #define lpfc_cntl_attr_flash_id_MASK            0x000000ff
3733 #define lpfc_cntl_attr_flash_id_WORD            word17
3734         uint32_t mbx_da_struct_ver;
3735         uint32_t ep_fw_da_struct_ver;
3736         uint32_t ncsi_ver_str[3];
3737         uint32_t dflt_ext_timeout;
3738         uint32_t model_number[8];
3739         uint32_t description[16];
3740         uint32_t serial_number[8];
3741         uint32_t ip_ver_str[8];
3742         uint32_t fw_ver_str[8];
3743         uint32_t bios_ver_str[8];
3744         uint32_t redboot_ver_str[8];
3745         uint32_t driver_ver_str[8];
3746         uint32_t flash_fw_ver_str[8];
3747         uint32_t functionality;
3748         uint32_t word105;
3749 #define lpfc_cntl_attr_max_cbd_len_SHIFT        0
3750 #define lpfc_cntl_attr_max_cbd_len_MASK         0x0000ffff
3751 #define lpfc_cntl_attr_max_cbd_len_WORD         word105
3752 #define lpfc_cntl_attr_asic_rev_SHIFT           16
3753 #define lpfc_cntl_attr_asic_rev_MASK            0x000000ff
3754 #define lpfc_cntl_attr_asic_rev_WORD            word105
3755 #define lpfc_cntl_attr_gen_guid0_SHIFT          24
3756 #define lpfc_cntl_attr_gen_guid0_MASK           0x000000ff
3757 #define lpfc_cntl_attr_gen_guid0_WORD           word105
3758         uint32_t gen_guid1_12[3];
3759         uint32_t word109;
3760 #define lpfc_cntl_attr_gen_guid13_14_SHIFT      0
3761 #define lpfc_cntl_attr_gen_guid13_14_MASK       0x0000ffff
3762 #define lpfc_cntl_attr_gen_guid13_14_WORD       word109
3763 #define lpfc_cntl_attr_gen_guid15_SHIFT         16
3764 #define lpfc_cntl_attr_gen_guid15_MASK          0x000000ff
3765 #define lpfc_cntl_attr_gen_guid15_WORD          word109
3766 #define lpfc_cntl_attr_hba_port_cnt_SHIFT       24
3767 #define lpfc_cntl_attr_hba_port_cnt_MASK        0x000000ff
3768 #define lpfc_cntl_attr_hba_port_cnt_WORD        word109
3769         uint32_t word110;
3770 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT       0
3771 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK        0x0000ffff
3772 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD        word110
3773 #define lpfc_cntl_attr_multi_func_dev_SHIFT     24
3774 #define lpfc_cntl_attr_multi_func_dev_MASK      0x000000ff
3775 #define lpfc_cntl_attr_multi_func_dev_WORD      word110
3776         uint32_t word111;
3777 #define lpfc_cntl_attr_cache_valid_SHIFT        0
3778 #define lpfc_cntl_attr_cache_valid_MASK         0x000000ff
3779 #define lpfc_cntl_attr_cache_valid_WORD         word111
3780 #define lpfc_cntl_attr_hba_status_SHIFT         8
3781 #define lpfc_cntl_attr_hba_status_MASK          0x000000ff
3782 #define lpfc_cntl_attr_hba_status_WORD          word111
3783 #define lpfc_cntl_attr_max_domain_SHIFT         16
3784 #define lpfc_cntl_attr_max_domain_MASK          0x000000ff
3785 #define lpfc_cntl_attr_max_domain_WORD          word111
3786 #define lpfc_cntl_attr_lnk_numb_SHIFT           24
3787 #define lpfc_cntl_attr_lnk_numb_MASK            0x0000003f
3788 #define lpfc_cntl_attr_lnk_numb_WORD            word111
3789 #define lpfc_cntl_attr_lnk_type_SHIFT           30
3790 #define lpfc_cntl_attr_lnk_type_MASK            0x00000003
3791 #define lpfc_cntl_attr_lnk_type_WORD            word111
3792         uint32_t fw_post_status;
3793         uint32_t hba_mtu[8];
3794         uint32_t word121;
3795         uint32_t reserved1[3];
3796         uint32_t word125;
3797 #define lpfc_cntl_attr_pci_vendor_id_SHIFT      0
3798 #define lpfc_cntl_attr_pci_vendor_id_MASK       0x0000ffff
3799 #define lpfc_cntl_attr_pci_vendor_id_WORD       word125
3800 #define lpfc_cntl_attr_pci_device_id_SHIFT      16
3801 #define lpfc_cntl_attr_pci_device_id_MASK       0x0000ffff
3802 #define lpfc_cntl_attr_pci_device_id_WORD       word125
3803         uint32_t word126;
3804 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT      0
3805 #define lpfc_cntl_attr_pci_subvdr_id_MASK       0x0000ffff
3806 #define lpfc_cntl_attr_pci_subvdr_id_WORD       word126
3807 #define lpfc_cntl_attr_pci_subsys_id_SHIFT      16
3808 #define lpfc_cntl_attr_pci_subsys_id_MASK       0x0000ffff
3809 #define lpfc_cntl_attr_pci_subsys_id_WORD       word126
3810         uint32_t word127;
3811 #define lpfc_cntl_attr_pci_bus_num_SHIFT        0
3812 #define lpfc_cntl_attr_pci_bus_num_MASK         0x000000ff
3813 #define lpfc_cntl_attr_pci_bus_num_WORD         word127
3814 #define lpfc_cntl_attr_pci_dev_num_SHIFT        8
3815 #define lpfc_cntl_attr_pci_dev_num_MASK         0x000000ff
3816 #define lpfc_cntl_attr_pci_dev_num_WORD         word127
3817 #define lpfc_cntl_attr_pci_fnc_num_SHIFT        16
3818 #define lpfc_cntl_attr_pci_fnc_num_MASK         0x000000ff
3819 #define lpfc_cntl_attr_pci_fnc_num_WORD         word127
3820 #define lpfc_cntl_attr_inf_type_SHIFT           24
3821 #define lpfc_cntl_attr_inf_type_MASK            0x000000ff
3822 #define lpfc_cntl_attr_inf_type_WORD            word127
3823         uint32_t unique_id[2];
3824         uint32_t word130;
3825 #define lpfc_cntl_attr_num_netfil_SHIFT         0
3826 #define lpfc_cntl_attr_num_netfil_MASK          0x000000ff
3827 #define lpfc_cntl_attr_num_netfil_WORD          word130
3828         uint32_t reserved2[4];
3829 };
3830
3831 struct lpfc_mbx_get_cntl_attributes {
3832         union  lpfc_sli4_cfg_shdr cfg_shdr;
3833         struct lpfc_controller_attribute cntl_attr;
3834 };
3835
3836 struct lpfc_mbx_get_port_name {
3837         struct mbox_header header;
3838         union {
3839                 struct {
3840                         uint32_t word4;
3841 #define lpfc_mbx_get_port_name_lnk_type_SHIFT   0
3842 #define lpfc_mbx_get_port_name_lnk_type_MASK    0x00000003
3843 #define lpfc_mbx_get_port_name_lnk_type_WORD    word4
3844                 } request;
3845                 struct {
3846                         uint32_t word4;
3847 #define lpfc_mbx_get_port_name_name0_SHIFT      0
3848 #define lpfc_mbx_get_port_name_name0_MASK       0x000000FF
3849 #define lpfc_mbx_get_port_name_name0_WORD       word4
3850 #define lpfc_mbx_get_port_name_name1_SHIFT      8
3851 #define lpfc_mbx_get_port_name_name1_MASK       0x000000FF
3852 #define lpfc_mbx_get_port_name_name1_WORD       word4
3853 #define lpfc_mbx_get_port_name_name2_SHIFT      16
3854 #define lpfc_mbx_get_port_name_name2_MASK       0x000000FF
3855 #define lpfc_mbx_get_port_name_name2_WORD       word4
3856 #define lpfc_mbx_get_port_name_name3_SHIFT      24
3857 #define lpfc_mbx_get_port_name_name3_MASK       0x000000FF
3858 #define lpfc_mbx_get_port_name_name3_WORD       word4
3859 #define LPFC_LINK_NUMBER_0                      0
3860 #define LPFC_LINK_NUMBER_1                      1
3861 #define LPFC_LINK_NUMBER_2                      2
3862 #define LPFC_LINK_NUMBER_3                      3
3863                 } response;
3864         } u;
3865 };
3866
3867 /* Mailbox Completion Queue Error Messages */
3868 #define MB_CQE_STATUS_SUCCESS                   0x0
3869 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES   0x1
3870 #define MB_CQE_STATUS_INVALID_PARAMETER         0x2
3871 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES    0x3
3872 #define MB_CEQ_STATUS_QUEUE_FLUSHING            0x4
3873 #define MB_CQE_STATUS_DMA_FAILED                0x5
3874
3875
3876 #define LPFC_MBX_WR_CONFIG_MAX_BDE              1
3877 struct lpfc_mbx_wr_object {
3878         struct mbox_header header;
3879         union {
3880                 struct {
3881                         uint32_t word4;
3882 #define lpfc_wr_object_eof_SHIFT                31
3883 #define lpfc_wr_object_eof_MASK                 0x00000001
3884 #define lpfc_wr_object_eof_WORD                 word4
3885 #define lpfc_wr_object_eas_SHIFT                29
3886 #define lpfc_wr_object_eas_MASK                 0x00000001
3887 #define lpfc_wr_object_eas_WORD                 word4
3888 #define lpfc_wr_object_write_length_SHIFT       0
3889 #define lpfc_wr_object_write_length_MASK        0x00FFFFFF
3890 #define lpfc_wr_object_write_length_WORD        word4
3891                         uint32_t write_offset;
3892                         uint32_t object_name[LPFC_MBX_OBJECT_NAME_LEN_DW];
3893                         uint32_t bde_count;
3894                         struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
3895                 } request;
3896                 struct {
3897                         uint32_t actual_write_length;
3898                         uint32_t word5;
3899 #define lpfc_wr_object_change_status_SHIFT      0
3900 #define lpfc_wr_object_change_status_MASK       0x000000FF
3901 #define lpfc_wr_object_change_status_WORD       word5
3902 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED      0x00
3903 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET       0x01
3904 #define LPFC_CHANGE_STATUS_FW_RESET             0x02
3905 #define LPFC_CHANGE_STATUS_PORT_MIGRATION       0x04
3906 #define LPFC_CHANGE_STATUS_PCI_RESET            0x05
3907 #define lpfc_wr_object_csf_SHIFT                8
3908 #define lpfc_wr_object_csf_MASK                 0x00000001
3909 #define lpfc_wr_object_csf_WORD                 word5
3910                 } response;
3911         } u;
3912 };
3913
3914 /* mailbox queue entry structure */
3915 struct lpfc_mqe {
3916         uint32_t word0;
3917 #define lpfc_mqe_status_SHIFT           16
3918 #define lpfc_mqe_status_MASK            0x0000FFFF
3919 #define lpfc_mqe_status_WORD            word0
3920 #define lpfc_mqe_command_SHIFT          8
3921 #define lpfc_mqe_command_MASK           0x000000FF
3922 #define lpfc_mqe_command_WORD           word0
3923         union {
3924                 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
3925                 /* sli4 mailbox commands */
3926                 struct lpfc_mbx_sli4_config sli4_config;
3927                 struct lpfc_mbx_init_vfi init_vfi;
3928                 struct lpfc_mbx_reg_vfi reg_vfi;
3929                 struct lpfc_mbx_reg_vfi unreg_vfi;
3930                 struct lpfc_mbx_init_vpi init_vpi;
3931                 struct lpfc_mbx_resume_rpi resume_rpi;
3932                 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
3933                 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
3934                 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
3935                 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
3936                 struct lpfc_mbx_reg_fcfi reg_fcfi;
3937                 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq;
3938                 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
3939                 struct lpfc_mbx_mq_create mq_create;
3940                 struct lpfc_mbx_mq_create_ext mq_create_ext;
3941                 struct lpfc_mbx_read_object read_object;
3942                 struct lpfc_mbx_eq_create eq_create;
3943                 struct lpfc_mbx_modify_eq_delay eq_delay;
3944                 struct lpfc_mbx_cq_create cq_create;
3945                 struct lpfc_mbx_cq_create_set cq_create_set;
3946                 struct lpfc_mbx_wq_create wq_create;
3947                 struct lpfc_mbx_rq_create rq_create;
3948                 struct lpfc_mbx_rq_create_v2 rq_create_v2;
3949                 struct lpfc_mbx_mq_destroy mq_destroy;
3950                 struct lpfc_mbx_eq_destroy eq_destroy;
3951                 struct lpfc_mbx_cq_destroy cq_destroy;
3952                 struct lpfc_mbx_wq_destroy wq_destroy;
3953                 struct lpfc_mbx_rq_destroy rq_destroy;
3954                 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
3955                 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
3956                 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
3957                 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
3958                 struct lpfc_mbx_nembed_cmd nembed_cmd;
3959                 struct lpfc_mbx_read_rev read_rev;
3960                 struct lpfc_mbx_read_vpi read_vpi;
3961                 struct lpfc_mbx_read_config rd_config;
3962                 struct lpfc_mbx_request_features req_ftrs;
3963                 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
3964                 struct lpfc_mbx_query_fw_config query_fw_cfg;
3965                 struct lpfc_mbx_set_beacon_config beacon_config;
3966                 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
3967                 struct lpfc_mbx_reg_congestion_buf reg_congestion_buf;
3968                 struct lpfc_mbx_set_link_diag_state link_diag_state;
3969                 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
3970                 struct lpfc_mbx_run_link_diag_test link_diag_test;
3971                 struct lpfc_mbx_get_func_cfg get_func_cfg;
3972                 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
3973                 struct lpfc_mbx_wr_object wr_object;
3974                 struct lpfc_mbx_get_port_name get_port_name;
3975                 struct lpfc_mbx_set_feature  set_feature;
3976                 struct lpfc_mbx_memory_dump_type3 mem_dump_type3;
3977                 struct lpfc_mbx_set_host_data set_host_data;
3978                 struct lpfc_mbx_set_trunk_mode set_trunk_mode;
3979                 struct lpfc_mbx_nop nop;
3980                 struct lpfc_mbx_set_ras_fwlog ras_fwlog;
3981         } un;
3982 };
3983
3984 struct lpfc_mcqe {
3985         uint32_t word0;
3986 #define lpfc_mcqe_status_SHIFT          0
3987 #define lpfc_mcqe_status_MASK           0x0000FFFF
3988 #define lpfc_mcqe_status_WORD           word0
3989 #define lpfc_mcqe_ext_status_SHIFT      16
3990 #define lpfc_mcqe_ext_status_MASK       0x0000FFFF
3991 #define lpfc_mcqe_ext_status_WORD       word0
3992         uint32_t mcqe_tag0;
3993         uint32_t mcqe_tag1;
3994         uint32_t trailer;
3995 #define lpfc_trailer_valid_SHIFT        31
3996 #define lpfc_trailer_valid_MASK         0x00000001
3997 #define lpfc_trailer_valid_WORD         trailer
3998 #define lpfc_trailer_async_SHIFT        30
3999 #define lpfc_trailer_async_MASK         0x00000001
4000 #define lpfc_trailer_async_WORD         trailer
4001 #define lpfc_trailer_hpi_SHIFT          29
4002 #define lpfc_trailer_hpi_MASK           0x00000001
4003 #define lpfc_trailer_hpi_WORD           trailer
4004 #define lpfc_trailer_completed_SHIFT    28
4005 #define lpfc_trailer_completed_MASK     0x00000001
4006 #define lpfc_trailer_completed_WORD     trailer
4007 #define lpfc_trailer_consumed_SHIFT     27
4008 #define lpfc_trailer_consumed_MASK      0x00000001
4009 #define lpfc_trailer_consumed_WORD      trailer
4010 #define lpfc_trailer_type_SHIFT         16
4011 #define lpfc_trailer_type_MASK          0x000000FF
4012 #define lpfc_trailer_type_WORD          trailer
4013 #define lpfc_trailer_code_SHIFT         8
4014 #define lpfc_trailer_code_MASK          0x000000FF
4015 #define lpfc_trailer_code_WORD          trailer
4016 #define LPFC_TRAILER_CODE_LINK  0x1
4017 #define LPFC_TRAILER_CODE_FCOE  0x2
4018 #define LPFC_TRAILER_CODE_DCBX  0x3
4019 #define LPFC_TRAILER_CODE_GRP5  0x5
4020 #define LPFC_TRAILER_CODE_FC    0x10
4021 #define LPFC_TRAILER_CODE_SLI   0x11
4022 #define LPFC_TRAILER_CODE_CMSTAT        0x13
4023 };
4024
4025 struct lpfc_acqe_link {
4026         uint32_t word0;
4027 #define lpfc_acqe_link_speed_SHIFT              24
4028 #define lpfc_acqe_link_speed_MASK               0x000000FF
4029 #define lpfc_acqe_link_speed_WORD               word0
4030 #define LPFC_ASYNC_LINK_SPEED_ZERO              0x0
4031 #define LPFC_ASYNC_LINK_SPEED_10MBPS            0x1
4032 #define LPFC_ASYNC_LINK_SPEED_100MBPS           0x2
4033 #define LPFC_ASYNC_LINK_SPEED_1GBPS             0x3
4034 #define LPFC_ASYNC_LINK_SPEED_10GBPS            0x4
4035 #define LPFC_ASYNC_LINK_SPEED_20GBPS            0x5
4036 #define LPFC_ASYNC_LINK_SPEED_25GBPS            0x6
4037 #define LPFC_ASYNC_LINK_SPEED_40GBPS            0x7
4038 #define LPFC_ASYNC_LINK_SPEED_100GBPS           0x8
4039 #define lpfc_acqe_link_duplex_SHIFT             16
4040 #define lpfc_acqe_link_duplex_MASK              0x000000FF
4041 #define lpfc_acqe_link_duplex_WORD              word0
4042 #define LPFC_ASYNC_LINK_DUPLEX_NONE             0x0
4043 #define LPFC_ASYNC_LINK_DUPLEX_HALF             0x1
4044 #define LPFC_ASYNC_LINK_DUPLEX_FULL             0x2
4045 #define lpfc_acqe_link_status_SHIFT             8
4046 #define lpfc_acqe_link_status_MASK              0x000000FF
4047 #define lpfc_acqe_link_status_WORD              word0
4048 #define LPFC_ASYNC_LINK_STATUS_DOWN             0x0
4049 #define LPFC_ASYNC_LINK_STATUS_UP               0x1
4050 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN     0x2
4051 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP       0x3
4052 #define lpfc_acqe_link_type_SHIFT               6
4053 #define lpfc_acqe_link_type_MASK                0x00000003
4054 #define lpfc_acqe_link_type_WORD                word0
4055 #define lpfc_acqe_link_number_SHIFT             0
4056 #define lpfc_acqe_link_number_MASK              0x0000003F
4057 #define lpfc_acqe_link_number_WORD              word0
4058         uint32_t word1;
4059 #define lpfc_acqe_link_fault_SHIFT      0
4060 #define lpfc_acqe_link_fault_MASK       0x000000FF
4061 #define lpfc_acqe_link_fault_WORD       word1
4062 #define LPFC_ASYNC_LINK_FAULT_NONE      0x0
4063 #define LPFC_ASYNC_LINK_FAULT_LOCAL     0x1
4064 #define LPFC_ASYNC_LINK_FAULT_REMOTE    0x2
4065 #define LPFC_ASYNC_LINK_FAULT_LR_LRR    0x3
4066 #define lpfc_acqe_logical_link_speed_SHIFT      16
4067 #define lpfc_acqe_logical_link_speed_MASK       0x0000FFFF
4068 #define lpfc_acqe_logical_link_speed_WORD       word1
4069         uint32_t event_tag;
4070         uint32_t trailer;
4071 #define LPFC_LINK_EVENT_TYPE_PHYSICAL   0x0
4072 #define LPFC_LINK_EVENT_TYPE_VIRTUAL    0x1
4073 };
4074
4075 struct lpfc_acqe_fip {
4076         uint32_t index;
4077         uint32_t word1;
4078 #define lpfc_acqe_fip_fcf_count_SHIFT           0
4079 #define lpfc_acqe_fip_fcf_count_MASK            0x0000FFFF
4080 #define lpfc_acqe_fip_fcf_count_WORD            word1
4081 #define lpfc_acqe_fip_event_type_SHIFT          16
4082 #define lpfc_acqe_fip_event_type_MASK           0x0000FFFF
4083 #define lpfc_acqe_fip_event_type_WORD           word1
4084         uint32_t event_tag;
4085         uint32_t trailer;
4086 #define LPFC_FIP_EVENT_TYPE_NEW_FCF             0x1
4087 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL      0x2
4088 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD            0x3
4089 #define LPFC_FIP_EVENT_TYPE_CVL                 0x4
4090 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD       0x5
4091 };
4092
4093 struct lpfc_acqe_dcbx {
4094         uint32_t tlv_ttl;
4095         uint32_t reserved;
4096         uint32_t event_tag;
4097         uint32_t trailer;
4098 };
4099
4100 struct lpfc_acqe_grp5 {
4101         uint32_t word0;
4102 #define lpfc_acqe_grp5_type_SHIFT               6
4103 #define lpfc_acqe_grp5_type_MASK                0x00000003
4104 #define lpfc_acqe_grp5_type_WORD                word0
4105 #define lpfc_acqe_grp5_number_SHIFT             0
4106 #define lpfc_acqe_grp5_number_MASK              0x0000003F
4107 #define lpfc_acqe_grp5_number_WORD              word0
4108         uint32_t word1;
4109 #define lpfc_acqe_grp5_llink_spd_SHIFT  16
4110 #define lpfc_acqe_grp5_llink_spd_MASK   0x0000FFFF
4111 #define lpfc_acqe_grp5_llink_spd_WORD   word1
4112         uint32_t event_tag;
4113         uint32_t trailer;
4114 };
4115
4116 extern const char *const trunk_errmsg[];
4117
4118 struct lpfc_acqe_fc_la {
4119         uint32_t word0;
4120 #define lpfc_acqe_fc_la_speed_SHIFT             24
4121 #define lpfc_acqe_fc_la_speed_MASK              0x000000FF
4122 #define lpfc_acqe_fc_la_speed_WORD              word0
4123 #define LPFC_FC_LA_SPEED_UNKNOWN                0x0
4124 #define LPFC_FC_LA_SPEED_1G             0x1
4125 #define LPFC_FC_LA_SPEED_2G             0x2
4126 #define LPFC_FC_LA_SPEED_4G             0x4
4127 #define LPFC_FC_LA_SPEED_8G             0x8
4128 #define LPFC_FC_LA_SPEED_10G            0xA
4129 #define LPFC_FC_LA_SPEED_16G            0x10
4130 #define LPFC_FC_LA_SPEED_32G            0x20
4131 #define LPFC_FC_LA_SPEED_64G            0x21
4132 #define LPFC_FC_LA_SPEED_128G           0x22
4133 #define LPFC_FC_LA_SPEED_256G           0x23
4134 #define lpfc_acqe_fc_la_topology_SHIFT          16
4135 #define lpfc_acqe_fc_la_topology_MASK           0x000000FF
4136 #define lpfc_acqe_fc_la_topology_WORD           word0
4137 #define LPFC_FC_LA_TOP_UNKOWN           0x0
4138 #define LPFC_FC_LA_TOP_P2P              0x1
4139 #define LPFC_FC_LA_TOP_FCAL             0x2
4140 #define LPFC_FC_LA_TOP_INTERNAL_LOOP    0x3
4141 #define LPFC_FC_LA_TOP_SERDES_LOOP      0x4
4142 #define lpfc_acqe_fc_la_att_type_SHIFT          8
4143 #define lpfc_acqe_fc_la_att_type_MASK           0x000000FF
4144 #define lpfc_acqe_fc_la_att_type_WORD           word0
4145 #define LPFC_FC_LA_TYPE_LINK_UP         0x1
4146 #define LPFC_FC_LA_TYPE_LINK_DOWN       0x2
4147 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA    0x3
4148 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN   0x4
4149 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK    0x5
4150 #define LPFC_FC_LA_TYPE_UNEXP_WWPN      0x6
4151 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT  0x7
4152 #define lpfc_acqe_fc_la_port_type_SHIFT         6
4153 #define lpfc_acqe_fc_la_port_type_MASK          0x00000003
4154 #define lpfc_acqe_fc_la_port_type_WORD          word0
4155 #define LPFC_LINK_TYPE_ETHERNET         0x0
4156 #define LPFC_LINK_TYPE_FC               0x1
4157 #define lpfc_acqe_fc_la_port_number_SHIFT       0
4158 #define lpfc_acqe_fc_la_port_number_MASK        0x0000003F
4159 #define lpfc_acqe_fc_la_port_number_WORD        word0
4160
4161 /* Attention Type is 0x07 (Trunking Event) word0 */
4162 #define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT   16
4163 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK    0x0000001
4164 #define lpfc_acqe_fc_la_trunk_link_status_port0_WORD    word0
4165 #define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT   17
4166 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK    0x0000001
4167 #define lpfc_acqe_fc_la_trunk_link_status_port1_WORD    word0
4168 #define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT   18
4169 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK    0x0000001
4170 #define lpfc_acqe_fc_la_trunk_link_status_port2_WORD    word0
4171 #define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT   19
4172 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK    0x0000001
4173 #define lpfc_acqe_fc_la_trunk_link_status_port3_WORD    word0
4174 #define lpfc_acqe_fc_la_trunk_config_port0_SHIFT        20
4175 #define lpfc_acqe_fc_la_trunk_config_port0_MASK         0x0000001
4176 #define lpfc_acqe_fc_la_trunk_config_port0_WORD         word0
4177 #define lpfc_acqe_fc_la_trunk_config_port1_SHIFT        21
4178 #define lpfc_acqe_fc_la_trunk_config_port1_MASK         0x0000001
4179 #define lpfc_acqe_fc_la_trunk_config_port1_WORD         word0
4180 #define lpfc_acqe_fc_la_trunk_config_port2_SHIFT        22
4181 #define lpfc_acqe_fc_la_trunk_config_port2_MASK         0x0000001
4182 #define lpfc_acqe_fc_la_trunk_config_port2_WORD         word0
4183 #define lpfc_acqe_fc_la_trunk_config_port3_SHIFT        23
4184 #define lpfc_acqe_fc_la_trunk_config_port3_MASK         0x0000001
4185 #define lpfc_acqe_fc_la_trunk_config_port3_WORD         word0
4186         uint32_t word1;
4187 #define lpfc_acqe_fc_la_llink_spd_SHIFT         16
4188 #define lpfc_acqe_fc_la_llink_spd_MASK          0x0000FFFF
4189 #define lpfc_acqe_fc_la_llink_spd_WORD          word1
4190 #define lpfc_acqe_fc_la_fault_SHIFT             0
4191 #define lpfc_acqe_fc_la_fault_MASK              0x000000FF
4192 #define lpfc_acqe_fc_la_fault_WORD              word1
4193 #define lpfc_acqe_fc_la_trunk_fault_SHIFT               0
4194 #define lpfc_acqe_fc_la_trunk_fault_MASK                0x0000000F
4195 #define lpfc_acqe_fc_la_trunk_fault_WORD                word1
4196 #define lpfc_acqe_fc_la_trunk_linkmask_SHIFT            4
4197 #define lpfc_acqe_fc_la_trunk_linkmask_MASK             0x000000F
4198 #define lpfc_acqe_fc_la_trunk_linkmask_WORD             word1
4199 #define LPFC_FC_LA_FAULT_NONE           0x0
4200 #define LPFC_FC_LA_FAULT_LOCAL          0x1
4201 #define LPFC_FC_LA_FAULT_REMOTE         0x2
4202         uint32_t event_tag;
4203         uint32_t trailer;
4204 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK           0x1
4205 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK       0x2
4206 };
4207
4208 struct lpfc_acqe_misconfigured_event {
4209         struct {
4210         uint32_t word0;
4211 #define lpfc_sli_misconfigured_port0_state_SHIFT        0
4212 #define lpfc_sli_misconfigured_port0_state_MASK         0x000000FF
4213 #define lpfc_sli_misconfigured_port0_state_WORD         word0
4214 #define lpfc_sli_misconfigured_port1_state_SHIFT        8
4215 #define lpfc_sli_misconfigured_port1_state_MASK         0x000000FF
4216 #define lpfc_sli_misconfigured_port1_state_WORD         word0
4217 #define lpfc_sli_misconfigured_port2_state_SHIFT        16
4218 #define lpfc_sli_misconfigured_port2_state_MASK         0x000000FF
4219 #define lpfc_sli_misconfigured_port2_state_WORD         word0
4220 #define lpfc_sli_misconfigured_port3_state_SHIFT        24
4221 #define lpfc_sli_misconfigured_port3_state_MASK         0x000000FF
4222 #define lpfc_sli_misconfigured_port3_state_WORD         word0
4223         uint32_t word1;
4224 #define lpfc_sli_misconfigured_port0_op_SHIFT           0
4225 #define lpfc_sli_misconfigured_port0_op_MASK            0x00000001
4226 #define lpfc_sli_misconfigured_port0_op_WORD            word1
4227 #define lpfc_sli_misconfigured_port0_severity_SHIFT     1
4228 #define lpfc_sli_misconfigured_port0_severity_MASK      0x00000003
4229 #define lpfc_sli_misconfigured_port0_severity_WORD      word1
4230 #define lpfc_sli_misconfigured_port1_op_SHIFT           8
4231 #define lpfc_sli_misconfigured_port1_op_MASK            0x00000001
4232 #define lpfc_sli_misconfigured_port1_op_WORD            word1
4233 #define lpfc_sli_misconfigured_port1_severity_SHIFT     9
4234 #define lpfc_sli_misconfigured_port1_severity_MASK      0x00000003
4235 #define lpfc_sli_misconfigured_port1_severity_WORD      word1
4236 #define lpfc_sli_misconfigured_port2_op_SHIFT           16
4237 #define lpfc_sli_misconfigured_port2_op_MASK            0x00000001
4238 #define lpfc_sli_misconfigured_port2_op_WORD            word1
4239 #define lpfc_sli_misconfigured_port2_severity_SHIFT     17
4240 #define lpfc_sli_misconfigured_port2_severity_MASK      0x00000003
4241 #define lpfc_sli_misconfigured_port2_severity_WORD      word1
4242 #define lpfc_sli_misconfigured_port3_op_SHIFT           24
4243 #define lpfc_sli_misconfigured_port3_op_MASK            0x00000001
4244 #define lpfc_sli_misconfigured_port3_op_WORD            word1
4245 #define lpfc_sli_misconfigured_port3_severity_SHIFT     25
4246 #define lpfc_sli_misconfigured_port3_severity_MASK      0x00000003
4247 #define lpfc_sli_misconfigured_port3_severity_WORD      word1
4248         } theEvent;
4249 #define LPFC_SLI_EVENT_STATUS_VALID                     0x00
4250 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT       0x01
4251 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE        0x02
4252 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED       0x03
4253 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED       0x04
4254 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED       0x05
4255 };
4256
4257 struct lpfc_acqe_cgn_signal {
4258         u32 word0;
4259 #define lpfc_warn_acqe_SHIFT            0
4260 #define lpfc_warn_acqe_MASK             0x7FFFFFFF
4261 #define lpfc_warn_acqe_WORD             word0
4262 #define lpfc_imm_acqe_SHIFT             31
4263 #define lpfc_imm_acqe_MASK              0x1
4264 #define lpfc_imm_acqe_WORD              word0
4265         u32 alarm_cnt;
4266         u32 word2;
4267         u32 trailer;
4268 };
4269
4270 struct lpfc_acqe_sli {
4271         uint32_t event_data1;
4272         uint32_t event_data2;
4273         uint32_t reserved;
4274         uint32_t trailer;
4275 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR          0x1
4276 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP           0x2
4277 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP           0x3
4278 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST          0x4
4279 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP           0x5
4280 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED       0x9
4281 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT        0xA
4282 #define LPFC_SLI_EVENT_TYPE_PORT_PARAMS_CHG     0xE
4283 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN       0xF
4284 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE      0x10
4285 #define LPFC_SLI_EVENT_TYPE_CGN_SIGNAL          0x11
4286 };
4287
4288 /*
4289  * Define the bootstrap mailbox (bmbx) region used to communicate
4290  * mailbox command between the host and port. The mailbox consists
4291  * of a payload area of 256 bytes and a completion queue of length
4292  * 16 bytes.
4293  */
4294 struct lpfc_bmbx_create {
4295         struct lpfc_mqe mqe;
4296         struct lpfc_mcqe mcqe;
4297 };
4298
4299 #define SGL_ALIGN_SZ 64
4300 #define SGL_PAGE_SIZE 4096
4301 /* align SGL addr on a size boundary - adjust address up */
4302 #define NO_XRI  0xffff
4303
4304 struct wqe_common {
4305         uint32_t word6;
4306 #define wqe_xri_tag_SHIFT     0
4307 #define wqe_xri_tag_MASK      0x0000FFFF
4308 #define wqe_xri_tag_WORD      word6
4309 #define wqe_ctxt_tag_SHIFT    16
4310 #define wqe_ctxt_tag_MASK     0x0000FFFF
4311 #define wqe_ctxt_tag_WORD     word6
4312         uint32_t word7;
4313 #define wqe_dif_SHIFT         0
4314 #define wqe_dif_MASK          0x00000003
4315 #define wqe_dif_WORD          word7
4316 #define LPFC_WQE_DIF_PASSTHRU   1
4317 #define LPFC_WQE_DIF_STRIP      2
4318 #define LPFC_WQE_DIF_INSERT     3
4319 #define wqe_ct_SHIFT          2
4320 #define wqe_ct_MASK           0x00000003
4321 #define wqe_ct_WORD           word7
4322 #define wqe_status_SHIFT      4
4323 #define wqe_status_MASK       0x0000000f
4324 #define wqe_status_WORD       word7
4325 #define wqe_cmnd_SHIFT        8
4326 #define wqe_cmnd_MASK         0x000000ff
4327 #define wqe_cmnd_WORD         word7
4328 #define wqe_class_SHIFT       16
4329 #define wqe_class_MASK        0x00000007
4330 #define wqe_class_WORD        word7
4331 #define wqe_ar_SHIFT          19
4332 #define wqe_ar_MASK           0x00000001
4333 #define wqe_ar_WORD           word7
4334 #define wqe_ag_SHIFT          wqe_ar_SHIFT
4335 #define wqe_ag_MASK           wqe_ar_MASK
4336 #define wqe_ag_WORD           wqe_ar_WORD
4337 #define wqe_pu_SHIFT          20
4338 #define wqe_pu_MASK           0x00000003
4339 #define wqe_pu_WORD           word7
4340 #define wqe_erp_SHIFT         22
4341 #define wqe_erp_MASK          0x00000001
4342 #define wqe_erp_WORD          word7
4343 #define wqe_conf_SHIFT        wqe_erp_SHIFT
4344 #define wqe_conf_MASK         wqe_erp_MASK
4345 #define wqe_conf_WORD         wqe_erp_WORD
4346 #define wqe_lnk_SHIFT         23
4347 #define wqe_lnk_MASK          0x00000001
4348 #define wqe_lnk_WORD          word7
4349 #define wqe_tmo_SHIFT         24
4350 #define wqe_tmo_MASK          0x000000ff
4351 #define wqe_tmo_WORD          word7
4352         uint32_t abort_tag; /* word 8 in WQE */
4353         uint32_t word9;
4354 #define wqe_reqtag_SHIFT      0
4355 #define wqe_reqtag_MASK       0x0000FFFF
4356 #define wqe_reqtag_WORD       word9
4357 #define wqe_temp_rpi_SHIFT    16
4358 #define wqe_temp_rpi_MASK     0x0000FFFF
4359 #define wqe_temp_rpi_WORD     word9
4360 #define wqe_rcvoxid_SHIFT     16
4361 #define wqe_rcvoxid_MASK      0x0000FFFF
4362 #define wqe_rcvoxid_WORD      word9
4363 #define wqe_sof_SHIFT         24
4364 #define wqe_sof_MASK          0x000000FF
4365 #define wqe_sof_WORD          word9
4366 #define wqe_eof_SHIFT         16
4367 #define wqe_eof_MASK          0x000000FF
4368 #define wqe_eof_WORD          word9
4369         uint32_t word10;
4370 #define wqe_ebde_cnt_SHIFT    0
4371 #define wqe_ebde_cnt_MASK     0x0000000f
4372 #define wqe_ebde_cnt_WORD     word10
4373 #define wqe_xchg_SHIFT        4
4374 #define wqe_xchg_MASK         0x00000001
4375 #define wqe_xchg_WORD         word10
4376 #define LPFC_SCSI_XCHG        0x0
4377 #define LPFC_NVME_XCHG        0x1
4378 #define wqe_appid_SHIFT       5
4379 #define wqe_appid_MASK        0x00000001
4380 #define wqe_appid_WORD        word10
4381 #define wqe_oas_SHIFT         6
4382 #define wqe_oas_MASK          0x00000001
4383 #define wqe_oas_WORD          word10
4384 #define wqe_lenloc_SHIFT      7
4385 #define wqe_lenloc_MASK       0x00000003
4386 #define wqe_lenloc_WORD       word10
4387 #define LPFC_WQE_LENLOC_NONE            0
4388 #define LPFC_WQE_LENLOC_WORD3   1
4389 #define LPFC_WQE_LENLOC_WORD12  2
4390 #define LPFC_WQE_LENLOC_WORD4   3
4391 #define wqe_qosd_SHIFT        9
4392 #define wqe_qosd_MASK         0x00000001
4393 #define wqe_qosd_WORD         word10
4394 #define wqe_xbl_SHIFT         11
4395 #define wqe_xbl_MASK          0x00000001
4396 #define wqe_xbl_WORD          word10
4397 #define wqe_iod_SHIFT         13
4398 #define wqe_iod_MASK          0x00000001
4399 #define wqe_iod_WORD          word10
4400 #define LPFC_WQE_IOD_NONE       0
4401 #define LPFC_WQE_IOD_WRITE      0
4402 #define LPFC_WQE_IOD_READ       1
4403 #define wqe_dbde_SHIFT        14
4404 #define wqe_dbde_MASK         0x00000001
4405 #define wqe_dbde_WORD         word10
4406 #define wqe_wqes_SHIFT        15
4407 #define wqe_wqes_MASK         0x00000001
4408 #define wqe_wqes_WORD         word10
4409 /* Note that this field overlaps above fields */
4410 #define wqe_wqid_SHIFT        1
4411 #define wqe_wqid_MASK         0x00007fff
4412 #define wqe_wqid_WORD         word10
4413 #define wqe_pri_SHIFT         16
4414 #define wqe_pri_MASK          0x00000007
4415 #define wqe_pri_WORD          word10
4416 #define wqe_pv_SHIFT          19
4417 #define wqe_pv_MASK           0x00000001
4418 #define wqe_pv_WORD           word10
4419 #define wqe_xc_SHIFT          21
4420 #define wqe_xc_MASK           0x00000001
4421 #define wqe_xc_WORD           word10
4422 #define wqe_sr_SHIFT          22
4423 #define wqe_sr_MASK           0x00000001
4424 #define wqe_sr_WORD           word10
4425 #define wqe_ccpe_SHIFT        23
4426 #define wqe_ccpe_MASK         0x00000001
4427 #define wqe_ccpe_WORD         word10
4428 #define wqe_ccp_SHIFT         24
4429 #define wqe_ccp_MASK          0x000000ff
4430 #define wqe_ccp_WORD          word10
4431         uint32_t word11;
4432 #define wqe_cmd_type_SHIFT    0
4433 #define wqe_cmd_type_MASK     0x0000000f
4434 #define wqe_cmd_type_WORD     word11
4435 #define wqe_els_id_SHIFT      4
4436 #define wqe_els_id_MASK       0x00000003
4437 #define wqe_els_id_WORD       word11
4438 #define LPFC_ELS_ID_FLOGI       3
4439 #define LPFC_ELS_ID_FDISC       2
4440 #define LPFC_ELS_ID_LOGO        1
4441 #define LPFC_ELS_ID_DEFAULT     0
4442 #define wqe_irsp_SHIFT        4
4443 #define wqe_irsp_MASK         0x00000001
4444 #define wqe_irsp_WORD         word11
4445 #define wqe_pbde_SHIFT        5
4446 #define wqe_pbde_MASK         0x00000001
4447 #define wqe_pbde_WORD         word11
4448 #define wqe_sup_SHIFT         6
4449 #define wqe_sup_MASK          0x00000001
4450 #define wqe_sup_WORD          word11
4451 #define wqe_wqec_SHIFT        7
4452 #define wqe_wqec_MASK         0x00000001
4453 #define wqe_wqec_WORD         word11
4454 #define wqe_irsplen_SHIFT     8
4455 #define wqe_irsplen_MASK      0x0000000f
4456 #define wqe_irsplen_WORD      word11
4457 #define wqe_cqid_SHIFT        16
4458 #define wqe_cqid_MASK         0x0000ffff
4459 #define wqe_cqid_WORD         word11
4460 #define LPFC_WQE_CQ_ID_DEFAULT  0xffff
4461 };
4462
4463 struct wqe_did {
4464         uint32_t word5;
4465 #define wqe_els_did_SHIFT         0
4466 #define wqe_els_did_MASK          0x00FFFFFF
4467 #define wqe_els_did_WORD          word5
4468 #define wqe_xmit_bls_pt_SHIFT         28
4469 #define wqe_xmit_bls_pt_MASK          0x00000003
4470 #define wqe_xmit_bls_pt_WORD          word5
4471 #define wqe_xmit_bls_ar_SHIFT         30
4472 #define wqe_xmit_bls_ar_MASK          0x00000001
4473 #define wqe_xmit_bls_ar_WORD          word5
4474 #define wqe_xmit_bls_xo_SHIFT         31
4475 #define wqe_xmit_bls_xo_MASK          0x00000001
4476 #define wqe_xmit_bls_xo_WORD          word5
4477 };
4478
4479 struct lpfc_wqe_generic{
4480         struct ulp_bde64 bde;
4481         uint32_t word3;
4482         uint32_t word4;
4483         uint32_t word5;
4484         struct wqe_common wqe_com;
4485         uint32_t payload[4];
4486 };
4487
4488 struct els_request64_wqe {
4489         struct ulp_bde64 bde;
4490         uint32_t payload_len;
4491         uint32_t word4;
4492 #define els_req64_sid_SHIFT         0
4493 #define els_req64_sid_MASK          0x00FFFFFF
4494 #define els_req64_sid_WORD          word4
4495 #define els_req64_sp_SHIFT          24
4496 #define els_req64_sp_MASK           0x00000001
4497 #define els_req64_sp_WORD           word4
4498 #define els_req64_vf_SHIFT          25
4499 #define els_req64_vf_MASK           0x00000001
4500 #define els_req64_vf_WORD           word4
4501         struct wqe_did  wqe_dest;
4502         struct wqe_common wqe_com; /* words 6-11 */
4503         uint32_t word12;
4504 #define els_req64_vfid_SHIFT        1
4505 #define els_req64_vfid_MASK         0x00000FFF
4506 #define els_req64_vfid_WORD         word12
4507 #define els_req64_pri_SHIFT         13
4508 #define els_req64_pri_MASK          0x00000007
4509 #define els_req64_pri_WORD          word12
4510         uint32_t word13;
4511 #define els_req64_hopcnt_SHIFT      24
4512 #define els_req64_hopcnt_MASK       0x000000ff
4513 #define els_req64_hopcnt_WORD       word13
4514         uint32_t word14;
4515         uint32_t max_response_payload_len;
4516 };
4517
4518 struct xmit_els_rsp64_wqe {
4519         struct ulp_bde64 bde;
4520         uint32_t response_payload_len;
4521         uint32_t word4;
4522 #define els_rsp64_sid_SHIFT         0
4523 #define els_rsp64_sid_MASK          0x00FFFFFF
4524 #define els_rsp64_sid_WORD          word4
4525 #define els_rsp64_sp_SHIFT          24
4526 #define els_rsp64_sp_MASK           0x00000001
4527 #define els_rsp64_sp_WORD           word4
4528         struct wqe_did wqe_dest;
4529         struct wqe_common wqe_com; /* words 6-11 */
4530         uint32_t word12;
4531 #define wqe_rsp_temp_rpi_SHIFT    0
4532 #define wqe_rsp_temp_rpi_MASK     0x0000FFFF
4533 #define wqe_rsp_temp_rpi_WORD     word12
4534         uint32_t rsvd_13_15[3];
4535 };
4536
4537 struct xmit_bls_rsp64_wqe {
4538         uint32_t payload0;
4539 /* Payload0 for BA_ACC */
4540 #define xmit_bls_rsp64_acc_seq_id_SHIFT        16
4541 #define xmit_bls_rsp64_acc_seq_id_MASK         0x000000ff
4542 #define xmit_bls_rsp64_acc_seq_id_WORD         payload0
4543 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT   24
4544 #define xmit_bls_rsp64_acc_seq_id_vald_MASK    0x000000ff
4545 #define xmit_bls_rsp64_acc_seq_id_vald_WORD    payload0
4546 /* Payload0 for BA_RJT */
4547 #define xmit_bls_rsp64_rjt_vspec_SHIFT   0
4548 #define xmit_bls_rsp64_rjt_vspec_MASK    0x000000ff
4549 #define xmit_bls_rsp64_rjt_vspec_WORD    payload0
4550 #define xmit_bls_rsp64_rjt_expc_SHIFT    8
4551 #define xmit_bls_rsp64_rjt_expc_MASK     0x000000ff
4552 #define xmit_bls_rsp64_rjt_expc_WORD     payload0
4553 #define xmit_bls_rsp64_rjt_rsnc_SHIFT    16
4554 #define xmit_bls_rsp64_rjt_rsnc_MASK     0x000000ff
4555 #define xmit_bls_rsp64_rjt_rsnc_WORD     payload0
4556         uint32_t word1;
4557 #define xmit_bls_rsp64_rxid_SHIFT  0
4558 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
4559 #define xmit_bls_rsp64_rxid_WORD   word1
4560 #define xmit_bls_rsp64_oxid_SHIFT  16
4561 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
4562 #define xmit_bls_rsp64_oxid_WORD   word1
4563         uint32_t word2;
4564 #define xmit_bls_rsp64_seqcnthi_SHIFT  0
4565 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
4566 #define xmit_bls_rsp64_seqcnthi_WORD   word2
4567 #define xmit_bls_rsp64_seqcntlo_SHIFT  16
4568 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
4569 #define xmit_bls_rsp64_seqcntlo_WORD   word2
4570         uint32_t rsrvd3;
4571         uint32_t rsrvd4;
4572         struct wqe_did  wqe_dest;
4573         struct wqe_common wqe_com; /* words 6-11 */
4574         uint32_t word12;
4575 #define xmit_bls_rsp64_temprpi_SHIFT  0
4576 #define xmit_bls_rsp64_temprpi_MASK   0x0000ffff
4577 #define xmit_bls_rsp64_temprpi_WORD   word12
4578         uint32_t rsvd_13_15[3];
4579 };
4580
4581 struct wqe_rctl_dfctl {
4582         uint32_t word5;
4583 #define wqe_si_SHIFT 2
4584 #define wqe_si_MASK  0x000000001
4585 #define wqe_si_WORD  word5
4586 #define wqe_la_SHIFT 3
4587 #define wqe_la_MASK  0x000000001
4588 #define wqe_la_WORD  word5
4589 #define wqe_xo_SHIFT    6
4590 #define wqe_xo_MASK     0x000000001
4591 #define wqe_xo_WORD     word5
4592 #define wqe_ls_SHIFT 7
4593 #define wqe_ls_MASK  0x000000001
4594 #define wqe_ls_WORD  word5
4595 #define wqe_dfctl_SHIFT 8
4596 #define wqe_dfctl_MASK  0x0000000ff
4597 #define wqe_dfctl_WORD  word5
4598 #define wqe_type_SHIFT 16
4599 #define wqe_type_MASK  0x0000000ff
4600 #define wqe_type_WORD  word5
4601 #define wqe_rctl_SHIFT 24
4602 #define wqe_rctl_MASK  0x0000000ff
4603 #define wqe_rctl_WORD  word5
4604 };
4605
4606 struct xmit_seq64_wqe {
4607         struct ulp_bde64 bde;
4608         uint32_t rsvd3;
4609         uint32_t relative_offset;
4610         struct wqe_rctl_dfctl wge_ctl;
4611         struct wqe_common wqe_com; /* words 6-11 */
4612         uint32_t xmit_len;
4613         uint32_t rsvd_12_15[3];
4614 };
4615 struct xmit_bcast64_wqe {
4616         struct ulp_bde64 bde;
4617         uint32_t seq_payload_len;
4618         uint32_t rsvd4;
4619         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4620         struct wqe_common wqe_com;     /* words 6-11 */
4621         uint32_t rsvd_12_15[4];
4622 };
4623
4624 struct gen_req64_wqe {
4625         struct ulp_bde64 bde;
4626         uint32_t request_payload_len;
4627         uint32_t relative_offset;
4628         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4629         struct wqe_common wqe_com;     /* words 6-11 */
4630         uint32_t rsvd_12_14[3];
4631         uint32_t max_response_payload_len;
4632 };
4633
4634 /* Define NVME PRLI request to fabric. NVME is a
4635  * fabric-only protocol.
4636  * Updated to red-lined v1.08 on Sept 16, 2016
4637  */
4638 struct lpfc_nvme_prli {
4639         uint32_t word1;
4640         /* The Response Code is defined in the FCP PRLI lpfc_hw.h */
4641 #define prli_acc_rsp_code_SHIFT         8
4642 #define prli_acc_rsp_code_MASK          0x0000000f
4643 #define prli_acc_rsp_code_WORD          word1
4644 #define prli_estabImagePair_SHIFT       13
4645 #define prli_estabImagePair_MASK        0x00000001
4646 #define prli_estabImagePair_WORD        word1
4647 #define prli_type_code_ext_SHIFT        16
4648 #define prli_type_code_ext_MASK         0x000000ff
4649 #define prli_type_code_ext_WORD         word1
4650 #define prli_type_code_SHIFT            24
4651 #define prli_type_code_MASK             0x000000ff
4652 #define prli_type_code_WORD             word1
4653         uint32_t word_rsvd2;
4654         uint32_t word_rsvd3;
4655
4656         uint32_t word4;
4657 #define prli_fba_SHIFT                  0
4658 #define prli_fba_MASK                   0x00000001
4659 #define prli_fba_WORD                   word4
4660 #define prli_disc_SHIFT                 3
4661 #define prli_disc_MASK                  0x00000001
4662 #define prli_disc_WORD                  word4
4663 #define prli_tgt_SHIFT                  4
4664 #define prli_tgt_MASK                   0x00000001
4665 #define prli_tgt_WORD                   word4
4666 #define prli_init_SHIFT                 5
4667 #define prli_init_MASK                  0x00000001
4668 #define prli_init_WORD                  word4
4669 #define prli_conf_SHIFT                 7
4670 #define prli_conf_MASK                  0x00000001
4671 #define prli_conf_WORD                  word4
4672 #define prli_nsler_SHIFT                8
4673 #define prli_nsler_MASK                 0x00000001
4674 #define prli_nsler_WORD                 word4
4675         uint32_t word5;
4676 #define prli_fb_sz_SHIFT                0
4677 #define prli_fb_sz_MASK                 0x0000ffff
4678 #define prli_fb_sz_WORD                 word5
4679 #define LPFC_NVMET_FB_SZ_MAX  65536   /* Driver target mode only. */
4680 };
4681
4682 struct create_xri_wqe {
4683         uint32_t rsrvd[5];           /* words 0-4 */
4684         struct wqe_did  wqe_dest;  /* word 5 */
4685         struct wqe_common wqe_com; /* words 6-11 */
4686         uint32_t rsvd_12_15[4];         /* word 12-15 */
4687 };
4688
4689 #define INHIBIT_ABORT 1
4690 #define T_REQUEST_TAG 3
4691 #define T_XRI_TAG 1
4692
4693 struct cmf_sync_wqe {
4694         uint32_t rsrvd[3];
4695         uint32_t word3;
4696 #define cmf_sync_interval_SHIFT 0
4697 #define cmf_sync_interval_MASK  0x00000ffff
4698 #define cmf_sync_interval_WORD  word3
4699 #define cmf_sync_afpin_SHIFT    16
4700 #define cmf_sync_afpin_MASK     0x000000001
4701 #define cmf_sync_afpin_WORD     word3
4702 #define cmf_sync_asig_SHIFT     17
4703 #define cmf_sync_asig_MASK      0x000000001
4704 #define cmf_sync_asig_WORD      word3
4705 #define cmf_sync_op_SHIFT       20
4706 #define cmf_sync_op_MASK        0x00000000f
4707 #define cmf_sync_op_WORD        word3
4708 #define cmf_sync_ver_SHIFT      24
4709 #define cmf_sync_ver_MASK       0x0000000ff
4710 #define cmf_sync_ver_WORD       word3
4711 #define LPFC_CMF_SYNC_VER       1
4712         uint32_t event_tag;
4713         uint32_t word5;
4714 #define cmf_sync_wsigmax_SHIFT  0
4715 #define cmf_sync_wsigmax_MASK   0x00000ffff
4716 #define cmf_sync_wsigmax_WORD   word5
4717 #define cmf_sync_wsigcnt_SHIFT  16
4718 #define cmf_sync_wsigcnt_MASK   0x00000ffff
4719 #define cmf_sync_wsigcnt_WORD   word5
4720         uint32_t word6;
4721         uint32_t word7;
4722 #define cmf_sync_cmnd_SHIFT     8
4723 #define cmf_sync_cmnd_MASK      0x0000000ff
4724 #define cmf_sync_cmnd_WORD      word7
4725         uint32_t word8;
4726         uint32_t word9;
4727 #define cmf_sync_reqtag_SHIFT   0
4728 #define cmf_sync_reqtag_MASK    0x00000ffff
4729 #define cmf_sync_reqtag_WORD    word9
4730 #define cmf_sync_wfpinmax_SHIFT 16
4731 #define cmf_sync_wfpinmax_MASK  0x0000000ff
4732 #define cmf_sync_wfpinmax_WORD  word9
4733 #define cmf_sync_wfpincnt_SHIFT 24
4734 #define cmf_sync_wfpincnt_MASK  0x0000000ff
4735 #define cmf_sync_wfpincnt_WORD  word9
4736         uint32_t word10;
4737 #define cmf_sync_qosd_SHIFT     9
4738 #define cmf_sync_qosd_MASK      0x00000001
4739 #define cmf_sync_qosd_WORD      word10
4740         uint32_t word11;
4741 #define cmf_sync_cmd_type_SHIFT 0
4742 #define cmf_sync_cmd_type_MASK  0x0000000f
4743 #define cmf_sync_cmd_type_WORD  word11
4744 #define cmf_sync_wqec_SHIFT     7
4745 #define cmf_sync_wqec_MASK      0x00000001
4746 #define cmf_sync_wqec_WORD      word11
4747 #define cmf_sync_cqid_SHIFT     16
4748 #define cmf_sync_cqid_MASK      0x0000ffff
4749 #define cmf_sync_cqid_WORD      word11
4750         uint32_t read_bytes;
4751         uint32_t word13;
4752         uint32_t word14;
4753         uint32_t word15;
4754 };
4755
4756 struct abort_cmd_wqe {
4757         uint32_t rsrvd[3];
4758         uint32_t word3;
4759 #define abort_cmd_ia_SHIFT  0
4760 #define abort_cmd_ia_MASK  0x000000001
4761 #define abort_cmd_ia_WORD  word3
4762 #define abort_cmd_criteria_SHIFT  8
4763 #define abort_cmd_criteria_MASK  0x0000000ff
4764 #define abort_cmd_criteria_WORD  word3
4765         uint32_t rsrvd4;
4766         uint32_t rsrvd5;
4767         struct wqe_common wqe_com;     /* words 6-11 */
4768         uint32_t rsvd_12_15[4];         /* word 12-15 */
4769 };
4770
4771 struct fcp_iwrite64_wqe {
4772         struct ulp_bde64 bde;
4773         uint32_t word3;
4774 #define cmd_buff_len_SHIFT  16
4775 #define cmd_buff_len_MASK  0x00000ffff
4776 #define cmd_buff_len_WORD  word3
4777 #define payload_offset_len_SHIFT 0
4778 #define payload_offset_len_MASK 0x0000ffff
4779 #define payload_offset_len_WORD word3
4780         uint32_t total_xfer_len;
4781         uint32_t initial_xfer_len;
4782         struct wqe_common wqe_com;     /* words 6-11 */
4783         uint32_t rsrvd12;
4784         struct ulp_bde64 ph_bde;       /* words 13-15 */
4785 };
4786
4787 struct fcp_iread64_wqe {
4788         struct ulp_bde64 bde;
4789         uint32_t word3;
4790 #define cmd_buff_len_SHIFT  16
4791 #define cmd_buff_len_MASK  0x00000ffff
4792 #define cmd_buff_len_WORD  word3
4793 #define payload_offset_len_SHIFT 0
4794 #define payload_offset_len_MASK 0x0000ffff
4795 #define payload_offset_len_WORD word3
4796         uint32_t total_xfer_len;       /* word 4 */
4797         uint32_t rsrvd5;               /* word 5 */
4798         struct wqe_common wqe_com;     /* words 6-11 */
4799         uint32_t rsrvd12;
4800         struct ulp_bde64 ph_bde;       /* words 13-15 */
4801 };
4802
4803 struct fcp_icmnd64_wqe {
4804         struct ulp_bde64 bde;          /* words 0-2 */
4805         uint32_t word3;
4806 #define cmd_buff_len_SHIFT  16
4807 #define cmd_buff_len_MASK  0x00000ffff
4808 #define cmd_buff_len_WORD  word3
4809 #define payload_offset_len_SHIFT 0
4810 #define payload_offset_len_MASK 0x0000ffff
4811 #define payload_offset_len_WORD word3
4812         uint32_t rsrvd4;               /* word 4 */
4813         uint32_t rsrvd5;               /* word 5 */
4814         struct wqe_common wqe_com;     /* words 6-11 */
4815         uint32_t rsvd_12_15[4];        /* word 12-15 */
4816 };
4817
4818 struct fcp_trsp64_wqe {
4819         struct ulp_bde64 bde;
4820         uint32_t response_len;
4821         uint32_t rsvd_4_5[2];
4822         struct wqe_common wqe_com;      /* words 6-11 */
4823         uint32_t rsvd_12_15[4];         /* word 12-15 */
4824 };
4825
4826 struct fcp_tsend64_wqe {
4827         struct ulp_bde64 bde;
4828         uint32_t payload_offset_len;
4829         uint32_t relative_offset;
4830         uint32_t reserved;
4831         struct wqe_common wqe_com;     /* words 6-11 */
4832         uint32_t fcp_data_len;         /* word 12 */
4833         uint32_t rsvd_13_15[3];        /* word 13-15 */
4834 };
4835
4836 struct fcp_treceive64_wqe {
4837         struct ulp_bde64 bde;
4838         uint32_t payload_offset_len;
4839         uint32_t relative_offset;
4840         uint32_t reserved;
4841         struct wqe_common wqe_com;     /* words 6-11 */
4842         uint32_t fcp_data_len;         /* word 12 */
4843         uint32_t rsvd_13_15[3];        /* word 13-15 */
4844 };
4845 #define TXRDY_PAYLOAD_LEN      12
4846
4847 #define CMD_SEND_FRAME  0xE1
4848
4849 struct send_frame_wqe {
4850         struct ulp_bde64 bde;          /* words 0-2 */
4851         uint32_t frame_len;            /* word 3 */
4852         uint32_t fc_hdr_wd0;           /* word 4 */
4853         uint32_t fc_hdr_wd1;           /* word 5 */
4854         struct wqe_common wqe_com;     /* words 6-11 */
4855         uint32_t fc_hdr_wd2;           /* word 12 */
4856         uint32_t fc_hdr_wd3;           /* word 13 */
4857         uint32_t fc_hdr_wd4;           /* word 14 */
4858         uint32_t fc_hdr_wd5;           /* word 15 */
4859 };
4860
4861 #define ELS_RDF_REG_TAG_CNT             4
4862 struct lpfc_els_rdf_reg_desc {
4863         struct fc_df_desc_fpin_reg      reg_desc;       /* descriptor header */
4864         __be32                          desc_tags[ELS_RDF_REG_TAG_CNT];
4865                                                         /* tags in reg_desc */
4866 };
4867
4868 struct lpfc_els_rdf_req {
4869         struct fc_els_rdf               rdf;       /* hdr up to descriptors */
4870         struct lpfc_els_rdf_reg_desc    reg_d1; /* 1st descriptor */
4871 };
4872
4873 struct lpfc_els_rdf_rsp {
4874         struct fc_els_rdf_resp          rdf_resp;  /* hdr up to descriptors */
4875         struct lpfc_els_rdf_reg_desc    reg_d1; /* 1st descriptor */
4876 };
4877
4878 union lpfc_wqe {
4879         uint32_t words[16];
4880         struct lpfc_wqe_generic generic;
4881         struct fcp_icmnd64_wqe fcp_icmd;
4882         struct fcp_iread64_wqe fcp_iread;
4883         struct fcp_iwrite64_wqe fcp_iwrite;
4884         struct abort_cmd_wqe abort_cmd;
4885         struct cmf_sync_wqe cmf_sync;
4886         struct create_xri_wqe create_xri;
4887         struct xmit_bcast64_wqe xmit_bcast64;
4888         struct xmit_seq64_wqe xmit_sequence;
4889         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4890         struct xmit_els_rsp64_wqe xmit_els_rsp;
4891         struct els_request64_wqe els_req;
4892         struct gen_req64_wqe gen_req;
4893         struct fcp_trsp64_wqe fcp_trsp;
4894         struct fcp_tsend64_wqe fcp_tsend;
4895         struct fcp_treceive64_wqe fcp_treceive;
4896         struct send_frame_wqe send_frame;
4897 };
4898
4899 union lpfc_wqe128 {
4900         uint32_t words[32];
4901         struct lpfc_wqe_generic generic;
4902         struct fcp_icmnd64_wqe fcp_icmd;
4903         struct fcp_iread64_wqe fcp_iread;
4904         struct fcp_iwrite64_wqe fcp_iwrite;
4905         struct abort_cmd_wqe abort_cmd;
4906         struct cmf_sync_wqe cmf_sync;
4907         struct create_xri_wqe create_xri;
4908         struct xmit_bcast64_wqe xmit_bcast64;
4909         struct xmit_seq64_wqe xmit_sequence;
4910         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4911         struct xmit_els_rsp64_wqe xmit_els_rsp;
4912         struct els_request64_wqe els_req;
4913         struct gen_req64_wqe gen_req;
4914         struct fcp_trsp64_wqe fcp_trsp;
4915         struct fcp_tsend64_wqe fcp_tsend;
4916         struct fcp_treceive64_wqe fcp_treceive;
4917         struct send_frame_wqe send_frame;
4918 };
4919
4920 #define MAGIC_NUMBER_G6 0xFEAA0003
4921 #define MAGIC_NUMBER_G7 0xFEAA0005
4922 #define MAGIC_NUMBER_G7P 0xFEAA0020
4923
4924 struct lpfc_grp_hdr {
4925         uint32_t size;
4926         uint32_t magic_number;
4927         uint32_t word2;
4928 #define lpfc_grp_hdr_file_type_SHIFT    24
4929 #define lpfc_grp_hdr_file_type_MASK     0x000000FF
4930 #define lpfc_grp_hdr_file_type_WORD     word2
4931 #define lpfc_grp_hdr_id_SHIFT           16
4932 #define lpfc_grp_hdr_id_MASK            0x000000FF
4933 #define lpfc_grp_hdr_id_WORD            word2
4934         uint8_t rev_name[128];
4935         uint8_t date[12];
4936         uint8_t revision[32];
4937 };
4938
4939 /* Defines for WQE command type */
4940 #define FCP_COMMAND             0x0
4941 #define NVME_READ_CMD           0x0
4942 #define FCP_COMMAND_DATA_OUT    0x1
4943 #define NVME_WRITE_CMD          0x1
4944 #define COMMAND_DATA_IN         0x0
4945 #define COMMAND_DATA_OUT        0x1
4946 #define FCP_COMMAND_TRECEIVE    0x2
4947 #define FCP_COMMAND_TRSP        0x3
4948 #define FCP_COMMAND_TSEND       0x7
4949 #define OTHER_COMMAND           0x8
4950 #define CMF_SYNC_COMMAND        0xA
4951 #define ELS_COMMAND_NON_FIP     0xC
4952 #define ELS_COMMAND_FIP         0xD
4953
4954 #define LPFC_NVME_EMBED_CMD     0x0
4955 #define LPFC_NVME_EMBED_WRITE   0x1
4956 #define LPFC_NVME_EMBED_READ    0x2
4957
4958 /* WQE Commands */
4959 #define CMD_ABORT_XRI_WQE       0x0F
4960 #define CMD_XMIT_SEQUENCE64_WQE 0x82
4961 #define CMD_XMIT_BCAST64_WQE    0x84
4962 #define CMD_ELS_REQUEST64_WQE   0x8A
4963 #define CMD_XMIT_ELS_RSP64_WQE  0x95
4964 #define CMD_XMIT_BLS_RSP64_WQE  0x97
4965 #define CMD_FCP_IWRITE64_WQE    0x98
4966 #define CMD_FCP_IREAD64_WQE     0x9A
4967 #define CMD_FCP_ICMND64_WQE     0x9C
4968 #define CMD_FCP_TSEND64_WQE     0x9F
4969 #define CMD_FCP_TRECEIVE64_WQE  0xA1
4970 #define CMD_FCP_TRSP64_WQE      0xA3
4971 #define CMD_GEN_REQUEST64_WQE   0xC2
4972 #define CMD_CMF_SYNC_WQE        0xE8
4973
4974 #define CMD_WQE_MASK            0xff
4975
4976
4977 #define LPFC_FW_DUMP    1
4978 #define LPFC_FW_RESET   2
4979 #define LPFC_DV_RESET   3
4980
4981 /* On some kernels, enum fc_ls_tlv_dtag does not have
4982  * these 2 enums defined, on other kernels it does.
4983  * To get aound this we need to add these 2 defines here.
4984  */
4985 #ifndef ELS_DTAG_LNK_FAULT_CAP
4986 #define ELS_DTAG_LNK_FAULT_CAP        0x0001000D
4987 #endif
4988 #ifndef ELS_DTAG_CG_SIGNAL_CAP
4989 #define ELS_DTAG_CG_SIGNAL_CAP        0x0001000F
4990 #endif
4991
4992 /*
4993  * Initializer useful for decoding FPIN string table.
4994  */
4995 #define FC_FPIN_CONGN_SEVERITY_INIT {                           \
4996         { FPIN_CONGN_SEVERITY_WARNING,          "Warning" },    \
4997         { FPIN_CONGN_SEVERITY_ERROR,            "Alarm" },      \
4998 }
4999
5000 /* EDC supports two descriptors.  When allocated, it is the
5001  * size of this structure plus each supported descriptor.
5002  */
5003 struct lpfc_els_edc_req {
5004         struct fc_els_edc               edc;       /* hdr up to descriptors */
5005         struct fc_diag_cg_sig_desc      cgn_desc;  /* 1st descriptor */
5006 };
5007
5008 /* Minimum structure defines for the EDC response.
5009  * Balance is in buffer.
5010  */
5011 struct lpfc_els_edc_rsp {
5012         struct fc_els_edc_resp          edc_rsp;   /* hdr up to descriptors */
5013         struct fc_diag_cg_sig_desc      cgn_desc;  /* 1st descriptor */
5014 };
5015
5016 /* Used for logging FPIN messages */
5017 #define LPFC_FPIN_WWPN_LINE_SZ  128
5018 #define LPFC_FPIN_WWPN_LINE_CNT 6
5019 #define LPFC_FPIN_WWPN_NUM_LINE 6