drivers/scsi/isci/host.c

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * BSD LICENSE
  25  *
  26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27  * All rights reserved.
  28  *
  29  * Redistribution and use in source and binary forms, with or without
  30  * modification, are permitted provided that the following conditions
  31  * are met:
  32  *
  33  *   * Redistributions of source code must retain the above copyright
  34  *     notice, this list of conditions and the following disclaimer.
  35  *   * Redistributions in binary form must reproduce the above copyright
  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *   * Neither the name of Intel Corporation nor the names of its
  40  *     contributors may be used to endorse or promote products derived
  41  *     from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  */
  55 #include <linux/circ_buf.h>
  56 #include <linux/device.h>
  57 #include <scsi/sas.h>
  58 #include "host.h"
  59 #include "isci.h"
  60 #include "port.h"
  61 #include "probe_roms.h"
  62 #include "remote_device.h"
  63 #include "request.h"
  64 #include "scu_completion_codes.h"
  65 #include "scu_event_codes.h"
  66 #include "registers.h"
  67 #include "scu_remote_node_context.h"
  68 #include "scu_task_context.h"
  69
  70 #define SCU_CONTEXT_RAM_INIT_STALL_TIME      200
  71
  72 #define smu_max_ports(dcc_value) \
  73         (\
  74                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
  75                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
  76         )
  77
  78 #define smu_max_task_contexts(dcc_value)        \
  79         (\
  80                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
  81                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
  82         )
  83
  84 #define smu_max_rncs(dcc_value) \
  85         (\
  86                 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
  87                  >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
  88         )
  89
  90 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT      100
  91
  92 /**
  93  *
  94  *
  95  * The number of milliseconds to wait while a given phy is consuming power
  96  * before allowing another set of phys to consume power. Ultimately, this will
  97  * be specified by OEM parameter.
  98  */
  99 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
 100
 101 /**
 102  * NORMALIZE_PUT_POINTER() -
 103  *
 104  * This macro will normalize the completion queue put pointer so its value can
 105  * be used as an array inde
 106  */
 107 #define NORMALIZE_PUT_POINTER(x) \
 108         ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
 109
 110
 111 /**
 112  * NORMALIZE_EVENT_POINTER() -
 113  *
 114  * This macro will normalize the completion queue event entry so its value can
 115  * be used as an index.
 116  */
 117 #define NORMALIZE_EVENT_POINTER(x) \
 118         (\
 119                 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
 120                 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
 121         )
 122
 123 /**
 124  * NORMALIZE_GET_POINTER() -
 125  *
 126  * This macro will normalize the completion queue get pointer so its value can
 127  * be used as an index into an array
 128  */
 129 #define NORMALIZE_GET_POINTER(x) \
 130         ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
 131
 132 /**
 133  * NORMALIZE_GET_POINTER_CYCLE_BIT() -
 134  *
 135  * This macro will normalize the completion queue cycle pointer so it matches
 136  * the completion queue cycle bit
 137  */
 138 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
 139         ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
 140
 141 /**
 142  * COMPLETION_QUEUE_CYCLE_BIT() -
 143  *
 144  * This macro will return the cycle bit of the completion queue entry
 145  */
 146 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
 147
 148 /* Init the state machine and call the state entry function (if any) */
 149 void sci_init_sm(struct sci_base_state_machine *sm,
 150                  const struct sci_base_state *state_table, u32 initial_state)
 151 {
 152         sci_state_transition_t handler;
 153
 154         sm->initial_state_id    = initial_state;
 155         sm->previous_state_id   = initial_state;
 156         sm->current_state_id    = initial_state;
 157         sm->state_table         = state_table;
 158
 159         handler = sm->state_table[initial_state].enter_state;
 160         if (handler)
 161                 handler(sm);
 162 }
 163
 164 /* Call the state exit fn, update the current state, call the state entry fn */
 165 void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
 166 {
 167         sci_state_transition_t handler;
 168
 169         handler = sm->state_table[sm->current_state_id].exit_state;
 170         if (handler)
 171                 handler(sm);
 172
 173         sm->previous_state_id = sm->current_state_id;
 174         sm->current_state_id = next_state;
 175
 176         handler = sm->state_table[sm->current_state_id].enter_state;
 177         if (handler)
 178                 handler(sm);
 179 }
 180
 181 static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost)
 182 {
 183         u32 get_value = ihost->completion_queue_get;
 184         u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
 185
 186         if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
 187             COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]))
 188                 return true;
 189
 190         return false;
 191 }
 192
 193 static bool sci_controller_isr(struct isci_host *ihost)
 194 {
 195         if (sci_controller_completion_queue_has_entries(ihost))
 196                 return true;
 197
 198         /* we have a spurious interrupt it could be that we have already
 199          * emptied the completion queue from a previous interrupt
 200          * FIXME: really!?
 201          */
 202         writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
 203
 204         /* There is a race in the hardware that could cause us not to be
 205          * notified of an interrupt completion if we do not take this
 206          * step.  We will mask then unmask the interrupts so if there is
 207          * another interrupt pending the clearing of the interrupt
 208          * source we get the next interrupt message.
 209          */
 210         spin_lock(&ihost->scic_lock);
 211         if (test_bit(IHOST_IRQ_ENABLED, &ihost->flags)) {
 212                 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
 213                 writel(0, &ihost->smu_registers->interrupt_mask);
 214         }
 215         spin_unlock(&ihost->scic_lock);
 216
 217         return false;
 218 }
 219
 220 irqreturn_t isci_msix_isr(int vec, void *data)
 221 {
 222         struct isci_host *ihost = data;
 223
 224         if (sci_controller_isr(ihost))
 225                 tasklet_schedule(&ihost->completion_tasklet);
 226
 227         return IRQ_HANDLED;
 228 }
 229
 230 static bool sci_controller_error_isr(struct isci_host *ihost)
 231 {
 232         u32 interrupt_status;
 233
 234         interrupt_status =
 235                 readl(&ihost->smu_registers->interrupt_status);
 236         interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
 237
 238         if (interrupt_status != 0) {
 239                 /*
 240                  * There is an error interrupt pending so let it through and handle
 241                  * in the callback */
 242                 return true;
 243         }
 244
 245         /*
 246          * There is a race in the hardware that could cause us not to be notified
 247          * of an interrupt completion if we do not take this step.  We will mask
 248          * then unmask the error interrupts so if there was another interrupt
 249          * pending we will be notified.
 250          * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
 251         writel(0xff, &ihost->smu_registers->interrupt_mask);
 252         writel(0, &ihost->smu_registers->interrupt_mask);
 253
 254         return false;
 255 }
 256
 257 static void sci_controller_task_completion(struct isci_host *ihost, u32 ent)
 258 {
 259         u32 index = SCU_GET_COMPLETION_INDEX(ent);
 260         struct isci_request *ireq = ihost->reqs[index];
 261
 262         /* Make sure that we really want to process this IO request */
 263         if (test_bit(IREQ_ACTIVE, &ireq->flags) &&
 264             ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
 265             ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index])
 266                 /* Yep this is a valid io request pass it along to the
 267                  * io request handler
 268                  */
 269                 sci_io_request_tc_completion(ireq, ent);
 270 }
 271
 272 static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent)
 273 {
 274         u32 index;
 275         struct isci_request *ireq;
 276         struct isci_remote_device *idev;
 277
 278         index = SCU_GET_COMPLETION_INDEX(ent);
 279
 280         switch (scu_get_command_request_type(ent)) {
 281         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
 282         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
 283                 ireq = ihost->reqs[index];
 284                 dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n",
 285                          __func__, ent, ireq);
 286                 /* @todo For a post TC operation we need to fail the IO
 287                  * request
 288                  */
 289                 break;
 290         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
 291         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
 292         case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
 293                 idev = ihost->device_table[index];
 294                 dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n",
 295                          __func__, ent, idev);
 296                 /* @todo For a port RNC operation we need to fail the
 297                  * device
 298                  */
 299                 break;
 300         default:
 301                 dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n",
 302                          __func__, ent);
 303                 break;
 304         }
 305 }
 306
 307 static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent)
 308 {
 309         u32 index;
 310         u32 frame_index;
 311
 312         struct scu_unsolicited_frame_header *frame_header;
 313         struct isci_phy *iphy;
 314         struct isci_remote_device *idev;
 315
 316         enum sci_status result = SCI_FAILURE;
 317
 318         frame_index = SCU_GET_FRAME_INDEX(ent);
 319
 320         frame_header = ihost->uf_control.buffers.array[frame_index].header;
 321         ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
 322
 323         if (SCU_GET_FRAME_ERROR(ent)) {
 324                 /*
 325                  * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
 326                  * /       this cause a problem? We expect the phy initialization will
 327                  * /       fail if there is an error in the frame. */
 328                 sci_controller_release_frame(ihost, frame_index);
 329                 return;
 330         }
 331
 332         if (frame_header->is_address_frame) {
 333                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
 334                 iphy = &ihost->phys[index];
 335                 result = sci_phy_frame_handler(iphy, frame_index);
 336         } else {
 337
 338                 index = SCU_GET_COMPLETION_INDEX(ent);
 339
 340                 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
 341                         /*
 342                          * This is a signature fis or a frame from a direct attached SATA
 343                          * device that has not yet been created.  In either case forwared
 344                          * the frame to the PE and let it take care of the frame data. */
 345                         index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
 346                         iphy = &ihost->phys[index];
 347                         result = sci_phy_frame_handler(iphy, frame_index);
 348                 } else {
 349                         if (index < ihost->remote_node_entries)
 350                                 idev = ihost->device_table[index];
 351                         else
 352                                 idev = NULL;
 353
 354                         if (idev != NULL)
 355                                 result = sci_remote_device_frame_handler(idev, frame_index);
 356                         else
 357                                 sci_controller_release_frame(ihost, frame_index);
 358                 }
 359         }
 360
 361         if (result != SCI_SUCCESS) {
 362                 /*
 363                  * / @todo Is there any reason to report some additional error message
 364                  * /       when we get this failure notifiction? */
 365         }
 366 }
 367
 368 static void sci_controller_event_completion(struct isci_host *ihost, u32 ent)
 369 {
 370         struct isci_remote_device *idev;
 371         struct isci_request *ireq;
 372         struct isci_phy *iphy;
 373         u32 index;
 374
 375         index = SCU_GET_COMPLETION_INDEX(ent);
 376
 377         switch (scu_get_event_type(ent)) {
 378         case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
 379                 /* / @todo The driver did something wrong and we need to fix the condtion. */
 380                 dev_err(&ihost->pdev->dev,
 381                         "%s: SCIC Controller 0x%p received SMU command error "
 382                         "0x%x\n",
 383                         __func__,
 384                         ihost,
 385                         ent);
 386                 break;
 387
 388         case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
 389         case SCU_EVENT_TYPE_SMU_ERROR:
 390         case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
 391                 /*
 392                  * / @todo This is a hardware failure and its likely that we want to
 393                  * /       reset the controller. */
 394                 dev_err(&ihost->pdev->dev,
 395                         "%s: SCIC Controller 0x%p received fatal controller "
 396                         "event  0x%x\n",
 397                         __func__,
 398                         ihost,
 399                         ent);
 400                 break;
 401
 402         case SCU_EVENT_TYPE_TRANSPORT_ERROR:
 403                 ireq = ihost->reqs[index];
 404                 sci_io_request_event_handler(ireq, ent);
 405                 break;
 406
 407         case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
 408                 switch (scu_get_event_specifier(ent)) {
 409                 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
 410                 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
 411                         ireq = ihost->reqs[index];
 412                         if (ireq != NULL)
 413                                 sci_io_request_event_handler(ireq, ent);
 414                         else
 415                                 dev_warn(&ihost->pdev->dev,
 416                                          "%s: SCIC Controller 0x%p received "
 417                                          "event 0x%x for io request object "
 418                                          "that doesnt exist.\n",
 419                                          __func__,
 420                                          ihost,
 421                                          ent);
 422
 423                         break;
 424
 425                 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
 426                         idev = ihost->device_table[index];
 427                         if (idev != NULL)
 428                                 sci_remote_device_event_handler(idev, ent);
 429                         else
 430                                 dev_warn(&ihost->pdev->dev,
 431                                          "%s: SCIC Controller 0x%p received "
 432                                          "event 0x%x for remote device object "
 433                                          "that doesnt exist.\n",
 434                                          __func__,
 435                                          ihost,
 436                                          ent);
 437
 438                         break;
 439                 }
 440                 break;
 441
 442         case SCU_EVENT_TYPE_BROADCAST_CHANGE:
 443         /*
 444          * direct the broadcast change event to the phy first and then let
 445          * the phy redirect the broadcast change to the port object */
 446         case SCU_EVENT_TYPE_ERR_CNT_EVENT:
 447         /*
 448          * direct error counter event to the phy object since that is where
 449          * we get the event notification.  This is a type 4 event. */
 450         case SCU_EVENT_TYPE_OSSP_EVENT:
 451                 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
 452                 iphy = &ihost->phys[index];
 453                 sci_phy_event_handler(iphy, ent);
 454                 break;
 455
 456         case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
 457         case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
 458         case SCU_EVENT_TYPE_RNC_OPS_MISC:
 459                 if (index < ihost->remote_node_entries) {
 460                         idev = ihost->device_table[index];
 461
 462                         if (idev != NULL)
 463                                 sci_remote_device_event_handler(idev, ent);
 464                 } else
 465                         dev_err(&ihost->pdev->dev,
 466                                 "%s: SCIC Controller 0x%p received event 0x%x "
 467                                 "for remote device object 0x%0x that doesnt "
 468                                 "exist.\n",
 469                                 __func__,
 470                                 ihost,
 471                                 ent,
 472                                 index);
 473
 474                 break;
 475
 476         default:
 477                 dev_warn(&ihost->pdev->dev,
 478                          "%s: SCIC Controller received unknown event code %x\n",
 479                          __func__,
 480                          ent);
 481                 break;
 482         }
 483 }
 484
 485 static void sci_controller_process_completions(struct isci_host *ihost)
 486 {
 487         u32 completion_count = 0;
 488         u32 ent;
 489         u32 get_index;
 490         u32 get_cycle;
 491         u32 event_get;
 492         u32 event_cycle;
 493
 494         dev_dbg(&ihost->pdev->dev,
 495                 "%s: completion queue begining get:0x%08x\n",
 496                 __func__,
 497                 ihost->completion_queue_get);
 498
 499         /* Get the component parts of the completion queue */
 500         get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get);
 501         get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get;
 502
 503         event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get);
 504         event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get;
 505
 506         while (
 507                 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
 508                 == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])
 509                 ) {
 510                 completion_count++;
 511
 512                 ent = ihost->completion_queue[get_index];
 513
 514                 /* increment the get pointer and check for rollover to toggle the cycle bit */
 515                 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
 516                              (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
 517                 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
 518
 519                 dev_dbg(&ihost->pdev->dev,
 520                         "%s: completion queue entry:0x%08x\n",
 521                         __func__,
 522                         ent);
 523
 524                 switch (SCU_GET_COMPLETION_TYPE(ent)) {
 525                 case SCU_COMPLETION_TYPE_TASK:
 526                         sci_controller_task_completion(ihost, ent);
 527                         break;
 528
 529                 case SCU_COMPLETION_TYPE_SDMA:
 530                         sci_controller_sdma_completion(ihost, ent);
 531                         break;
 532
 533                 case SCU_COMPLETION_TYPE_UFI:
 534                         sci_controller_unsolicited_frame(ihost, ent);
 535                         break;
 536
 537                 case SCU_COMPLETION_TYPE_EVENT:
 538                         sci_controller_event_completion(ihost, ent);
 539                         break;
 540
 541                 case SCU_COMPLETION_TYPE_NOTIFY: {
 542                         event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) <<
 543                                        (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
 544                         event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
 545
 546                         sci_controller_event_completion(ihost, ent);
 547                         break;
 548                 }
 549                 default:
 550                         dev_warn(&ihost->pdev->dev,
 551                                  "%s: SCIC Controller received unknown "
 552                                  "completion type %x\n",
 553                                  __func__,
 554                                  ent);
 555                         break;
 556                 }
 557         }
 558
 559         /* Update the get register if we completed one or more entries */
 560         if (completion_count > 0) {
 561                 ihost->completion_queue_get =
 562                         SMU_CQGR_GEN_BIT(ENABLE) |
 563                         SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
 564                         event_cycle |
 565                         SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) |
 566                         get_cycle |
 567                         SMU_CQGR_GEN_VAL(POINTER, get_index);
 568
 569                 writel(ihost->completion_queue_get,
 570                        &ihost->smu_registers->completion_queue_get);
 571
 572         }
 573
 574         dev_dbg(&ihost->pdev->dev,
 575                 "%s: completion queue ending get:0x%08x\n",
 576                 __func__,
 577                 ihost->completion_queue_get);
 578
 579 }
 580
 581 static void sci_controller_error_handler(struct isci_host *ihost)
 582 {
 583         u32 interrupt_status;
 584
 585         interrupt_status =
 586                 readl(&ihost->smu_registers->interrupt_status);
 587
 588         if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
 589             sci_controller_completion_queue_has_entries(ihost)) {
 590
 591                 sci_controller_process_completions(ihost);
 592                 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
 593         } else {
 594                 dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__,
 595                         interrupt_status);
 596
 597                 sci_change_state(&ihost->sm, SCIC_FAILED);
 598
 599                 return;
 600         }
 601
 602         /* If we dont process any completions I am not sure that we want to do this.
 603          * We are in the middle of a hardware fault and should probably be reset.
 604          */
 605         writel(0, &ihost->smu_registers->interrupt_mask);
 606 }
 607
 608 irqreturn_t isci_intx_isr(int vec, void *data)
 609 {
 610         irqreturn_t ret = IRQ_NONE;
 611         struct isci_host *ihost = data;
 612
 613         if (sci_controller_isr(ihost)) {
 614                 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
 615                 tasklet_schedule(&ihost->completion_tasklet);
 616                 ret = IRQ_HANDLED;
 617         } else if (sci_controller_error_isr(ihost)) {
 618                 spin_lock(&ihost->scic_lock);
 619                 sci_controller_error_handler(ihost);
 620                 spin_unlock(&ihost->scic_lock);
 621                 ret = IRQ_HANDLED;
 622         }
 623
 624         return ret;
 625 }
 626
 627 irqreturn_t isci_error_isr(int vec, void *data)
 628 {
 629         struct isci_host *ihost = data;
 630
 631         if (sci_controller_error_isr(ihost))
 632                 sci_controller_error_handler(ihost);
 633
 634         return IRQ_HANDLED;
 635 }
 636
 637 /**
 638  * isci_host_start_complete() - This function is called by the core library,
 639  *    through the ISCI Module, to indicate controller start status.
 640  * @isci_host: This parameter specifies the ISCI host object
 641  * @completion_status: This parameter specifies the completion status from the
 642  *    core library.
 643  *
 644  */
 645 static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
 646 {
 647         if (completion_status != SCI_SUCCESS)
 648                 dev_info(&ihost->pdev->dev,
 649                         "controller start timed out, continuing...\n");
 650         clear_bit(IHOST_START_PENDING, &ihost->flags);
 651         wake_up(&ihost->eventq);
 652 }
 653
 654 int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
 655 {
 656         struct sas_ha_struct *ha = SHOST_TO_SAS_HA(shost);
 657         struct isci_host *ihost = ha->lldd_ha;
 658
 659         if (test_bit(IHOST_START_PENDING, &ihost->flags))
 660                 return 0;
 661
 662         sas_drain_work(ha);
 663
 664         return 1;
 665 }
 666
 667 /**
 668  * sci_controller_get_suggested_start_timeout() - This method returns the
 669  *    suggested sci_controller_start() timeout amount.  The user is free to
 670  *    use any timeout value, but this method provides the suggested minimum
 671  *    start timeout value.  The returned value is based upon empirical
 672  *    information determined as a result of interoperability testing.
 673  * @controller: the handle to the controller object for which to return the
 674  *    suggested start timeout.
 675  *
 676  * This method returns the number of milliseconds for the suggested start
 677  * operation timeout.
 678  */
 679 static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost)
 680 {
 681         /* Validate the user supplied parameters. */
 682         if (!ihost)
 683                 return 0;
 684
 685         /*
 686          * The suggested minimum timeout value for a controller start operation:
 687          *
 688          *     Signature FIS Timeout
 689          *   + Phy Start Timeout
 690          *   + Number of Phy Spin Up Intervals
 691          *   ---------------------------------
 692          *   Number of milliseconds for the controller start operation.
 693          *
 694          * NOTE: The number of phy spin up intervals will be equivalent
 695          *       to the number of phys divided by the number phys allowed
 696          *       per interval - 1 (once OEM parameters are supported).
 697          *       Currently we assume only 1 phy per interval. */
 698
 699         return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
 700                 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
 701                 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
 702 }
 703
 704 static void sci_controller_enable_interrupts(struct isci_host *ihost)
 705 {
 706         set_bit(IHOST_IRQ_ENABLED, &ihost->flags);
 707         writel(0, &ihost->smu_registers->interrupt_mask);
 708 }
 709
 710 void sci_controller_disable_interrupts(struct isci_host *ihost)
 711 {
 712         clear_bit(IHOST_IRQ_ENABLED, &ihost->flags);
 713         writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
 714         readl(&ihost->smu_registers->interrupt_mask); /* flush */
 715 }
 716
 717 static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost)
 718 {
 719         u32 port_task_scheduler_value;
 720
 721         port_task_scheduler_value =
 722                 readl(&ihost->scu_registers->peg0.ptsg.control);
 723         port_task_scheduler_value |=
 724                 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
 725                  SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
 726         writel(port_task_scheduler_value,
 727                &ihost->scu_registers->peg0.ptsg.control);
 728 }
 729
 730 static void sci_controller_assign_task_entries(struct isci_host *ihost)
 731 {
 732         u32 task_assignment;
 733
 734         /*
 735          * Assign all the TCs to function 0
 736          * TODO: Do we actually need to read this register to write it back?
 737          */
 738
 739         task_assignment =
 740                 readl(&ihost->smu_registers->task_context_assignment[0]);
 741
 742         task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
 743                 (SMU_TCA_GEN_VAL(ENDING,  ihost->task_context_entries - 1)) |
 744                 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
 745
 746         writel(task_assignment,
 747                 &ihost->smu_registers->task_context_assignment[0]);
 748
 749 }
 750
 751 static void sci_controller_initialize_completion_queue(struct isci_host *ihost)
 752 {
 753         u32 index;
 754         u32 completion_queue_control_value;
 755         u32 completion_queue_get_value;
 756         u32 completion_queue_put_value;
 757
 758         ihost->completion_queue_get = 0;
 759
 760         completion_queue_control_value =
 761                 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
 762                  SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
 763
 764         writel(completion_queue_control_value,
 765                &ihost->smu_registers->completion_queue_control);
 766
 767
 768         /* Set the completion queue get pointer and enable the queue */
 769         completion_queue_get_value = (
 770                 (SMU_CQGR_GEN_VAL(POINTER, 0))
 771                 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
 772                 | (SMU_CQGR_GEN_BIT(ENABLE))
 773                 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
 774                 );
 775
 776         writel(completion_queue_get_value,
 777                &ihost->smu_registers->completion_queue_get);
 778
 779         /* Set the completion queue put pointer */
 780         completion_queue_put_value = (
 781                 (SMU_CQPR_GEN_VAL(POINTER, 0))
 782                 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
 783                 );
 784
 785         writel(completion_queue_put_value,
 786                &ihost->smu_registers->completion_queue_put);
 787
 788         /* Initialize the cycle bit of the completion queue entries */
 789         for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
 790                 /*
 791                  * If get.cycle_bit != completion_queue.cycle_bit
 792                  * its not a valid completion queue entry
 793                  * so at system start all entries are invalid */
 794                 ihost->completion_queue[index] = 0x80000000;
 795         }
 796 }
 797
 798 static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost)
 799 {
 800         u32 frame_queue_control_value;
 801         u32 frame_queue_get_value;
 802         u32 frame_queue_put_value;
 803
 804         /* Write the queue size */
 805         frame_queue_control_value =
 806                 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
 807
 808         writel(frame_queue_control_value,
 809                &ihost->scu_registers->sdma.unsolicited_frame_queue_control);
 810
 811         /* Setup the get pointer for the unsolicited frame queue */
 812         frame_queue_get_value = (
 813                 SCU_UFQGP_GEN_VAL(POINTER, 0)
 814                 |  SCU_UFQGP_GEN_BIT(ENABLE_BIT)
 815                 );
 816
 817         writel(frame_queue_get_value,
 818                &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
 819         /* Setup the put pointer for the unsolicited frame queue */
 820         frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
 821         writel(frame_queue_put_value,
 822                &ihost->scu_registers->sdma.unsolicited_frame_put_pointer);
 823 }
 824
 825 void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status)
 826 {
 827         if (ihost->sm.current_state_id == SCIC_STARTING) {
 828                 /*
 829                  * We move into the ready state, because some of the phys/ports
 830                  * may be up and operational.
 831                  */
 832                 sci_change_state(&ihost->sm, SCIC_READY);
 833
 834                 isci_host_start_complete(ihost, status);
 835         }
 836 }
 837
 838 static bool is_phy_starting(struct isci_phy *iphy)
 839 {
 840         enum sci_phy_states state;
 841
 842         state = iphy->sm.current_state_id;
 843         switch (state) {
 844         case SCI_PHY_STARTING:
 845         case SCI_PHY_SUB_INITIAL:
 846         case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
 847         case SCI_PHY_SUB_AWAIT_IAF_UF:
 848         case SCI_PHY_SUB_AWAIT_SAS_POWER:
 849         case SCI_PHY_SUB_AWAIT_SATA_POWER:
 850         case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
 851         case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
 852         case SCI_PHY_SUB_AWAIT_OSSP_EN:
 853         case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
 854         case SCI_PHY_SUB_FINAL:
 855                 return true;
 856         default:
 857                 return false;
 858         }
 859 }
 860
 861 bool is_controller_start_complete(struct isci_host *ihost)
 862 {
 863         int i;
 864
 865         for (i = 0; i < SCI_MAX_PHYS; i++) {
 866                 struct isci_phy *iphy = &ihost->phys[i];
 867                 u32 state = iphy->sm.current_state_id;
 868
 869                 /* in apc mode we need to check every phy, in
 870                  * mpc mode we only need to check phys that have
 871                  * been configured into a port
 872                  */
 873                 if (is_port_config_apc(ihost))
 874                         /* pass */;
 875                 else if (!phy_get_non_dummy_port(iphy))
 876                         continue;
 877
 878                 /* The controller start operation is complete iff:
 879                  * - all links have been given an opportunity to start
 880                  * - have no indication of a connected device
 881                  * - have an indication of a connected device and it has
 882                  *   finished the link training process.
 883                  */
 884                 if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) ||
 885                     (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) ||
 886                     (iphy->is_in_link_training == true && is_phy_starting(iphy)) ||
 887                     (ihost->port_agent.phy_ready_mask != ihost->port_agent.phy_configured_mask))
 888                         return false;
 889         }
 890
 891         return true;
 892 }
 893
 894 /**
 895  * sci_controller_start_next_phy - start phy
 896  * @scic: controller
 897  *
 898  * If all the phys have been started, then attempt to transition the
 899  * controller to the READY state and inform the user
 900  * (sci_cb_controller_start_complete()).
 901  */
 902 static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost)
 903 {
 904         struct sci_oem_params *oem = &ihost->oem_parameters;
 905         struct isci_phy *iphy;
 906         enum sci_status status;
 907
 908         status = SCI_SUCCESS;
 909
 910         if (ihost->phy_startup_timer_pending)
 911                 return status;
 912
 913         if (ihost->next_phy_to_start >= SCI_MAX_PHYS) {
 914                 if (is_controller_start_complete(ihost)) {
 915                         sci_controller_transition_to_ready(ihost, SCI_SUCCESS);
 916                         sci_del_timer(&ihost->phy_timer);
 917                         ihost->phy_startup_timer_pending = false;
 918                 }
 919         } else {
 920                 iphy = &ihost->phys[ihost->next_phy_to_start];
 921
 922                 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
 923                         if (phy_get_non_dummy_port(iphy) == NULL) {
 924                                 ihost->next_phy_to_start++;
 925
 926                                 /* Caution recursion ahead be forwarned
 927                                  *
 928                                  * The PHY was never added to a PORT in MPC mode
 929                                  * so start the next phy in sequence This phy
 930                                  * will never go link up and will not draw power
 931                                  * the OEM parameters either configured the phy
 932                                  * incorrectly for the PORT or it was never
 933                                  * assigned to a PORT
 934                                  */
 935                                 return sci_controller_start_next_phy(ihost);
 936                         }
 937                 }
 938
 939                 status = sci_phy_start(iphy);
 940
 941                 if (status == SCI_SUCCESS) {
 942                         sci_mod_timer(&ihost->phy_timer,
 943                                       SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
 944                         ihost->phy_startup_timer_pending = true;
 945                 } else {
 946                         dev_warn(&ihost->pdev->dev,
 947                                  "%s: Controller stop operation failed "
 948                                  "to stop phy %d because of status "
 949                                  "%d.\n",
 950                                  __func__,
 951                                  ihost->phys[ihost->next_phy_to_start].phy_index,
 952                                  status);
 953                 }
 954
 955                 ihost->next_phy_to_start++;
 956         }
 957
 958         return status;
 959 }
 960
 961 static void phy_startup_timeout(unsigned long data)
 962 {
 963         struct sci_timer *tmr = (struct sci_timer *)data;
 964         struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer);
 965         unsigned long flags;
 966         enum sci_status status;
 967
 968         spin_lock_irqsave(&ihost->scic_lock, flags);
 969
 970         if (tmr->cancel)
 971                 goto done;
 972
 973         ihost->phy_startup_timer_pending = false;
 974
 975         do {
 976                 status = sci_controller_start_next_phy(ihost);
 977         } while (status != SCI_SUCCESS);
 978
 979 done:
 980         spin_unlock_irqrestore(&ihost->scic_lock, flags);
 981 }
 982
 983 static u16 isci_tci_active(struct isci_host *ihost)
 984 {
 985         return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
 986 }
 987
 988 static enum sci_status sci_controller_start(struct isci_host *ihost,
 989                                              u32 timeout)
 990 {
 991         enum sci_status result;
 992         u16 index;
 993
 994         if (ihost->sm.current_state_id != SCIC_INITIALIZED) {
 995                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
 996                          __func__, ihost->sm.current_state_id);
 997                 return SCI_FAILURE_INVALID_STATE;
 998         }
 999
1000         /* Build the TCi free pool */
1001         BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
1002         ihost->tci_head = 0;
1003         ihost->tci_tail = 0;
1004         for (index = 0; index < ihost->task_context_entries; index++)
1005                 isci_tci_free(ihost, index);
1006
1007         /* Build the RNi free pool */
1008         sci_remote_node_table_initialize(&ihost->available_remote_nodes,
1009                                          ihost->remote_node_entries);
1010
1011         /*
1012          * Before anything else lets make sure we will not be
1013          * interrupted by the hardware.
1014          */
1015         sci_controller_disable_interrupts(ihost);
1016
1017         /* Enable the port task scheduler */
1018         sci_controller_enable_port_task_scheduler(ihost);
1019
1020         /* Assign all the task entries to ihost physical function */
1021         sci_controller_assign_task_entries(ihost);
1022
1023         /* Now initialize the completion queue */
1024         sci_controller_initialize_completion_queue(ihost);
1025
1026         /* Initialize the unsolicited frame queue for use */
1027         sci_controller_initialize_unsolicited_frame_queue(ihost);
1028
1029         /* Start all of the ports on this controller */
1030         for (index = 0; index < ihost->logical_port_entries; index++) {
1031                 struct isci_port *iport = &ihost->ports[index];
1032
1033                 result = sci_port_start(iport);
1034                 if (result)
1035                         return result;
1036         }
1037
1038         sci_controller_start_next_phy(ihost);
1039
1040         sci_mod_timer(&ihost->timer, timeout);
1041
1042         sci_change_state(&ihost->sm, SCIC_STARTING);
1043
1044         return SCI_SUCCESS;
1045 }
1046
1047 void isci_host_scan_start(struct Scsi_Host *shost)
1048 {
1049         struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
1050         unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost);
1051
1052         set_bit(IHOST_START_PENDING, &ihost->flags);
1053
1054         spin_lock_irq(&ihost->scic_lock);
1055         sci_controller_start(ihost, tmo);
1056         sci_controller_enable_interrupts(ihost);
1057         spin_unlock_irq(&ihost->scic_lock);
1058 }
1059
1060 static void isci_host_stop_complete(struct isci_host *ihost)
1061 {
1062         sci_controller_disable_interrupts(ihost);
1063         clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1064         wake_up(&ihost->eventq);
1065 }
1066
1067 static void sci_controller_completion_handler(struct isci_host *ihost)
1068 {
1069         /* Empty out the completion queue */
1070         if (sci_controller_completion_queue_has_entries(ihost))
1071                 sci_controller_process_completions(ihost);
1072
1073         /* Clear the interrupt and enable all interrupts again */
1074         writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
1075         /* Could we write the value of SMU_ISR_COMPLETION? */
1076         writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
1077         writel(0, &ihost->smu_registers->interrupt_mask);
1078 }
1079
1080 void ireq_done(struct isci_host *ihost, struct isci_request *ireq, struct sas_task *task)
1081 {
1082         task->lldd_task = NULL;
1083         if (!test_bit(IREQ_ABORT_PATH_ACTIVE, &ireq->flags) &&
1084             !(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1085                 if (test_bit(IREQ_COMPLETE_IN_TARGET, &ireq->flags)) {
1086                         /* Normal notification (task_done) */
1087                         dev_dbg(&ihost->pdev->dev,
1088                                 "%s: Normal - ireq/task = %p/%p\n",
1089                                 __func__, ireq, task);
1090
1091                         task->task_done(task);
1092                 } else {
1093                         dev_dbg(&ihost->pdev->dev,
1094                                 "%s: Error - ireq/task = %p/%p\n",
1095                                 __func__, ireq, task);
1096
1097                         sas_task_abort(task);
1098                 }
1099         }
1100         if (test_and_clear_bit(IREQ_ABORT_PATH_ACTIVE, &ireq->flags))
1101                 wake_up_all(&ihost->eventq);
1102
1103         if (!test_bit(IREQ_NO_AUTO_FREE_TAG, &ireq->flags))
1104                 isci_free_tag(ihost, ireq->io_tag);
1105 }
1106 /**
1107  * isci_host_completion_routine() - This function is the delayed service
1108  *    routine that calls the sci core library's completion handler. It's
1109  *    scheduled as a tasklet from the interrupt service routine when interrupts
1110  *    in use, or set as the timeout function in polled mode.
1111  * @data: This parameter specifies the ISCI host object
1112  *
1113  */
1114 void isci_host_completion_routine(unsigned long data)
1115 {
1116         struct isci_host *ihost = (struct isci_host *)data;
1117         u16 active;
1118
1119         spin_lock_irq(&ihost->scic_lock);
1120         sci_controller_completion_handler(ihost);
1121         spin_unlock_irq(&ihost->scic_lock);
1122
1123         /* the coalesence timeout doubles at each encoding step, so
1124          * update it based on the ilog2 value of the outstanding requests
1125          */
1126         active = isci_tci_active(ihost);
1127         writel(SMU_ICC_GEN_VAL(NUMBER, active) |
1128                SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)),
1129                &ihost->smu_registers->interrupt_coalesce_control);
1130 }
1131
1132 /**
1133  * sci_controller_stop() - This method will stop an individual controller
1134  *    object.This method will invoke the associated user callback upon
1135  *    completion.  The completion callback is called when the following
1136  *    conditions are met: -# the method return status is SCI_SUCCESS. -# the
1137  *    controller has been quiesced. This method will ensure that all IO
1138  *    requests are quiesced, phys are stopped, and all additional operation by
1139  *    the hardware is halted.
1140  * @controller: the handle to the controller object to stop.
1141  * @timeout: This parameter specifies the number of milliseconds in which the
1142  *    stop operation should complete.
1143  *
1144  * The controller must be in the STARTED or STOPPED state. Indicate if the
1145  * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1146  * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1147  * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1148  * controller is not either in the STARTED or STOPPED states.
1149  */
1150 static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout)
1151 {
1152         if (ihost->sm.current_state_id != SCIC_READY) {
1153                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
1154                          __func__, ihost->sm.current_state_id);
1155                 return SCI_FAILURE_INVALID_STATE;
1156         }
1157
1158         sci_mod_timer(&ihost->timer, timeout);
1159         sci_change_state(&ihost->sm, SCIC_STOPPING);
1160         return SCI_SUCCESS;
1161 }
1162
1163 /**
1164  * sci_controller_reset() - This method will reset the supplied core
1165  *    controller regardless of the state of said controller.  This operation is
1166  *    considered destructive.  In other words, all current operations are wiped
1167  *    out.  No IO completions for outstanding devices occur.  Outstanding IO
1168  *    requests are not aborted or completed at the actual remote device.
1169  * @controller: the handle to the controller object to reset.
1170  *
1171  * Indicate if the controller reset method succeeded or failed in some way.
1172  * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1173  * the controller reset operation is unable to complete.
1174  */
1175 static enum sci_status sci_controller_reset(struct isci_host *ihost)
1176 {
1177         switch (ihost->sm.current_state_id) {
1178         case SCIC_RESET:
1179         case SCIC_READY:
1180         case SCIC_STOPPING:
1181         case SCIC_FAILED:
1182                 /*
1183                  * The reset operation is not a graceful cleanup, just
1184                  * perform the state transition.
1185                  */
1186                 sci_change_state(&ihost->sm, SCIC_RESETTING);
1187                 return SCI_SUCCESS;
1188         default:
1189                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
1190                          __func__, ihost->sm.current_state_id);
1191                 return SCI_FAILURE_INVALID_STATE;
1192         }
1193 }
1194
1195 static enum sci_status sci_controller_stop_phys(struct isci_host *ihost)
1196 {
1197         u32 index;
1198         enum sci_status status;
1199         enum sci_status phy_status;
1200
1201         status = SCI_SUCCESS;
1202
1203         for (index = 0; index < SCI_MAX_PHYS; index++) {
1204                 phy_status = sci_phy_stop(&ihost->phys[index]);
1205
1206                 if (phy_status != SCI_SUCCESS &&
1207                     phy_status != SCI_FAILURE_INVALID_STATE) {
1208                         status = SCI_FAILURE;
1209
1210                         dev_warn(&ihost->pdev->dev,
1211                                  "%s: Controller stop operation failed to stop "
1212                                  "phy %d because of status %d.\n",
1213                                  __func__,
1214                                  ihost->phys[index].phy_index, phy_status);
1215                 }
1216         }
1217
1218         return status;
1219 }
1220
1221
1222 /**
1223  * isci_host_deinit - shutdown frame reception and dma
1224  * @ihost: host to take down
1225  *
1226  * This is called in either the driver shutdown or the suspend path.  In
1227  * the shutdown case libsas went through port teardown and normal device
1228  * removal (i.e. physical links stayed up to service scsi_device removal
1229  * commands).  In the suspend case we disable the hardware without
1230  * notifying libsas of the link down events since we want libsas to
1231  * remember the domain across the suspend/resume cycle
1232  */
1233 void isci_host_deinit(struct isci_host *ihost)
1234 {
1235         int i;
1236
1237         /* disable output data selects */
1238         for (i = 0; i < isci_gpio_count(ihost); i++)
1239                 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
1240
1241         set_bit(IHOST_STOP_PENDING, &ihost->flags);
1242
1243         spin_lock_irq(&ihost->scic_lock);
1244         sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT);
1245         spin_unlock_irq(&ihost->scic_lock);
1246
1247         wait_for_stop(ihost);
1248
1249         /* phy stop is after controller stop to allow port and device to
1250          * go idle before shutting down the phys, but the expectation is
1251          * that i/o has been shut off well before we reach this
1252          * function.
1253          */
1254         sci_controller_stop_phys(ihost);
1255
1256         /* disable sgpio: where the above wait should give time for the
1257          * enclosure to sample the gpios going inactive
1258          */
1259         writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
1260
1261         spin_lock_irq(&ihost->scic_lock);
1262         sci_controller_reset(ihost);
1263         spin_unlock_irq(&ihost->scic_lock);
1264
1265         /* Cancel any/all outstanding port timers */
1266         for (i = 0; i < ihost->logical_port_entries; i++) {
1267                 struct isci_port *iport = &ihost->ports[i];
1268                 del_timer_sync(&iport->timer.timer);
1269         }
1270
1271         /* Cancel any/all outstanding phy timers */
1272         for (i = 0; i < SCI_MAX_PHYS; i++) {
1273                 struct isci_phy *iphy = &ihost->phys[i];
1274                 del_timer_sync(&iphy->sata_timer.timer);
1275         }
1276
1277         del_timer_sync(&ihost->port_agent.timer.timer);
1278
1279         del_timer_sync(&ihost->power_control.timer.timer);
1280
1281         del_timer_sync(&ihost->timer.timer);
1282
1283         del_timer_sync(&ihost->phy_timer.timer);
1284 }
1285
1286 static void __iomem *scu_base(struct isci_host *isci_host)
1287 {
1288         struct pci_dev *pdev = isci_host->pdev;
1289         int id = isci_host->id;
1290
1291         return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
1292 }
1293
1294 static void __iomem *smu_base(struct isci_host *isci_host)
1295 {
1296         struct pci_dev *pdev = isci_host->pdev;
1297         int id = isci_host->id;
1298
1299         return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
1300 }
1301
1302 static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm)
1303 {
1304         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1305
1306         sci_change_state(&ihost->sm, SCIC_RESET);
1307 }
1308
1309 static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm)
1310 {
1311         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1312
1313         sci_del_timer(&ihost->timer);
1314 }
1315
1316 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1317 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1318 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US                    2700000
1319 #define INTERRUPT_COALESCE_NUMBER_MAX                        256
1320 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN                7
1321 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX                28
1322
1323 /**
1324  * sci_controller_set_interrupt_coalescence() - This method allows the user to
1325  *    configure the interrupt coalescence.
1326  * @controller: This parameter represents the handle to the controller object
1327  *    for which its interrupt coalesce register is overridden.
1328  * @coalesce_number: Used to control the number of entries in the Completion
1329  *    Queue before an interrupt is generated. If the number of entries exceed
1330  *    this number, an interrupt will be generated. The valid range of the input
1331  *    is [0, 256]. A setting of 0 results in coalescing being disabled.
1332  * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1333  *    input is [0, 2700000] . A setting of 0 is allowed and results in no
1334  *    interrupt coalescing timeout.
1335  *
1336  * Indicate if the user successfully set the interrupt coalesce parameters.
1337  * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1338  * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1339  */
1340 static enum sci_status
1341 sci_controller_set_interrupt_coalescence(struct isci_host *ihost,
1342                                          u32 coalesce_number,
1343                                          u32 coalesce_timeout)
1344 {
1345         u8 timeout_encode = 0;
1346         u32 min = 0;
1347         u32 max = 0;
1348
1349         /* Check if the input parameters fall in the range. */
1350         if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
1351                 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1352
1353         /*
1354          *  Defined encoding for interrupt coalescing timeout:
1355          *              Value   Min      Max     Units
1356          *              -----   ---      ---     -----
1357          *              0       -        -       Disabled
1358          *              1       13.3     20.0    ns
1359          *              2       26.7     40.0
1360          *              3       53.3     80.0
1361          *              4       106.7    160.0
1362          *              5       213.3    320.0
1363          *              6       426.7    640.0
1364          *              7       853.3    1280.0
1365          *              8       1.7      2.6     us
1366          *              9       3.4      5.1
1367          *              10      6.8      10.2
1368          *              11      13.7     20.5
1369          *              12      27.3     41.0
1370          *              13      54.6     81.9
1371          *              14      109.2    163.8
1372          *              15      218.5    327.7
1373          *              16      436.9    655.4
1374          *              17      873.8    1310.7
1375          *              18      1.7      2.6     ms
1376          *              19      3.5      5.2
1377          *              20      7.0      10.5
1378          *              21      14.0     21.0
1379          *              22      28.0     41.9
1380          *              23      55.9     83.9
1381          *              24      111.8    167.8
1382          *              25      223.7    335.5
1383          *              26      447.4    671.1
1384          *              27      894.8    1342.2
1385          *              28      1.8      2.7     s
1386          *              Others Undefined */
1387
1388         /*
1389          * Use the table above to decide the encode of interrupt coalescing timeout
1390          * value for register writing. */
1391         if (coalesce_timeout == 0)
1392                 timeout_encode = 0;
1393         else{
1394                 /* make the timeout value in unit of (10 ns). */
1395                 coalesce_timeout = coalesce_timeout * 100;
1396                 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
1397                 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
1398
1399                 /* get the encode of timeout for register writing. */
1400                 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
1401                       timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
1402                       timeout_encode++) {
1403                         if (min <= coalesce_timeout &&  max > coalesce_timeout)
1404                                 break;
1405                         else if (coalesce_timeout >= max && coalesce_timeout < min * 2
1406                                  && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
1407                                 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
1408                                         break;
1409                                 else{
1410                                         timeout_encode++;
1411                                         break;
1412                                 }
1413                         } else {
1414                                 max = max * 2;
1415                                 min = min * 2;
1416                         }
1417                 }
1418
1419                 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
1420                         /* the value is out of range. */
1421                         return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1422         }
1423
1424         writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1425                SMU_ICC_GEN_VAL(TIMER, timeout_encode),
1426                &ihost->smu_registers->interrupt_coalesce_control);
1427
1428
1429         ihost->interrupt_coalesce_number = (u16)coalesce_number;
1430         ihost->interrupt_coalesce_timeout = coalesce_timeout / 100;
1431
1432         return SCI_SUCCESS;
1433 }
1434
1435
1436 static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm)
1437 {
1438         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1439         u32 val;
1440
1441         /* enable clock gating for power control of the scu unit */
1442         val = readl(&ihost->smu_registers->clock_gating_control);
1443         val &= ~(SMU_CGUCR_GEN_BIT(REGCLK_ENABLE) |
1444                  SMU_CGUCR_GEN_BIT(TXCLK_ENABLE) |
1445                  SMU_CGUCR_GEN_BIT(XCLK_ENABLE));
1446         val |= SMU_CGUCR_GEN_BIT(IDLE_ENABLE);
1447         writel(val, &ihost->smu_registers->clock_gating_control);
1448
1449         /* set the default interrupt coalescence number and timeout value. */
1450         sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1451 }
1452
1453 static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm)
1454 {
1455         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1456
1457         /* disable interrupt coalescence. */
1458         sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1459 }
1460
1461 static enum sci_status sci_controller_stop_ports(struct isci_host *ihost)
1462 {
1463         u32 index;
1464         enum sci_status port_status;
1465         enum sci_status status = SCI_SUCCESS;
1466
1467         for (index = 0; index < ihost->logical_port_entries; index++) {
1468                 struct isci_port *iport = &ihost->ports[index];
1469
1470                 port_status = sci_port_stop(iport);
1471
1472                 if ((port_status != SCI_SUCCESS) &&
1473                     (port_status != SCI_FAILURE_INVALID_STATE)) {
1474                         status = SCI_FAILURE;
1475
1476                         dev_warn(&ihost->pdev->dev,
1477                                  "%s: Controller stop operation failed to "
1478                                  "stop port %d because of status %d.\n",
1479                                  __func__,
1480                                  iport->logical_port_index,
1481                                  port_status);
1482                 }
1483         }
1484
1485         return status;
1486 }
1487
1488 static enum sci_status sci_controller_stop_devices(struct isci_host *ihost)
1489 {
1490         u32 index;
1491         enum sci_status status;
1492         enum sci_status device_status;
1493
1494         status = SCI_SUCCESS;
1495
1496         for (index = 0; index < ihost->remote_node_entries; index++) {
1497                 if (ihost->device_table[index] != NULL) {
1498                         /* / @todo What timeout value do we want to provide to this request? */
1499                         device_status = sci_remote_device_stop(ihost->device_table[index], 0);
1500
1501                         if ((device_status != SCI_SUCCESS) &&
1502                             (device_status != SCI_FAILURE_INVALID_STATE)) {
1503                                 dev_warn(&ihost->pdev->dev,
1504                                          "%s: Controller stop operation failed "
1505                                          "to stop device 0x%p because of "
1506                                          "status %d.\n",
1507                                          __func__,
1508                                          ihost->device_table[index], device_status);
1509                         }
1510                 }
1511         }
1512
1513         return status;
1514 }
1515
1516 static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm)
1517 {
1518         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1519
1520         sci_controller_stop_devices(ihost);
1521         sci_controller_stop_ports(ihost);
1522
1523         if (!sci_controller_has_remote_devices_stopping(ihost))
1524                 isci_host_stop_complete(ihost);
1525 }
1526
1527 static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm)
1528 {
1529         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1530
1531         sci_del_timer(&ihost->timer);
1532 }
1533
1534 static void sci_controller_reset_hardware(struct isci_host *ihost)
1535 {
1536         /* Disable interrupts so we dont take any spurious interrupts */
1537         sci_controller_disable_interrupts(ihost);
1538
1539         /* Reset the SCU */
1540         writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
1541
1542         /* Delay for 1ms to before clearing the CQP and UFQPR. */
1543         udelay(1000);
1544
1545         /* The write to the CQGR clears the CQP */
1546         writel(0x00000000, &ihost->smu_registers->completion_queue_get);
1547
1548         /* The write to the UFQGP clears the UFQPR */
1549         writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
1550
1551         /* clear all interrupts */
1552         writel(~SMU_INTERRUPT_STATUS_RESERVED_MASK, &ihost->smu_registers->interrupt_status);
1553 }
1554
1555 static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm)
1556 {
1557         struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1558
1559         sci_controller_reset_hardware(ihost);
1560         sci_change_state(&ihost->sm, SCIC_RESET);
1561 }
1562
1563 static const struct sci_base_state sci_controller_state_table[] = {
1564         [SCIC_INITIAL] = {
1565                 .enter_state = sci_controller_initial_state_enter,
1566         },
1567         [SCIC_RESET] = {},
1568         [SCIC_INITIALIZING] = {},
1569         [SCIC_INITIALIZED] = {},
1570         [SCIC_STARTING] = {
1571                 .exit_state  = sci_controller_starting_state_exit,
1572         },
1573         [SCIC_READY] = {
1574                 .enter_state = sci_controller_ready_state_enter,
1575                 .exit_state  = sci_controller_ready_state_exit,
1576         },
1577         [SCIC_RESETTING] = {
1578                 .enter_state = sci_controller_resetting_state_enter,
1579         },
1580         [SCIC_STOPPING] = {
1581                 .enter_state = sci_controller_stopping_state_enter,
1582                 .exit_state = sci_controller_stopping_state_exit,
1583         },
1584         [SCIC_FAILED] = {}
1585 };
1586
1587 static void controller_timeout(unsigned long data)
1588 {
1589         struct sci_timer *tmr = (struct sci_timer *)data;
1590         struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer);
1591         struct sci_base_state_machine *sm = &ihost->sm;
1592         unsigned long flags;
1593
1594         spin_lock_irqsave(&ihost->scic_lock, flags);
1595
1596         if (tmr->cancel)
1597                 goto done;
1598
1599         if (sm->current_state_id == SCIC_STARTING)
1600                 sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT);
1601         else if (sm->current_state_id == SCIC_STOPPING) {
1602                 sci_change_state(sm, SCIC_FAILED);
1603                 isci_host_stop_complete(ihost);
1604         } else  /* / @todo Now what do we want to do in this case? */
1605                 dev_err(&ihost->pdev->dev,
1606                         "%s: Controller timer fired when controller was not "
1607                         "in a state being timed.\n",
1608                         __func__);
1609
1610 done:
1611         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1612 }
1613
1614 static enum sci_status sci_controller_construct(struct isci_host *ihost,
1615                                                 void __iomem *scu_base,
1616                                                 void __iomem *smu_base)
1617 {
1618         u8 i;
1619
1620         sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL);
1621
1622         ihost->scu_registers = scu_base;
1623         ihost->smu_registers = smu_base;
1624
1625         sci_port_configuration_agent_construct(&ihost->port_agent);
1626
1627         /* Construct the ports for this controller */
1628         for (i = 0; i < SCI_MAX_PORTS; i++)
1629                 sci_port_construct(&ihost->ports[i], i, ihost);
1630         sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost);
1631
1632         /* Construct the phys for this controller */
1633         for (i = 0; i < SCI_MAX_PHYS; i++) {
1634                 /* Add all the PHYs to the dummy port */
1635                 sci_phy_construct(&ihost->phys[i],
1636                                   &ihost->ports[SCI_MAX_PORTS], i);
1637         }
1638
1639         ihost->invalid_phy_mask = 0;
1640
1641         sci_init_timer(&ihost->timer, controller_timeout);
1642
1643         return sci_controller_reset(ihost);
1644 }
1645
1646 int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version)
1647 {
1648         int i;
1649
1650         for (i = 0; i < SCI_MAX_PORTS; i++)
1651                 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
1652                         return -EINVAL;
1653
1654         for (i = 0; i < SCI_MAX_PHYS; i++)
1655                 if (oem->phys[i].sas_address.high == 0 &&
1656                     oem->phys[i].sas_address.low == 0)
1657                         return -EINVAL;
1658
1659         if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
1660                 for (i = 0; i < SCI_MAX_PHYS; i++)
1661                         if (oem->ports[i].phy_mask != 0)
1662                                 return -EINVAL;
1663         } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1664                 u8 phy_mask = 0;
1665
1666                 for (i = 0; i < SCI_MAX_PHYS; i++)
1667                         phy_mask |= oem->ports[i].phy_mask;
1668
1669                 if (phy_mask == 0)
1670                         return -EINVAL;
1671         } else
1672                 return -EINVAL;
1673
1674         if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT ||
1675             oem->controller.max_concurr_spin_up < 1)
1676                 return -EINVAL;
1677
1678         if (oem->controller.do_enable_ssc) {
1679                 if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1)
1680                         return -EINVAL;
1681
1682                 if (version >= ISCI_ROM_VER_1_1) {
1683                         u8 test = oem->controller.ssc_sata_tx_spread_level;
1684
1685                         switch (test) {
1686                         case 0:
1687                         case 2:
1688                         case 3:
1689                         case 6:
1690                         case 7:
1691                                 break;
1692                         default:
1693                                 return -EINVAL;
1694                         }
1695
1696                         test = oem->controller.ssc_sas_tx_spread_level;
1697                         if (oem->controller.ssc_sas_tx_type == 0) {
1698                                 switch (test) {
1699                                 case 0:
1700                                 case 2:
1701                                 case 3:
1702                                         break;
1703                                 default:
1704                                         return -EINVAL;
1705                                 }
1706                         } else if (oem->controller.ssc_sas_tx_type == 1) {
1707                                 switch (test) {
1708                                 case 0:
1709                                 case 3:
1710                                 case 6:
1711                                         break;
1712                                 default:
1713                                         return -EINVAL;
1714                                 }
1715                         }
1716                 }
1717         }
1718
1719         return 0;
1720 }
1721
1722 static u8 max_spin_up(struct isci_host *ihost)
1723 {
1724         if (ihost->user_parameters.max_concurr_spinup)
1725                 return min_t(u8, ihost->user_parameters.max_concurr_spinup,
1726                              MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1727         else
1728                 return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up,
1729                              MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1730 }
1731
1732 static void power_control_timeout(unsigned long data)
1733 {
1734         struct sci_timer *tmr = (struct sci_timer *)data;
1735         struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer);
1736         struct isci_phy *iphy;
1737         unsigned long flags;
1738         u8 i;
1739
1740         spin_lock_irqsave(&ihost->scic_lock, flags);
1741
1742         if (tmr->cancel)
1743                 goto done;
1744
1745         ihost->power_control.phys_granted_power = 0;
1746
1747         if (ihost->power_control.phys_waiting == 0) {
1748                 ihost->power_control.timer_started = false;
1749                 goto done;
1750         }
1751
1752         for (i = 0; i < SCI_MAX_PHYS; i++) {
1753
1754                 if (ihost->power_control.phys_waiting == 0)
1755                         break;
1756
1757                 iphy = ihost->power_control.requesters[i];
1758                 if (iphy == NULL)
1759                         continue;
1760
1761                 if (ihost->power_control.phys_granted_power >= max_spin_up(ihost))
1762                         break;
1763
1764                 ihost->power_control.requesters[i] = NULL;
1765                 ihost->power_control.phys_waiting--;
1766                 ihost->power_control.phys_granted_power++;
1767                 sci_phy_consume_power_handler(iphy);
1768
1769                 if (iphy->protocol == SAS_PROTOCOL_SSP) {
1770                         u8 j;
1771
1772                         for (j = 0; j < SCI_MAX_PHYS; j++) {
1773                                 struct isci_phy *requester = ihost->power_control.requesters[j];
1774
1775                                 /*
1776                                  * Search the power_control queue to see if there are other phys
1777                                  * attached to the same remote device. If found, take all of
1778                                  * them out of await_sas_power state.
1779                                  */
1780                                 if (requester != NULL && requester != iphy) {
1781                                         u8 other = memcmp(requester->frame_rcvd.iaf.sas_addr,
1782                                                           iphy->frame_rcvd.iaf.sas_addr,
1783                                                           sizeof(requester->frame_rcvd.iaf.sas_addr));
1784
1785                                         if (other == 0) {
1786                                                 ihost->power_control.requesters[j] = NULL;
1787                                                 ihost->power_control.phys_waiting--;
1788                                                 sci_phy_consume_power_handler(requester);
1789                                         }
1790                                 }
1791                         }
1792                 }
1793         }
1794
1795         /*
1796          * It doesn't matter if the power list is empty, we need to start the
1797          * timer in case another phy becomes ready.
1798          */
1799         sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1800         ihost->power_control.timer_started = true;
1801
1802 done:
1803         spin_unlock_irqrestore(&ihost->scic_lock, flags);
1804 }
1805
1806 void sci_controller_power_control_queue_insert(struct isci_host *ihost,
1807                                                struct isci_phy *iphy)
1808 {
1809         BUG_ON(iphy == NULL);
1810
1811         if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) {
1812                 ihost->power_control.phys_granted_power++;
1813                 sci_phy_consume_power_handler(iphy);
1814
1815                 /*
1816                  * stop and start the power_control timer. When the timer fires, the
1817                  * no_of_phys_granted_power will be set to 0
1818                  */
1819                 if (ihost->power_control.timer_started)
1820                         sci_del_timer(&ihost->power_control.timer);
1821
1822                 sci_mod_timer(&ihost->power_control.timer,
1823                                  SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1824                 ihost->power_control.timer_started = true;
1825
1826         } else {
1827                 /*
1828                  * There are phys, attached to the same sas address as this phy, are
1829                  * already in READY state, this phy don't need wait.
1830                  */
1831                 u8 i;
1832                 struct isci_phy *current_phy;
1833
1834                 for (i = 0; i < SCI_MAX_PHYS; i++) {
1835                         u8 other;
1836                         current_phy = &ihost->phys[i];
1837
1838                         other = memcmp(current_phy->frame_rcvd.iaf.sas_addr,
1839                                        iphy->frame_rcvd.iaf.sas_addr,
1840                                        sizeof(current_phy->frame_rcvd.iaf.sas_addr));
1841
1842                         if (current_phy->sm.current_state_id == SCI_PHY_READY &&
1843                             current_phy->protocol == SAS_PROTOCOL_SSP &&
1844                             other == 0) {
1845                                 sci_phy_consume_power_handler(iphy);
1846                                 break;
1847                         }
1848                 }
1849
1850                 if (i == SCI_MAX_PHYS) {
1851                         /* Add the phy in the waiting list */
1852                         ihost->power_control.requesters[iphy->phy_index] = iphy;
1853                         ihost->power_control.phys_waiting++;
1854                 }
1855         }
1856 }
1857
1858 void sci_controller_power_control_queue_remove(struct isci_host *ihost,
1859                                                struct isci_phy *iphy)
1860 {
1861         BUG_ON(iphy == NULL);
1862
1863         if (ihost->power_control.requesters[iphy->phy_index])
1864                 ihost->power_control.phys_waiting--;
1865
1866         ihost->power_control.requesters[iphy->phy_index] = NULL;
1867 }
1868
1869 static int is_long_cable(int phy, unsigned char selection_byte)
1870 {
1871         return !!(selection_byte & (1 << phy));
1872 }
1873
1874 static int is_medium_cable(int phy, unsigned char selection_byte)
1875 {
1876         return !!(selection_byte & (1 << (phy + 4)));
1877 }
1878
1879 static enum cable_selections decode_selection_byte(
1880         int phy,
1881         unsigned char selection_byte)
1882 {
1883         return ((selection_byte & (1 << phy)) ? 1 : 0)
1884                 + (selection_byte & (1 << (phy + 4)) ? 2 : 0);
1885 }
1886
1887 static unsigned char *to_cable_select(struct isci_host *ihost)
1888 {
1889         if (is_cable_select_overridden())
1890                 return ((unsigned char *)&cable_selection_override)
1891                         + ihost->id;
1892         else
1893                 return &ihost->oem_parameters.controller.cable_selection_mask;
1894 }
1895
1896 enum cable_selections decode_cable_selection(struct isci_host *ihost, int phy)
1897 {
1898         return decode_selection_byte(phy, *to_cable_select(ihost));
1899 }
1900
1901 char *lookup_cable_names(enum cable_selections selection)
1902 {
1903         static char *cable_names[] = {
1904                 [short_cable]     = "short",
1905                 [long_cable]      = "long",
1906                 [medium_cable]    = "medium",
1907                 [undefined_cable] = "<undefined, assumed long>" /* bit 0==1 */
1908         };
1909         return (selection <= undefined_cable) ? cable_names[selection]
1910                                               : cable_names[undefined_cable];
1911 }
1912
1913 #define AFE_REGISTER_WRITE_DELAY 10
1914
1915 static void sci_controller_afe_initialization(struct isci_host *ihost)
1916 {
1917         struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
1918         const struct sci_oem_params *oem = &ihost->oem_parameters;
1919         struct pci_dev *pdev = ihost->pdev;
1920         u32 afe_status;
1921         u32 phy_id;
1922         unsigned char cable_selection_mask = *to_cable_select(ihost);
1923
1924         /* Clear DFX Status registers */
1925         writel(0x0081000f, &afe->afe_dfx_master_control0);
1926         udelay(AFE_REGISTER_WRITE_DELAY);
1927
1928         if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) {
1929                 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
1930                  * Timer, PM Stagger Timer
1931                  */
1932                 writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
1933                 udelay(AFE_REGISTER_WRITE_DELAY);
1934         }
1935
1936         /* Configure bias currents to normal */
1937         if (is_a2(pdev))
1938                 writel(0x00005A00, &afe->afe_bias_control);
1939         else if (is_b0(pdev) || is_c0(pdev))
1940                 writel(0x00005F00, &afe->afe_bias_control);
1941         else if (is_c1(pdev))
1942                 writel(0x00005500, &afe->afe_bias_control);
1943
1944         udelay(AFE_REGISTER_WRITE_DELAY);
1945
1946         /* Enable PLL */
1947         if (is_a2(pdev))
1948                 writel(0x80040908, &afe->afe_pll_control0);
1949         else if (is_b0(pdev) || is_c0(pdev))
1950                 writel(0x80040A08, &afe->afe_pll_control0);
1951         else if (is_c1(pdev)) {
1952                 writel(0x80000B08, &afe->afe_pll_control0);
1953                 udelay(AFE_REGISTER_WRITE_DELAY);
1954                 writel(0x00000B08, &afe->afe_pll_control0);
1955                 udelay(AFE_REGISTER_WRITE_DELAY);
1956                 writel(0x80000B08, &afe->afe_pll_control0);
1957         }
1958
1959         udelay(AFE_REGISTER_WRITE_DELAY);
1960
1961         /* Wait for the PLL to lock */
1962         do {
1963                 afe_status = readl(&afe->afe_common_block_status);
1964                 udelay(AFE_REGISTER_WRITE_DELAY);
1965         } while ((afe_status & 0x00001000) == 0);
1966
1967         if (is_a2(pdev)) {
1968                 /* Shorten SAS SNW lock time (RxLock timer value from 76
1969                  * us to 50 us)
1970                  */
1971                 writel(0x7bcc96ad, &afe->afe_pmsn_master_control0);
1972                 udelay(AFE_REGISTER_WRITE_DELAY);
1973         }
1974
1975         for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
1976                 struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_id];
1977                 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
1978                 int cable_length_long =
1979                         is_long_cable(phy_id, cable_selection_mask);
1980                 int cable_length_medium =
1981                         is_medium_cable(phy_id, cable_selection_mask);
1982
1983                 if (is_a2(pdev)) {
1984                         /* All defaults, except the Receive Word
1985                          * Alignament/Comma Detect Enable....(0xe800)
1986                          */
1987                         writel(0x00004512, &xcvr->afe_xcvr_control0);
1988                         udelay(AFE_REGISTER_WRITE_DELAY);
1989
1990                         writel(0x0050100F, &xcvr->afe_xcvr_control1);
1991                         udelay(AFE_REGISTER_WRITE_DELAY);
1992                 } else if (is_b0(pdev)) {
1993                         /* Configure transmitter SSC parameters */
1994                         writel(0x00030000, &xcvr->afe_tx_ssc_control);
1995                         udelay(AFE_REGISTER_WRITE_DELAY);
1996                 } else if (is_c0(pdev)) {
1997                         /* Configure transmitter SSC parameters */
1998                         writel(0x00010202, &xcvr->afe_tx_ssc_control);
1999                         udelay(AFE_REGISTER_WRITE_DELAY);
2000
2001                         /* All defaults, except the Receive Word
2002                          * Alignament/Comma Detect Enable....(0xe800)
2003                          */
2004                         writel(0x00014500, &xcvr->afe_xcvr_control0);
2005                         udelay(AFE_REGISTER_WRITE_DELAY);
2006                 } else if (is_c1(pdev)) {
2007                         /* Configure transmitter SSC parameters */
2008                         writel(0x00010202, &xcvr->afe_tx_ssc_control);
2009                         udelay(AFE_REGISTER_WRITE_DELAY);
2010
2011                         /* All defaults, except the Receive Word
2012                          * Alignament/Comma Detect Enable....(0xe800)
2013                          */
2014                         writel(0x0001C500, &xcvr->afe_xcvr_control0);
2015                         udelay(AFE_REGISTER_WRITE_DELAY);
2016                 }
2017
2018                 /* Power up TX and RX out from power down (PWRDNTX and
2019                  * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
2020                  */
2021                 if (is_a2(pdev))
2022                         writel(0x000003F0, &xcvr->afe_channel_control);
2023                 else if (is_b0(pdev)) {
2024                         writel(0x000003D7, &xcvr->afe_channel_control);
2025                         udelay(AFE_REGISTER_WRITE_DELAY);
2026
2027                         writel(0x000003D4, &xcvr->afe_channel_control);
2028                 } else if (is_c0(pdev)) {
2029                         writel(0x000001E7, &xcvr->afe_channel_control);
2030                         udelay(AFE_REGISTER_WRITE_DELAY);
2031
2032                         writel(0x000001E4, &xcvr->afe_channel_control);
2033                 } else if (is_c1(pdev)) {
2034                         writel(cable_length_long ? 0x000002F7 : 0x000001F7,
2035                                &xcvr->afe_channel_control);
2036                         udelay(AFE_REGISTER_WRITE_DELAY);
2037
2038                         writel(cable_length_long ? 0x000002F4 : 0x000001F4,
2039                                &xcvr->afe_channel_control);
2040                 }
2041                 udelay(AFE_REGISTER_WRITE_DELAY);
2042
2043                 if (is_a2(pdev)) {
2044                         /* Enable TX equalization (0xe824) */
2045                         writel(0x00040000, &xcvr->afe_tx_control);
2046                         udelay(AFE_REGISTER_WRITE_DELAY);
2047                 }
2048
2049                 if (is_a2(pdev) || is_b0(pdev))
2050                         /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
2051                          * TPD=0x0(TX Power On), RDD=0x0(RX Detect
2052                          * Enabled) ....(0xe800)
2053                          */
2054                         writel(0x00004100, &xcvr->afe_xcvr_control0);
2055                 else if (is_c0(pdev))
2056                         writel(0x00014100, &xcvr->afe_xcvr_control0);
2057                 else if (is_c1(pdev))
2058                         writel(0x0001C100, &xcvr->afe_xcvr_control0);
2059                 udelay(AFE_REGISTER_WRITE_DELAY);
2060
2061                 /* Leave DFE/FFE on */
2062                 if (is_a2(pdev))
2063                         writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2064                 else if (is_b0(pdev)) {
2065                         writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2066                         udelay(AFE_REGISTER_WRITE_DELAY);
2067                         /* Enable TX equalization (0xe824) */
2068                         writel(0x00040000, &xcvr->afe_tx_control);
2069                 } else if (is_c0(pdev)) {
2070                         writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
2071                         udelay(AFE_REGISTER_WRITE_DELAY);
2072
2073                         writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
2074                         udelay(AFE_REGISTER_WRITE_DELAY);
2075
2076                         /* Enable TX equalization (0xe824) */
2077                         writel(0x00040000, &xcvr->afe_tx_control);
2078                 } else if (is_c1(pdev)) {
2079                         writel(cable_length_long ? 0x01500C0C :
2080                                cable_length_medium ? 0x01400C0D : 0x02400C0D,
2081                                &xcvr->afe_xcvr_control1);
2082                         udelay(AFE_REGISTER_WRITE_DELAY);
2083
2084                         writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
2085                         udelay(AFE_REGISTER_WRITE_DELAY);
2086
2087                         writel(cable_length_long ? 0x33091C1F :
2088                                cable_length_medium ? 0x3315181F : 0x2B17161F,
2089                                &xcvr->afe_rx_ssc_control0);
2090                         udelay(AFE_REGISTER_WRITE_DELAY);
2091
2092                         /* Enable TX equalization (0xe824) */
2093                         writel(0x00040000, &xcvr->afe_tx_control);
2094                 }
2095
2096                 udelay(AFE_REGISTER_WRITE_DELAY);
2097
2098                 writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0);
2099                 udelay(AFE_REGISTER_WRITE_DELAY);
2100
2101                 writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1);
2102                 udelay(AFE_REGISTER_WRITE_DELAY);
2103
2104                 writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2);
2105                 udelay(AFE_REGISTER_WRITE_DELAY);
2106
2107                 writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3);
2108                 udelay(AFE_REGISTER_WRITE_DELAY);
2109         }
2110
2111         /* Transfer control to the PEs */
2112         writel(0x00010f00, &afe->afe_dfx_master_control0);
2113         udelay(AFE_REGISTER_WRITE_DELAY);
2114 }
2115
2116 static void sci_controller_initialize_power_control(struct isci_host *ihost)
2117 {
2118         sci_init_timer(&ihost->power_control.timer, power_control_timeout);
2119
2120         memset(ihost->power_control.requesters, 0,
2121                sizeof(ihost->power_control.requesters));
2122
2123         ihost->power_control.phys_waiting = 0;
2124         ihost->power_control.phys_granted_power = 0;
2125 }
2126
2127 static enum sci_status sci_controller_initialize(struct isci_host *ihost)
2128 {
2129         struct sci_base_state_machine *sm = &ihost->sm;
2130         enum sci_status result = SCI_FAILURE;
2131         unsigned long i, state, val;
2132
2133         if (ihost->sm.current_state_id != SCIC_RESET) {
2134                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2135                          __func__, ihost->sm.current_state_id);
2136                 return SCI_FAILURE_INVALID_STATE;
2137         }
2138
2139         sci_change_state(sm, SCIC_INITIALIZING);
2140
2141         sci_init_timer(&ihost->phy_timer, phy_startup_timeout);
2142
2143         ihost->next_phy_to_start = 0;
2144         ihost->phy_startup_timer_pending = false;
2145
2146         sci_controller_initialize_power_control(ihost);
2147
2148         /*
2149          * There is nothing to do here for B0 since we do not have to
2150          * program the AFE registers.
2151          * / @todo The AFE settings are supposed to be correct for the B0 but
2152          * /       presently they seem to be wrong. */
2153         sci_controller_afe_initialization(ihost);
2154
2155
2156         /* Take the hardware out of reset */
2157         writel(0, &ihost->smu_registers->soft_reset_control);
2158
2159         /*
2160          * / @todo Provide meaningfull error code for hardware failure
2161          * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2162         for (i = 100; i >= 1; i--) {
2163                 u32 status;
2164
2165                 /* Loop until the hardware reports success */
2166                 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2167                 status = readl(&ihost->smu_registers->control_status);
2168
2169                 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
2170                         break;
2171         }
2172         if (i == 0)
2173                 goto out;
2174
2175         /*
2176          * Determine what are the actaul device capacities that the
2177          * hardware will support */
2178         val = readl(&ihost->smu_registers->device_context_capacity);
2179
2180         /* Record the smaller of the two capacity values */
2181         ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
2182         ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
2183         ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
2184
2185         /*
2186          * Make all PEs that are unassigned match up with the
2187          * logical ports
2188          */
2189         for (i = 0; i < ihost->logical_port_entries; i++) {
2190                 struct scu_port_task_scheduler_group_registers __iomem
2191                         *ptsg = &ihost->scu_registers->peg0.ptsg;
2192
2193                 writel(i, &ptsg->protocol_engine[i]);
2194         }
2195
2196         /* Initialize hardware PCI Relaxed ordering in DMA engines */
2197         val = readl(&ihost->scu_registers->sdma.pdma_configuration);
2198         val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2199         writel(val, &ihost->scu_registers->sdma.pdma_configuration);
2200
2201         val = readl(&ihost->scu_registers->sdma.cdma_configuration);
2202         val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2203         writel(val, &ihost->scu_registers->sdma.cdma_configuration);
2204
2205         /*
2206          * Initialize the PHYs before the PORTs because the PHY registers
2207          * are accessed during the port initialization.
2208          */
2209         for (i = 0; i < SCI_MAX_PHYS; i++) {
2210                 result = sci_phy_initialize(&ihost->phys[i],
2211                                             &ihost->scu_registers->peg0.pe[i].tl,
2212                                             &ihost->scu_registers->peg0.pe[i].ll);
2213                 if (result != SCI_SUCCESS)
2214                         goto out;
2215         }
2216
2217         for (i = 0; i < ihost->logical_port_entries; i++) {
2218                 struct isci_port *iport = &ihost->ports[i];
2219
2220                 iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i];
2221                 iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0];
2222                 iport->viit_registers = &ihost->scu_registers->peg0.viit[i];
2223         }
2224
2225         result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent);
2226
2227  out:
2228         /* Advance the controller state machine */
2229         if (result == SCI_SUCCESS)
2230                 state = SCIC_INITIALIZED;
2231         else
2232                 state = SCIC_FAILED;
2233         sci_change_state(sm, state);
2234
2235         return result;
2236 }
2237
2238 static int sci_controller_dma_alloc(struct isci_host *ihost)
2239 {
2240         struct device *dev = &ihost->pdev->dev;
2241         size_t size;
2242         int i;
2243
2244         /* detect re-initialization */
2245         if (ihost->completion_queue)
2246                 return 0;
2247
2248         size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
2249         ihost->completion_queue = dmam_alloc_coherent(dev, size, &ihost->cq_dma,
2250                                                       GFP_KERNEL);
2251         if (!ihost->completion_queue)
2252                 return -ENOMEM;
2253
2254         size = ihost->remote_node_entries * sizeof(union scu_remote_node_context);
2255         ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &ihost->rnc_dma,
2256                                                                GFP_KERNEL);
2257
2258         if (!ihost->remote_node_context_table)
2259                 return -ENOMEM;
2260
2261         size = ihost->task_context_entries * sizeof(struct scu_task_context),
2262         ihost->task_context_table = dmam_alloc_coherent(dev, size, &ihost->tc_dma,
2263                                                         GFP_KERNEL);
2264         if (!ihost->task_context_table)
2265                 return -ENOMEM;
2266
2267         size = SCI_UFI_TOTAL_SIZE;
2268         ihost->ufi_buf = dmam_alloc_coherent(dev, size, &ihost->ufi_dma, GFP_KERNEL);
2269         if (!ihost->ufi_buf)
2270                 return -ENOMEM;
2271
2272         for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) {
2273                 struct isci_request *ireq;
2274                 dma_addr_t dma;
2275
2276                 ireq = dmam_alloc_coherent(dev, sizeof(*ireq), &dma, GFP_KERNEL);
2277                 if (!ireq)
2278                         return -ENOMEM;
2279
2280                 ireq->tc = &ihost->task_context_table[i];
2281                 ireq->owning_controller = ihost;
2282                 ireq->request_daddr = dma;
2283                 ireq->isci_host = ihost;
2284                 ihost->reqs[i] = ireq;
2285         }
2286
2287         return 0;
2288 }
2289
2290 static int sci_controller_mem_init(struct isci_host *ihost)
2291 {
2292         int err = sci_controller_dma_alloc(ihost);
2293
2294         if (err)
2295                 return err;
2296
2297         writel(lower_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_lower);
2298         writel(upper_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_upper);
2299
2300         writel(lower_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_lower);
2301         writel(upper_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_upper);
2302
2303         writel(lower_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_lower);
2304         writel(upper_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_upper);
2305
2306         sci_unsolicited_frame_control_construct(ihost);
2307
2308         /*
2309          * Inform the silicon as to the location of the UF headers and
2310          * address table.
2311          */
2312         writel(lower_32_bits(ihost->uf_control.headers.physical_address),
2313                 &ihost->scu_registers->sdma.uf_header_base_address_lower);
2314         writel(upper_32_bits(ihost->uf_control.headers.physical_address),
2315                 &ihost->scu_registers->sdma.uf_header_base_address_upper);
2316
2317         writel(lower_32_bits(ihost->uf_control.address_table.physical_address),
2318                 &ihost->scu_registers->sdma.uf_address_table_lower);
2319         writel(upper_32_bits(ihost->uf_control.address_table.physical_address),
2320                 &ihost->scu_registers->sdma.uf_address_table_upper);
2321
2322         return 0;
2323 }
2324
2325 /**
2326  * isci_host_init - (re-)initialize hardware and internal (private) state
2327  * @ihost: host to init
2328  *
2329  * Any public facing objects (like asd_sas_port, and asd_sas_phys), or
2330  * one-time initialization objects like locks and waitqueues, are
2331  * not touched (they are initialized in isci_host_alloc)
2332  */
2333 int isci_host_init(struct isci_host *ihost)
2334 {
2335         int i, err;
2336         enum sci_status status;
2337
2338         spin_lock_irq(&ihost->scic_lock);
2339         status = sci_controller_construct(ihost, scu_base(ihost), smu_base(ihost));
2340         spin_unlock_irq(&ihost->scic_lock);
2341         if (status != SCI_SUCCESS) {
2342                 dev_err(&ihost->pdev->dev,
2343                         "%s: sci_controller_construct failed - status = %x\n",
2344                         __func__,
2345                         status);
2346                 return -ENODEV;
2347         }
2348
2349         spin_lock_irq(&ihost->scic_lock);
2350         status = sci_controller_initialize(ihost);
2351         spin_unlock_irq(&ihost->scic_lock);
2352         if (status != SCI_SUCCESS) {
2353                 dev_warn(&ihost->pdev->dev,
2354                          "%s: sci_controller_initialize failed -"
2355                          " status = 0x%x\n",
2356                          __func__, status);
2357                 return -ENODEV;
2358         }
2359
2360         err = sci_controller_mem_init(ihost);
2361         if (err)
2362                 return err;
2363
2364         /* enable sgpio */
2365         writel(1, &ihost->scu_registers->peg0.sgpio.interface_control);
2366         for (i = 0; i < isci_gpio_count(ihost); i++)
2367                 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
2368         writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code);
2369
2370         return 0;
2371 }
2372
2373 void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport,
2374                             struct isci_phy *iphy)
2375 {
2376         switch (ihost->sm.current_state_id) {
2377         case SCIC_STARTING:
2378                 sci_del_timer(&ihost->phy_timer);
2379                 ihost->phy_startup_timer_pending = false;
2380                 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2381                                                   iport, iphy);
2382                 sci_controller_start_next_phy(ihost);
2383                 break;
2384         case SCIC_READY:
2385                 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2386                                                   iport, iphy);
2387                 break;
2388         default:
2389                 dev_dbg(&ihost->pdev->dev,
2390                         "%s: SCIC Controller linkup event from phy %d in "
2391                         "unexpected state %d\n", __func__, iphy->phy_index,
2392                         ihost->sm.current_state_id);
2393         }
2394 }
2395
2396 void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport,
2397                               struct isci_phy *iphy)
2398 {
2399         switch (ihost->sm.current_state_id) {
2400         case SCIC_STARTING:
2401         case SCIC_READY:
2402                 ihost->port_agent.link_down_handler(ihost, &ihost->port_agent,
2403                                                    iport, iphy);
2404                 break;
2405         default:
2406                 dev_dbg(&ihost->pdev->dev,
2407                         "%s: SCIC Controller linkdown event from phy %d in "
2408                         "unexpected state %d\n",
2409                         __func__,
2410                         iphy->phy_index,
2411                         ihost->sm.current_state_id);
2412         }
2413 }
2414
2415 bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost)
2416 {
2417         u32 index;
2418
2419         for (index = 0; index < ihost->remote_node_entries; index++) {
2420                 if ((ihost->device_table[index] != NULL) &&
2421                    (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
2422                         return true;
2423         }
2424
2425         return false;
2426 }
2427
2428 void sci_controller_remote_device_stopped(struct isci_host *ihost,
2429                                           struct isci_remote_device *idev)
2430 {
2431         if (ihost->sm.current_state_id != SCIC_STOPPING) {
2432                 dev_dbg(&ihost->pdev->dev,
2433                         "SCIC Controller 0x%p remote device stopped event "
2434                         "from device 0x%p in unexpected state %d\n",
2435                         ihost, idev,
2436                         ihost->sm.current_state_id);
2437                 return;
2438         }
2439
2440         if (!sci_controller_has_remote_devices_stopping(ihost))
2441                 isci_host_stop_complete(ihost);
2442 }
2443
2444 void sci_controller_post_request(struct isci_host *ihost, u32 request)
2445 {
2446         dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n",
2447                 __func__, ihost->id, request);
2448
2449         writel(request, &ihost->smu_registers->post_context_port);
2450 }
2451
2452 struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag)
2453 {
2454         u16 task_index;
2455         u16 task_sequence;
2456
2457         task_index = ISCI_TAG_TCI(io_tag);
2458
2459         if (task_index < ihost->task_context_entries) {
2460                 struct isci_request *ireq = ihost->reqs[task_index];
2461
2462                 if (test_bit(IREQ_ACTIVE, &ireq->flags)) {
2463                         task_sequence = ISCI_TAG_SEQ(io_tag);
2464
2465                         if (task_sequence == ihost->io_request_sequence[task_index])
2466                                 return ireq;
2467                 }
2468         }
2469
2470         return NULL;
2471 }
2472
2473 /**
2474  * This method allocates remote node index and the reserves the remote node
2475  *    context space for use. This method can fail if there are no more remote
2476  *    node index available.
2477  * @scic: This is the controller object which contains the set of
2478  *    free remote node ids
2479  * @sci_dev: This is the device object which is requesting the a remote node
2480  *    id
2481  * @node_id: This is the remote node id that is assinged to the device if one
2482  *    is available
2483  *
2484  * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2485  * node index available.
2486  */
2487 enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost,
2488                                                             struct isci_remote_device *idev,
2489                                                             u16 *node_id)
2490 {
2491         u16 node_index;
2492         u32 remote_node_count = sci_remote_device_node_count(idev);
2493
2494         node_index = sci_remote_node_table_allocate_remote_node(
2495                 &ihost->available_remote_nodes, remote_node_count
2496                 );
2497
2498         if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
2499                 ihost->device_table[node_index] = idev;
2500
2501                 *node_id = node_index;
2502
2503                 return SCI_SUCCESS;
2504         }
2505
2506         return SCI_FAILURE_INSUFFICIENT_RESOURCES;
2507 }
2508
2509 void sci_controller_free_remote_node_context(struct isci_host *ihost,
2510                                              struct isci_remote_device *idev,
2511                                              u16 node_id)
2512 {
2513         u32 remote_node_count = sci_remote_device_node_count(idev);
2514
2515         if (ihost->device_table[node_id] == idev) {
2516                 ihost->device_table[node_id] = NULL;
2517
2518                 sci_remote_node_table_release_remote_node_index(
2519                         &ihost->available_remote_nodes, remote_node_count, node_id
2520                         );
2521         }
2522 }
2523
2524 void sci_controller_copy_sata_response(void *response_buffer,
2525                                        void *frame_header,
2526                                        void *frame_buffer)
2527 {
2528         /* XXX type safety? */
2529         memcpy(response_buffer, frame_header, sizeof(u32));
2530
2531         memcpy(response_buffer + sizeof(u32),
2532                frame_buffer,
2533                sizeof(struct dev_to_host_fis) - sizeof(u32));
2534 }
2535
2536 void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index)
2537 {
2538         if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index))
2539                 writel(ihost->uf_control.get,
2540                         &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
2541 }
2542
2543 void isci_tci_free(struct isci_host *ihost, u16 tci)
2544 {
2545         u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1);
2546
2547         ihost->tci_pool[tail] = tci;
2548         ihost->tci_tail = tail + 1;
2549 }
2550
2551 static u16 isci_tci_alloc(struct isci_host *ihost)
2552 {
2553         u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1);
2554         u16 tci = ihost->tci_pool[head];
2555
2556         ihost->tci_head = head + 1;
2557         return tci;
2558 }
2559
2560 static u16 isci_tci_space(struct isci_host *ihost)
2561 {
2562         return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
2563 }
2564
2565 u16 isci_alloc_tag(struct isci_host *ihost)
2566 {
2567         if (isci_tci_space(ihost)) {
2568                 u16 tci = isci_tci_alloc(ihost);
2569                 u8 seq = ihost->io_request_sequence[tci];
2570
2571                 return ISCI_TAG(seq, tci);
2572         }
2573
2574         return SCI_CONTROLLER_INVALID_IO_TAG;
2575 }
2576
2577 enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2578 {
2579         u16 tci = ISCI_TAG_TCI(io_tag);
2580         u16 seq = ISCI_TAG_SEQ(io_tag);
2581
2582         /* prevent tail from passing head */
2583         if (isci_tci_active(ihost) == 0)
2584                 return SCI_FAILURE_INVALID_IO_TAG;
2585
2586         if (seq == ihost->io_request_sequence[tci]) {
2587                 ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
2588
2589                 isci_tci_free(ihost, tci);
2590
2591                 return SCI_SUCCESS;
2592         }
2593         return SCI_FAILURE_INVALID_IO_TAG;
2594 }
2595
2596 enum sci_status sci_controller_start_io(struct isci_host *ihost,
2597                                         struct isci_remote_device *idev,
2598                                         struct isci_request *ireq)
2599 {
2600         enum sci_status status;
2601
2602         if (ihost->sm.current_state_id != SCIC_READY) {
2603                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2604                          __func__, ihost->sm.current_state_id);
2605                 return SCI_FAILURE_INVALID_STATE;
2606         }
2607
2608         status = sci_remote_device_start_io(ihost, idev, ireq);
2609         if (status != SCI_SUCCESS)
2610                 return status;
2611
2612         set_bit(IREQ_ACTIVE, &ireq->flags);
2613         sci_controller_post_request(ihost, ireq->post_context);
2614         return SCI_SUCCESS;
2615 }
2616
2617 enum sci_status sci_controller_terminate_request(struct isci_host *ihost,
2618                                                  struct isci_remote_device *idev,
2619                                                  struct isci_request *ireq)
2620 {
2621         /* terminate an ongoing (i.e. started) core IO request.  This does not
2622          * abort the IO request at the target, but rather removes the IO
2623          * request from the host controller.
2624          */
2625         enum sci_status status;
2626
2627         if (ihost->sm.current_state_id != SCIC_READY) {
2628                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2629                          __func__, ihost->sm.current_state_id);
2630                 return SCI_FAILURE_INVALID_STATE;
2631         }
2632         status = sci_io_request_terminate(ireq);
2633
2634         dev_dbg(&ihost->pdev->dev, "%s: status=%d; ireq=%p; flags=%lx\n",
2635                 __func__, status, ireq, ireq->flags);
2636
2637         if ((status == SCI_SUCCESS) &&
2638             !test_bit(IREQ_PENDING_ABORT, &ireq->flags) &&
2639             !test_and_set_bit(IREQ_TC_ABORT_POSTED, &ireq->flags)) {
2640                 /* Utilize the original post context command and or in the
2641                  * POST_TC_ABORT request sub-type.
2642                  */
2643                 sci_controller_post_request(
2644                         ihost, ireq->post_context |
2645                                 SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
2646         }
2647         return status;
2648 }
2649
2650 /**
2651  * sci_controller_complete_io() - This method will perform core specific
2652  *    completion operations for an IO request.  After this method is invoked,
2653  *    the user should consider the IO request as invalid until it is properly
2654  *    reused (i.e. re-constructed).
2655  * @ihost: The handle to the controller object for which to complete the
2656  *    IO request.
2657  * @idev: The handle to the remote device object for which to complete
2658  *    the IO request.
2659  * @ireq: the handle to the io request object to complete.
2660  */
2661 enum sci_status sci_controller_complete_io(struct isci_host *ihost,
2662                                            struct isci_remote_device *idev,
2663                                            struct isci_request *ireq)
2664 {
2665         enum sci_status status;
2666         u16 index;
2667
2668         switch (ihost->sm.current_state_id) {
2669         case SCIC_STOPPING:
2670                 /* XXX: Implement this function */
2671                 return SCI_FAILURE;
2672         case SCIC_READY:
2673                 status = sci_remote_device_complete_io(ihost, idev, ireq);
2674                 if (status != SCI_SUCCESS)
2675                         return status;
2676
2677                 index = ISCI_TAG_TCI(ireq->io_tag);
2678                 clear_bit(IREQ_ACTIVE, &ireq->flags);
2679                 return SCI_SUCCESS;
2680         default:
2681                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2682                          __func__, ihost->sm.current_state_id);
2683                 return SCI_FAILURE_INVALID_STATE;
2684         }
2685
2686 }
2687
2688 enum sci_status sci_controller_continue_io(struct isci_request *ireq)
2689 {
2690         struct isci_host *ihost = ireq->owning_controller;
2691
2692         if (ihost->sm.current_state_id != SCIC_READY) {
2693                 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2694                          __func__, ihost->sm.current_state_id);
2695                 return SCI_FAILURE_INVALID_STATE;
2696         }
2697
2698         set_bit(IREQ_ACTIVE, &ireq->flags);
2699         sci_controller_post_request(ihost, ireq->post_context);
2700         return SCI_SUCCESS;
2701 }
2702
2703 /**
2704  * sci_controller_start_task() - This method is called by the SCIC user to
2705  *    send/start a framework task management request.
2706  * @controller: the handle to the controller object for which to start the task
2707  *    management request.
2708  * @remote_device: the handle to the remote device object for which to start
2709  *    the task management request.
2710  * @task_request: the handle to the task request object to start.
2711  */
2712 enum sci_task_status sci_controller_start_task(struct isci_host *ihost,
2713                                                struct isci_remote_device *idev,
2714                                                struct isci_request *ireq)
2715 {
2716         enum sci_status status;
2717
2718         if (ihost->sm.current_state_id != SCIC_READY) {
2719                 dev_warn(&ihost->pdev->dev,
2720                          "%s: SCIC Controller starting task from invalid "
2721                          "state\n",
2722                          __func__);
2723                 return SCI_TASK_FAILURE_INVALID_STATE;
2724         }
2725
2726         status = sci_remote_device_start_task(ihost, idev, ireq);
2727         switch (status) {
2728         case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
2729                 set_bit(IREQ_ACTIVE, &ireq->flags);
2730
2731                 /*
2732                  * We will let framework know this task request started successfully,
2733                  * although core is still woring on starting the request (to post tc when
2734                  * RNC is resumed.)
2735                  */
2736                 return SCI_SUCCESS;
2737         case SCI_SUCCESS:
2738                 set_bit(IREQ_ACTIVE, &ireq->flags);
2739                 sci_controller_post_request(ihost, ireq->post_context);
2740                 break;
2741         default:
2742                 break;
2743         }
2744
2745         return status;
2746 }
2747
2748 static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data)
2749 {
2750         int d;
2751
2752         /* no support for TX_GP_CFG */
2753         if (reg_index == 0)
2754                 return -EINVAL;
2755
2756         for (d = 0; d < isci_gpio_count(ihost); d++) {
2757                 u32 val = 0x444; /* all ODx.n clear */
2758                 int i;
2759
2760                 for (i = 0; i < 3; i++) {
2761                         int bit = (i << 2) + 2;
2762
2763                         bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i),
2764                                                        write_data, reg_index,
2765                                                        reg_count);
2766                         if (bit < 0)
2767                                 break;
2768
2769                         /* if od is set, clear the 'invert' bit */
2770                         val &= ~(bit << ((i << 2) + 2));
2771                 }
2772
2773                 if (i < 3)
2774                         break;
2775                 writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]);
2776         }
2777
2778         /* unless reg_index is > 1, we should always be able to write at
2779          * least one register
2780          */
2781         return d > 0;
2782 }
2783
2784 int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index,
2785                     u8 reg_count, u8 *write_data)
2786 {
2787         struct isci_host *ihost = sas_ha->lldd_ha;
2788         int written;
2789
2790         switch (reg_type) {
2791         case SAS_GPIO_REG_TX_GP:
2792                 written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data);
2793                 break;
2794         default:
2795                 written = -EINVAL;
2796         }
2797
2798         return written;
2799 }