drivers/scsi/isci/core/scu_registers.h

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * BSD LICENSE
  25  *
  26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27  * All rights reserved.
  28  *
  29  * Redistribution and use in source and binary forms, with or without
  30  * modification, are permitted provided that the following conditions
  31  * are met:
  32  *
  33  *   * Redistributions of source code must retain the above copyright
  34  *     notice, this list of conditions and the following disclaimer.
  35  *   * Redistributions in binary form must reproduce the above copyright
  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *   * Neither the name of Intel Corporation nor the names of its
  40  *     contributors may be used to endorse or promote products derived
  41  *     from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  */
  55
  56 #ifndef _SCU_REGISTERS_H_
  57 #define _SCU_REGISTERS_H_
  58
  59 /**
  60  * This file contains the constants and structures for the SCU memory mapped
  61  *    registers.
  62  *
  63  *
  64  */
  65
  66 #include "sci_types.h"
  67 #include "scu_viit_data.h"
  68
  69
  70 /* Generate a value for an SCU register */
  71 #define SCU_GEN_VALUE(name, value) \
  72         (((value) << name ## _SHIFT) & (name ## _MASK))
  73
  74 /*
  75  * Generate a bit value for an SCU register
  76  * Make sure that the register MASK is just a single bit */
  77 #define SCU_GEN_BIT(name) \
  78         SCU_GEN_VALUE(name, ((u32)1))
  79
  80 #define SCU_SET_BIT(name, reg_value) \
  81         ((reg_value) | SCU_GEN_BIT(name))
  82
  83 #define SCU_CLEAR_BIT(name, reg_value) \
  84         ((reg_value)$ ~(SCU_GEN_BIT(name)))
  85
  86 /*
  87  * *****************************************************************************
  88  * Unions for bitfield definitions of SCU Registers
  89  * SMU Post Context Port
  90  * ***************************************************************************** */
  91 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT         (0)
  92 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK          (0x00000FFF)
  93 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_SHIFT    (12)
  94 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK     (0x0000F000)
  95 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_SHIFT       (16)
  96 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK        (0x00030000)
  97 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_SHIFT       (18)
  98 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK        (0x00FC0000)
  99 #define SMU_POST_CONTEXT_PORT_RESERVED_MASK               (0xFF000000)
 100
 101 #define SMU_PCP_GEN_VAL(name, value) \
 102         SCU_GEN_VALUE(SMU_POST_CONTEXT_PORT_ ## name, value)
 103
 104 /* ***************************************************************************** */
 105 #define SMU_INTERRUPT_STATUS_COMPLETION_SHIFT       (31)
 106 #define SMU_INTERRUPT_STATUS_COMPLETION_MASK        (0x80000000)
 107 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_SHIFT    (1)
 108 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK     (0x00000002)
 109 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT      (0)
 110 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK       (0x00000001)
 111 #define SMU_INTERRUPT_STATUS_RESERVED_MASK          (0x7FFFFFFC)
 112
 113 #define SMU_ISR_GEN_BIT(name) \
 114         SCU_GEN_BIT(SMU_INTERRUPT_STATUS_ ## name)
 115
 116 #define SMU_ISR_QUEUE_ERROR   SMU_ISR_GEN_BIT(QUEUE_ERROR)
 117 #define SMU_ISR_QUEUE_SUSPEND SMU_ISR_GEN_BIT(QUEUE_SUSPEND)
 118 #define SMU_ISR_COMPLETION    SMU_ISR_GEN_BIT(COMPLETION)
 119
 120 /* ***************************************************************************** */
 121 #define SMU_INTERRUPT_MASK_COMPLETION_SHIFT         (31)
 122 #define SMU_INTERRUPT_MASK_COMPLETION_MASK          (0x80000000)
 123 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_SHIFT      (1)
 124 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_MASK       (0x00000002)
 125 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT        (0)
 126 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_MASK         (0x00000001)
 127 #define SMU_INTERRUPT_MASK_RESERVED_MASK            (0x7FFFFFFC)
 128
 129 #define SMU_IMR_GEN_BIT(name) \
 130         SCU_GEN_BIT(SMU_INTERRUPT_MASK_ ## name)
 131
 132 #define SMU_IMR_QUEUE_ERROR   SMU_IMR_GEN_BIT(QUEUE_ERROR)
 133 #define SMU_IMR_QUEUE_SUSPEND SMU_IMR_GEN_BIT(QUEUE_SUSPEND)
 134 #define SMU_IMR_COMPLETION    SMU_IMR_GEN_BIT(COMPLETION)
 135
 136 /* ***************************************************************************** */
 137 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_SHIFT    (0)
 138 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_MASK     (0x0000001F)
 139 #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_SHIFT   (8)
 140 #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_MASK    (0x0000FF00)
 141 #define SMU_INTERRUPT_COALESCING_CONTROL_RESERVED_MASK  (0xFFFF00E0)
 142
 143 #define SMU_ICC_GEN_VAL(name, value) \
 144         SCU_GEN_VALUE(SMU_INTERRUPT_COALESCING_CONTROL_ ## name, value)
 145
 146 /* ***************************************************************************** */
 147 #define SMU_TASK_CONTEXT_RANGE_START_SHIFT      (0)
 148 #define SMU_TASK_CONTEXT_RANGE_START_MASK       (0x00000FFF)
 149 #define SMU_TASK_CONTEXT_RANGE_ENDING_SHIFT     (16)
 150 #define SMU_TASK_CONTEXT_RANGE_ENDING_MASK      (0x0FFF0000)
 151 #define SMU_TASK_CONTEXT_RANGE_ENABLE_SHIFT     (31)
 152 #define SMU_TASK_CONTEXT_RANGE_ENABLE_MASK      (0x80000000)
 153 #define SMU_TASK_CONTEXT_RANGE_RESERVED_MASK    (0x7000F000)
 154
 155 #define SMU_TCR_GEN_VAL(name, value) \
 156         SCU_GEN_VALUE(SMU_TASK_CONTEXT_RANGE_ ## name, value)
 157
 158 #define SMU_TCR_GEN_BIT(name, value) \
 159         SCU_GEN_BIT(SMU_TASK_CONTEXT_RANGE_ ## name)
 160
 161 /* ***************************************************************************** */
 162
 163 #define SMU_COMPLETION_QUEUE_PUT_POINTER_SHIFT          (0)
 164 #define SMU_COMPLETION_QUEUE_PUT_POINTER_MASK           (0x00003FFF)
 165 #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_SHIFT        (15)
 166 #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_MASK         (0x00008000)
 167 #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_SHIFT    (16)
 168 #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_MASK     (0x03FF0000)
 169 #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_SHIFT  (26)
 170 #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_MASK   (0x04000000)
 171 #define SMU_COMPLETION_QUEUE_PUT_RESERVED_MASK          (0xF8004000)
 172
 173 #define SMU_CQPR_GEN_VAL(name, value) \
 174         SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_PUT_ ## name, value)
 175
 176 #define SMU_CQPR_GEN_BIT(name) \
 177         SCU_GEN_BIT(SMU_COMPLETION_QUEUE_PUT_ ## name)
 178
 179 /* ***************************************************************************** */
 180
 181 #define SMU_COMPLETION_QUEUE_GET_POINTER_SHIFT          (0)
 182 #define SMU_COMPLETION_QUEUE_GET_POINTER_MASK           (0x00003FFF)
 183 #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT        (15)
 184 #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_MASK         (0x00008000)
 185 #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT    (16)
 186 #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK     (0x03FF0000)
 187 #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT  (26)
 188 #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_MASK   (0x04000000)
 189 #define SMU_COMPLETION_QUEUE_GET_ENABLE_SHIFT           (30)
 190 #define SMU_COMPLETION_QUEUE_GET_ENABLE_MASK            (0x40000000)
 191 #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_SHIFT     (31)
 192 #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_MASK      (0x80000000)
 193 #define SMU_COMPLETION_QUEUE_GET_RESERVED_MASK          (0x38004000)
 194
 195 #define SMU_CQGR_GEN_VAL(name, value) \
 196         SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_GET_ ## name, value)
 197
 198 #define SMU_CQGR_GEN_BIT(name) \
 199         SCU_GEN_BIT(SMU_COMPLETION_QUEUE_GET_ ## name)
 200
 201 #define SMU_CQGR_CYCLE_BIT \
 202         SMU_CQGR_GEN_BIT(CYCLE_BIT)
 203
 204 #define SMU_CQGR_EVENT_CYCLE_BIT \
 205         SMU_CQGR_GEN_BIT(EVENT_CYCLE_BIT)
 206
 207 #define SMU_CQGR_GET_POINTER_SET(value) \
 208         SMU_CQGR_GEN_VAL(POINTER, value)
 209
 210
 211 /* ***************************************************************************** */
 212 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_SHIFT  (0)
 213 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_MASK   (0x00003FFF)
 214 #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_SHIFT  (16)
 215 #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_MASK   (0x03FF0000)
 216 #define SMU_COMPLETION_QUEUE_CONTROL_RESERVED_MASK      (0xFC00C000)
 217
 218 #define SMU_CQC_GEN_VAL(name, value) \
 219         SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_CONTROL_ ## name, value)
 220
 221 #define SMU_CQC_QUEUE_LIMIT_SET(value) \
 222         SMU_CQC_GEN_VAL(QUEUE_LIMIT, value)
 223
 224 #define SMU_CQC_EVENT_LIMIT_SET(value) \
 225         SMU_CQC_GEN_VAL(EVENT_LIMIT, value)
 226
 227
 228 /* ***************************************************************************** */
 229 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT    (0)
 230 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK     (0x00000FFF)
 231 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT    (12)
 232 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK     (0x00007000)
 233 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT   (15)
 234 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK    (0x07FF8000)
 235 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_SHIFT   (27)
 236 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK    (0x08000000)
 237 #define SMU_DEVICE_CONTEXT_CAPACITY_RESERVED_MASK   (0xF0000000)
 238
 239 #define SMU_DCC_GEN_VAL(name, value) \
 240         SCU_GEN_VALUE(SMU_DEVICE_CONTEXT_CAPACITY_ ## name, value)
 241
 242 #define SMU_DCC_GET_MAX_PEG(value) \
 243         (\
 244                 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK) \
 245                 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \
 246         )
 247
 248 #define SMU_DCC_GET_MAX_LP(value) \
 249         (\
 250                 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
 251                 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \
 252         )
 253
 254 #define SMU_DCC_GET_MAX_TC(value) \
 255         (\
 256                 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
 257                 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT \
 258         )
 259
 260 #define SMU_DCC_GET_MAX_RNC(value) \
 261         (\
 262                 ((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
 263                 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT \
 264         )
 265
 266 /* -------------------------------------------------------------------------- */
 267
 268 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_SHIFT      (0)
 269 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_MASK       (0x00000001)
 270 #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_SHIFT    (1)
 271 #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_MASK     (0x00000002)
 272 #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_SHIFT     (16)
 273 #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_MASK      (0x00010000)
 274 #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_SHIFT   (17)
 275 #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_MASK    (0x00020000)
 276 #define SMU_CONTROL_STATUS_RESERVED_MASK                        (0xFFFCFFFC)
 277
 278 #define SMU_SMUCSR_GEN_BIT(name) \
 279         SCU_GEN_BIT(SMU_CONTROL_STATUS_ ## name)
 280
 281 #define SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \
 282         (SMU_SMUCSR_GEN_BIT(SCHEDULER_RAM_INIT_COMPLETED))
 283
 284 #define SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED   \
 285         (SMU_SMUCSR_GEN_BIT(CONTEXT_RAM_INIT_COMPLETED))
 286
 287 #define SCU_RAM_INIT_COMPLETED \
 288         (\
 289                 SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \
 290                 | SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \
 291         )
 292
 293 /* -------------------------------------------------------------------------- */
 294
 295 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_SHIFT  (0)
 296 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_MASK   (0x00000001)
 297 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_SHIFT  (1)
 298 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_MASK   (0x00000002)
 299 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_SHIFT  (2)
 300 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_MASK   (0x00000004)
 301 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_SHIFT  (3)
 302 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_MASK   (0x00000008)
 303 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_SHIFT  (8)
 304 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_MASK   (0x00000100)
 305 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_SHIFT  (9)
 306 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_MASK   (0x00000200)
 307 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_SHIFT  (10)
 308 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_MASK   (0x00000400)
 309 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_SHIFT  (11)
 310 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_MASK   (0x00000800)
 311
 312 #define SMU_RESET_PROTOCOL_ENGINE(peg, pe) \
 313         ((1 << (pe)) << ((peg) * 8))
 314
 315 #define SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \
 316         (\
 317                 SMU_RESET_PROTOCOL_ENGINE(peg, 0) \
 318                 | SMU_RESET_PROTOCOL_ENGINE(peg, 1) \
 319                 | SMU_RESET_PROTOCOL_ENGINE(peg, 2) \
 320                 | SMU_RESET_PROTOCOL_ENGINE(peg, 3) \
 321         )
 322
 323 #define SMU_RESET_ALL_PROTOCOL_ENGINES() \
 324         (\
 325                 SMU_RESET_PEG_PROTOCOL_ENGINES(0) \
 326                 | SMU_RESET_PEG_PROTOCOL_ENGINES(1) \
 327         )
 328
 329 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_SHIFT  (16)
 330 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_MASK   (0x00010000)
 331 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_SHIFT  (17)
 332 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_MASK   (0x00020000)
 333 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_SHIFT  (18)
 334 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_MASK   (0x00040000)
 335 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_SHIFT  (19)
 336 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_MASK   (0x00080000)
 337
 338 #define SMU_RESET_WIDE_PORT_QUEUE(peg, wide_port) \
 339         ((1 << ((wide_port) / 2)) << ((peg) * 2) << 16)
 340
 341 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_SHIFT      (20)
 342 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_MASK       (0x00100000)
 343 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_SHIFT      (21)
 344 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_MASK       (0x00200000)
 345 #define SMU_SOFTRESET_CONTROL_RESET_SCU_SHIFT       (22)
 346 #define SMU_SOFTRESET_CONTROL_RESET_SCU_MASK        (0x00400000)
 347
 348 /*
 349  * It seems to make sense that if you are going to reset the protocol
 350  * engine group that you would also reset all of the protocol engines */
 351 #define SMU_RESET_PROTOCOL_ENGINE_GROUP(peg) \
 352         (\
 353                 (1 << ((peg) + 20)) \
 354                 | SMU_RESET_WIDE_PORT_QUEUE(peg, 0) \
 355                 | SMU_RESET_WIDE_PORT_QUEUE(peg, 1) \
 356                 | SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \
 357         )
 358
 359 #define SMU_RESET_ALL_PROTOCOL_ENGINE_GROUPS() \
 360         (\
 361                 SMU_RESET_PROTOCOL_ENGINE_GROUP(0) \
 362                 | SMU_RESET_PROTOCOL_ENGINE_GROUP(1) \
 363         )
 364
 365 #define SMU_RESET_SCU()  (0xFFFFFFFF)
 366
 367
 368
 369 /* ***************************************************************************** */
 370 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_SHIFT              (0)
 371 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_MASK               (0x00000FFF)
 372 #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_SHIFT                (16)
 373 #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_MASK                 (0x0FFF0000)
 374 #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_SHIFT    (31)
 375 #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_MASK     (0x80000000)
 376 #define SMU_TASK_CONTEXT_ASSIGNMENT_RESERVED_MASK               (0x7000F000)
 377
 378 #define SMU_TCA_GEN_VAL(name, value) \
 379         SCU_GEN_VALUE(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name, value)
 380
 381 #define SMU_TCA_GEN_BIT(name) \
 382         SCU_GEN_BIT(SMU_TASK_CONTEXT_ASSIGNMENT_ ## name)
 383
 384 /* ***************************************************************************** */
 385 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_SHIFT   (0)
 386 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_MASK    (0x00000FFF)
 387 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_RESERVED_MASK      (0xFFFFF000)
 388
 389 #define SCU_UFQC_GEN_VAL(name, value) \
 390         SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_ ## name, value)
 391
 392 #define SCU_UFQC_QUEUE_SIZE_SET(value) \
 393         SCU_UFQC_GEN_VAL(QUEUE_SIZE, value)
 394
 395 /* ***************************************************************************** */
 396 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_SHIFT      (0)
 397 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_MASK       (0x00000FFF)
 398 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_SHIFT    (12)
 399 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_MASK     (0x00001000)
 400 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_RESERVED_MASK      (0xFFFFE000)
 401
 402 #define SCU_UFQPP_GEN_VAL(name, value) \
 403         SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name, value)
 404
 405 #define SCU_UFQPP_GEN_BIT(name) \
 406         SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_ ## name)
 407
 408 /*
 409  * *****************************************************************************
 410  * * SDMA Registers
 411  * ***************************************************************************** */
 412 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_SHIFT      (0)
 413 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_MASK       (0x00000FFF)
 414 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_SHIFT    (12)
 415 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_MASK     (12)
 416 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_SHIFT   (31)
 417 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_MASK    (0x80000000)
 418 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_RESERVED_MASK      (0x7FFFE000)
 419
 420 #define SCU_UFQGP_GEN_VAL(name, value) \
 421         SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name, value)
 422
 423 #define SCU_UFQGP_GEN_BIT(name) \
 424         SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ ## name)
 425
 426 #define SCU_UFQGP_CYCLE_BIT(value) \
 427         SCU_UFQGP_GEN_BIT(CYCLE_BIT, value)
 428
 429 #define SCU_UFQGP_GET_POINTER(value) \
 430         SCU_UFQGP_GEN_VALUE(POINTER, value)
 431
 432 #define SCU_UFQGP_ENABLE(value) \
 433         (SCU_UFQGP_GEN_BIT(ENABLE) | value)
 434
 435 #define SCU_UFQGP_DISABLE(value) \
 436         (~SCU_UFQGP_GEN_BIT(ENABLE) & value)
 437
 438 #define SCU_UFQGP_VALUE(bit, value) \
 439         (SCU_UFQGP_CYCLE_BIT(bit) | SCU_UFQGP_GET_POINTER(value))
 440
 441 /* ***************************************************************************** */
 442 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SHIFT                               (0)
 443 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_MASK                                (0x0000FFFF)
 444 #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT                    (16)
 445 #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK                     (0x00010000)
 446 #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_SHIFT                            (17)
 447 #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_MASK                             (0x00020000)
 448 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_SHIFT                   (18)
 449 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_MASK                    (0x00040000)
 450 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_SHIFT               (19)
 451 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_MASK                (0x00080000)
 452 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_SHIFT     (20)
 453 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_MASK      (0x00100000)
 454 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_SHIFT        (21)
 455 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_MASK         (0x00200000)
 456 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_SHIFT                        (22)
 457 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_MASK                         (0x00400000)
 458 #define SCU_PDMA_CONFIGURATION_RESERVED_MASK                                        (0xFF800000)
 459
 460 #define SCU_PDMACR_GEN_VALUE(name, value) \
 461         SCU_GEN_VALUE(SCU_PDMA_CONFIGURATION_ ## name, value)
 462
 463 #define SCU_PDMACR_GEN_BIT(name) \
 464         SCU_GEN_BIT(SCU_PDMA_CONFIGURATION_ ## name)
 465
 466 #define SCU_PDMACR_BE_GEN_BIT(name) \
 467         SCU_PCMACR_GEN_BIT(BIG_ENDIAN_CONTROL_ ## name)
 468
 469 /* ***************************************************************************** */
 470 #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT                    (8)
 471 #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK                     (0x00000100)
 472
 473 #define SCU_CDMACR_GEN_BIT(name) \
 474         SCU_GEN_BIT(SCU_CDMA_CONFIGURATION_ ## name)
 475
 476 /*
 477  * *****************************************************************************
 478  * * SCU Link Layer Registers
 479  * ***************************************************************************** */
 480 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_SHIFT             (0)
 481 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_MASK              (0x000000FF)
 482 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_SHIFT           (8)
 483 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_MASK            (0x0000FF00)
 484 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_SHIFT   (16)
 485 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_MASK    (0x00FF0000)
 486 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_SHIFT  (24)
 487 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_MASK   (0xFF000000)
 488 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_REQUIRED_MASK             (0x00000000)
 489 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_DEFAULT_MASK              (0x7D00676F)
 490 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_RESERVED_MASK             (0x00FF0000)
 491
 492 #define SCU_SAS_SPDTOV_GEN_VALUE(name, value) \
 493         SCU_GEN_VALUE(SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_ ## name, value)
 494
 495
 496 #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_SHIFT            (2)
 497 #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_MASK             (0x00000004)
 498 #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_SHIFT  (4)
 499 #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_MASK   (0x00000010)
 500 #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_SHIFT     (5)
 501 #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_MASK      (0x00000020)
 502 #define SCU_LINK_STATUS_RESERVED_MASK                       (0xFFFFFFCD)
 503
 504 #define SCU_SAS_LLSTA_GEN_BIT(name) \
 505         SCU_GEN_BIT(SCU_LINK_STATUS_ ## name)
 506
 507
 508 /* TODO: Where is the SATA_PSELTOV register? */
 509
 510 /*
 511  * *****************************************************************************
 512  * * SCU SAS Maximum Arbitration Wait Time Timeout Register
 513  * ***************************************************************************** */
 514 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_SHIFT       (0)
 515 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_MASK        (0x00007FFF)
 516 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_SHIFT       (15)
 517 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_MASK        (0x00008000)
 518
 519 #define SCU_SAS_MAWTTOV_GEN_VALUE(name, value) \
 520         SCU_GEN_VALUE(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name, value)
 521
 522 #define SCU_SAS_MAWTTOV_GEN_BIT(name) \
 523         SCU_GEN_BIT(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_ ## name)
 524
 525
 526 /*
 527  * TODO: Where is the SAS_LNKTOV regsiter?
 528  * TODO: Where is the SAS_PHYTOV register? */
 529
 530 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_SHIFT            (1)
 531 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_MASK             (0x00000002)
 532 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_SHIFT            (2)
 533 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_MASK             (0x00000004)
 534 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_SHIFT            (3)
 535 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_MASK             (0x00000008)
 536 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_SHIFT          (8)
 537 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_MASK           (0x00000100)
 538 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_SHIFT         (9)
 539 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_MASK          (0x00000200)
 540 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_SHIFT         (10)
 541 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_MASK          (0x00000400)
 542 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_SHIFT         (11)
 543 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_MASK          (0x00000800)
 544 #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_SHIFT           (16)
 545 #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_MASK            (0x000F0000)
 546 #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_SHIFT    (24)
 547 #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_MASK     (0x0F000000)
 548 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_SHIFT           (28)
 549 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_MASK            (0x70000000)
 550 #define SCU_SAS_TRANSMIT_IDENTIFICATION_RESERVED_MASK               (0x80F0F1F1)
 551
 552 #define SCU_SAS_TIID_GEN_VAL(name, value) \
 553         SCU_GEN_VALUE(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name, value)
 554
 555 #define SCU_SAS_TIID_GEN_BIT(name) \
 556         SCU_GEN_BIT(SCU_SAS_TRANSMIT_IDENTIFICATION_ ## name)
 557
 558 /* SAS Identify Frame PHY Identifier Register */
 559 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_SHIFT      (16)
 560 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_MASK       (0x00010000)
 561 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_SHIFT   (17)
 562 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_MASK    (0x00020000)
 563 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_SHIFT  (18)
 564 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_MASK   (0x00040000)
 565 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_SHIFT                       (24)
 566 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_MASK                        (0xFF000000)
 567 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_RESERVED_MASK                  (0x00F800FF)
 568
 569 #define SCU_SAS_TIPID_GEN_VALUE(name, value) \
 570         SCU_GEN_VALUE(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name, value)
 571
 572 #define SCU_SAS_TIPID_GEN_BIT(name) \
 573         SCU_GEN_BIT(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ ## name)
 574
 575
 576 #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_SHIFT                     (4)
 577 #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_MASK                      (0x00000010)
 578 #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_SHIFT                          (6)
 579 #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_MASK                           (0x00000040)
 580 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_SHIFT                   (7)
 581 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_MASK                    (0x00000080)
 582 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_SHIFT                 (8)
 583 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_MASK                  (0x00000100)
 584 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_SHIFT            (9)
 585 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_MASK             (0x00000200)
 586 #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_SHIFT             (11)
 587 #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_MASK              (0x00000800)
 588 #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_SHIFT                    (12)
 589 #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_MASK                     (0x00001000)
 590 #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_SHIFT      (13)
 591 #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_MASK       (0x00002000)
 592 #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_SHIFT                          (14)
 593 #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_MASK                           (0x00004000)
 594 #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_SHIFT                          (15)
 595 #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_MASK                           (0x00008000)
 596 #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_SHIFT        (23)
 597 #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_MASK         (0x00800000)
 598 #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_SHIFT              (27)
 599 #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_MASK               (0x08000000)
 600 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_SHIFT    (28)
 601 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_MASK     (0x10000000)
 602 #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_SHIFT                           (29)
 603 #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_MASK                            (0x20000000)
 604 #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_SHIFT                    (30)
 605 #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_MASK                     (0x40000000)
 606 #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_SHIFT                   (31)
 607 #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_MASK                    (0x80000000)
 608 #define SCU_SAS_PHY_CONFIGURATION_REQUIRED_MASK                             (0x0100000F)
 609 #define SCU_SAS_PHY_CONFIGURATION_DEFAULT_MASK                              (0x4180100F)
 610 #define SCU_SAS_PHY_CONFIGURATION_RESERVED_MASK                             (0x00000000)
 611
 612 #define SCU_SAS_PCFG_GEN_BIT(name) \
 613         SCU_GEN_BIT(SCU_SAS_PHY_CONFIGURATION_ ## name)
 614
 615
 616 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT    (0)
 617 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK     (0x0003FFFF)
 618 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_SHIFT   (31)
 619 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_MASK    (0x80000000)
 620 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_RESERVED_MASK  (0x7FFC0000)
 621
 622 #define SCU_ENSPINUP_GEN_VAL(name, value) \
 623         SCU_GEN_VALUE(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name, value)
 624
 625 #define SCU_ENSPINUP_GEN_BIT(name) \
 626         SCU_GEN_BIT(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ ## name)
 627
 628
 629 #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_SHIFT     (1)
 630 #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_MASK      (0x00000002)
 631 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_SHIFT       (4)
 632 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_MASK        (0x000000F0)
 633 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_SHIFT     (8)
 634 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_MASK      (0x00000100)
 635 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_SHIFT      (9)
 636 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_MASK       (0x00000201)
 637 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_SHIFT     (10)
 638 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_MASK      (0x00000401)
 639 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_SHIFT      (11)
 640 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_MASK       (0x00000801)
 641 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_SHIFT     (12)
 642 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_MASK      (0x00001001)
 643 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_SHIFT      (13)
 644 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_MASK       (0x00002001)
 645 #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_SHIFT   (31)
 646 #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_MASK    (0x80000000)
 647 #define SCU_LINK_LAYER_PHY_CAPABILITIES_DEFAULT_MASK        (0x00003F01)
 648 #define SCU_LINK_LAYER_PHY_CAPABILITIES_REQUIRED_MASK       (0x00000001)
 649 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RESERVED_MASK       (0x7FFFC00D)
 650
 651 #define SCU_SAS_PHYCAP_GEN_VAL(name, value) \
 652         SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name, value)
 653
 654 #define SCU_SAS_PHYCAP_GEN_BIT(name) \
 655         SCU_GEN_BIT(SCU_LINK_LAYER_PHY_CAPABILITIES_ ## name)
 656
 657
 658 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_SHIFT  (0)
 659 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_MASK   (0x000000FF)
 660 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_SHIFT         (31)
 661 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_MASK          (0x80000000)
 662 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_RESERVED_MASK                          (0x7FFFFF00)
 663
 664 #define SCU_PSZGCR_GEN_VAL(name, value) \
 665         SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name, value)
 666
 667 #define SCU_PSZGCR_GEN_BIT(name) \
 668         SCU_GEN_BIT(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_ ## name)
 669
 670 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_SHIFT        (1)
 671 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_MASK         (0x00000002)
 672 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_SHIFT      (2)
 673 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_MASK       (0x00000004)
 674 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_SHIFT        (4)
 675 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_MASK         (0x00000010)
 676 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_SHIFT      (5)
 677 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_MASK       (0x00000020)
 678 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_SHIFT (16)
 679 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_MASK  (0x00030000)
 680 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_SHIFT      (19)
 681 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_MASK       (0x00080000)
 682 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_SHIFT (20)
 683 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_MASK  (0x00300000)
 684 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_SHIFT      (23)
 685 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_MASK       (0x00800000)
 686 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_SHIFT (24)
 687 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_MASK  (0x03000000)
 688 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_SHIFT      (27)
 689 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_MASK       (0x08000000)
 690 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_SHIFT (28)
 691 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_MASK  (0x30000000)
 692 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_SHIFT      (31)
 693 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_MASK       (0x80000000)
 694 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_RESERVED_MASK             (0x4444FFC9)
 695
 696 #define SCU_PEG_SCUVZECR_GEN_VAL(name, val) \
 697         SCU_GEN_VALUE(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name, val)
 698
 699 #define SCU_PEG_SCUVZECR_GEN_BIT(name) \
 700         SCU_GEN_BIT(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ ## name)
 701
 702
 703 /*
 704  * *****************************************************************************
 705  * * Port Task Scheduler registers shift and mask values
 706  * ***************************************************************************** */
 707 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_SHIFT     (0)
 708 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_MASK      (0x0000FFFF)
 709 #define SCU_PTSG_CONTROL_TASK_TIMEOUT_SHIFT         (16)
 710 #define SCU_PTSG_CONTROL_TASK_TIMEOUT_MASK          (0x00FF0000)
 711 #define SCU_PTSG_CONTROL_PTSG_ENABLE_SHIFT          (24)
 712 #define SCU_PTSG_CONTROL_PTSG_ENABLE_MASK           (0x01000000)
 713 #define SCU_PTSG_CONTROL_ETM_ENABLE_SHIFT           (25)
 714 #define SCU_PTSG_CONTROL_ETM_ENABLE_MASK            (0x02000000)
 715 #define SCU_PTSG_CONTROL_DEFAULT_MASK               (0x00020002)
 716 #define SCU_PTSG_CONTROL_REQUIRED_MASK              (0x00000000)
 717 #define SCU_PTSG_CONTROL_RESERVED_MASK              (0xFC000000)
 718
 719 #define SCU_PTSGCR_GEN_VAL(name, val) \
 720         SCU_GEN_VALUE(SCU_PTSG_CONTROL_ ## name, val)
 721
 722 #define SCU_PTSGCR_GEN_BIT(name) \
 723         SCU_GEN_BIT(SCU_PTSG_CONTROL_ ## name)
 724
 725
 726 /* ***************************************************************************** */
 727 #define SCU_PTSG_REAL_TIME_CLOCK_SHIFT          (0)
 728 #define SCU_PTSG_REAL_TIME_CLOCK_MASK           (0x0000FFFF)
 729 #define SCU_PTSG_REAL_TIME_CLOCK_RESERVED_MASK  (0xFFFF0000)
 730
 731 #define SCU_RTCR_GEN_VAL(name, val) \
 732         SCU_GEN_VALUE(SCU_PTSG_ ## name, val)
 733
 734
 735 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_SHIFT  (0)
 736 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_MASK   (0x00FFFFFF)
 737 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_RESERVED_MASK          (0xFF000000)
 738
 739 #define SCU_RTCCR_GEN_VAL(name, val) \
 740         SCU_GEN_VALUE(SCU_PTSG_REAL_TIME_CLOCK_CONTROL_ ## name, val)
 741
 742
 743 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_SHIFT  (0)
 744 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_MASK   (0x00000001)
 745 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_SHIFT   (1)
 746 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_MASK    (0x00000002)
 747 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_RESERVED_MASK  (0xFFFFFFFC)
 748
 749 #define SCU_PTSxCR_GEN_BIT(name) \
 750         SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ ## name)
 751
 752
 753 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_SHIFT             (0)
 754 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_MASK              (0x00000001)
 755 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_SHIFT    (1)
 756 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_MASK     (0x00000002)
 757 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_SHIFT             (2)
 758 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_MASK              (0x00000004)
 759 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_RESERVED_MASK                   (0xFFFFFFF8)
 760
 761 #define SCU_PTSxSR_GEN_BIT(name) \
 762         SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ ## name)
 763
 764
 765 /*
 766  * *****************************************************************************
 767  * * SGPIO Register shift and mask values
 768  * ***************************************************************************** */
 769 #define SCU_SGPIO_CONTROL_SGPIO_ENABLE_SHIFT                    (0)
 770 #define SCU_SGPIO_CONTROL_SGPIO_ENABLE_MASK                     (0x00000001)
 771 #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_SHIFT       (1)
 772 #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_MASK        (0x00000002)
 773 #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_SHIFT (2)
 774 #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_MASK  (0x00000004)
 775 #define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_SHIFT                  (15)
 776 #define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_MASK                   (0x00008000)
 777 #define SCU_SGPIO_CONTROL_SGPIO_RESERVED_MASK                   (0xFFFF7FF8)
 778
 779 #define SCU_SGICRx_GEN_BIT(name) \
 780         SCU_GEN_BIT(SCU_SGPIO_CONTROL_SGPIO_ ## name)
 781
 782 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_SHIFT      (0)
 783 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_MASK       (0x0000000F)
 784 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_SHIFT      (4)
 785 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_MASK       (0x000000F0)
 786 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_SHIFT      (8)
 787 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_MASK       (0x00000F00)
 788 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_SHIFT      (12)
 789 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_MASK       (0x0000F000)
 790 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_RESERVED_MASK (0xFFFF0000)
 791
 792 #define SCU_SGPBRx_GEN_VAL(name, value) \
 793         SCU_GEN_VALUE(SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_ ## name, value)
 794
 795 #define SCU_SGPIO_START_DRIVE_LOWER_R0_SHIFT        (0)
 796 #define SCU_SGPIO_START_DRIVE_LOWER_R0_MASK         (0x00000003)
 797 #define SCU_SGPIO_START_DRIVE_LOWER_R1_SHIFT        (4)
 798 #define SCU_SGPIO_START_DRIVE_LOWER_R1_MASK         (0x00000030)
 799 #define SCU_SGPIO_START_DRIVE_LOWER_R2_SHIFT        (8)
 800 #define SCU_SGPIO_START_DRIVE_LOWER_R2_MASK         (0x00000300)
 801 #define SCU_SGPIO_START_DRIVE_LOWER_R3_SHIFT        (12)
 802 #define SCU_SGPIO_START_DRIVE_LOWER_R3_MASK         (0x00003000)
 803 #define SCU_SGPIO_START_DRIVE_LOWER_RESERVED_MASK   (0xFFFF8888)
 804
 805 #define SCU_SGSDLRx_GEN_VAL(name, value) \
 806         SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_ ## name, value)
 807
 808 #define SCU_SGPIO_START_DRIVE_UPPER_R0_SHIFT        (0)
 809 #define SCU_SGPIO_START_DRIVE_UPPER_R0_MASK         (0x00000003)
 810 #define SCU_SGPIO_START_DRIVE_UPPER_R1_SHIFT        (4)
 811 #define SCU_SGPIO_START_DRIVE_UPPER_R1_MASK         (0x00000030)
 812 #define SCU_SGPIO_START_DRIVE_UPPER_R2_SHIFT        (8)
 813 #define SCU_SGPIO_START_DRIVE_UPPER_R2_MASK         (0x00000300)
 814 #define SCU_SGPIO_START_DRIVE_UPPER_R3_SHIFT        (12)
 815 #define SCU_SGPIO_START_DRIVE_UPPER_R3_MASK         (0x00003000)
 816 #define SCU_SGPIO_START_DRIVE_UPPER_RESERVED_MASK   (0xFFFF8888)
 817
 818 #define SCU_SGSDURx_GEN_VAL(name, value) \
 819         SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_ ## name, value)
 820
 821 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_SHIFT      (0)
 822 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_MASK       (0x00000003)
 823 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_SHIFT      (4)
 824 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_MASK       (0x00000030)
 825 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_SHIFT      (8)
 826 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_MASK       (0x00000300)
 827 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_SHIFT      (12)
 828 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_MASK       (0x00003000)
 829 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_RESERVED_MASK (0xFFFF8888)
 830
 831 #define SCU_SGSIDLRx_GEN_VAL(name, value) \
 832         SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_ ## name, value)
 833
 834 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_SHIFT      (0)
 835 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_MASK       (0x00000003)
 836 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_SHIFT      (4)
 837 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_MASK       (0x00000030)
 838 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_SHIFT      (8)
 839 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_MASK       (0x00000300)
 840 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_SHIFT      (12)
 841 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_MASK       (0x00003000)
 842 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_RESERVED_MASK (0xFFFF8888)
 843
 844 #define SCU_SGSIDURx_GEN_VAL(name, value) \
 845         SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_ ## name, value)
 846
 847 #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_SHIFT            (0)
 848 #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_MASK             (0x0000000F)
 849 #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_RESERVED_MASK    (0xFFFFFFF0)
 850
 851 #define SCU_SGVSCR_GEN_VAL(value) \
 852         SCU_GEN_VALUE(SCU_SGPIO_VENDOR_SPECIFIC_CODE ## name, value)
 853
 854 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_SHIFT           (0)
 855 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_MASK            (0x00000003)
 856 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_SHIFT    (2)
 857 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_MASK     (0x00000004)
 858 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_SHIFT      (3)
 859 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_MASK       (0x00000008)
 860 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_SHIFT           (4)
 861 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_MASK            (0x00000030)
 862 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_SHIFT    (6)
 863 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_MASK     (0x00000040)
 864 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_SHIFT      (7)
 865 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_MASK       (0x00000080)
 866 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_SHIFT           (8)
 867 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_MASK            (0x00000300)
 868 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_SHIFT    (10)
 869 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_MASK     (0x00000400)
 870 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_SHIFT      (11)
 871 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_MASK       (0x00000800)
 872 #define SCU_SGPIO_OUPUT_DATA_SELECT_RESERVED_MASK               (0xFFFFF000)
 873
 874 #define SCU_SGODSR_GEN_VAL(name, value) \
 875         SCU_GEN_VALUE(SCU_SGPIO_OUPUT_DATA_SELECT_ ## name, value)
 876
 877 #define SCU_SGODSR_GEN_BIT(name) \
 878         SCU_GEN_BIT(SCU_SGPIO_OUPUT_DATA_SELECT_ ## name)
 879
 880 /*
 881  * *****************************************************************************
 882  * * SMU Registers
 883  * ***************************************************************************** */
 884
 885 /*
 886  * ----------------------------------------------------------------------------
 887  * SMU Registers
 888  * These registers are based off of BAR0
 889  *
 890  * To calculate the offset for other functions use
 891  *       BAR0 + FN# * SystemPageSize * 2
 892  *
 893  * The TCA is only accessable from FN#0 (Physical Function) and each
 894  * is programmed by (BAR0 + SCU_SMU_TCA_OFFSET + (FN# * 0x04)) or
 895  *    TCA0 for FN#0 is at BAR0 + 0x0400
 896  *    TCA1 for FN#1 is at BAR0 + 0x0404
 897  *    etc.
 898  * ----------------------------------------------------------------------------
 899  * Accessable to all FN#s */
 900 #define SCU_SMU_PCP_OFFSET          0x0000
 901 #define SCU_SMU_AMR_OFFSET          0x0004
 902 #define SCU_SMU_ISR_OFFSET          0x0010
 903 #define SCU_SMU_IMR_OFFSET          0x0014
 904 #define SCU_SMU_ICC_OFFSET          0x0018
 905 #define SCU_SMU_HTTLBAR_OFFSET      0x0020
 906 #define SCU_SMU_HTTUBAR_OFFSET      0x0024
 907 #define SCU_SMU_TCR_OFFSET          0x0028
 908 #define SCU_SMU_CQLBAR_OFFSET       0x0030
 909 #define SCU_SMU_CQUBAR_OFFSET       0x0034
 910 #define SCU_SMU_CQPR_OFFSET         0x0040
 911 #define SCU_SMU_CQGR_OFFSET         0x0044
 912 #define SCU_SMU_CQC_OFFSET          0x0048
 913 /* Accessable to FN#0 only */
 914 #define SCU_SMU_RNCLBAR_OFFSET      0x0080
 915 #define SCU_SMU_RNCUBAR_OFFSET      0x0084
 916 #define SCU_SMU_DCC_OFFSET          0x0090
 917 #define SCU_SMU_DFC_OFFSET          0x0094
 918 #define SCU_SMU_SMUCSR_OFFSET       0x0098
 919 #define SCU_SMU_SCUSRCR_OFFSET      0x009C
 920 #define SCU_SMU_SMAW_OFFSET         0x00A0
 921 #define SCU_SMU_SMDW_OFFSET         0x00A4
 922 /* Accessable to FN#0 only */
 923 #define SCU_SMU_TCA_OFFSET          0x0400
 924 /* Accessable to all FN#s */
 925 #define SCU_SMU_MT_MLAR0_OFFSET     0x2000
 926 #define SCU_SMU_MT_MUAR0_OFFSET     0x2004
 927 #define SCU_SMU_MT_MDR0_OFFSET      0x2008
 928 #define SCU_SMU_MT_VCR0_OFFSET      0x200C
 929 #define SCU_SMU_MT_MLAR1_OFFSET     0x2010
 930 #define SCU_SMU_MT_MUAR1_OFFSET     0x2014
 931 #define SCU_SMU_MT_MDR1_OFFSET      0x2018
 932 #define SCU_SMU_MT_VCR1_OFFSET      0x201C
 933 #define SCU_SMU_MPBA_OFFSET         0x3000
 934
 935 /**
 936  * struct smu_registers - These are the SMU registers
 937  *
 938  *
 939  */
 940 struct smu_registers {
 941 /* 0x0000 PCP */
 942         u32 post_context_port;
 943 /* 0x0004 AMR */
 944         u32 address_modifier;
 945         u32 reserved_08;
 946         u32 reserved_0C;
 947 /* 0x0010 ISR */
 948         u32 interrupt_status;
 949 /* 0x0014 IMR */
 950         u32 interrupt_mask;
 951 /* 0x0018 ICC */
 952         u32 interrupt_coalesce_control;
 953         u32 reserved_1C;
 954 /* 0x0020 HTTLBAR */
 955         u32 host_task_table_lower;
 956 /* 0x0024 HTTUBAR */
 957         u32 host_task_table_upper;
 958 /* 0x0028 TCR */
 959         u32 task_context_range;
 960         u32 reserved_2C;
 961 /* 0x0030 CQLBAR */
 962         u32 completion_queue_lower;
 963 /* 0x0034 CQUBAR */
 964         u32 completion_queue_upper;
 965         u32 reserved_38;
 966         u32 reserved_3C;
 967 /* 0x0040 CQPR */
 968         u32 completion_queue_put;
 969 /* 0x0044 CQGR */
 970         u32 completion_queue_get;
 971 /* 0x0048 CQC */
 972         u32 completion_queue_control;
 973         u32 reserved_4C;
 974         u32 reserved_5x[4];
 975         u32 reserved_6x[4];
 976         u32 reserved_7x[4];
 977 /*
 978  * Accessable to FN#0 only
 979  * 0x0080 RNCLBAR */
 980         u32 remote_node_context_lower;
 981 /* 0x0084 RNCUBAR */
 982         u32 remote_node_context_upper;
 983         u32 reserved_88;
 984         u32 reserved_8C;
 985 /* 0x0090 DCC */
 986         u32 device_context_capacity;
 987 /* 0x0094 DFC */
 988         u32 device_function_capacity;
 989 /* 0x0098 SMUCSR */
 990         u32 control_status;
 991 /* 0x009C SCUSRCR */
 992         u32 soft_reset_control;
 993 /* 0x00A0 SMAW */
 994         u32 mmr_address_window;
 995 /* 0x00A4 SMDW */
 996         u32 mmr_data_window;
 997         u32 reserved_A8;
 998         u32 reserved_AC;
 999 /* A whole bunch of reserved space */
1000         u32 reserved_Bx[4];
1001         u32 reserved_Cx[4];
1002         u32 reserved_Dx[4];
1003         u32 reserved_Ex[4];
1004         u32 reserved_Fx[4];
1005         u32 reserved_1xx[64];
1006         u32 reserved_2xx[64];
1007         u32 reserved_3xx[64];
1008 /*
1009  * Accessable to FN#0 only
1010  * 0x0400 TCA */
1011         u32 task_context_assignment[256];
1012 /* MSI-X registers not included */
1013 };
1014
1015 /*
1016  * *****************************************************************************
1017  * SDMA Registers
1018  * ***************************************************************************** */
1019 #define SCU_SDMA_BASE               0x6000
1020 #define SCU_SDMA_PUFATLHAR_OFFSET   0x0000
1021 #define SCU_SDMA_PUFATUHAR_OFFSET   0x0004
1022 #define SCU_SDMA_UFLHBAR_OFFSET     0x0008
1023 #define SCU_SDMA_UFUHBAR_OFFSET     0x000C
1024 #define SCU_SDMA_UFQC_OFFSET        0x0010
1025 #define SCU_SDMA_UFQPP_OFFSET       0x0014
1026 #define SCU_SDMA_UFQGP_OFFSET       0x0018
1027 #define SCU_SDMA_PDMACR_OFFSET      0x001C
1028 #define SCU_SDMA_CDMACR_OFFSET      0x0080
1029
1030 /**
1031  * struct scu_sdma_registers - These are the SCU SDMA Registers
1032  *
1033  *
1034  */
1035 struct scu_sdma_registers {
1036 /* 0x0000 PUFATLHAR */
1037         u32 uf_address_table_lower;
1038 /* 0x0004 PUFATUHAR */
1039         u32 uf_address_table_upper;
1040 /* 0x0008 UFLHBAR */
1041         u32 uf_header_base_address_lower;
1042 /* 0x000C UFUHBAR */
1043         u32 uf_header_base_address_upper;
1044 /* 0x0010 UFQC */
1045         u32 unsolicited_frame_queue_control;
1046 /* 0x0014 UFQPP */
1047         u32 unsolicited_frame_put_pointer;
1048 /* 0x0018 UFQGP */
1049         u32 unsolicited_frame_get_pointer;
1050 /* 0x001C PDMACR */
1051         u32 pdma_configuration;
1052 /* Reserved until offset 0x80 */
1053         u32 reserved_0020_007C[0x18];
1054 /* 0x0080 CDMACR */
1055         u32 cdma_configuration;
1056 /* Remainder SDMA register space */
1057         u32 reserved_0084_0400[0xDF];
1058
1059 };
1060
1061 /*
1062  * *****************************************************************************
1063  * * SCU Link Registers
1064  * ***************************************************************************** */
1065 #define SCU_PEG0_OFFSET    0x0000
1066 #define SCU_PEG1_OFFSET    0x8000
1067
1068 #define SCU_TL0_OFFSET     0x0000
1069 #define SCU_TL1_OFFSET     0x0400
1070 #define SCU_TL2_OFFSET     0x0800
1071 #define SCU_TL3_OFFSET     0x0C00
1072
1073 #define SCU_LL_OFFSET      0x0080
1074 #define SCU_LL0_OFFSET     (SCU_TL0_OFFSET + SCU_LL_OFFSET)
1075 #define SCU_LL1_OFFSET     (SCU_TL1_OFFSET + SCU_LL_OFFSET)
1076 #define SCU_LL2_OFFSET     (SCU_TL2_OFFSET + SCU_LL_OFFSET)
1077 #define SCU_LL3_OFFSET     (SCU_TL3_OFFSET + SCU_LL_OFFSET)
1078
1079 /* Transport Layer Offsets (PEG + TL) */
1080 #define SCU_TLCR_OFFSET         0x0000
1081 #define SCU_TLADTR_OFFSET       0x0004
1082 #define SCU_TLTTMR_OFFSET       0x0008
1083 #define SCU_TLEECR0_OFFSET      0x000C
1084 #define SCU_STPTLDARNI_OFFSET   0x0010
1085
1086
1087 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_SHIFT    (0)
1088 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_MASK     (0x00000001)
1089 #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_SHIFT (1)
1090 #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_MASK  (0x00000002)
1091 #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_SHIFT     (3)
1092 #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_MASK      (0x00000008)
1093 #define SCU_TLCR_CMD_NAK_STATUS_CODE_SHIFT         (4)
1094 #define SCU_TLCR_CMD_NAK_STATUS_CODE_MASK          (0x00000010)
1095 #define SCU_TLCR_RESERVED_MASK                     (0xFFFFFFEB)
1096
1097 #define SCU_TLCR_GEN_BIT(name) \
1098         SCU_GEN_BIT(SCU_TLCR_ ## name)
1099
1100 /**
1101  * struct scu_transport_layer_registers - These are the SCU Transport Layer
1102  *    registers
1103  *
1104  *
1105  */
1106 struct scu_transport_layer_registers {
1107         /* 0x0000 TLCR */
1108         u32 control;
1109         /* 0x0004 TLADTR */
1110         u32 arbitration_delay_timer;
1111         /* 0x0008 TLTTMR */
1112         u32 timer_test_mode;
1113         /* 0x000C reserved */
1114         u32 reserved_0C;
1115         /* 0x0010 STPTLDARNI */
1116         u32 stp_rni;
1117         /* 0x0014 TLFEWPORCTRL */
1118         u32 tlfe_wpo_read_control;
1119         /* 0x0018 TLFEWPORDATA */
1120         u32 tlfe_wpo_read_data;
1121         /* 0x001C RXTLSSCSR1 */
1122         u32 rxtl_single_step_control_status_1;
1123         /* 0x0020 RXTLSSCSR2 */
1124         u32 rxtl_single_step_control_status_2;
1125         /* 0x0024 AWTRDDCR */
1126         u32 tlfe_awt_retry_delay_debug_control;
1127         /* Remainder of TL memory space */
1128         u32 reserved_0028_007F[0x16];
1129
1130 };
1131
1132 /* Protocol Engine Group Registers */
1133 #define SCU_SCUVZECRx_OFFSET        0x1080
1134
1135 /* Link Layer Offsets (PEG + TL + LL) */
1136 #define SCU_SAS_SPDTOV_OFFSET       0x0000
1137 #define SCU_SAS_LLSTA_OFFSET        0x0004
1138 #define SCU_SATA_PSELTOV_OFFSET     0x0008
1139 #define SCU_SAS_TIMETOV_OFFSET      0x0010
1140 #define SCU_SAS_LOSTOT_OFFSET       0x0014
1141 #define SCU_SAS_LNKTOV_OFFSET       0x0018
1142 #define SCU_SAS_PHYTOV_OFFSET       0x001C
1143 #define SCU_SAS_AFERCNT_OFFSET      0x0020
1144 #define SCU_SAS_WERCNT_OFFSET       0x0024
1145 #define SCU_SAS_TIID_OFFSET         0x0028
1146 #define SCU_SAS_TIDNH_OFFSET        0x002C
1147 #define SCU_SAS_TIDNL_OFFSET        0x0030
1148 #define SCU_SAS_TISSAH_OFFSET       0x0034
1149 #define SCU_SAS_TISSAL_OFFSET       0x0038
1150 #define SCU_SAS_TIPID_OFFSET        0x003C
1151 #define SCU_SAS_TIRES2_OFFSET       0x0040
1152 #define SCU_SAS_ADRSTA_OFFSET       0x0044
1153 #define SCU_SAS_MAWTTOV_OFFSET      0x0048
1154 #define SCU_SAS_FRPLDFIL_OFFSET     0x0054
1155 #define SCU_SAS_RFCNT_OFFSET        0x0060
1156 #define SCU_SAS_TFCNT_OFFSET        0x0064
1157 #define SCU_SAS_RFDCNT_OFFSET       0x0068
1158 #define SCU_SAS_TFDCNT_OFFSET       0x006C
1159 #define SCU_SAS_LERCNT_OFFSET       0x0070
1160 #define SCU_SAS_RDISERRCNT_OFFSET   0x0074
1161 #define SCU_SAS_CRERCNT_OFFSET      0x0078
1162 #define SCU_STPCTL_OFFSET           0x007C
1163 #define SCU_SAS_PCFG_OFFSET         0x0080
1164 #define SCU_SAS_CLKSM_OFFSET        0x0084
1165 #define SCU_SAS_TXCOMWAKE_OFFSET    0x0088
1166 #define SCU_SAS_TXCOMINIT_OFFSET    0x008C
1167 #define SCU_SAS_TXCOMSAS_OFFSET     0x0090
1168 #define SCU_SAS_COMINIT_OFFSET      0x0094
1169 #define SCU_SAS_COMWAKE_OFFSET      0x0098
1170 #define SCU_SAS_COMSAS_OFFSET       0x009C
1171 #define SCU_SAS_SFERCNT_OFFSET      0x00A0
1172 #define SCU_SAS_CDFERCNT_OFFSET     0x00A4
1173 #define SCU_SAS_DNFERCNT_OFFSET     0x00A8
1174 #define SCU_SAS_PRSTERCNT_OFFSET    0x00AC
1175 #define SCU_SAS_CNTCTL_OFFSET       0x00B0
1176 #define SCU_SAS_SSPTOV_OFFSET       0x00B4
1177 #define SCU_FTCTL_OFFSET            0x00B8
1178 #define SCU_FRCTL_OFFSET            0x00BC
1179 #define SCU_FTWMRK_OFFSET           0x00C0
1180 #define SCU_ENSPINUP_OFFSET         0x00C4
1181 #define SCU_SAS_TRNTOV_OFFSET       0x00C8
1182 #define SCU_SAS_PHYCAP_OFFSET       0x00CC
1183 #define SCU_SAS_PHYCTL_OFFSET       0x00D0
1184 #define SCU_SAS_LLCTL_OFFSET        0x00D8
1185 #define SCU_AFE_XCVRCR_OFFSET       0x00DC
1186 #define SCU_AFE_LUTCR_OFFSET        0x00E0
1187
1188 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT                  (0)
1189 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK                   (0x00000003)
1190 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1                   (0)
1191 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2                   (1)
1192 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3                   (2)
1193 #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_SHIFT            (2)
1194 #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_MASK             (0x000003FC)
1195 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_SHIFT   (16)
1196 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_MASK    (0x00010000)
1197 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_SHIFT (17)
1198 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_MASK  (0x00020000)
1199 #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_SHIFT       (24)
1200 #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_MASK        (0xFF000000)
1201 #define SCU_SAS_LINK_LAYER_CONTROL_RESERVED                             (0x00FCFC00)
1202
1203 #define SCU_SAS_LLCTL_GEN_VAL(name, value) \
1204         SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_CONTROL_ ## name, value)
1205
1206 #define SCU_SAS_LLCTL_GEN_BIT(name) \
1207         SCU_GEN_BIT(SCU_SAS_LINK_LAYER_CONTROL_ ## name)
1208
1209
1210 /* #define SCU_FRXHECR_DCNT_OFFSET      0x00B0 */
1211 #define SCU_PSZGCR_OFFSET           0x00E4
1212 #define SCU_SAS_RECPHYCAP_OFFSET    0x00E8
1213 /* #define SCU_TX_LUTSEL_OFFSET         0x00B8 */
1214
1215 #define SCU_SAS_PTxC_OFFSET         0x00D4 /* Same offset as SAS_TCTSTM */
1216
1217 /**
1218  * struct scu_link_layer_registers - SCU Link Layer Registers
1219  *
1220  *
1221  */
1222 struct scu_link_layer_registers {
1223 /* 0x0000 SAS_SPDTOV */
1224         u32 speed_negotiation_timers;
1225 /* 0x0004 SAS_LLSTA */
1226         u32 link_layer_status;
1227 /* 0x0008 SATA_PSELTOV */
1228         u32 port_selector_timeout;
1229         u32 reserved0C;
1230 /* 0x0010 SAS_TIMETOV */
1231         u32 timeout_unit_value;
1232 /* 0x0014 SAS_RCDTOV */
1233         u32 rcd_timeout;
1234 /* 0x0018 SAS_LNKTOV */
1235         u32 link_timer_timeouts;
1236 /* 0x001C SAS_PHYTOV */
1237         u32 sas_phy_timeouts;
1238 /* 0x0020 SAS_AFERCNT */
1239         u32 received_address_frame_error_counter;
1240 /* 0x0024 SAS_WERCNT */
1241         u32 invalid_dword_counter;
1242 /* 0x0028 SAS_TIID */
1243         u32 transmit_identification;
1244 /* 0x002C SAS_TIDNH */
1245         u32 sas_device_name_high;
1246 /* 0x0030 SAS_TIDNL */
1247         u32 sas_device_name_low;
1248 /* 0x0034 SAS_TISSAH */
1249         u32 source_sas_address_high;
1250 /* 0x0038 SAS_TISSAL */
1251         u32 source_sas_address_low;
1252 /* 0x003C SAS_TIPID */
1253         u32 identify_frame_phy_id;
1254 /* 0x0040 SAS_TIRES2 */
1255         u32 identify_frame_reserved;
1256 /* 0x0044 SAS_ADRSTA */
1257         u32 received_address_frame;
1258 /* 0x0048 SAS_MAWTTOV */
1259         u32 maximum_arbitration_wait_timer_timeout;
1260 /* 0x004C SAS_PTxC */
1261         u32 transmit_primitive;
1262 /* 0x0050 SAS_RORES */
1263         u32 error_counter_event_notification_control;
1264 /* 0x0054 SAS_FRPLDFIL */
1265         u32 frxq_payload_fill_threshold;
1266 /* 0x0058 SAS_LLHANG_TOT */
1267         u32 link_layer_hang_detection_timeout;
1268         u32 reserved_5C;
1269 /* 0x0060 SAS_RFCNT */
1270         u32 received_frame_count;
1271 /* 0x0064 SAS_TFCNT */
1272         u32 transmit_frame_count;
1273 /* 0x0068 SAS_RFDCNT */
1274         u32 received_dword_count;
1275 /* 0x006C SAS_TFDCNT */
1276         u32 transmit_dword_count;
1277 /* 0x0070 SAS_LERCNT */
1278         u32 loss_of_sync_error_count;
1279 /* 0x0074 SAS_RDISERRCNT */
1280         u32 running_disparity_error_count;
1281 /* 0x0078 SAS_CRERCNT */
1282         u32 received_frame_crc_error_count;
1283 /* 0x007C STPCTL */
1284         u32 stp_control;
1285 /* 0x0080 SAS_PCFG */
1286         u32 phy_configuration;
1287 /* 0x0084 SAS_CLKSM */
1288         u32 clock_skew_management;
1289 /* 0x0088 SAS_TXCOMWAKE */
1290         u32 transmit_comwake_signal;
1291 /* 0x008C SAS_TXCOMINIT */
1292         u32 transmit_cominit_signal;
1293 /* 0x0090 SAS_TXCOMSAS */
1294         u32 transmit_comsas_signal;
1295 /* 0x0094 SAS_COMINIT */
1296         u32 cominit_control;
1297 /* 0x0098 SAS_COMWAKE */
1298         u32 comwake_control;
1299 /* 0x009C SAS_COMSAS */
1300         u32 comsas_control;
1301 /* 0x00A0 SAS_SFERCNT */
1302         u32 received_short_frame_count;
1303 /* 0x00A4 SAS_CDFERCNT */
1304         u32 received_frame_without_credit_count;
1305 /* 0x00A8 SAS_DNFERCNT */
1306         u32 received_frame_after_done_count;
1307 /* 0x00AC SAS_PRSTERCNT */
1308         u32 phy_reset_problem_count;
1309 /* 0x00B0 SAS_CNTCTL */
1310         u32 counter_control;
1311 /* 0x00B4 SAS_SSPTOV */
1312         u32 ssp_timer_timeout_values;
1313 /* 0x00B8 FTCTL */
1314         u32 ftx_control;
1315 /* 0x00BC FRCTL */
1316         u32 frx_control;
1317 /* 0x00C0 FTWMRK */
1318         u32 ftx_watermark;
1319 /* 0x00C4 ENSPINUP */
1320         u32 notify_enable_spinup_control;
1321 /* 0x00C8 SAS_TRNTOV */
1322         u32 sas_training_sequence_timer_values;
1323 /* 0x00CC SAS_PHYCAP */
1324         u32 phy_capabilities;
1325 /* 0x00D0 SAS_PHYCTL */
1326         u32 phy_control;
1327         u32 reserved_d4;
1328 /* 0x00D8 LLCTL */
1329         u32 link_layer_control;
1330 /* 0x00DC AFE_XCVRCR */
1331         u32 afe_xcvr_control;
1332 /* 0x00E0 AFE_LUTCR */
1333         u32 afe_lookup_table_control;
1334 /* 0x00E4 PSZGCR */
1335         u32 phy_source_zone_group_control;
1336 /* 0x00E8 SAS_RECPHYCAP */
1337         u32 receive_phycap;
1338         u32 reserved_ec;
1339 /* 0x00F0 SNAFERXRSTCTL */
1340         u32 speed_negotiation_afe_rx_reset_control;
1341 /* 0x00F4 SAS_SSIPMCTL */
1342         u32 power_management_control;
1343 /* 0x00F8 SAS_PSPREQ_PRIM */
1344         u32 sas_pm_partial_request_primitive;
1345 /* 0x00FC SAS_PSSREQ_PRIM */
1346         u32 sas_pm_slumber_request_primitive;
1347 /* 0x0100 SAS_PPSACK_PRIM */
1348         u32 sas_pm_ack_primitive_register;
1349 /* 0x0104 SAS_PSNAK_PRIM */
1350         u32 sas_pm_nak_primitive_register;
1351 /* 0x0108 SAS_SSIPMTOV */
1352         u32 sas_primitive_timeout;
1353         u32 reserved_10c;
1354 /* 0x0110 - 0x011C PLAPRDCTRLxREG */
1355         u32 pla_product_control[4];
1356 /* 0x0120 PLAPRDSUMREG */
1357         u32 pla_product_sum;
1358 /* 0x0124 PLACONTROLREG */
1359         u32 pla_control;
1360 /* Remainder of memory space 896 bytes */
1361         u32 reserved_0128_037f[0x96];
1362
1363 };
1364
1365 /*
1366  * 0x00D4 // Same offset as SAS_TCTSTM SAS_PTxC
1367  *   u32   primitive_transmit_control; */
1368
1369 /*
1370  * ----------------------------------------------------------------------------
1371  * SGPIO
1372  * ---------------------------------------------------------------------------- */
1373 #define SCU_SGPIO_OFFSET         0x1400
1374
1375 /* #define SCU_SGPIO_OFFSET         0x6000   // later moves to 0x1400 see HSD 652625 */
1376 #define SCU_SGPIO_SGICR_OFFSET   0x0000
1377 #define SCU_SGPIO_SGPBR_OFFSET   0x0004
1378 #define SCU_SGPIO_SGSDLR_OFFSET  0x0008
1379 #define SCU_SGPIO_SGSDUR_OFFSET  0x000C
1380 #define SCU_SGPIO_SGSIDLR_OFFSET 0x0010
1381 #define SCU_SGPIO_SGSIDUR_OFFSET 0x0014
1382 #define SCU_SGPIO_SGVSCR_OFFSET  0x0018
1383 /* Address from 0x0820 to 0x083C */
1384 #define SCU_SGPIO_SGODSR_OFFSET  0x0020
1385
1386 /**
1387  * struct scu_sgpio_registers - SCU SGPIO Registers
1388  *
1389  *
1390  */
1391 struct scu_sgpio_registers {
1392 /* 0x0000 SGPIO_SGICR */
1393         u32 interface_control;
1394 /* 0x0004 SGPIO_SGPBR */
1395         u32 blink_rate;
1396 /* 0x0008 SGPIO_SGSDLR */
1397         u32 start_drive_lower;
1398 /* 0x000C SGPIO_SGSDUR */
1399         u32 start_drive_upper;
1400 /* 0x0010 SGPIO_SGSIDLR */
1401         u32 serial_input_lower;
1402 /* 0x0014 SGPIO_SGSIDUR */
1403         u32 serial_input_upper;
1404 /* 0x0018 SGPIO_SGVSCR */
1405         u32 vendor_specific_code;
1406 /* 0x0020 SGPIO_SGODSR */
1407         u32 ouput_data_select[8];
1408 /* Remainder of memory space 256 bytes */
1409         u32 reserved_1444_14ff[0x31];
1410
1411 };
1412
1413 /*
1414  * *****************************************************************************
1415  * * Defines for VIIT entry offsets
1416  * * Access additional entries by SCU_VIIT_BASE + index * 0x10
1417  * ***************************************************************************** */
1418 #define     SCU_VIIT_BASE     0x1c00
1419
1420 struct SCU_VIIT_REGISTERS {
1421         u32 registers[256];
1422 };
1423
1424 /*
1425  * *****************************************************************************
1426  * * SCU PORT TASK SCHEDULER REGISTERS
1427  * ***************************************************************************** */
1428
1429 #define SCU_PTSG_BASE               0x1000
1430
1431 #define SCU_PTSG_PTSGCR_OFFSET      0x0000
1432 #define SCU_PTSG_RTCR_OFFSET        0x0004
1433 #define SCU_PTSG_RTCCR_OFFSET       0x0008
1434 #define SCU_PTSG_PTS0CR_OFFSET      0x0010
1435 #define SCU_PTSG_PTS0SR_OFFSET      0x0014
1436 #define SCU_PTSG_PTS1CR_OFFSET      0x0018
1437 #define SCU_PTSG_PTS1SR_OFFSET      0x001C
1438 #define SCU_PTSG_PTS2CR_OFFSET      0x0020
1439 #define SCU_PTSG_PTS2SR_OFFSET      0x0024
1440 #define SCU_PTSG_PTS3CR_OFFSET      0x0028
1441 #define SCU_PTSG_PTS3SR_OFFSET      0x002C
1442 #define SCU_PTSG_PCSPE0CR_OFFSET    0x0030
1443 #define SCU_PTSG_PCSPE1CR_OFFSET    0x0034
1444 #define SCU_PTSG_PCSPE2CR_OFFSET    0x0038
1445 #define SCU_PTSG_PCSPE3CR_OFFSET    0x003C
1446 #define SCU_PTSG_ETMTSCCR_OFFSET    0x0040
1447 #define SCU_PTSG_ETMRNSCCR_OFFSET   0x0044
1448
1449 /**
1450  * struct scu_port_task_scheduler_registers - These are the control/stats pairs
1451  *    for each Port Task Scheduler.
1452  *
1453  *
1454  */
1455 struct scu_port_task_scheduler_registers {
1456         u32 control;
1457         u32 status;
1458 };
1459
1460 typedef u32 SCU_PORT_PE_CONFIGURATION_REGISTER_T;
1461
1462 /**
1463  * struct scu_port_task_scheduler_group_registers - These are the PORT Task
1464  *    Scheduler registers
1465  *
1466  *
1467  */
1468 struct scu_port_task_scheduler_group_registers {
1469 /* 0x0000 PTSGCR */
1470         u32 control;
1471 /* 0x0004 RTCR */
1472         u32 real_time_clock;
1473 /* 0x0008 RTCCR */
1474         u32 real_time_clock_control;
1475 /* 0x000C */
1476         u32 reserved_0C;
1477 /*
1478  * 0x0010 PTS0CR
1479  * 0x0014 PTS0SR
1480  * 0x0018 PTS1CR
1481  * 0x001C PTS1SR
1482  * 0x0020 PTS2CR
1483  * 0x0024 PTS2SR
1484  * 0x0028 PTS3CR
1485  * 0x002C PTS3SR */
1486         struct scu_port_task_scheduler_registers port[4];
1487 /*
1488  * 0x0030 PCSPE0CR
1489  * 0x0034 PCSPE1CR
1490  * 0x0038 PCSPE2CR
1491  * 0x003C PCSPE3CR */
1492         SCU_PORT_PE_CONFIGURATION_REGISTER_T protocol_engine[4];
1493 /* 0x0040 ETMTSCCR */
1494         u32 tc_scanning_interval_control;
1495 /* 0x0044 ETMRNSCCR */
1496         u32 rnc_scanning_interval_control;
1497 /* Remainder of memory space 128 bytes */
1498         u32 reserved_1048_107f[0x0E];
1499
1500 };
1501
1502 #define SCU_PTSG_SCUVZECR_OFFSET        0x003C
1503
1504 /*
1505  * *****************************************************************************
1506  * * AFE REGISTERS
1507  * ***************************************************************************** */
1508 #define SCU_AFE_MMR_BASE                  0xE000
1509
1510 /*
1511  * AFE 0 is at offset 0x0800
1512  * AFE 1 is at offset 0x0900
1513  * AFE 2 is at offset 0x0a00
1514  * AFE 3 is at offset 0x0b00 */
1515 struct scu_afe_transceiver {
1516         /* 0x0000 AFE_XCVR_CTRL0 */
1517         u32 afe_xcvr_control0;
1518         /* 0x0004 AFE_XCVR_CTRL1 */
1519         u32 afe_xcvr_control1;
1520         /* 0x0008 */
1521         u32 reserved_0008;
1522         /* 0x000c afe_dfx_rx_control0 */
1523         u32 afe_dfx_rx_control0;
1524         /* 0x0010 AFE_DFX_RX_CTRL1 */
1525         u32 afe_dfx_rx_control1;
1526         /* 0x0014 */
1527         u32 reserved_0014;
1528         /* 0x0018 AFE_DFX_RX_STS0 */
1529         u32 afe_dfx_rx_status0;
1530         /* 0x001c AFE_DFX_RX_STS1 */
1531         u32 afe_dfx_rx_status1;
1532         /* 0x0020 */
1533         u32 reserved_0020;
1534         /* 0x0024 AFE_TX_CTRL */
1535         u32 afe_tx_control;
1536         /* 0x0028 AFE_TX_AMP_CTRL0 */
1537         u32 afe_tx_amp_control0;
1538         /* 0x002c AFE_TX_AMP_CTRL1 */
1539         u32 afe_tx_amp_control1;
1540         /* 0x0030 AFE_TX_AMP_CTRL2 */
1541         u32 afe_tx_amp_control2;
1542         /* 0x0034 AFE_TX_AMP_CTRL3 */
1543         u32 afe_tx_amp_control3;
1544         /* 0x0038 afe_tx_ssc_control */
1545         u32 afe_tx_ssc_control;
1546         /* 0x003c */
1547         u32 reserved_003c;
1548         /* 0x0040 AFE_RX_SSC_CTRL0 */
1549         u32 afe_rx_ssc_control0;
1550         /* 0x0044 AFE_RX_SSC_CTRL1 */
1551         u32 afe_rx_ssc_control1;
1552         /* 0x0048 AFE_RX_SSC_CTRL2 */
1553         u32 afe_rx_ssc_control2;
1554         /* 0x004c AFE_RX_EQ_STS0 */
1555         u32 afe_rx_eq_status0;
1556         /* 0x0050 AFE_RX_EQ_STS1 */
1557         u32 afe_rx_eq_status1;
1558         /* 0x0054 AFE_RX_CDR_STS */
1559         u32 afe_rx_cdr_status;
1560         /* 0x0058 */
1561         u32 reserved_0058;
1562         /* 0x005c AFE_CHAN_CTRL */
1563         u32 afe_channel_control;
1564         /* 0x0060-0x006c */
1565         u32 reserved_0060_006c[0x04];
1566         /* 0x0070 AFE_XCVR_EC_STS0 */
1567         u32 afe_xcvr_error_capture_status0;
1568         /* 0x0074 AFE_XCVR_EC_STS1 */
1569         u32 afe_xcvr_error_capture_status1;
1570         /* 0x0078 AFE_XCVR_EC_STS2 */
1571         u32 afe_xcvr_error_capture_status2;
1572         /* 0x007c afe_xcvr_ec_status3 */
1573         u32 afe_xcvr_error_capture_status3;
1574         /* 0x0080 AFE_XCVR_EC_STS4 */
1575         u32 afe_xcvr_error_capture_status4;
1576         /* 0x0084 AFE_XCVR_EC_STS5 */
1577         u32 afe_xcvr_error_capture_status5;
1578         /* 0x0088-0x00fc */
1579         u32 reserved_008c_00fc[0x1e];
1580 };
1581
1582 /**
1583  * struct scu_afe_registers - AFE Regsiters
1584  *
1585  *
1586  */
1587 /* Uaoa AFE registers */
1588 struct scu_afe_registers {
1589         /* 0Xe000 AFE_BIAS_CTRL */
1590         u32 afe_bias_control;
1591         u32 reserved_0004;
1592         /* 0x0008 AFE_PLL_CTRL0 */
1593         u32 afe_pll_control0;
1594         /* 0x000c AFE_PLL_CTRL1 */
1595         u32 afe_pll_control1;
1596         /* 0x0010 AFE_PLL_CTRL2 */
1597         u32 afe_pll_control2;
1598         /* 0x0014 AFE_CB_STS */
1599         u32 afe_common_block_status;
1600         /* 0x0018-0x007c */
1601         u32 reserved_18_7c[0x1a];
1602         /* 0x0080 AFE_PMSN_MCTRL0 */
1603         u32 afe_pmsn_master_control0;
1604         /* 0x0084 AFE_PMSN_MCTRL1 */
1605         u32 afe_pmsn_master_control1;
1606         /* 0x0088 AFE_PMSN_MCTRL2 */
1607         u32 afe_pmsn_master_control2;
1608         /* 0x008C-0x00fc */
1609         u32 reserved_008c_00fc[0x1D];
1610         /* 0x0100 AFE_DFX_MST_CTRL0 */
1611         u32 afe_dfx_master_control0;
1612         /* 0x0104 AFE_DFX_MST_CTRL1 */
1613         u32 afe_dfx_master_control1;
1614         /* 0x0108 AFE_DFX_DCL_CTRL */
1615         u32 afe_dfx_dcl_control;
1616         /* 0x010c AFE_DFX_DMON_CTRL */
1617         u32 afe_dfx_digital_monitor_control;
1618         /* 0x0110 AFE_DFX_AMONP_CTRL */
1619         u32 afe_dfx_analog_p_monitor_control;
1620         /* 0x0114 AFE_DFX_AMONN_CTRL */
1621         u32 afe_dfx_analog_n_monitor_control;
1622         /* 0x0118 AFE_DFX_NTL_STS */
1623         u32 afe_dfx_ntl_status;
1624         /* 0x011c AFE_DFX_FIFO_STS0 */
1625         u32 afe_dfx_fifo_status0;
1626         /* 0x0120 AFE_DFX_FIFO_STS1 */
1627         u32 afe_dfx_fifo_status1;
1628         /* 0x0124 AFE_DFX_MPAT_CTRL */
1629         u32 afe_dfx_master_pattern_control;
1630         /* 0x0128 AFE_DFX_P0_CTRL */
1631         u32 afe_dfx_p0_control;
1632         /* 0x012c-0x01a8 AFE_DFX_P0_DRx */
1633         u32 afe_dfx_p0_data[32];
1634         /* 0x01ac */
1635         u32 reserved_01ac;
1636         /* 0x01b0-0x020c AFE_DFX_P0_IRx */
1637         u32 afe_dfx_p0_instruction[24];
1638         /* 0x0210 */
1639         u32 reserved_0210;
1640         /* 0x0214 AFE_DFX_P1_CTRL */
1641         u32 afe_dfx_p1_control;
1642         /* 0x0218-0x245 AFE_DFX_P1_DRx */
1643         u32 afe_dfx_p1_data[16];
1644         /* 0x0258-0x029c */
1645         u32 reserved_0258_029c[0x12];
1646         /* 0x02a0-0x02bc AFE_DFX_P1_IRx */
1647         u32 afe_dfx_p1_instruction[8];
1648         /* 0x02c0-0x2fc */
1649         u32 reserved_02c0_02fc[0x10];
1650         /* 0x0300 AFE_DFX_TX_PMSN_CTRL */
1651         u32 afe_dfx_tx_pmsn_control;
1652         /* 0x0304 AFE_DFX_RX_PMSN_CTRL */
1653         u32 afe_dfx_rx_pmsn_control;
1654         u32 reserved_0308;
1655         /* 0x030c AFE_DFX_NOA_CTRL0 */
1656         u32 afe_dfx_noa_control0;
1657         /* 0x0310 AFE_DFX_NOA_CTRL1 */
1658         u32 afe_dfx_noa_control1;
1659         /* 0x0314 AFE_DFX_NOA_CTRL2 */
1660         u32 afe_dfx_noa_control2;
1661         /* 0x0318 AFE_DFX_NOA_CTRL3 */
1662         u32 afe_dfx_noa_control3;
1663         /* 0x031c AFE_DFX_NOA_CTRL4 */
1664         u32 afe_dfx_noa_control4;
1665         /* 0x0320 AFE_DFX_NOA_CTRL5 */
1666         u32 afe_dfx_noa_control5;
1667         /* 0x0324 AFE_DFX_NOA_CTRL6 */
1668         u32 afe_dfx_noa_control6;
1669         /* 0x0328 AFE_DFX_NOA_CTRL7 */
1670         u32 afe_dfx_noa_control7;
1671         /* 0x032c-0x07fc */
1672         u32 reserved_032c_07fc[0x135];
1673
1674         /* 0x0800-0x0bfc */
1675         struct scu_afe_transceiver scu_afe_xcvr[4];
1676
1677         /* 0x0c00-0x0ffc */
1678         u32 reserved_0c00_0ffc[0x0100];
1679 };
1680
1681 struct SCU_PROTOCOL_ENGINE_GROUP_REGISTERS {
1682         u32 table[0xE0];
1683 };
1684
1685
1686 struct SCU_VIIT_IIT {
1687         u32 table[256];
1688 };
1689
1690 /**
1691  * Placeholder for the ZONE Partition Table information ZONING will not be
1692  *    included in the 1.1 release.
1693  *
1694  *
1695  */
1696 struct SCU_ZONE_PARTITION_TABLE {
1697         u32 table[2048];
1698 };
1699
1700 /**
1701  * Placeholder for the CRAM register since I am not sure if we need to
1702  *    read/write to these registers as yet.
1703  *
1704  *
1705  */
1706 struct SCU_COMPLETION_RAM {
1707         u32 ram[128];
1708 };
1709
1710 /**
1711  * Placeholder for the FBRAM registers since I am not sure if we need to
1712  *    read/write to these registers as yet.
1713  *
1714  *
1715  */
1716 struct SCU_FRAME_BUFFER_RAM {
1717         u32 ram[128];
1718 };
1719
1720 #define SCU_SCRATCH_RAM_SIZE_IN_DWORDS  256
1721
1722 /**
1723  * Placeholder for the scratch RAM registers.
1724  *
1725  *
1726  */
1727 struct SCU_SCRATCH_RAM {
1728         u32 ram[SCU_SCRATCH_RAM_SIZE_IN_DWORDS];
1729 };
1730
1731 /**
1732  * Placeholder since I am not yet sure what these registers are here for.
1733  *
1734  *
1735  */
1736 struct NOA_PROTOCOL_ENGINE_PARTITION {
1737         u32 reserved[64];
1738 };
1739
1740 /**
1741  * Placeholder since I am not yet sure what these registers are here for.
1742  *
1743  *
1744  */
1745 struct NOA_HUB_PARTITION {
1746         u32 reserved[64];
1747 };
1748
1749 /**
1750  * Placeholder since I am not yet sure what these registers are here for.
1751  *
1752  *
1753  */
1754 struct NOA_HOST_INTERFACE_PARTITION {
1755         u32 reserved[64];
1756 };
1757
1758 /**
1759  * struct TRANSPORT_LINK_LAYER_PAIR - The SCU Hardware pairs up the TL
1760  *    registers with the LL registers so we must place them adjcent to make the
1761  *    array of registers in the PEG.
1762  *
1763  *
1764  */
1765 struct TRANSPORT_LINK_LAYER_PAIR {
1766         struct scu_transport_layer_registers tl;
1767         struct scu_link_layer_registers ll;
1768 };
1769
1770 /**
1771  * struct SCU_PEG_REGISTERS - SCU Protocol Engine Memory mapped register space.
1772  *     These registers are unique to each protocol engine group.  There can be
1773  *    at most two PEG for a single SCU part.
1774  *
1775  *
1776  */
1777 struct SCU_PEG_REGISTERS {
1778         struct TRANSPORT_LINK_LAYER_PAIR pe[4];
1779         struct scu_port_task_scheduler_group_registers ptsg;
1780         struct SCU_PROTOCOL_ENGINE_GROUP_REGISTERS peg;
1781         struct scu_sgpio_registers sgpio;
1782         u32 reserved_01500_1BFF[0x1C0];
1783         struct scu_viit_entry viit[64];
1784         struct SCU_ZONE_PARTITION_TABLE zpt0;
1785         struct SCU_ZONE_PARTITION_TABLE zpt1;
1786 };
1787
1788 /**
1789  * struct scu_registers - SCU regsiters including both PEG registers if we turn
1790  *    on that compile option. All of these registers are in the memory mapped
1791  *    space returned from BAR1.
1792  *
1793  *
1794  */
1795 struct scu_registers {
1796         /* 0x0000 - PEG 0 */
1797         struct SCU_PEG_REGISTERS peg0;
1798
1799         /* 0x6000 - SDMA and Miscellaneous */
1800         struct scu_sdma_registers sdma;
1801         struct SCU_COMPLETION_RAM cram;
1802         struct SCU_FRAME_BUFFER_RAM fbram;
1803         u32 reserved_6800_69FF[0x80];
1804         struct NOA_PROTOCOL_ENGINE_PARTITION noa_pe;
1805         struct NOA_HUB_PARTITION noa_hub;
1806         struct NOA_HOST_INTERFACE_PARTITION noa_if;
1807         u32 reserved_6d00_7fff[0x4c0];
1808
1809         /* 0x8000 - PEG 1 */
1810         struct SCU_PEG_REGISTERS peg1;
1811
1812         /* 0xE000 - AFE Registers */
1813         struct scu_afe_registers afe;
1814
1815         /* 0xF000 - reserved */
1816         u32 reserved_f000_211fff[0x80c00];
1817
1818         /* 0x212000 - scratch RAM */
1819         struct SCU_SCRATCH_RAM scratch_ram;
1820
1821 };
1822
1823
1824 #endif   /* _SCU_REGISTERS_HEADER_ */