drivers/scsi/isci/core/scic_sds_controller_registers.h

   1 /*
   2  * This file is provided under a dual BSD/GPLv2 license.  When using or
   3  * redistributing this file, you may do so under either license.
   4  *
   5  * GPL LICENSE SUMMARY
   6  *
   7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * BSD LICENSE
  25  *
  26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  27  * All rights reserved.
  28  *
  29  * Redistribution and use in source and binary forms, with or without
  30  * modification, are permitted provided that the following conditions
  31  * are met:
  32  *
  33  *   * Redistributions of source code must retain the above copyright
  34  *     notice, this list of conditions and the following disclaimer.
  35  *   * Redistributions in binary form must reproduce the above copyright
  36  *     notice, this list of conditions and the following disclaimer in
  37  *     the documentation and/or other materials provided with the
  38  *     distribution.
  39  *   * Neither the name of Intel Corporation nor the names of its
  40  *     contributors may be used to endorse or promote products derived
  41  *     from this software without specific prior written permission.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  */
  55
  56 #ifndef _SCIC_SDS_CONTROLLER_REGISTERS_H_
  57 #define _SCIC_SDS_CONTROLLER_REGISTERS_H_
  58
  59 /**
  60  * This file contains macros used to perform the register reads/writes to the
  61  *    SCU hardware.
  62  *
  63  *
  64  */
  65
  66 #include "scu_registers.h"
  67 #include "scic_sds_controller.h"
  68
  69 /**
  70  * scic_sds_controller_smu_register_read() -
  71  *
  72  * SMU_REGISTER_ACCESS_MACROS
  73  */
  74 #define scic_sds_controller_smu_register_read(controller, reg) \
  75         smu_register_read(\
  76                 (controller), \
  77                 (controller)->smu_registers->reg \
  78                 )
  79
  80 #define scic_sds_controller_smu_register_write(controller, reg, value) \
  81         smu_register_write(\
  82                 (controller), \
  83                 (controller)->smu_registers->reg, \
  84                 (value) \
  85                 )
  86
  87 /**
  88  * scu_afe_register_write() -
  89  *
  90  * AFE_REGISTER_ACCESS_MACROS
  91  */
  92 #define scu_afe_register_write(controller, reg, value) \
  93         scu_register_write(\
  94                 (controller), \
  95                 (controller)->scu_registers->afe.reg, \
  96                 (value) \
  97                 )
  98
  99 #define scu_afe_txreg_write(controller, phy, reg, value) \
 100         scu_register_write(\
 101                 (controller), \
 102                 (controller)->scu_registers->afe.scu_afe_xcvr[phy].reg,\
 103                 (value) \
 104                 )
 105
 106 #define scu_afe_register_read(controller, reg) \
 107         scu_register_read(\
 108                 (controller), \
 109                 (controller)->scu_registers->afe.reg \
 110                 )
 111
 112 /**
 113  * scu_controller_viit_register_write() -
 114  *
 115  * VIIT_REGISTER_ACCESS_MACROS
 116  */
 117 #define scu_controller_viit_register_write(controller, index, reg, value) \
 118         scu_register_write(\
 119                 (controller), \
 120                 (controller)->scu_registers->peg0.viit[index].reg, \
 121                 value \
 122                 )
 123
 124 /*
 125  * *****************************************************************************
 126  * * SMU REGISTERS
 127  * ***************************************************************************** */
 128
 129 /**
 130  * SMU_PCP_WRITE() -
 131  *
 132  * struct smu_registers
 133  */
 134 #define SMU_PCP_WRITE(controller, value) \
 135         scic_sds_controller_smu_register_write(\
 136                 controller, post_context_port, value \
 137                 )
 138
 139 #define SMU_TCR_READ(controller, value) \
 140         scic_sds_controller_smu_register_read(\
 141                 controller, task_context_range \
 142                 )
 143
 144 #define SMU_TCR_WRITE(controller, value) \
 145         scic_sds_controller_smu_register_write(\
 146                 controller, task_context_range, value \
 147                 )
 148
 149 #define SMU_HTTBAR_WRITE(controller, address) \
 150         { \
 151                 scic_sds_controller_smu_register_write(\
 152                         controller, \
 153                         host_task_table_lower, \
 154                         lower_32_bits(address) \
 155                         ); \
 156                 scic_sds_controller_smu_register_write(\
 157                         controller, \
 158                         host_task_table_upper, \
 159                         upper_32_bits(address) \
 160                         ); \
 161         }
 162
 163 #define SMU_CQBAR_WRITE(controller, address) \
 164         { \
 165                 scic_sds_controller_smu_register_write(\
 166                         controller, \
 167                         completion_queue_lower, \
 168                         lower_32_bits(address) \
 169                         ); \
 170                 scic_sds_controller_smu_register_write(\
 171                         controller, \
 172                         completion_queue_upper, \
 173                         upper_32_bits(address) \
 174                         ); \
 175         }
 176
 177 #define SMU_CQGR_WRITE(controller, value) \
 178         scic_sds_controller_smu_register_write(\
 179                 controller, completion_queue_get, value \
 180                 )
 181
 182 #define SMU_CQGR_READ(controller, value) \
 183         scic_sds_controller_smu_register_read(\
 184                 controller, completion_queue_get \
 185                 )
 186
 187 #define SMU_CQPR_WRITE(controller, value) \
 188         scic_sds_controller_smu_register_write(\
 189                 controller, completion_queue_put, value \
 190                 )
 191
 192 #define SMU_RNCBAR_WRITE(controller, address) \
 193         { \
 194                 scic_sds_controller_smu_register_write(\
 195                         controller, \
 196                         remote_node_context_lower, \
 197                         lower_32_bits(address) \
 198                         ); \
 199                 scic_sds_controller_smu_register_write(\
 200                         controller, \
 201                         remote_node_context_upper, \
 202                         upper_32_bits(address) \
 203                         ); \
 204         }
 205
 206 #define SMU_AMR_READ(controller) \
 207         scic_sds_controller_smu_register_read(\
 208                 controller, address_modifier \
 209                 )
 210
 211 #define SMU_IMR_READ(controller) \
 212         scic_sds_controller_smu_register_read(\
 213                 controller, interrupt_mask \
 214                 )
 215
 216 #define SMU_IMR_WRITE(controller, mask) \
 217         scic_sds_controller_smu_register_write(\
 218                 controller, interrupt_mask, mask \
 219                 )
 220
 221 #define SMU_ISR_READ(controller) \
 222         scic_sds_controller_smu_register_read(\
 223                 controller, interrupt_status \
 224                 )
 225
 226 #define SMU_ISR_WRITE(controller, status) \
 227         scic_sds_controller_smu_register_write(\
 228                 controller, interrupt_status, status \
 229                 )
 230
 231 #define SMU_ICC_READ(controller) \
 232         scic_sds_controller_smu_register_read(\
 233                 controller, interrupt_coalesce_control \
 234                 )
 235
 236 #define SMU_ICC_WRITE(controller, value) \
 237         scic_sds_controller_smu_register_write(\
 238                 controller, interrupt_coalesce_control, value \
 239                 )
 240
 241 #define SMU_CQC_WRITE(controller, value) \
 242         scic_sds_controller_smu_register_write(\
 243                 controller, completion_queue_control, value \
 244                 )
 245
 246 #define SMU_SMUSRCR_WRITE(controller, value) \
 247         scic_sds_controller_smu_register_write(\
 248                 controller, soft_reset_control, value \
 249                 )
 250
 251 #define SMU_TCA_WRITE(controller, index, value) \
 252         scic_sds_controller_smu_register_write(\
 253                 controller, task_context_assignment[index], value \
 254                 )
 255
 256 #define SMU_TCA_READ(controller, index) \
 257         scic_sds_controller_smu_register_read(\
 258                 controller, task_context_assignment[index] \
 259                 )
 260
 261 #define SMU_DCC_READ(controller) \
 262         scic_sds_controller_smu_register_read(\
 263                 controller, device_context_capacity \
 264                 )
 265
 266 #define SMU_DFC_READ(controller) \
 267         scic_sds_controller_smu_register_read(\
 268                 controller, device_function_capacity \
 269                 )
 270
 271 #define SMU_SMUCSR_READ(controller) \
 272         scic_sds_controller_smu_register_read(\
 273                 controller, control_status \
 274                 )
 275
 276 #define SMU_CQPR_READ(controller) \
 277         scic_sds_controller_smu_register_read(\
 278                 controller, completion_queue_put \
 279                 )
 280
 281
 282 /**
 283  * scic_sds_controller_scu_register_read() -
 284  *
 285  * SCU_REGISTER_ACCESS_MACROS
 286  */
 287 #define scic_sds_controller_scu_register_read(controller, reg) \
 288         scu_register_read(\
 289                 (controller), \
 290                 (controller)->scu_registers->reg \
 291                 )
 292
 293 #define scic_sds_controller_scu_register_write(controller, reg, value) \
 294         scu_register_write(\
 295                 (controller), \
 296                 (controller)->scu_registers->reg, \
 297                 (value) \
 298                 )
 299
 300
 301 /*
 302  * ****************************************************************************
 303  * *  SCU SDMA REGISTERS
 304  * **************************************************************************** */
 305
 306 /**
 307  * scu_sdma_register_read() -
 308  *
 309  * SCU_SDMA_REGISTER_ACCESS_MACROS
 310  */
 311 #define scu_sdma_register_read(controller, reg) \
 312         scu_register_read(\
 313                 (controller), \
 314                 (controller)->scu_registers->sdma.reg \
 315                 )
 316
 317 #define scu_sdma_register_write(controller, reg, value) \
 318         scu_register_write(\
 319                 (controller), \
 320                 (controller)->scu_registers->sdma.reg, \
 321                 (value) \
 322                 )
 323
 324 /**
 325  * SCU_PUFATHAR_WRITE() -
 326  *
 327  * struct scu_sdma_registers
 328  */
 329 #define SCU_PUFATHAR_WRITE(controller, address) \
 330         { \
 331                 scu_sdma_register_write(\
 332                         controller, \
 333                         uf_address_table_lower, \
 334                         lower_32_bits(address) \
 335                         ); \
 336                 scu_sdma_register_write(\
 337                         controller, \
 338                         uf_address_table_upper, \
 339                         upper_32_bits(address) \
 340                         ); \
 341         }
 342
 343 #define SCU_UFHBAR_WRITE(controller, address) \
 344         { \
 345                 scu_sdma_register_write(\
 346                         controller, \
 347                         uf_header_base_address_lower, \
 348                         lower_32_bits(address) \
 349                         ); \
 350                 scu_sdma_register_write(\
 351                         controller, \
 352                         uf_header_base_address_upper, \
 353                         upper_32_bits(address) \
 354                         ); \
 355         }
 356
 357 #define SCU_UFQC_READ(controller) \
 358         scu_sdma_register_read(\
 359                 controller,  \
 360                 unsolicited_frame_queue_control \
 361                 )
 362
 363 #define SCU_UFQC_WRITE(controller, value) \
 364         scu_sdma_register_write(\
 365                 controller, \
 366                 unsolicited_frame_queue_control, \
 367                 value \
 368                 )
 369
 370 #define SCU_UFQPP_READ(controller) \
 371         scu_sdma_register_read(\
 372                 controller, \
 373                 unsolicited_frame_put_pointer \
 374                 )
 375
 376 #define SCU_UFQPP_WRITE(controller, value) \
 377         scu_sdma_register_write(\
 378                 controller, \
 379                 unsolicited_frame_put_pointer, \
 380                 value \
 381                 )
 382
 383 #define SCU_UFQGP_WRITE(controller, value) \
 384         scu_sdma_register_write(\
 385                 controller, \
 386                 unsolicited_frame_get_pointer, \
 387                 value \
 388                 )
 389
 390 #define SCU_PDMACR_READ(controller) \
 391         scu_sdma_register_read(\
 392                 controller, \
 393                 pdma_configuration \
 394                 )
 395
 396 #define SCU_PDMACR_WRITE(controller, value) \
 397         scu_sdma_register_write(\
 398                 controller, \
 399                 pdma_configuration, \
 400                 value \
 401                 )
 402
 403 #define SCU_CDMACR_READ(controller) \
 404         scu_sdma_register_read(\
 405                 controller, \
 406                 cdma_configuration \
 407                 )
 408
 409 #define SCU_CDMACR_WRITE(controller, value) \
 410         scu_sdma_register_write(\
 411                 controller, \
 412                 cdma_configuration, \
 413                 value \
 414                 )
 415
 416 /*
 417  * *****************************************************************************
 418  * * SCU Port Task Scheduler Group Registers
 419  * ***************************************************************************** */
 420
 421 /**
 422  * scu_ptsg_register_read() -
 423  *
 424  * SCU_PTSG_REGISTER_ACCESS_MACROS
 425  */
 426 #define scu_ptsg_register_read(controller, reg) \
 427         scu_register_read(\
 428                 (controller), \
 429                 (controller)->scu_registers->peg0.ptsg.reg \
 430                 )
 431
 432 #define scu_ptsg_register_write(controller, reg, value) \
 433         scu_register_write(\
 434                 (controller), \
 435                 (controller)->scu_registers->peg0.ptsg.reg, \
 436                 (value) \
 437                 )
 438
 439 /**
 440  * SCU_PTSGCR_READ() -
 441  *
 442  * SCU_PTSG_REGISTERS
 443  */
 444 #define SCU_PTSGCR_READ(controller) \
 445         scu_ptsg_register_read(\
 446                 (controller), \
 447                 control \
 448                 )
 449
 450 #define SCU_PTSGCR_WRITE(controller, value) \
 451         scu_ptsg_register_write(\
 452                 (controller), \
 453                 control, \
 454                 value \
 455                 )
 456
 457 #define SCU_PTSGRTC_READ(controller) \
 458         scu_ptsg_register_read(\
 459                 contoller, \
 460                 real_time_clock \
 461                 )
 462
 463 #endif /* _SCIC_SDS_CONTROLLER_REGISTERS_H_ */