2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
24 #include <scsi/scsicam.h>
31 struct access_method {
32 void (*submit_command)(struct ctlr_info *h,
33 struct CommandList *c);
34 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
35 bool (*intr_pending)(struct ctlr_info *h);
36 unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
39 struct hpsa_scsi_dev_t {
41 int bus, target, lun; /* as presented to the OS */
42 unsigned char scsi3addr[8]; /* as presented to the HW */
43 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
44 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
45 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
46 unsigned char model[16]; /* bytes 16-31 of inquiry data */
47 unsigned char raid_level; /* from inquiry page 0xC1 */
48 unsigned char volume_offline; /* discovered via TUR or VPD */
49 u16 queue_depth; /* max queue_depth for this device */
50 atomic_t ioaccel_cmds_out; /* Only used for physical devices
51 * counts commands sent to physical
52 * device via "ioaccel" path.
55 int offload_config; /* I/O accel RAID offload configured */
56 int offload_enabled; /* I/O accel RAID offload enabled */
57 int offload_to_be_enabled;
58 int hba_ioaccel_enabled;
59 int offload_to_mirror; /* Send next I/O accelerator RAID
60 * offload request to mirror drive
62 struct raid_map_data raid_map; /* I/O accelerator RAID map */
65 * Pointers from logical drive map indices to the phys drives that
66 * make those logical drives. Note, multiple logical drives may
67 * share physical drives. You can have for instance 5 physical
68 * drives with 3 logical drives each using those same 5 physical
69 * disks. We need these pointers for counting i/o's out to physical
70 * devices in order to honor physical device queue depth limits.
72 struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
74 #define HPSA_DO_NOT_EXPOSE 0x0
75 #define HPSA_SG_ATTACH 0x1
76 #define HPSA_ULD_ATTACH 0x2
77 #define HPSA_SCSI_ADD (HPSA_SG_ATTACH | HPSA_ULD_ATTACH)
81 struct reply_queue_buffer {
90 struct bmic_controller_parameters {
92 u8 enable_command_list_verification;
93 u8 backed_out_write_drives;
94 u16 stripes_for_parity;
95 u8 parity_distribution_mode_flags;
96 u16 max_driver_requests;
97 u16 elevator_trend_count;
99 u8 force_scan_complete;
100 u8 scsi_transfer_mode;
104 u8 host_sdb_asic_fix;
105 u8 pdpi_burst_from_host_disabled;
106 char software_name[64];
107 char hardware_name[32];
109 u8 snapshot_priority;
111 u8 post_prompt_timeout;
112 u8 automatic_drive_slamming;
115 #define HBA_MODE_ENABLED_FLAG (1 << 3)
116 u8 cache_nvram_flags;
117 u8 drive_config_flags;
119 u8 temp_warning_level;
120 u8 temp_shutdown_level;
121 u8 temp_condition_reset;
122 u8 max_coalesce_commands;
123 u32 max_coalesce_delay;
134 struct pci_dev *pdev;
138 int nr_cmds; /* Number of commands allowed on this controller */
139 #define HPSA_CMDS_RESERVED_FOR_ABORTS 2
140 #define HPSA_CMDS_RESERVED_FOR_DRIVER 1
141 struct CfgTable __iomem *cfgtable;
142 int interrupts_enabled;
145 atomic_t commands_outstanding;
146 # define PERF_MODE_INT 0
147 # define DOORBELL_INT 1
148 # define SIMPLE_MODE_INT 2
149 # define MEMQ_MODE_INT 3
150 unsigned int intr[MAX_REPLY_QUEUES];
151 unsigned int msix_vector;
152 unsigned int msi_vector;
153 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
154 struct access_method access;
155 char hba_mode_enabled;
157 /* queue and queue Info */
162 u8 max_cmd_sg_entries;
164 struct SGDescriptor **cmd_sg_list;
165 struct ioaccel2_sg_element **ioaccel2_cmd_sg_list;
167 /* pointers to command and error info pool */
168 struct CommandList *cmd_pool;
169 dma_addr_t cmd_pool_dhandle;
170 struct io_accel1_cmd *ioaccel_cmd_pool;
171 dma_addr_t ioaccel_cmd_pool_dhandle;
172 struct io_accel2_cmd *ioaccel2_cmd_pool;
173 dma_addr_t ioaccel2_cmd_pool_dhandle;
174 struct ErrorInfo *errinfo_pool;
175 dma_addr_t errinfo_pool_dhandle;
176 unsigned long *cmd_pool_bits;
178 spinlock_t scan_lock;
179 wait_queue_head_t scan_wait_queue;
181 struct Scsi_Host *scsi_host;
182 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
183 int ndevices; /* number of used elements in .dev[] array. */
184 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
186 * Performant mode tables.
190 struct TransTable_struct __iomem *transtable;
191 unsigned long transMethod;
193 /* cap concurrent passthrus at some reasonable maximum */
194 #define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
195 atomic_t passthru_cmds_avail;
198 * Performant mode completion buffers
200 size_t reply_queue_size;
201 struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
203 u32 *blockFetchTable;
204 u32 *ioaccel1_blockFetchTable;
205 u32 *ioaccel2_blockFetchTable;
206 u32 __iomem *ioaccel2_bft2_regs;
207 unsigned char *hba_inquiry_data;
212 u64 last_intr_timestamp;
214 u64 last_heartbeat_timestamp;
215 u32 heartbeat_sample_interval;
216 atomic_t firmware_flash_in_progress;
217 u32 __percpu *lockup_detected;
218 struct delayed_work monitor_ctlr_work;
219 struct delayed_work rescan_ctlr_work;
220 int remove_in_progress;
221 /* Address of h->q[x] is passed to intr handler to know which queue */
222 u8 q[MAX_REPLY_QUEUES];
223 u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
224 #define HPSATMF_BITS_SUPPORTED (1 << 0)
225 #define HPSATMF_PHYS_LUN_RESET (1 << 1)
226 #define HPSATMF_PHYS_NEX_RESET (1 << 2)
227 #define HPSATMF_PHYS_TASK_ABORT (1 << 3)
228 #define HPSATMF_PHYS_TSET_ABORT (1 << 4)
229 #define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
230 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
231 #define HPSATMF_PHYS_QRY_TASK (1 << 7)
232 #define HPSATMF_PHYS_QRY_TSET (1 << 8)
233 #define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
234 #define HPSATMF_IOACCEL_ENABLED (1 << 15)
235 #define HPSATMF_MASK_SUPPORTED (1 << 16)
236 #define HPSATMF_LOG_LUN_RESET (1 << 17)
237 #define HPSATMF_LOG_NEX_RESET (1 << 18)
238 #define HPSATMF_LOG_TASK_ABORT (1 << 19)
239 #define HPSATMF_LOG_TSET_ABORT (1 << 20)
240 #define HPSATMF_LOG_CLEAR_ACA (1 << 21)
241 #define HPSATMF_LOG_CLEAR_TSET (1 << 22)
242 #define HPSATMF_LOG_QRY_TASK (1 << 23)
243 #define HPSATMF_LOG_QRY_TSET (1 << 24)
244 #define HPSATMF_LOG_QRY_ASYNC (1 << 25)
246 #define CTLR_STATE_CHANGE_EVENT (1 << 0)
247 #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
248 #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
249 #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
250 #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
251 #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
252 #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
254 #define RESCAN_REQUIRED_EVENT_BITS \
255 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
256 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
257 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
258 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
259 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
260 spinlock_t offline_device_lock;
261 struct list_head offline_device_list;
262 int acciopath_status;
263 int raid_offload_debug;
264 int needs_abort_tags_swizzled;
265 struct workqueue_struct *resubmit_wq;
266 struct workqueue_struct *rescan_ctlr_wq;
267 atomic_t abort_cmds_available;
268 wait_queue_head_t abort_cmd_wait_queue;
271 struct offline_device_entry {
272 unsigned char scsi3addr[8];
273 struct list_head offline_list;
276 #define HPSA_ABORT_MSG 0
277 #define HPSA_DEVICE_RESET_MSG 1
278 #define HPSA_RESET_TYPE_CONTROLLER 0x00
279 #define HPSA_RESET_TYPE_BUS 0x01
280 #define HPSA_RESET_TYPE_TARGET 0x03
281 #define HPSA_RESET_TYPE_LUN 0x04
282 #define HPSA_MSG_SEND_RETRY_LIMIT 10
283 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
285 /* Maximum time in seconds driver will wait for command completions
286 * when polling before giving up.
288 #define HPSA_MAX_POLL_TIME_SECS (20)
290 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
291 * how many times to retry TEST UNIT READY on a device
292 * while waiting for it to become ready before giving up.
293 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
294 * between sending TURs while waiting for a device
297 #define HPSA_TUR_RETRY_LIMIT (20)
298 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
300 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
301 * to become ready, in seconds, before giving up on it.
302 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
303 * between polling the board to see if it is ready, in
304 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
305 * HPSA_BOARD_READY_ITERATIONS are derived from those.
307 #define HPSA_BOARD_READY_WAIT_SECS (120)
308 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
309 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
310 #define HPSA_BOARD_READY_POLL_INTERVAL \
311 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
312 #define HPSA_BOARD_READY_ITERATIONS \
313 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
314 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
315 #define HPSA_BOARD_NOT_READY_ITERATIONS \
316 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
317 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
318 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
319 #define HPSA_POST_RESET_NOOP_RETRIES (12)
321 /* Defining the diffent access_menthods */
323 * Memory mapped FIFO interface (SMART 53xx cards)
325 #define SA5_DOORBELL 0x20
326 #define SA5_REQUEST_PORT_OFFSET 0x40
327 #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
328 #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
329 #define SA5_REPLY_INTR_MASK_OFFSET 0x34
330 #define SA5_REPLY_PORT_OFFSET 0x44
331 #define SA5_INTR_STATUS 0x30
332 #define SA5_SCRATCHPAD_OFFSET 0xB0
334 #define SA5_CTCFG_OFFSET 0xB4
335 #define SA5_CTMEM_OFFSET 0xB8
337 #define SA5_INTR_OFF 0x08
338 #define SA5B_INTR_OFF 0x04
339 #define SA5_INTR_PENDING 0x08
340 #define SA5B_INTR_PENDING 0x04
341 #define FIFO_EMPTY 0xffffffff
342 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
344 #define HPSA_ERROR_BIT 0x02
346 /* Performant mode flags */
347 #define SA5_PERF_INTR_PENDING 0x04
348 #define SA5_PERF_INTR_OFF 0x05
349 #define SA5_OUTDB_STATUS_PERF_BIT 0x01
350 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
351 #define SA5_OUTDB_CLEAR 0xA0
352 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01
353 #define SA5_OUTDB_STATUS 0x9C
356 #define HPSA_INTR_ON 1
357 #define HPSA_INTR_OFF 0
360 * Inbound Post Queue offsets for IO Accelerator Mode 2
362 #define IOACCEL2_INBOUND_POSTQ_32 0x48
363 #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
364 #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
367 Send the command to the hardware
369 static void SA5_submit_command(struct ctlr_info *h,
370 struct CommandList *c)
372 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
373 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
376 static void SA5_submit_command_no_read(struct ctlr_info *h,
377 struct CommandList *c)
379 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
382 static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
383 struct CommandList *c)
385 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
389 * This card is the opposite of the other cards.
390 * 0 turns interrupts on...
391 * 0x08 turns them off...
393 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
395 if (val) { /* Turn interrupts on */
396 h->interrupts_enabled = 1;
397 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
398 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
399 } else { /* Turn them off */
400 h->interrupts_enabled = 0;
402 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
403 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
407 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
409 if (val) { /* turn on interrupts */
410 h->interrupts_enabled = 1;
411 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
412 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
414 h->interrupts_enabled = 0;
415 writel(SA5_PERF_INTR_OFF,
416 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
417 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
421 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
423 struct reply_queue_buffer *rq = &h->reply_queue[q];
424 unsigned long register_value = FIFO_EMPTY;
426 /* msi auto clears the interrupt pending bit. */
427 if (unlikely(!(h->msi_vector || h->msix_vector))) {
428 /* flush the controller write of the reply queue by reading
429 * outbound doorbell status register.
431 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
432 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
433 /* Do a read in order to flush the write to the controller
436 (void) readl(h->vaddr + SA5_OUTDB_STATUS);
439 if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
440 register_value = rq->head[rq->current_entry];
442 atomic_dec(&h->commands_outstanding);
444 register_value = FIFO_EMPTY;
446 /* Check for wraparound */
447 if (rq->current_entry == h->max_commands) {
448 rq->current_entry = 0;
451 return register_value;
455 * returns value read from hardware.
456 * returns FIFO_EMPTY if there is nothing to read
458 static unsigned long SA5_completed(struct ctlr_info *h,
459 __attribute__((unused)) u8 q)
461 unsigned long register_value
462 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
464 if (register_value != FIFO_EMPTY)
465 atomic_dec(&h->commands_outstanding);
468 if (register_value != FIFO_EMPTY)
469 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
472 dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
475 return register_value;
478 * Returns true if an interrupt is pending..
480 static bool SA5_intr_pending(struct ctlr_info *h)
482 unsigned long register_value =
483 readl(h->vaddr + SA5_INTR_STATUS);
484 return register_value & SA5_INTR_PENDING;
487 static bool SA5_performant_intr_pending(struct ctlr_info *h)
489 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
494 /* Read outbound doorbell to flush */
495 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
496 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
499 #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
501 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
503 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
505 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
509 #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
510 #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
511 #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
512 #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
514 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
517 struct reply_queue_buffer *rq = &h->reply_queue[q];
519 BUG_ON(q >= h->nreply_queues);
521 register_value = rq->head[rq->current_entry];
522 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
523 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
524 if (++rq->current_entry == rq->size)
525 rq->current_entry = 0;
529 * Don't really need to write the new index after each command,
530 * but with current driver design this is easiest.
533 writel((q << 24) | rq->current_entry, h->vaddr +
534 IOACCEL_MODE1_CONSUMER_INDEX);
535 atomic_dec(&h->commands_outstanding);
537 return (unsigned long) register_value;
540 static struct access_method SA5_access = {
547 static struct access_method SA5_ioaccel_mode1_access = {
549 SA5_performant_intr_mask,
550 SA5_ioaccel_mode1_intr_pending,
551 SA5_ioaccel_mode1_completed,
554 static struct access_method SA5_ioaccel_mode2_access = {
555 SA5_submit_command_ioaccel2,
556 SA5_performant_intr_mask,
557 SA5_performant_intr_pending,
558 SA5_performant_completed,
561 static struct access_method SA5_performant_access = {
563 SA5_performant_intr_mask,
564 SA5_performant_intr_pending,
565 SA5_performant_completed,
568 static struct access_method SA5_performant_access_no_read = {
569 SA5_submit_command_no_read,
570 SA5_performant_intr_mask,
571 SA5_performant_intr_pending,
572 SA5_performant_completed,
578 struct access_method *access;