3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* This code should work for both the S3C2400 and the S3C2410
25 * as they seem to have the same I2C controller inside.
26 * The different address mapping is handled by the s3c24xx.h files below.
31 #ifdef CONFIG_DRIVER_S3C24X0_I2C
33 #if defined(CONFIG_S3C2400)
35 #elif defined(CONFIG_S3C2410)
40 #ifdef CONFIG_HARD_I2C
48 #define IIC_NOK_LA 3 /* Lost arbitration */
49 #define IIC_NOK_TOUT 4 /* time out */
51 #define IICSTAT_BSY 0x20 /* Busy bit */
52 #define IICSTAT_NACK 0x01 /* Nack bit */
53 #define IICCON_IRPND 0x10 /* Interrupt pending bit */
54 #define IIC_MODE_MT 0xC0 /* Master Transmit Mode */
55 #define IIC_MODE_MR 0x80 /* Master Receive Mode */
56 #define IIC_START_STOP 0x20 /* START / STOP */
57 #define IIC_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
59 #define IIC_TIMEOUT 1 /* 1 seconde */
62 static int GetIICSDA(void)
64 return (rGPEDAT & 0x8000) >> 15;
67 static void SetIICSDA(int x)
69 rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
72 static void SetIICSCL(int x)
74 rGPEDAT = (rGPEDAT & ~0x4000) | (x&1) << 14;
78 static int WaitForXfer(void)
82 i = IIC_TIMEOUT * 1000;
84 while ((i > 0) && !(status & IICCON_IRPND)) {
90 return(status & IICCON_IRPND) ? IIC_OK : IIC_NOK_TOUT;
93 static int IsACK(void)
95 return(!(rIICSTAT & IICSTAT_NACK));
98 static void ReadWriteByte(void)
100 rIICCON &= ~IICCON_IRPND;
103 void i2c_init (int speed, int slaveadd)
105 ulong freq, pres = 16, div;
108 /* wait for some time to give previous transfer a chance to finish */
110 i = IIC_TIMEOUT * 1000;
112 while ((i > 0) && (status & IICSTAT_BSY)) {
118 if ((status & IICSTAT_BSY) || GetIICSDA() == 0) {
119 ulong old_gpecon = rGPECON;
120 /* bus still busy probably by (most) previously interrupted transfer */
122 /* set IICSDA and IICSCL (GPE15, GPE14) to GPIO */
123 rGPECON = (rGPECON & ~0xF0000000) | 0x10000000;
125 /* toggle IICSCL until bus idle */
126 SetIICSCL(0); udelay(1000);
128 while ((i > 0) && (GetIICSDA() != 1)) {
129 SetIICSCL(1); udelay(1000);
130 SetIICSCL(0); udelay(1000);
133 SetIICSCL(1); udelay(1000);
135 /* restore pin functions */
136 rGPECON = old_gpecon;
139 /* calculate prescaler and divisor values */
141 if ((freq / pres / (16+1)) > speed)
142 /* set prescaler to 512 */
146 while ((freq / pres / (div+1)) > speed)
149 /* set prescaler, divisor according to freq, also set
151 rIICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
153 /* init to SLAVE REVEIVE and set slaveaddr */
156 /* program Master Transmit (and implicit STOP) */
157 rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
162 cmd_type is 0 for write 1 for read.
164 addr_len can take any value from 0-255, it is only limited
165 by the char, we could make it larger if needed. If it is
166 0 we skip the address write cycle.
170 int i2c_transfer(unsigned char cmd_type,
172 unsigned char addr[],
173 unsigned char addr_len,
174 unsigned char data[],
175 unsigned short data_len)
177 int i, status, result;
179 if (data == 0 || data_len == 0) {
180 /*Don't support data transfer of no length or to address 0*/
181 printf( "i2c_transfer: bad call\n" );
187 /* Check I2C bus idle */
188 i = IIC_TIMEOUT * 1000;
190 while ((i > 0) && (status & IICSTAT_BSY)) {
197 if (status & IICSTAT_BSY) {
198 result = IIC_NOK_TOUT;
208 if (addr && addr_len) {
211 rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
213 while ((i < addr_len) && (result == IIC_OK)) {
214 result = WaitForXfer();
220 while ((i < data_len) && (result == IIC_OK)) {
221 result = WaitForXfer();
229 rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
231 while ((i < data_len) && (result = IIC_OK)) {
232 result = WaitForXfer();
239 if (result == IIC_OK)
240 result = WaitForXfer();
243 rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
248 if (addr && addr_len) {
249 rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
252 rIICSTAT |= IIC_START_STOP;
253 result = WaitForXfer();
256 while ((i < addr_len) && (result == IIC_OK)) {
259 result = WaitForXfer();
265 rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA | IIC_START_STOP;
267 result = WaitForXfer();
269 while ((i < data_len) && (result == IIC_OK)) {
270 /* disable ACK for final READ */
271 if (i == data_len - 1)
274 result = WaitForXfer();
283 rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
286 rIICSTAT |= IIC_START_STOP;
287 result = WaitForXfer();
291 while ((i < data_len) && (result == IIC_OK)) {
292 /* disable ACK for final READ */
293 if (i == data_len - 1)
296 result = WaitForXfer();
306 rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
311 printf( "i2c_transfer: bad call\n" );
319 int i2c_probe (uchar chip)
326 * What is needed is to send the chip address and verify that the
327 * address was <ACK>ed (i.e. there was a chip at that address which
328 * drove the data line low).
330 return(i2c_transfer (IIC_READ, chip << 1, 0, 0, buf, 1) != IIC_OK);
333 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
339 printf ("I2C read: addr len %d not supported\n", alen);
344 xaddr[0] = (addr >> 24) & 0xFF;
345 xaddr[1] = (addr >> 16) & 0xFF;
346 xaddr[2] = (addr >> 8) & 0xFF;
347 xaddr[3] = addr & 0xFF;
351 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
353 * EEPROM chips that implement "address overflow" are ones
354 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
355 * address and the extra bits end up in the "chip address"
356 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
357 * four 256 byte chips.
359 * Note that we consider the length of the address field to
360 * still be one byte because the extra address bits are
361 * hidden in the chip address.
364 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
366 if( (ret = i2c_transfer(IIC_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
367 printf( "I2c read: failed %d\n", ret);
373 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
378 printf ("I2C write: addr len %d not supported\n", alen);
383 xaddr[0] = (addr >> 24) & 0xFF;
384 xaddr[1] = (addr >> 16) & 0xFF;
385 xaddr[2] = (addr >> 8) & 0xFF;
386 xaddr[3] = addr & 0xFF;
389 #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
391 * EEPROM chips that implement "address overflow" are ones
392 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
393 * address and the extra bits end up in the "chip address"
394 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
395 * four 256 byte chips.
397 * Note that we consider the length of the address field to
398 * still be one byte because the extra address bits are
399 * hidden in the chip address.
402 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
404 return (i2c_transfer(IIC_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
407 #endif /* CONFIG_HARD_I2C */
409 #endif /* CONFIG_DRIVER_S3C24X0_I2C */