1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
11 #include <dm/device_compat.h>
12 #include <linux/bitops.h>
13 #include <linux/iopoll.h>
15 #define STM32_RTC_TR 0x00
16 #define STM32_RTC_DR 0x04
17 #define STM32_RTC_ISR 0x0C
18 #define STM32_RTC_PRER 0x10
19 #define STM32_RTC_CR 0x18
20 #define STM32_RTC_WPR 0x24
22 /* STM32_RTC_TR bit fields */
23 #define STM32_RTC_SEC_SHIFT 0
24 #define STM32_RTC_SEC GENMASK(6, 0)
25 #define STM32_RTC_MIN_SHIFT 8
26 #define STM32_RTC_MIN GENMASK(14, 8)
27 #define STM32_RTC_HOUR_SHIFT 16
28 #define STM32_RTC_HOUR GENMASK(21, 16)
30 /* STM32_RTC_DR bit fields */
31 #define STM32_RTC_DATE_SHIFT 0
32 #define STM32_RTC_DATE GENMASK(5, 0)
33 #define STM32_RTC_MONTH_SHIFT 8
34 #define STM32_RTC_MONTH GENMASK(12, 8)
35 #define STM32_RTC_WDAY_SHIFT 13
36 #define STM32_RTC_WDAY GENMASK(15, 13)
37 #define STM32_RTC_YEAR_SHIFT 16
38 #define STM32_RTC_YEAR GENMASK(23, 16)
40 /* STM32_RTC_CR bit fields */
41 #define STM32_RTC_CR_FMT BIT(6)
43 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
44 #define STM32_RTC_ISR_INITS BIT(4)
45 #define STM32_RTC_ISR_RSF BIT(5)
46 #define STM32_RTC_ISR_INITF BIT(6)
47 #define STM32_RTC_ISR_INIT BIT(7)
49 /* STM32_RTC_PRER bit fields */
50 #define STM32_RTC_PRER_PRED_S_SHIFT 0
51 #define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
52 #define STM32_RTC_PRER_PRED_A_SHIFT 16
53 #define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
55 /* STM32_RTC_WPR key constants */
56 #define RTC_WPR_1ST_KEY 0xCA
57 #define RTC_WPR_2ND_KEY 0x53
58 #define RTC_WPR_WRONG_KEY 0xFF
60 struct stm32_rtc_priv {
64 static int stm32_rtc_get(struct udevice *dev, struct rtc_time *tm)
66 struct stm32_rtc_priv *priv = dev_get_priv(dev);
69 tr = readl(priv->base + STM32_RTC_TR);
70 dr = readl(priv->base + STM32_RTC_DR);
72 tm->tm_sec = bcd2bin((tr & STM32_RTC_SEC) >> STM32_RTC_SEC_SHIFT);
73 tm->tm_min = bcd2bin((tr & STM32_RTC_MIN) >> STM32_RTC_MIN_SHIFT);
74 tm->tm_hour = bcd2bin((tr & STM32_RTC_HOUR) >> STM32_RTC_HOUR_SHIFT);
76 tm->tm_mday = bcd2bin((dr & STM32_RTC_DATE) >> STM32_RTC_DATE_SHIFT);
77 tm->tm_mon = bcd2bin((dr & STM32_RTC_MONTH) >> STM32_RTC_MONTH_SHIFT);
79 bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT);
80 tm->tm_wday = bcd2bin((dr & STM32_RTC_WDAY) >> STM32_RTC_WDAY_SHIFT);
84 dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
85 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
86 tm->tm_hour, tm->tm_min, tm->tm_sec);
91 static void stm32_rtc_unlock(struct udevice *dev)
93 struct stm32_rtc_priv *priv = dev_get_priv(dev);
95 writel(RTC_WPR_1ST_KEY, priv->base + STM32_RTC_WPR);
96 writel(RTC_WPR_2ND_KEY, priv->base + STM32_RTC_WPR);
99 static void stm32_rtc_lock(struct udevice *dev)
101 struct stm32_rtc_priv *priv = dev_get_priv(dev);
103 writel(RTC_WPR_WRONG_KEY, priv->base + STM32_RTC_WPR);
106 static int stm32_rtc_enter_init_mode(struct udevice *dev)
108 struct stm32_rtc_priv *priv = dev_get_priv(dev);
109 u32 isr = readl(priv->base + STM32_RTC_ISR);
111 if (!(isr & STM32_RTC_ISR_INITF)) {
112 isr |= STM32_RTC_ISR_INIT;
113 writel(isr, priv->base + STM32_RTC_ISR);
115 return readl_poll_timeout(priv->base + STM32_RTC_ISR,
117 (isr & STM32_RTC_ISR_INITF),
124 static int stm32_rtc_wait_sync(struct udevice *dev)
126 struct stm32_rtc_priv *priv = dev_get_priv(dev);
127 u32 isr = readl(priv->base + STM32_RTC_ISR);
129 isr &= ~STM32_RTC_ISR_RSF;
130 writel(isr, priv->base + STM32_RTC_ISR);
133 * Wait for RSF to be set to ensure the calendar registers are
134 * synchronised, it takes around 2 rtc_ck clock cycles
136 return readl_poll_timeout(priv->base + STM32_RTC_ISR,
137 isr, (isr & STM32_RTC_ISR_RSF),
141 static void stm32_rtc_exit_init_mode(struct udevice *dev)
143 struct stm32_rtc_priv *priv = dev_get_priv(dev);
144 u32 isr = readl(priv->base + STM32_RTC_ISR);
146 isr &= ~STM32_RTC_ISR_INIT;
147 writel(isr, priv->base + STM32_RTC_ISR);
150 static int stm32_rtc_set_time(struct udevice *dev, u32 time, u32 date)
152 struct stm32_rtc_priv *priv = dev_get_priv(dev);
155 stm32_rtc_unlock(dev);
157 ret = stm32_rtc_enter_init_mode(dev);
161 writel(time, priv->base + STM32_RTC_TR);
162 writel(date, priv->base + STM32_RTC_DR);
164 stm32_rtc_exit_init_mode(dev);
166 ret = stm32_rtc_wait_sync(dev);
173 static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm)
177 dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
178 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
179 tm->tm_hour, tm->tm_min, tm->tm_sec);
181 if (tm->tm_year < 2000 || tm->tm_year > 2099)
184 /* Time in BCD format */
185 t = (bin2bcd(tm->tm_sec) << STM32_RTC_SEC_SHIFT) & STM32_RTC_SEC;
186 t |= (bin2bcd(tm->tm_min) << STM32_RTC_MIN_SHIFT) & STM32_RTC_MIN;
187 t |= (bin2bcd(tm->tm_hour) << STM32_RTC_HOUR_SHIFT) & STM32_RTC_HOUR;
189 /* Date in BCD format */
190 d = (bin2bcd(tm->tm_mday) << STM32_RTC_DATE_SHIFT) & STM32_RTC_DATE;
191 d |= (bin2bcd(tm->tm_mon) << STM32_RTC_MONTH_SHIFT) & STM32_RTC_MONTH;
192 d |= (bin2bcd(tm->tm_year - 2000) << STM32_RTC_YEAR_SHIFT) &
194 d |= (bin2bcd(tm->tm_wday) << STM32_RTC_WDAY_SHIFT) & STM32_RTC_WDAY;
196 return stm32_rtc_set_time(dev, t, d);
199 static int stm32_rtc_reset(struct udevice *dev)
201 dev_dbg(dev, "Reset DATE\n");
203 return stm32_rtc_set_time(dev, 0, 0);
206 static int stm32_rtc_init(struct udevice *dev)
208 struct stm32_rtc_priv *priv = dev_get_priv(dev);
209 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
213 u32 isr = readl(priv->base + STM32_RTC_ISR);
215 if (isr & STM32_RTC_ISR_INITS)
218 ret = clk_get_by_index(dev, 1, &clk);
222 ret = clk_enable(&clk);
228 rate = clk_get_rate(&clk);
230 /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
231 pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
232 pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
234 for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
235 pred_s = (rate / (pred_a + 1)) - 1;
237 if (((pred_s + 1) * (pred_a + 1)) == rate)
242 * Can't find a 1Hz, so give priority to RTC power consumption
243 * by choosing the higher possible value for prediv_a
245 if (pred_s > pred_s_max || pred_a > pred_a_max) {
247 pred_s = (rate / (pred_a + 1)) - 1;
250 stm32_rtc_unlock(dev);
252 ret = stm32_rtc_enter_init_mode(dev);
255 "Can't enter in init mode. Prescaler config failed.\n");
259 prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
260 prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
261 writel(prer, priv->base + STM32_RTC_PRER);
263 /* Force 24h time format */
264 cr = readl(priv->base + STM32_RTC_CR);
265 cr &= ~STM32_RTC_CR_FMT;
266 writel(cr, priv->base + STM32_RTC_CR);
268 stm32_rtc_exit_init_mode(dev);
270 ret = stm32_rtc_wait_sync(dev);
283 static int stm32_rtc_probe(struct udevice *dev)
285 struct stm32_rtc_priv *priv = dev_get_priv(dev);
289 priv->base = dev_read_addr(dev);
290 if (priv->base == FDT_ADDR_T_NONE)
293 ret = clk_get_by_index(dev, 0, &clk);
297 ret = clk_enable(&clk);
303 ret = stm32_rtc_init(dev);
313 static const struct rtc_ops stm32_rtc_ops = {
314 .get = stm32_rtc_get,
315 .set = stm32_rtc_set,
316 .reset = stm32_rtc_reset,
319 static const struct udevice_id stm32_rtc_ids[] = {
320 { .compatible = "st,stm32mp1-rtc" },
324 U_BOOT_DRIVER(rtc_stm32) = {
327 .probe = stm32_rtc_probe,
328 .of_match = stm32_rtc_ids,
329 .ops = &stm32_rtc_ops,
330 .priv_auto_alloc_size = sizeof(struct stm32_rtc_priv),