2 * rtc-twl.c -- TWL Real Time Clock interface
4 * Copyright (C) 2007 MontaVista Software, Inc
5 * Author: Alexandre Rusev <source@mvista.com>
7 * Based on original TI driver twl4030-rtc.c
8 * Copyright (C) 2006 Texas Instruments, Inc.
11 * Copyright (C) 2003 MontaVista Software, Inc.
12 * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
13 * Copyright (C) 2006 David Brownell
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/kernel.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/rtc.h>
27 #include <linux/bcd.h>
28 #include <linux/platform_device.h>
29 #include <linux/interrupt.h>
32 #include <linux/i2c/twl.h>
36 * RTC block register offsets (use TWL_MODULE_RTC)
47 REG_ALARM_SECONDS_REG,
48 REG_ALARM_MINUTES_REG,
56 REG_RTC_INTERRUPTS_REG,
61 static const u8 twl4030_rtc_reg_map[] = {
62 [REG_SECONDS_REG] = 0x00,
63 [REG_MINUTES_REG] = 0x01,
64 [REG_HOURS_REG] = 0x02,
65 [REG_DAYS_REG] = 0x03,
66 [REG_MONTHS_REG] = 0x04,
67 [REG_YEARS_REG] = 0x05,
68 [REG_WEEKS_REG] = 0x06,
70 [REG_ALARM_SECONDS_REG] = 0x07,
71 [REG_ALARM_MINUTES_REG] = 0x08,
72 [REG_ALARM_HOURS_REG] = 0x09,
73 [REG_ALARM_DAYS_REG] = 0x0A,
74 [REG_ALARM_MONTHS_REG] = 0x0B,
75 [REG_ALARM_YEARS_REG] = 0x0C,
77 [REG_RTC_CTRL_REG] = 0x0D,
78 [REG_RTC_STATUS_REG] = 0x0E,
79 [REG_RTC_INTERRUPTS_REG] = 0x0F,
81 [REG_RTC_COMP_LSB_REG] = 0x10,
82 [REG_RTC_COMP_MSB_REG] = 0x11,
84 static const u8 twl6030_rtc_reg_map[] = {
85 [REG_SECONDS_REG] = 0x00,
86 [REG_MINUTES_REG] = 0x01,
87 [REG_HOURS_REG] = 0x02,
88 [REG_DAYS_REG] = 0x03,
89 [REG_MONTHS_REG] = 0x04,
90 [REG_YEARS_REG] = 0x05,
91 [REG_WEEKS_REG] = 0x06,
93 [REG_ALARM_SECONDS_REG] = 0x08,
94 [REG_ALARM_MINUTES_REG] = 0x09,
95 [REG_ALARM_HOURS_REG] = 0x0A,
96 [REG_ALARM_DAYS_REG] = 0x0B,
97 [REG_ALARM_MONTHS_REG] = 0x0C,
98 [REG_ALARM_YEARS_REG] = 0x0D,
100 [REG_RTC_CTRL_REG] = 0x10,
101 [REG_RTC_STATUS_REG] = 0x11,
102 [REG_RTC_INTERRUPTS_REG] = 0x12,
104 [REG_RTC_COMP_LSB_REG] = 0x13,
105 [REG_RTC_COMP_MSB_REG] = 0x14,
108 /* RTC_CTRL_REG bitfields */
109 #define BIT_RTC_CTRL_REG_STOP_RTC_M 0x01
110 #define BIT_RTC_CTRL_REG_ROUND_30S_M 0x02
111 #define BIT_RTC_CTRL_REG_AUTO_COMP_M 0x04
112 #define BIT_RTC_CTRL_REG_MODE_12_24_M 0x08
113 #define BIT_RTC_CTRL_REG_TEST_MODE_M 0x10
114 #define BIT_RTC_CTRL_REG_SET_32_COUNTER_M 0x20
115 #define BIT_RTC_CTRL_REG_GET_TIME_M 0x40
116 #define BIT_RTC_CTRL_REG_RTC_V_OPT 0x80
118 /* RTC_STATUS_REG bitfields */
119 #define BIT_RTC_STATUS_REG_RUN_M 0x02
120 #define BIT_RTC_STATUS_REG_1S_EVENT_M 0x04
121 #define BIT_RTC_STATUS_REG_1M_EVENT_M 0x08
122 #define BIT_RTC_STATUS_REG_1H_EVENT_M 0x10
123 #define BIT_RTC_STATUS_REG_1D_EVENT_M 0x20
124 #define BIT_RTC_STATUS_REG_ALARM_M 0x40
125 #define BIT_RTC_STATUS_REG_POWER_UP_M 0x80
127 /* RTC_INTERRUPTS_REG bitfields */
128 #define BIT_RTC_INTERRUPTS_REG_EVERY_M 0x03
129 #define BIT_RTC_INTERRUPTS_REG_IT_TIMER_M 0x04
130 #define BIT_RTC_INTERRUPTS_REG_IT_ALARM_M 0x08
133 /* REG_SECONDS_REG through REG_YEARS_REG is how many registers? */
134 #define ALL_TIME_REGS 6
136 /*----------------------------------------------------------------------*/
137 static u8 *rtc_reg_map;
140 * Supports 1 byte read from TWL RTC register.
142 static int twl_rtc_read_u8(u8 *data, u8 reg)
146 ret = twl_i2c_read_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
148 pr_err("twl_rtc: Could not read TWL"
149 "register %X - error %d\n", reg, ret);
154 * Supports 1 byte write to TWL RTC registers.
156 static int twl_rtc_write_u8(u8 data, u8 reg)
160 ret = twl_i2c_write_u8(TWL_MODULE_RTC, data, (rtc_reg_map[reg]));
162 pr_err("twl_rtc: Could not write TWL"
163 "register %X - error %d\n", reg, ret);
168 * Cache the value for timer/alarm interrupts register; this is
169 * only changed by callers holding rtc ops lock (or resume).
171 static unsigned char rtc_irq_bits;
174 * Enable 1/second update and/or alarm interrupts.
176 static int set_rtc_irq_bit(unsigned char bit)
181 /* if the bit is set, return from here */
182 if (rtc_irq_bits & bit)
185 val = rtc_irq_bits | bit;
186 val &= ~BIT_RTC_INTERRUPTS_REG_EVERY_M;
187 ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
195 * Disable update and/or alarm interrupts.
197 static int mask_rtc_irq_bit(unsigned char bit)
202 /* if the bit is clear, return from here */
203 if (!(rtc_irq_bits & bit))
206 val = rtc_irq_bits & ~bit;
207 ret = twl_rtc_write_u8(val, REG_RTC_INTERRUPTS_REG);
214 static int twl_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
216 struct platform_device *pdev = to_platform_device(dev);
217 int irq = platform_get_irq(pdev, 0);
218 static bool twl_rtc_wake_enabled;
222 ret = set_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
223 if (device_can_wakeup(dev) && !twl_rtc_wake_enabled) {
224 enable_irq_wake(irq);
225 twl_rtc_wake_enabled = true;
228 ret = mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
229 if (twl_rtc_wake_enabled) {
230 disable_irq_wake(irq);
231 twl_rtc_wake_enabled = false;
239 * Gets current TWL RTC time and date parameters.
241 * The RTC's time/alarm representation is not what gmtime(3) requires
244 * - Months are 1..12 vs Linux 0-11
245 * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
247 static int twl_rtc_read_time(struct device *dev, struct rtc_time *tm)
249 unsigned char rtc_data[ALL_TIME_REGS];
254 ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
256 dev_err(dev, "%s: reading CTRL_REG, error %d\n", __func__, ret);
259 /* for twl6030/32 make sure BIT_RTC_CTRL_REG_GET_TIME_M is clear */
260 if (twl_class_is_6030()) {
261 if (save_control & BIT_RTC_CTRL_REG_GET_TIME_M) {
262 save_control &= ~BIT_RTC_CTRL_REG_GET_TIME_M;
263 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
265 dev_err(dev, "%s clr GET_TIME, error %d\n",
272 /* Copy RTC counting registers to static registers or latches */
273 rtc_control = save_control | BIT_RTC_CTRL_REG_GET_TIME_M;
275 /* for twl6030/32 enable read access to static shadowed registers */
276 if (twl_class_is_6030())
277 rtc_control |= BIT_RTC_CTRL_REG_RTC_V_OPT;
279 ret = twl_rtc_write_u8(rtc_control, REG_RTC_CTRL_REG);
281 dev_err(dev, "%s: writing CTRL_REG, error %d\n", __func__, ret);
285 ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
286 (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
289 dev_err(dev, "%s: reading data, error %d\n", __func__, ret);
293 /* for twl6030 restore original state of rtc control register */
294 if (twl_class_is_6030()) {
295 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
297 dev_err(dev, "%s: restore CTRL_REG, error %d\n",
303 tm->tm_sec = bcd2bin(rtc_data[0]);
304 tm->tm_min = bcd2bin(rtc_data[1]);
305 tm->tm_hour = bcd2bin(rtc_data[2]);
306 tm->tm_mday = bcd2bin(rtc_data[3]);
307 tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
308 tm->tm_year = bcd2bin(rtc_data[5]) + 100;
313 static int twl_rtc_set_time(struct device *dev, struct rtc_time *tm)
315 unsigned char save_control;
316 unsigned char rtc_data[ALL_TIME_REGS];
319 rtc_data[0] = bin2bcd(tm->tm_sec);
320 rtc_data[1] = bin2bcd(tm->tm_min);
321 rtc_data[2] = bin2bcd(tm->tm_hour);
322 rtc_data[3] = bin2bcd(tm->tm_mday);
323 rtc_data[4] = bin2bcd(tm->tm_mon + 1);
324 rtc_data[5] = bin2bcd(tm->tm_year - 100);
326 /* Stop RTC while updating the TC registers */
327 ret = twl_rtc_read_u8(&save_control, REG_RTC_CTRL_REG);
331 save_control &= ~BIT_RTC_CTRL_REG_STOP_RTC_M;
332 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
336 /* update all the time registers in one shot */
337 ret = twl_i2c_write(TWL_MODULE_RTC, rtc_data,
338 (rtc_reg_map[REG_SECONDS_REG]), ALL_TIME_REGS);
340 dev_err(dev, "rtc_set_time error %d\n", ret);
345 save_control |= BIT_RTC_CTRL_REG_STOP_RTC_M;
346 ret = twl_rtc_write_u8(save_control, REG_RTC_CTRL_REG);
353 * Gets current TWL RTC alarm time.
355 static int twl_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
357 unsigned char rtc_data[ALL_TIME_REGS];
360 ret = twl_i2c_read(TWL_MODULE_RTC, rtc_data,
361 (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
363 dev_err(dev, "rtc_read_alarm error %d\n", ret);
367 /* some of these fields may be wildcard/"match all" */
368 alm->time.tm_sec = bcd2bin(rtc_data[0]);
369 alm->time.tm_min = bcd2bin(rtc_data[1]);
370 alm->time.tm_hour = bcd2bin(rtc_data[2]);
371 alm->time.tm_mday = bcd2bin(rtc_data[3]);
372 alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
373 alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
375 /* report cached alarm enable state */
376 if (rtc_irq_bits & BIT_RTC_INTERRUPTS_REG_IT_ALARM_M)
382 static int twl_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
384 unsigned char alarm_data[ALL_TIME_REGS];
387 ret = twl_rtc_alarm_irq_enable(dev, 0);
391 alarm_data[0] = bin2bcd(alm->time.tm_sec);
392 alarm_data[1] = bin2bcd(alm->time.tm_min);
393 alarm_data[2] = bin2bcd(alm->time.tm_hour);
394 alarm_data[3] = bin2bcd(alm->time.tm_mday);
395 alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
396 alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
398 /* update all the alarm registers in one shot */
399 ret = twl_i2c_write(TWL_MODULE_RTC, alarm_data,
400 (rtc_reg_map[REG_ALARM_SECONDS_REG]), ALL_TIME_REGS);
402 dev_err(dev, "rtc_set_alarm error %d\n", ret);
407 ret = twl_rtc_alarm_irq_enable(dev, 1);
412 static irqreturn_t twl_rtc_interrupt(int irq, void *rtc)
414 unsigned long events;
419 res = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
423 * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
424 * only one (ALARM or RTC) interrupt source may be enabled
425 * at time, we also could check our results
426 * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
428 if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
429 events = RTC_IRQF | RTC_AF;
431 events = RTC_IRQF | RTC_PF;
433 res = twl_rtc_write_u8(BIT_RTC_STATUS_REG_ALARM_M,
438 if (twl_class_is_4030()) {
439 /* Clear on Read enabled. RTC_IT bit of TWL4030_INT_PWR_ISR1
440 * needs 2 reads to clear the interrupt. One read is done in
441 * do_twl_pwrirq(). Doing the second read, to clear
444 * FIXME the reason PWR_ISR1 needs an extra read is that
445 * RTC_IF retriggered until we cleared REG_ALARM_M above.
446 * But re-reading like this is a bad hack; by doing so we
447 * risk wrongly clearing status for some other IRQ (losing
448 * the interrupt). Be smarter about handling RTC_UF ...
450 res = twl_i2c_read_u8(TWL4030_MODULE_INT,
451 &rd_reg, TWL4030_INT_PWR_ISR1);
456 /* Notify RTC core on event */
457 rtc_update_irq(rtc, 1, events);
464 static struct rtc_class_ops twl_rtc_ops = {
465 .read_time = twl_rtc_read_time,
466 .set_time = twl_rtc_set_time,
467 .read_alarm = twl_rtc_read_alarm,
468 .set_alarm = twl_rtc_set_alarm,
469 .alarm_irq_enable = twl_rtc_alarm_irq_enable,
472 /*----------------------------------------------------------------------*/
474 static int twl_rtc_probe(struct platform_device *pdev)
476 struct rtc_device *rtc;
478 int irq = platform_get_irq(pdev, 0);
484 /* Initialize the register map */
485 if (twl_class_is_4030())
486 rtc_reg_map = (u8 *)twl4030_rtc_reg_map;
488 rtc_reg_map = (u8 *)twl6030_rtc_reg_map;
490 ret = twl_rtc_read_u8(&rd_reg, REG_RTC_STATUS_REG);
494 if (rd_reg & BIT_RTC_STATUS_REG_POWER_UP_M)
495 dev_warn(&pdev->dev, "Power up reset detected.\n");
497 if (rd_reg & BIT_RTC_STATUS_REG_ALARM_M)
498 dev_warn(&pdev->dev, "Pending Alarm interrupt detected.\n");
500 /* Clear RTC Power up reset and pending alarm interrupts */
501 ret = twl_rtc_write_u8(rd_reg, REG_RTC_STATUS_REG);
505 if (twl_class_is_6030()) {
506 twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
508 twl6030_interrupt_unmask(TWL6030_RTC_INT_MASK,
512 dev_info(&pdev->dev, "Enabling TWL-RTC\n");
513 ret = twl_rtc_write_u8(BIT_RTC_CTRL_REG_STOP_RTC_M, REG_RTC_CTRL_REG);
517 /* ensure interrupts are disabled, bootloaders can be strange */
518 ret = twl_rtc_write_u8(0, REG_RTC_INTERRUPTS_REG);
520 dev_warn(&pdev->dev, "unable to disable interrupt\n");
522 /* init cached IRQ enable bits */
523 ret = twl_rtc_read_u8(&rtc_irq_bits, REG_RTC_INTERRUPTS_REG);
527 rtc = rtc_device_register(pdev->name,
528 &pdev->dev, &twl_rtc_ops, THIS_MODULE);
531 dev_err(&pdev->dev, "can't register RTC device, err %ld\n",
536 ret = request_threaded_irq(irq, NULL, twl_rtc_interrupt,
537 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
538 dev_name(&rtc->dev), rtc);
540 dev_err(&pdev->dev, "IRQ is not free.\n");
544 platform_set_drvdata(pdev, rtc);
545 device_init_wakeup(&pdev->dev, 1);
549 rtc_device_unregister(rtc);
555 * Disable all TWL RTC module interrupts.
556 * Sets status flag to free.
558 static int twl_rtc_remove(struct platform_device *pdev)
560 /* leave rtc running, but disable irqs */
561 struct rtc_device *rtc = platform_get_drvdata(pdev);
562 int irq = platform_get_irq(pdev, 0);
564 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
565 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
566 if (twl_class_is_6030()) {
567 twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
569 twl6030_interrupt_mask(TWL6030_RTC_INT_MASK,
576 rtc_device_unregister(rtc);
580 static void twl_rtc_shutdown(struct platform_device *pdev)
582 /* mask timer interrupts, but leave alarm interrupts on to enable
583 power-on when alarm is triggered */
584 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
587 #ifdef CONFIG_PM_SLEEP
588 static unsigned char irqstat;
590 static int twl_rtc_suspend(struct device *dev)
592 irqstat = rtc_irq_bits;
594 mask_rtc_irq_bit(BIT_RTC_INTERRUPTS_REG_IT_TIMER_M);
598 static int twl_rtc_resume(struct device *dev)
600 set_rtc_irq_bit(irqstat);
605 static SIMPLE_DEV_PM_OPS(twl_rtc_pm_ops, twl_rtc_suspend, twl_rtc_resume);
608 static const struct of_device_id twl_rtc_of_match[] = {
609 {.compatible = "ti,twl4030-rtc", },
612 MODULE_DEVICE_TABLE(of, twl_rtc_of_match);
615 MODULE_ALIAS("platform:twl_rtc");
617 static struct platform_driver twl4030rtc_driver = {
618 .probe = twl_rtc_probe,
619 .remove = twl_rtc_remove,
620 .shutdown = twl_rtc_shutdown,
622 .owner = THIS_MODULE,
624 .pm = &twl_rtc_pm_ops,
625 .of_match_table = of_match_ptr(twl_rtc_of_match),
629 module_platform_driver(twl4030rtc_driver);
631 MODULE_AUTHOR("Texas Instruments, MontaVista Software");
632 MODULE_LICENSE("GPL");