1 // SPDX-License-Identifier: GPL-2.0
3 * RTC driver for the StarFive JH7110 SoC
5 * Copyright (C) 2021 StarFive Technology Co., Ltd.
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/reset.h>
13 #include <linux/completion.h>
14 #include <linux/interrupt.h>
16 #include <linux/module.h>
18 #include <linux/of_irq.h>
19 #include <linux/iopoll.h>
20 #include <linux/platform_device.h>
21 #include <linux/rtc.h>
24 #define SFT_RTC_CFG 0x00
25 #define SFT_RTC_SW_CAL_VALUE 0x04
26 #define SFT_RTC_HW_CAL_CFG 0x08
27 #define SFT_RTC_CMP_CFG 0x0C
28 #define SFT_RTC_IRQ_EN 0x10
29 #define SFT_RTC_IRQ_EVEVT 0x14
30 #define SFT_RTC_IRQ_STATUS 0x18
31 #define SFT_RTC_CAL_VALUE 0x24
32 #define SFT_RTC_CFG_TIME 0x28
33 #define SFT_RTC_CFG_DATE 0x2C
34 #define SFT_RTC_ACT_TIME 0x34
35 #define SFT_RTC_ACT_DATE 0x38
36 #define SFT_RTC_TIME 0x3C
37 #define SFT_RTC_DATE 0x40
38 #define SFT_RTC_TIME_LATCH 0x44
39 #define SFT_RTC_DATE_LATCH 0x48
42 #define RTC_CFG_ENABLE_SHIFT 0 /* RW: RTC Enable. */
43 #define RTC_CFG_CAL_EN_HW_SHIFT 1 /* RW: Enable of hardware calibretion. */
44 #define RTC_CFG_CAL_SEL_SHIFT 2 /* RW: select the hw/sw calibretion mode.*/
45 #define RTC_CFG_HOUR_MODE_SHIFT 3 /* RW: time hour mode. 24h|12h */
47 /* RTC_SW_CAL_VALUE */
48 #define RTC_SW_CAL_VALUE_MASK GENMASK(15, 0)
49 #define RTC_SW_CAL_MAX RTC_SW_CAL_VALUE_MASK
50 #define RTC_SW_CAL_MIN 0
51 #define RTC_TICKS_PER_SEC 32768 /* Number of ticks per second */
52 #define RTC_PPB_MULT 1000000000LL /* Multiplier for ppb conversions */
55 #define RTC_HW_CAL_REF_SEL_SHIFT 0
56 #define RTC_HW_CAL_FRQ_SEL_SHIFT 1
58 /* IRQ_EN/IRQ_EVEVT/IRQ_STATUS */
59 #define RTC_IRQ_CAL_START BIT(0)
60 #define RTC_IRQ_CAL_FINISH BIT(1)
61 #define RTC_IRQ_CMP BIT(2)
62 #define RTC_IRQ_1SEC BIT(3)
63 #define RTC_IRQ_ALAEM BIT(4)
64 #define RTC_IRQ_EVT_UPDATE_PSE BIT(31) /* WO: Enable of update time&&date, IRQ_EVEVT only */
65 #define RTC_IRQ_ALL (RTC_IRQ_CAL_START \
66 | RTC_IRQ_CAL_FINISH \
72 #define RTC_CAL_VALUE_MASK GENMASK(15, 0)
74 /* CFG_TIME/ACT_TIME/RTC_TIME */
75 #define TIME_SEC_MASK GENMASK(6, 0)
76 #define TIME_MIN_MASK GENMASK(13, 7)
77 #define TIME_HOUR_MASK GENMASK(20, 14)
79 /* CFG_DATE/ACT_DATE/RTC_DATE */
80 #define DATE_DAY_MASK GENMASK(5, 0)
81 #define DATE_MON_MASK GENMASK(10, 6)
82 #define DATE_YEAR_MASK GENMASK(18, 11)
84 #define INT_TIMEOUT_US 180
87 RTC_HOUR_MODE_12H = 0,
96 enum RTC_HW_CAL_REF_MODE {
101 static const unsigned long refclk_list[] = {
137 struct rtc_device *rtc_dev;
138 struct completion cal_done;
139 struct completion onesec_done;
142 struct reset_control *rst_apb;
143 struct reset_control *rst_cal;
144 struct reset_control *rst_osc;
149 int one_sec_pulse_irq;
152 static inline void sft_rtc_set_enabled(struct sft_rtc *srtc, bool enabled)
157 val = readl(srtc->regs + SFT_RTC_CFG);
158 val |= BIT(RTC_CFG_ENABLE_SHIFT);
159 writel(val, srtc->regs + SFT_RTC_CFG);
161 val = readl(srtc->regs + SFT_RTC_CFG);
162 val &= ~BIT(RTC_CFG_ENABLE_SHIFT);
163 writel(val, srtc->regs + SFT_RTC_CFG);
167 static inline bool sft_rtc_get_enabled(struct sft_rtc *srtc)
169 return !!(readl(srtc->regs + SFT_RTC_CFG) & BIT(RTC_CFG_ENABLE_SHIFT));
172 static inline void sft_rtc_set_mode(struct sft_rtc *srtc, enum RTC_HOUR_MODE mode)
176 val = readl(srtc->regs + SFT_RTC_CFG);
177 val |= mode << RTC_CFG_HOUR_MODE_SHIFT;
178 writel(val, srtc->regs + SFT_RTC_CFG);
181 static inline int sft_rtc_irq_enable(struct sft_rtc *srtc, u32 irq, bool enable)
185 if (!(irq & RTC_IRQ_ALL))
189 val = readl(srtc->regs + SFT_RTC_IRQ_EN);
191 writel(val, srtc->regs + SFT_RTC_IRQ_EN);
193 val = readl(srtc->regs + SFT_RTC_IRQ_EN);
195 writel(val, srtc->regs + SFT_RTC_IRQ_EN);
201 sft_rtc_set_cal_hw_enable(struct sft_rtc *srtc, bool enable)
206 val = readl(srtc->regs + SFT_RTC_CFG);
207 val |= BIT(RTC_CFG_CAL_EN_HW_SHIFT);
208 writel(val, srtc->regs + SFT_RTC_CFG);
210 val = readl(srtc->regs + SFT_RTC_CFG);
211 val &= ~BIT(RTC_CFG_CAL_EN_HW_SHIFT);
212 writel(val, srtc->regs + SFT_RTC_CFG);
217 sft_rtc_set_cal_mode(struct sft_rtc *srtc, enum RTC_CAL_MODE mode)
221 val = readl(srtc->regs + SFT_RTC_CFG);
222 val |= mode << RTC_CFG_CAL_SEL_SHIFT;
223 writel(val, srtc->regs + SFT_RTC_CFG);
226 static int sft_rtc_get_hw_calclk(struct device *dev, unsigned long freq)
230 for (i = 0; i < ARRAY_SIZE(refclk_list); i++)
231 if (refclk_list[i] == freq)
234 dev_err(dev, "refclk: %ldHz do not support.\n", freq);
238 static inline void sft_rtc_reg2time(struct rtc_time *tm, u32 reg)
240 tm->tm_hour = bcd2bin(FIELD_GET(TIME_HOUR_MASK, reg));
241 tm->tm_min = bcd2bin(FIELD_GET(TIME_MIN_MASK, reg));
242 tm->tm_sec = bcd2bin(FIELD_GET(TIME_SEC_MASK, reg));
245 static inline void sft_rtc_reg2date(struct rtc_time *tm, u32 reg)
247 tm->tm_year = bcd2bin(FIELD_GET(DATE_YEAR_MASK, reg)) + 100;
248 tm->tm_mon = bcd2bin(FIELD_GET(DATE_MON_MASK, reg)) - 1;
249 tm->tm_mday = bcd2bin(FIELD_GET(DATE_DAY_MASK, reg));
252 static inline u32 sft_rtc_time2reg(struct rtc_time *tm)
254 return FIELD_PREP(TIME_HOUR_MASK, bin2bcd(tm->tm_hour)) |
255 FIELD_PREP(TIME_MIN_MASK, bin2bcd(tm->tm_min)) |
256 FIELD_PREP(TIME_SEC_MASK, bin2bcd(tm->tm_sec));
259 static inline u32 sft_rtc_date2reg(struct rtc_time *tm)
261 return FIELD_PREP(DATE_YEAR_MASK, bin2bcd(tm->tm_year - 100)) |
262 FIELD_PREP(DATE_MON_MASK, bin2bcd(tm->tm_mon + 1)) |
263 FIELD_PREP(DATE_DAY_MASK, bin2bcd(tm->tm_mday));
266 static inline void sft_rtc_update_pulse(struct sft_rtc *srtc)
270 val = readl(srtc->regs + SFT_RTC_IRQ_EVEVT);
271 val |= RTC_IRQ_EVT_UPDATE_PSE;
272 writel(val, srtc->regs + SFT_RTC_IRQ_EVEVT);
275 static irqreturn_t sft_rtc_irq_handler(int irq, void *data)
277 struct sft_rtc *srtc = data;
283 val = readl(srtc->regs + SFT_RTC_IRQ_EVEVT);
284 if (val & RTC_IRQ_CAL_START)
285 irq_mask |= RTC_IRQ_CAL_START;
287 if (val & RTC_IRQ_CAL_FINISH) {
288 irq_mask |= RTC_IRQ_CAL_FINISH;
289 complete(&srtc->cal_done);
292 if (val & RTC_IRQ_CMP)
293 irq_mask |= RTC_IRQ_CMP;
295 if (val & RTC_IRQ_1SEC) {
297 irq_mask |= RTC_IRQ_1SEC;
298 complete(&srtc->onesec_done);
301 if (val & RTC_IRQ_ALAEM) {
303 irq_mask |= RTC_IRQ_ALAEM;
304 /* Make sure aie_timer will pop out from timerqueue */
305 srtc->rtc_dev->aie_timer.node.expires -= 1 * NSEC_PER_SEC;
306 dev_info(&srtc->rtc_dev->dev, "alarm expires");
309 writel(irq_mask, srtc->regs + SFT_RTC_IRQ_EVEVT);
311 /* Wait interrupt flag clear */
312 ret = readl_poll_timeout_atomic(srtc->regs + SFT_RTC_IRQ_EVEVT, val,
313 (val & irq_mask) == 0, 0, INT_TIMEOUT_US);
315 dev_warn(&srtc->rtc_dev->dev, "fail to clear rtc interrupt flag\n");
318 rtc_update_irq(srtc->rtc_dev, 1, irq_flags | RTC_IRQF);
323 static int sft_rtc_read_time(struct device *dev, struct rtc_time *tm)
325 struct sft_rtc *srtc = dev_get_drvdata(dev);
328 /* If the RTC is disabled, assume the values are invalid */
329 if (!sft_rtc_get_enabled(srtc))
332 val = readl(srtc->regs + SFT_RTC_TIME_LATCH);
333 sft_rtc_reg2time(tm, val);
335 val = readl(srtc->regs + SFT_RTC_DATE_LATCH);
336 sft_rtc_reg2date(tm, val);
341 static int sft_rtc_set_time(struct device *dev, struct rtc_time *tm)
343 struct sft_rtc *srtc = dev_get_drvdata(dev);
347 val = sft_rtc_time2reg(tm);
348 writel(val, srtc->regs + SFT_RTC_CFG_TIME);
350 val = sft_rtc_date2reg(tm);
351 writel(val, srtc->regs + SFT_RTC_CFG_DATE);
354 sft_rtc_update_pulse(srtc);
356 /* Ensure that data is fully written */
357 ret = wait_for_completion_interruptible_timeout(&srtc->onesec_done,
358 usecs_to_jiffies(120));
361 "rtc wait for completion interruptible timeout.\n");
366 static int sft_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
368 struct sft_rtc *srtc = dev_get_drvdata(dev);
370 return sft_rtc_irq_enable(srtc, RTC_IRQ_ALAEM, enabled);
373 static int sft_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
375 struct sft_rtc *srtc = dev_get_drvdata(dev);
378 val = readl(srtc->regs + SFT_RTC_ACT_TIME);
379 sft_rtc_reg2time(&alarm->time, val);
381 val = readl(srtc->regs + SFT_RTC_ACT_DATE);
382 sft_rtc_reg2date(&alarm->time, val);
387 static int sft_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
389 struct sft_rtc *srtc = dev_get_drvdata(dev);
392 sft_rtc_alarm_irq_enable(dev, 0);
394 val = sft_rtc_time2reg(&alarm->time);
395 writel(val, srtc->regs + SFT_RTC_ACT_TIME);
397 val = sft_rtc_date2reg(&alarm->time);
398 writel(val, srtc->regs + SFT_RTC_ACT_DATE);
400 sft_rtc_alarm_irq_enable(dev, alarm->enabled);
405 static int sft_rtc_get_offset(struct device *dev, long *offset)
407 struct sft_rtc *srtc = dev_get_drvdata(dev);
411 val = readl(srtc->regs + SFT_RTC_CAL_VALUE)
412 & RTC_SW_CAL_VALUE_MASK;
415 * the adjust val range is [0x0000-0xffff],
416 * the default val is 0x7fff (32768-1),mapping offset=0 ;
418 tmp = (s64)val - RTC_TICKS_PER_SEC;
420 tmp = div_s64(tmp, RTC_TICKS_PER_SEC);
422 /* Offset value operates in negative way, so swap sign */
428 static int sft_rtc_set_offset(struct device *dev, long offset)
430 struct sft_rtc *srtc = dev_get_drvdata(dev);
434 tmp = offset * RTC_TICKS_PER_SEC;
435 tmp = div_s64(tmp, RTC_PPB_MULT);
437 tmp = RTC_TICKS_PER_SEC - tmp;
439 if (tmp > RTC_SW_CAL_MAX || tmp < RTC_SW_CAL_MIN) {
440 dev_err(dev, "offset is out of range.\n");
444 val = tmp & RTC_SW_CAL_VALUE_MASK;
445 /* set software calibration value */
446 writel(val, srtc->regs + SFT_RTC_SW_CAL_VALUE);
448 /* set CFG_RTC-cal_sel to select calibretion by software. */
449 sft_rtc_set_cal_mode(srtc, RTC_CAL_MODE_SW);
454 static __maybe_unused int
455 sft_rtc_hw_adjustment(struct device *dev, unsigned int enable)
457 struct sft_rtc *srtc = dev_get_drvdata(dev);
460 if (srtc->hw_cal_map <= 0) {
461 dev_err(dev, "fail to get cal-clock-freq.\n");
466 sft_rtc_irq_enable(srtc, RTC_IRQ_CAL_FINISH, true);
468 /* Set reference clock frequency value */
469 val = readl(srtc->regs + SFT_RTC_HW_CAL_CFG);
470 val |= (srtc->hw_cal_map << RTC_HW_CAL_FRQ_SEL_SHIFT);
471 writel(val, srtc->regs + SFT_RTC_HW_CAL_CFG);
473 /* Set CFG_RTC-cal_sel to select calibretion by hardware. */
474 sft_rtc_set_cal_mode(srtc, RTC_CAL_MODE_HW);
476 /* Set CFG_RTC-cal_en_hw to launch hardware calibretion.*/
477 sft_rtc_set_cal_hw_enable(srtc, true);
479 wait_for_completion_interruptible_timeout(&srtc->cal_done,
480 usecs_to_jiffies(100));
482 sft_rtc_irq_enable(srtc, RTC_IRQ_CAL_FINISH, false);
484 sft_rtc_set_cal_mode(srtc, RTC_CAL_MODE_SW);
485 sft_rtc_set_cal_hw_enable(srtc, false);
491 static int sft_rtc_get_cal_clk(struct device *dev, struct sft_rtc *srtc)
493 struct device_node *np = dev->of_node;
494 unsigned long cal_clk_freq;
498 srtc->cal_clk = devm_clk_get(dev, "cal_clk");
499 if (IS_ERR(srtc->cal_clk))
500 return PTR_ERR(srtc->cal_clk);
502 clk_prepare_enable(srtc->cal_clk);
504 cal_clk_freq = clk_get_rate(srtc->cal_clk);
507 "get rate failed, next try to get from dts.\n");
508 ret = of_property_read_u32(np, "rtc,cal-clock-freq", &freq);
510 cal_clk_freq = (u64)freq;
513 "Need rtc,cal-clock-freq define in dts.\n");
514 goto err_disable_cal_clk;
518 srtc->hw_cal_map = sft_rtc_get_hw_calclk(dev, cal_clk_freq);
519 if (srtc->hw_cal_map < 0) {
520 ret = srtc->hw_cal_map;
521 goto err_disable_cal_clk;
527 clk_disable_unprepare(srtc->cal_clk);
532 static int sft_rtc_get_irq(struct platform_device *pdev, struct sft_rtc *srtc)
536 srtc->rtc_irq = platform_get_irq_byname(pdev, "rtc");
537 if (srtc->rtc_irq < 0)
540 ret = devm_request_irq(&pdev->dev, srtc->rtc_irq,
541 sft_rtc_irq_handler, 0,
542 KBUILD_MODNAME, srtc);
544 dev_err(&pdev->dev, "Failed to request interrupt, %d\n", ret);
549 static const struct rtc_class_ops starfive_rtc_ops = {
550 .read_time = sft_rtc_read_time,
551 .set_time = sft_rtc_set_time,
552 .read_alarm = sft_rtc_read_alarm,
553 .set_alarm = sft_rtc_set_alarm,
554 .alarm_irq_enable = sft_rtc_alarm_irq_enable,
555 .set_offset = sft_rtc_set_offset,
556 .read_offset = sft_rtc_get_offset,
559 static int sft_rtc_probe(struct platform_device *pdev)
561 struct device *dev = &pdev->dev;
562 struct sft_rtc *srtc;
566 srtc = devm_kzalloc(dev, sizeof(*srtc), GFP_KERNEL);
570 srtc->regs = devm_platform_ioremap_resource(pdev, 0);
571 if (IS_ERR(srtc->regs))
572 return PTR_ERR(srtc->regs);
574 srtc->pclk = devm_clk_get(dev, "pclk");
575 if (IS_ERR(srtc->pclk)) {
576 ret = PTR_ERR(srtc->pclk);
578 "Failed to retrieve the peripheral clock, %d\n", ret);
582 srtc->rst_apb = devm_reset_control_get_exclusive(dev, "rst_apb");
583 if (IS_ERR(srtc->rst_apb)) {
584 ret = PTR_ERR(srtc->rst_apb);
586 "Failed to retrieve the rtc apb reset, %d\n", ret);
590 srtc->rst_cal = devm_reset_control_get_exclusive(dev, "rst_cal");
591 if (IS_ERR(srtc->rst_cal)) {
592 ret = PTR_ERR(srtc->rst_cal);
594 "Failed to retrieve the rtc cal reset, %d\n", ret);
598 srtc->rst_osc = devm_reset_control_get_exclusive(dev, "rst_osc");
599 if (IS_ERR(srtc->rst_osc)) {
600 ret = PTR_ERR(srtc->rst_osc);
602 "Failed to retrieve the rtc osc reset, %d\n", ret);
606 init_completion(&srtc->cal_done);
607 init_completion(&srtc->onesec_done);
609 ret = clk_prepare_enable(srtc->pclk);
612 "Failed to enable the peripheral clock, %d\n", ret);
616 ret = sft_rtc_get_cal_clk(dev, srtc);
618 goto err_disable_pclk;
620 reset_control_deassert(srtc->rst_osc);
621 reset_control_deassert(srtc->rst_apb);
622 reset_control_deassert(srtc->rst_cal);
624 ret = sft_rtc_get_irq(pdev, srtc);
626 goto err_disable_cal_clk;
628 srtc->rtc_dev = devm_rtc_allocate_device(dev);
629 if (IS_ERR(srtc->rtc_dev))
630 return PTR_ERR(srtc->rtc_dev);
632 platform_set_drvdata(pdev, srtc);
634 /* The RTC supports 01.01.2001 - 31.12.2099 */
635 srtc->rtc_dev->range_min = mktime64(2001, 1, 1, 0, 0, 0);
636 srtc->rtc_dev->range_max = mktime64(2099, 12, 31, 23, 59, 59);
638 srtc->rtc_dev->ops = &starfive_rtc_ops;
639 device_init_wakeup(dev, true);
641 /* Always use 24-hour mode and keep the RTC values */
642 sft_rtc_set_mode(srtc, RTC_HOUR_MODE_24H);
644 sft_rtc_set_enabled(srtc, true);
646 if (device_property_read_bool(dev, "rtc,hw-adjustment"))
647 sft_rtc_hw_adjustment(dev, true);
650 * If rtc time is out of supported range, reset it to the minimum time.
651 * notice that, actual year = 1900 + tm.tm_year
652 * actual month = 1 + tm.tm_mon
654 sft_rtc_read_time(dev, &tm);
655 if (tm.tm_year < 101 || tm.tm_year > 199 || tm.tm_mon < 0 || tm.tm_mon > 11 ||
656 tm.tm_mday < 1 || tm.tm_mday > 31 || tm.tm_hour < 0 || tm.tm_hour > 23 ||
657 tm.tm_min < 0 || tm.tm_min > 59 || tm.tm_sec < 0 || tm.tm_sec > 59) {
658 rtc_time64_to_tm(srtc->rtc_dev->range_min, &tm);
659 sft_rtc_set_time(dev, &tm);
662 ret = devm_rtc_register_device(srtc->rtc_dev);
664 goto err_disable_wakeup;
669 device_init_wakeup(dev, false);
672 clk_disable_unprepare(srtc->cal_clk);
675 clk_disable_unprepare(srtc->pclk);
680 static int sft_rtc_remove(struct platform_device *pdev)
682 struct sft_rtc *srtc = platform_get_drvdata(pdev);
684 sft_rtc_alarm_irq_enable(&pdev->dev, 0);
685 device_init_wakeup(&pdev->dev, 0);
687 clk_disable_unprepare(srtc->pclk);
688 clk_disable_unprepare(srtc->cal_clk);
693 #ifdef CONFIG_PM_SLEEP
694 static int sft_rtc_suspend(struct device *dev)
696 struct sft_rtc *srtc = dev_get_drvdata(dev);
698 if (device_may_wakeup(dev))
699 enable_irq_wake(srtc->rtc_irq);
704 static int sft_rtc_resume(struct device *dev)
706 struct sft_rtc *srtc = dev_get_drvdata(dev);
708 if (device_may_wakeup(dev))
709 disable_irq_wake(srtc->rtc_irq);
715 static SIMPLE_DEV_PM_OPS(sft_rtc_pm_ops, sft_rtc_suspend, sft_rtc_resume);
717 static const struct of_device_id sft_rtc_of_match[] = {
718 { .compatible = "starfive,rtc_hms" },
721 MODULE_DEVICE_TABLE(of, sft_rtc_of_match);
723 static struct platform_driver starfive_rtc_driver = {
725 .name = "starfive-rtc",
726 .of_match_table = sft_rtc_of_match,
727 .pm = &sft_rtc_pm_ops,
729 .probe = sft_rtc_probe,
730 .remove = sft_rtc_remove,
732 module_platform_driver(starfive_rtc_driver);
734 MODULE_AUTHOR("Samin Guo <samin.guo@starfivetech.com>");
735 MODULE_AUTHOR("Hal Feng <hal.feng@starfivetech.com>");
736 MODULE_DESCRIPTION("StarFive RTC driver");
737 MODULE_LICENSE("GPL v2");
738 MODULE_ALIAS("platform:starfive-rtc");