1 // SPDX-License-Identifier: GPL-2.0
3 * RTC driver for the Micro Crystal RV3032
5 * Copyright (C) 2020 Micro Crystal SA
7 * Alexandre Belloni <alexandre.belloni@bootlin.com>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/bcd.h>
14 #include <linux/bitfield.h>
15 #include <linux/bitops.h>
16 #include <linux/hwmon.h>
17 #include <linux/i2c.h>
18 #include <linux/interrupt.h>
19 #include <linux/kernel.h>
20 #include <linux/log2.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/regmap.h>
24 #include <linux/rtc.h>
26 #define RV3032_SEC 0x01
27 #define RV3032_MIN 0x02
28 #define RV3032_HOUR 0x03
29 #define RV3032_WDAY 0x04
30 #define RV3032_DAY 0x05
31 #define RV3032_MONTH 0x06
32 #define RV3032_YEAR 0x07
33 #define RV3032_ALARM_MIN 0x08
34 #define RV3032_ALARM_HOUR 0x09
35 #define RV3032_ALARM_DAY 0x0A
36 #define RV3032_STATUS 0x0D
37 #define RV3032_TLSB 0x0E
38 #define RV3032_TMSB 0x0F
39 #define RV3032_CTRL1 0x10
40 #define RV3032_CTRL2 0x11
41 #define RV3032_CTRL3 0x12
42 #define RV3032_TS_CTRL 0x13
43 #define RV3032_CLK_IRQ 0x14
44 #define RV3032_EEPROM_ADDR 0x3D
45 #define RV3032_EEPROM_DATA 0x3E
46 #define RV3032_EEPROM_CMD 0x3F
47 #define RV3032_RAM1 0x40
48 #define RV3032_PMU 0xC0
49 #define RV3032_OFFSET 0xC1
50 #define RV3032_CLKOUT1 0xC2
51 #define RV3032_CLKOUT2 0xC3
52 #define RV3032_TREF0 0xC4
53 #define RV3032_TREF1 0xC5
55 #define RV3032_STATUS_VLF BIT(0)
56 #define RV3032_STATUS_PORF BIT(1)
57 #define RV3032_STATUS_EVF BIT(2)
58 #define RV3032_STATUS_AF BIT(3)
59 #define RV3032_STATUS_TF BIT(4)
60 #define RV3032_STATUS_UF BIT(5)
61 #define RV3032_STATUS_TLF BIT(6)
62 #define RV3032_STATUS_THF BIT(7)
64 #define RV3032_TLSB_CLKF BIT(1)
65 #define RV3032_TLSB_EEBUSY BIT(2)
66 #define RV3032_TLSB_TEMP GENMASK(7, 4)
68 #define RV3032_CLKOUT2_HFD_MSK GENMASK(4, 0)
69 #define RV3032_CLKOUT2_FD_MSK GENMASK(6, 5)
70 #define RV3032_CLKOUT2_OS BIT(7)
72 #define RV3032_CTRL1_EERD BIT(3)
73 #define RV3032_CTRL1_WADA BIT(5)
75 #define RV3032_CTRL2_STOP BIT(0)
76 #define RV3032_CTRL2_EIE BIT(2)
77 #define RV3032_CTRL2_AIE BIT(3)
78 #define RV3032_CTRL2_TIE BIT(4)
79 #define RV3032_CTRL2_UIE BIT(5)
80 #define RV3032_CTRL2_CLKIE BIT(6)
81 #define RV3032_CTRL2_TSE BIT(7)
83 #define RV3032_PMU_TCM GENMASK(1, 0)
84 #define RV3032_PMU_TCR GENMASK(3, 2)
85 #define RV3032_PMU_BSM GENMASK(5, 4)
86 #define RV3032_PMU_NCLKE BIT(6)
88 #define RV3032_PMU_BSM_DSM 1
89 #define RV3032_PMU_BSM_LSM 2
91 #define RV3032_OFFSET_MSK GENMASK(5, 0)
93 #define RV3032_EVT_CTRL_TSR BIT(2)
95 #define RV3032_EEPROM_CMD_UPDATE 0x11
96 #define RV3032_EEPROM_CMD_WRITE 0x21
97 #define RV3032_EEPROM_CMD_READ 0x22
99 #define RV3032_EEPROM_USER 0xCB
101 #define RV3032_EEBUSY_POLL 10000
102 #define RV3032_EEBUSY_TIMEOUT 100000
104 #define OFFSET_STEP_PPT 238419
107 struct regmap *regmap;
108 struct rtc_device *rtc;
109 #ifdef CONFIG_COMMON_CLK
110 struct clk_hw clkout_hw;
114 static u16 rv3032_trickle_resistors[] = {1000, 2000, 7000, 11000};
115 static u16 rv3032_trickle_voltages[] = {0, 1750, 3000, 4400};
117 static int rv3032_exit_eerd(struct rv3032_data *rv3032, u32 eerd)
122 return regmap_update_bits(rv3032->regmap, RV3032_CTRL1, RV3032_CTRL1_EERD, 0);
125 static int rv3032_enter_eerd(struct rv3032_data *rv3032, u32 *eerd)
130 ret = regmap_read(rv3032->regmap, RV3032_CTRL1, &ctrl1);
134 *eerd = ctrl1 & RV3032_CTRL1_EERD;
138 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL1,
139 RV3032_CTRL1_EERD, RV3032_CTRL1_EERD);
143 ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
144 !(status & RV3032_TLSB_EEBUSY),
145 RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
147 rv3032_exit_eerd(rv3032, *eerd);
155 static int rv3032_update_cfg(struct rv3032_data *rv3032, unsigned int reg,
156 unsigned int mask, unsigned int val)
161 ret = rv3032_enter_eerd(rv3032, &eerd);
165 ret = regmap_update_bits(rv3032->regmap, reg, mask, val);
169 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, RV3032_EEPROM_CMD_UPDATE);
173 usleep_range(46000, RV3032_EEBUSY_TIMEOUT);
175 ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
176 !(status & RV3032_TLSB_EEBUSY),
177 RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
180 rv3032_exit_eerd(rv3032, eerd);
185 static irqreturn_t rv3032_handle_irq(int irq, void *dev_id)
187 struct rv3032_data *rv3032 = dev_id;
188 unsigned long events = 0;
189 u32 status = 0, ctrl = 0;
191 if (regmap_read(rv3032->regmap, RV3032_STATUS, &status) < 0 ||
196 if (status & RV3032_STATUS_TF) {
197 status |= RV3032_STATUS_TF;
198 ctrl |= RV3032_CTRL2_TIE;
202 if (status & RV3032_STATUS_AF) {
203 status |= RV3032_STATUS_AF;
204 ctrl |= RV3032_CTRL2_AIE;
208 if (status & RV3032_STATUS_UF) {
209 status |= RV3032_STATUS_UF;
210 ctrl |= RV3032_CTRL2_UIE;
215 rtc_update_irq(rv3032->rtc, 1, events);
216 regmap_update_bits(rv3032->regmap, RV3032_STATUS, status, 0);
217 regmap_update_bits(rv3032->regmap, RV3032_CTRL2, ctrl, 0);
223 static int rv3032_get_time(struct device *dev, struct rtc_time *tm)
225 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
229 ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
233 if (status & (RV3032_STATUS_PORF | RV3032_STATUS_VLF))
236 ret = regmap_bulk_read(rv3032->regmap, RV3032_SEC, date, sizeof(date));
240 tm->tm_sec = bcd2bin(date[0] & 0x7f);
241 tm->tm_min = bcd2bin(date[1] & 0x7f);
242 tm->tm_hour = bcd2bin(date[2] & 0x3f);
243 tm->tm_wday = date[3] & 0x7;
244 tm->tm_mday = bcd2bin(date[4] & 0x3f);
245 tm->tm_mon = bcd2bin(date[5] & 0x1f) - 1;
246 tm->tm_year = bcd2bin(date[6]) + 100;
251 static int rv3032_set_time(struct device *dev, struct rtc_time *tm)
253 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
257 date[0] = bin2bcd(tm->tm_sec);
258 date[1] = bin2bcd(tm->tm_min);
259 date[2] = bin2bcd(tm->tm_hour);
260 date[3] = tm->tm_wday;
261 date[4] = bin2bcd(tm->tm_mday);
262 date[5] = bin2bcd(tm->tm_mon + 1);
263 date[6] = bin2bcd(tm->tm_year - 100);
265 ret = regmap_bulk_write(rv3032->regmap, RV3032_SEC, date,
270 ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
271 RV3032_STATUS_PORF | RV3032_STATUS_VLF, 0);
276 static int rv3032_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
278 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
280 int status, ctrl, ret;
282 ret = regmap_bulk_read(rv3032->regmap, RV3032_ALARM_MIN, alarmvals,
287 ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
291 ret = regmap_read(rv3032->regmap, RV3032_CTRL2, &ctrl);
295 alrm->time.tm_sec = 0;
296 alrm->time.tm_min = bcd2bin(alarmvals[0] & 0x7f);
297 alrm->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f);
298 alrm->time.tm_mday = bcd2bin(alarmvals[2] & 0x3f);
300 alrm->enabled = !!(ctrl & RV3032_CTRL2_AIE);
301 alrm->pending = (status & RV3032_STATUS_AF) && alrm->enabled;
306 static int rv3032_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
308 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
313 /* The alarm has no seconds, round up to nearest minute */
314 if (alrm->time.tm_sec) {
315 time64_t alarm_time = rtc_tm_to_time64(&alrm->time);
317 alarm_time += 60 - alrm->time.tm_sec;
318 rtc_time64_to_tm(alarm_time, &alrm->time);
321 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
322 RV3032_CTRL2_AIE | RV3032_CTRL2_UIE, 0);
326 alarmvals[0] = bin2bcd(alrm->time.tm_min);
327 alarmvals[1] = bin2bcd(alrm->time.tm_hour);
328 alarmvals[2] = bin2bcd(alrm->time.tm_mday);
330 ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
331 RV3032_STATUS_AF, 0);
335 ret = regmap_bulk_write(rv3032->regmap, RV3032_ALARM_MIN, alarmvals,
341 if (rv3032->rtc->uie_rtctimer.enabled)
342 ctrl |= RV3032_CTRL2_UIE;
343 if (rv3032->rtc->aie_timer.enabled)
344 ctrl |= RV3032_CTRL2_AIE;
347 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
348 RV3032_CTRL2_UIE | RV3032_CTRL2_AIE, ctrl);
353 static int rv3032_alarm_irq_enable(struct device *dev, unsigned int enabled)
355 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
359 if (rv3032->rtc->uie_rtctimer.enabled)
360 ctrl |= RV3032_CTRL2_UIE;
361 if (rv3032->rtc->aie_timer.enabled)
362 ctrl |= RV3032_CTRL2_AIE;
365 ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
366 RV3032_STATUS_AF | RV3032_STATUS_UF, 0);
370 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
371 RV3032_CTRL2_UIE | RV3032_CTRL2_AIE, ctrl);
378 static int rv3032_read_offset(struct device *dev, long *offset)
380 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
381 int ret, value, steps;
383 ret = regmap_read(rv3032->regmap, RV3032_OFFSET, &value);
387 steps = sign_extend32(FIELD_GET(RV3032_OFFSET_MSK, value), 5);
389 *offset = DIV_ROUND_CLOSEST(steps * OFFSET_STEP_PPT, 1000);
394 static int rv3032_set_offset(struct device *dev, long offset)
396 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
398 offset = clamp(offset, -7629L, 7391L) * 1000;
399 offset = DIV_ROUND_CLOSEST(offset, OFFSET_STEP_PPT);
401 return rv3032_update_cfg(rv3032, RV3032_OFFSET, RV3032_OFFSET_MSK,
402 FIELD_PREP(RV3032_OFFSET_MSK, offset));
405 static int rv3032_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
407 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
408 int status, val = 0, ret = 0;
412 ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
416 if (status & (RV3032_STATUS_PORF | RV3032_STATUS_VLF))
417 val = RTC_VL_DATA_INVALID;
418 return put_user(val, (unsigned int __user *)arg);
425 static int rv3032_nvram_write(void *priv, unsigned int offset, void *val, size_t bytes)
427 return regmap_bulk_write(priv, RV3032_RAM1 + offset, val, bytes);
430 static int rv3032_nvram_read(void *priv, unsigned int offset, void *val, size_t bytes)
432 return regmap_bulk_read(priv, RV3032_RAM1 + offset, val, bytes);
435 static int rv3032_eeprom_write(void *priv, unsigned int offset, void *val, size_t bytes)
437 struct rv3032_data *rv3032 = priv;
442 ret = rv3032_enter_eerd(rv3032, &eerd);
446 for (i = 0; i < bytes; i++) {
447 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_ADDR,
448 RV3032_EEPROM_USER + offset + i);
452 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_DATA, buf[i]);
456 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD,
457 RV3032_EEPROM_CMD_WRITE);
461 usleep_range(RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
463 ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
464 !(status & RV3032_TLSB_EEBUSY),
465 RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
471 rv3032_exit_eerd(rv3032, eerd);
476 static int rv3032_eeprom_read(void *priv, unsigned int offset, void *val, size_t bytes)
478 struct rv3032_data *rv3032 = priv;
479 u32 status, eerd, data;
483 ret = rv3032_enter_eerd(rv3032, &eerd);
487 for (i = 0; i < bytes; i++) {
488 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_ADDR,
489 RV3032_EEPROM_USER + offset + i);
493 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD,
494 RV3032_EEPROM_CMD_READ);
498 ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
499 !(status & RV3032_TLSB_EEBUSY),
500 RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
504 ret = regmap_read(rv3032->regmap, RV3032_EEPROM_DATA, &data);
511 rv3032_exit_eerd(rv3032, eerd);
516 static int rv3032_trickle_charger_setup(struct device *dev, struct rv3032_data *rv3032)
518 u32 val, ohms, voltage;
521 val = FIELD_PREP(RV3032_PMU_TCM, 1) | FIELD_PREP(RV3032_PMU_BSM, RV3032_PMU_BSM_DSM);
522 if (!device_property_read_u32(dev, "trickle-voltage-millivolt", &voltage)) {
523 for (i = 0; i < ARRAY_SIZE(rv3032_trickle_voltages); i++)
524 if (voltage == rv3032_trickle_voltages[i])
526 if (i < ARRAY_SIZE(rv3032_trickle_voltages))
527 val = FIELD_PREP(RV3032_PMU_TCM, i) |
528 FIELD_PREP(RV3032_PMU_BSM, RV3032_PMU_BSM_LSM);
531 if (device_property_read_u32(dev, "trickle-resistor-ohms", &ohms))
534 for (i = 0; i < ARRAY_SIZE(rv3032_trickle_resistors); i++)
535 if (ohms == rv3032_trickle_resistors[i])
538 if (i >= ARRAY_SIZE(rv3032_trickle_resistors)) {
539 dev_warn(dev, "invalid trickle resistor value\n");
544 return rv3032_update_cfg(rv3032, RV3032_PMU,
545 RV3032_PMU_TCR | RV3032_PMU_TCM | RV3032_PMU_BSM,
546 val | FIELD_PREP(RV3032_PMU_TCR, i));
549 #ifdef CONFIG_COMMON_CLK
550 #define clkout_hw_to_rv3032(hw) container_of(hw, struct rv3032_data, clkout_hw)
552 static int clkout_xtal_rates[] = {
559 #define RV3032_HFD_STEP 8192
561 static unsigned long rv3032_clkout_recalc_rate(struct clk_hw *hw,
562 unsigned long parent_rate)
565 struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
567 ret = regmap_read(rv3032->regmap, RV3032_CLKOUT2, &clkout);
571 if (clkout & RV3032_CLKOUT2_OS) {
572 unsigned long rate = FIELD_GET(RV3032_CLKOUT2_HFD_MSK, clkout) << 8;
574 ret = regmap_read(rv3032->regmap, RV3032_CLKOUT1, &clkout);
580 return rate * RV3032_HFD_STEP;
583 return clkout_xtal_rates[FIELD_GET(RV3032_CLKOUT2_FD_MSK, clkout)];
586 static long rv3032_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
587 unsigned long *prate)
591 if (rate < RV3032_HFD_STEP)
592 for (i = 0; i < ARRAY_SIZE(clkout_xtal_rates); i++)
593 if (clkout_xtal_rates[i] <= rate)
594 return clkout_xtal_rates[i];
596 hfd = DIV_ROUND_CLOSEST(rate, RV3032_HFD_STEP);
598 return RV3032_HFD_STEP * clamp(hfd, 0, 8192);
601 static int rv3032_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
602 unsigned long parent_rate)
604 struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
608 for (i = 0; i < ARRAY_SIZE(clkout_xtal_rates); i++) {
609 if (clkout_xtal_rates[i] == rate) {
610 return rv3032_update_cfg(rv3032, RV3032_CLKOUT2, 0xff,
611 FIELD_PREP(RV3032_CLKOUT2_FD_MSK, i));
615 hfd = DIV_ROUND_CLOSEST(rate, RV3032_HFD_STEP);
616 hfd = clamp(hfd, 1, 8192) - 1;
618 ret = rv3032_enter_eerd(rv3032, &eerd);
622 ret = regmap_write(rv3032->regmap, RV3032_CLKOUT1, hfd & 0xff);
626 ret = regmap_write(rv3032->regmap, RV3032_CLKOUT2, RV3032_CLKOUT2_OS |
627 FIELD_PREP(RV3032_CLKOUT2_HFD_MSK, hfd >> 8));
631 ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, RV3032_EEPROM_CMD_UPDATE);
635 usleep_range(46000, RV3032_EEBUSY_TIMEOUT);
637 ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
638 !(status & RV3032_TLSB_EEBUSY),
639 RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
642 rv3032_exit_eerd(rv3032, eerd);
647 static int rv3032_clkout_prepare(struct clk_hw *hw)
649 struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
651 return rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_NCLKE, 0);
654 static void rv3032_clkout_unprepare(struct clk_hw *hw)
656 struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
658 rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_NCLKE, RV3032_PMU_NCLKE);
661 static int rv3032_clkout_is_prepared(struct clk_hw *hw)
664 struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
666 ret = regmap_read(rv3032->regmap, RV3032_PMU, &val);
670 return !(val & RV3032_PMU_NCLKE);
673 static const struct clk_ops rv3032_clkout_ops = {
674 .prepare = rv3032_clkout_prepare,
675 .unprepare = rv3032_clkout_unprepare,
676 .is_prepared = rv3032_clkout_is_prepared,
677 .recalc_rate = rv3032_clkout_recalc_rate,
678 .round_rate = rv3032_clkout_round_rate,
679 .set_rate = rv3032_clkout_set_rate,
682 static int rv3032_clkout_register_clk(struct rv3032_data *rv3032,
683 struct i2c_client *client)
687 struct clk_init_data init;
688 struct device_node *node = client->dev.of_node;
690 ret = regmap_update_bits(rv3032->regmap, RV3032_TLSB, RV3032_TLSB_CLKF, 0);
694 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2, RV3032_CTRL2_CLKIE, 0);
698 ret = regmap_write(rv3032->regmap, RV3032_CLK_IRQ, 0);
702 init.name = "rv3032-clkout";
703 init.ops = &rv3032_clkout_ops;
705 init.parent_names = NULL;
706 init.num_parents = 0;
707 rv3032->clkout_hw.init = &init;
709 of_property_read_string(node, "clock-output-names", &init.name);
711 clk = devm_clk_register(&client->dev, &rv3032->clkout_hw);
713 of_clk_add_provider(node, of_clk_src_simple_get, clk);
719 static int rv3032_hwmon_read_temp(struct device *dev, long *mC)
721 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
726 ret = regmap_bulk_read(rv3032->regmap, RV3032_TLSB, buf, sizeof(buf));
730 temp = sign_extend32(buf[1], 7) << 4;
731 temp |= FIELD_GET(RV3032_TLSB_TEMP, buf[0]);
733 /* No blocking or shadowing on RV3032_TLSB and RV3032_TMSB */
737 ret = regmap_bulk_read(rv3032->regmap, RV3032_TLSB, buf, sizeof(buf));
741 temp = sign_extend32(buf[1], 7) << 4;
742 temp |= FIELD_GET(RV3032_TLSB_TEMP, buf[0]);
743 } while (temp != prev);
745 *mC = (temp * 1000) / 16;
750 static umode_t rv3032_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
751 u32 attr, int channel)
753 if (type != hwmon_temp)
757 case hwmon_temp_input:
764 static int rv3032_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
765 u32 attr, int channel, long *temp)
770 case hwmon_temp_input:
771 err = rv3032_hwmon_read_temp(dev, temp);
781 static const struct hwmon_channel_info *rv3032_hwmon_info[] = {
782 HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
783 HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST),
787 static const struct hwmon_ops rv3032_hwmon_hwmon_ops = {
788 .is_visible = rv3032_hwmon_is_visible,
789 .read = rv3032_hwmon_read,
792 static const struct hwmon_chip_info rv3032_hwmon_chip_info = {
793 .ops = &rv3032_hwmon_hwmon_ops,
794 .info = rv3032_hwmon_info,
797 static void rv3032_hwmon_register(struct device *dev)
799 struct rv3032_data *rv3032 = dev_get_drvdata(dev);
801 if (!IS_REACHABLE(CONFIG_HWMON))
804 devm_hwmon_device_register_with_info(dev, "rv3032", rv3032, &rv3032_hwmon_chip_info, NULL);
807 static const struct rtc_class_ops rv3032_rtc_ops = {
808 .read_time = rv3032_get_time,
809 .set_time = rv3032_set_time,
810 .read_offset = rv3032_read_offset,
811 .set_offset = rv3032_set_offset,
812 .ioctl = rv3032_ioctl,
813 .read_alarm = rv3032_get_alarm,
814 .set_alarm = rv3032_set_alarm,
815 .alarm_irq_enable = rv3032_alarm_irq_enable,
818 static const struct regmap_config regmap_config = {
821 .max_register = 0xCA,
824 static int rv3032_probe(struct i2c_client *client)
826 struct rv3032_data *rv3032;
828 struct nvmem_config nvmem_cfg = {
829 .name = "rv3032_nvram",
833 .type = NVMEM_TYPE_BATTERY_BACKED,
834 .reg_read = rv3032_nvram_read,
835 .reg_write = rv3032_nvram_write,
837 struct nvmem_config eeprom_cfg = {
838 .name = "rv3032_eeprom",
842 .type = NVMEM_TYPE_EEPROM,
843 .reg_read = rv3032_eeprom_read,
844 .reg_write = rv3032_eeprom_write,
847 rv3032 = devm_kzalloc(&client->dev, sizeof(struct rv3032_data),
852 rv3032->regmap = devm_regmap_init_i2c(client, ®map_config);
853 if (IS_ERR(rv3032->regmap))
854 return PTR_ERR(rv3032->regmap);
856 i2c_set_clientdata(client, rv3032);
858 ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
862 rv3032->rtc = devm_rtc_allocate_device(&client->dev);
863 if (IS_ERR(rv3032->rtc))
864 return PTR_ERR(rv3032->rtc);
866 if (client->irq > 0) {
867 ret = devm_request_threaded_irq(&client->dev, client->irq,
868 NULL, rv3032_handle_irq,
869 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
872 dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
877 clear_bit(RTC_FEATURE_ALARM, rv3032->rtc->features);
879 ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL1,
880 RV3032_CTRL1_WADA, RV3032_CTRL1_WADA);
884 rv3032_trickle_charger_setup(&client->dev, rv3032);
886 rv3032->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
887 rv3032->rtc->range_max = RTC_TIMESTAMP_END_2099;
888 rv3032->rtc->ops = &rv3032_rtc_ops;
889 ret = devm_rtc_register_device(rv3032->rtc);
893 nvmem_cfg.priv = rv3032->regmap;
894 devm_rtc_nvmem_register(rv3032->rtc, &nvmem_cfg);
895 eeprom_cfg.priv = rv3032;
896 devm_rtc_nvmem_register(rv3032->rtc, &eeprom_cfg);
898 rv3032->rtc->max_user_freq = 1;
900 #ifdef CONFIG_COMMON_CLK
901 rv3032_clkout_register_clk(rv3032, client);
904 rv3032_hwmon_register(&client->dev);
909 static const __maybe_unused struct of_device_id rv3032_of_match[] = {
910 { .compatible = "microcrystal,rv3032", },
913 MODULE_DEVICE_TABLE(of, rv3032_of_match);
915 static struct i2c_driver rv3032_driver = {
917 .name = "rtc-rv3032",
918 .of_match_table = of_match_ptr(rv3032_of_match),
920 .probe_new = rv3032_probe,
922 module_i2c_driver(rv3032_driver);
924 MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
925 MODULE_DESCRIPTION("Micro Crystal RV3032 RTC driver");
926 MODULE_LICENSE("GPL v2");