2 * DaVinci Power Management and Real Time Clock Driver for TI platforms
4 * Copyright (C) 2009 Texas Instruments, Inc
6 * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/delay.h>
27 #include <linux/spinlock.h>
28 #include <linux/rtc.h>
29 #include <linux/bcd.h>
30 #include <linux/platform_device.h>
32 #include <linux/slab.h>
35 * The DaVinci RTC is a simple RTC with the following
36 * Sec: 0 - 59 : BCD count
37 * Min: 0 - 59 : BCD count
38 * Hour: 0 - 23 : BCD count
39 * Day: 0 - 0x7FFF(32767) : Binary count ( Over 89 years )
42 /* PRTC interface registers */
43 #define DAVINCI_PRTCIF_PID 0x00
44 #define PRTCIF_CTLR 0x04
45 #define PRTCIF_LDATA 0x08
46 #define PRTCIF_UDATA 0x0C
47 #define PRTCIF_INTEN 0x10
48 #define PRTCIF_INTFLG 0x14
50 /* PRTCIF_CTLR bit fields */
51 #define PRTCIF_CTLR_BUSY BIT(31)
52 #define PRTCIF_CTLR_SIZE BIT(25)
53 #define PRTCIF_CTLR_DIR BIT(24)
54 #define PRTCIF_CTLR_BENU_MSB BIT(23)
55 #define PRTCIF_CTLR_BENU_3RD_BYTE BIT(22)
56 #define PRTCIF_CTLR_BENU_2ND_BYTE BIT(21)
57 #define PRTCIF_CTLR_BENU_LSB BIT(20)
58 #define PRTCIF_CTLR_BENU_MASK (0x00F00000)
59 #define PRTCIF_CTLR_BENL_MSB BIT(19)
60 #define PRTCIF_CTLR_BENL_3RD_BYTE BIT(18)
61 #define PRTCIF_CTLR_BENL_2ND_BYTE BIT(17)
62 #define PRTCIF_CTLR_BENL_LSB BIT(16)
63 #define PRTCIF_CTLR_BENL_MASK (0x000F0000)
65 /* PRTCIF_INTEN bit fields */
66 #define PRTCIF_INTEN_RTCSS BIT(1)
67 #define PRTCIF_INTEN_RTCIF BIT(0)
68 #define PRTCIF_INTEN_MASK (PRTCIF_INTEN_RTCSS \
71 /* PRTCIF_INTFLG bit fields */
72 #define PRTCIF_INTFLG_RTCSS BIT(1)
73 #define PRTCIF_INTFLG_RTCIF BIT(0)
74 #define PRTCIF_INTFLG_MASK (PRTCIF_INTFLG_RTCSS \
75 | PRTCIF_INTFLG_RTCIF)
77 /* PRTC subsystem registers */
78 #define PRTCSS_RTC_INTC_EXTENA1 (0x0C)
79 #define PRTCSS_RTC_CTRL (0x10)
80 #define PRTCSS_RTC_WDT (0x11)
81 #define PRTCSS_RTC_TMR0 (0x12)
82 #define PRTCSS_RTC_TMR1 (0x13)
83 #define PRTCSS_RTC_CCTRL (0x14)
84 #define PRTCSS_RTC_SEC (0x15)
85 #define PRTCSS_RTC_MIN (0x16)
86 #define PRTCSS_RTC_HOUR (0x17)
87 #define PRTCSS_RTC_DAY0 (0x18)
88 #define PRTCSS_RTC_DAY1 (0x19)
89 #define PRTCSS_RTC_AMIN (0x1A)
90 #define PRTCSS_RTC_AHOUR (0x1B)
91 #define PRTCSS_RTC_ADAY0 (0x1C)
92 #define PRTCSS_RTC_ADAY1 (0x1D)
93 #define PRTCSS_RTC_CLKC_CNT (0x20)
95 /* PRTCSS_RTC_INTC_EXTENA1 */
96 #define PRTCSS_RTC_INTC_EXTENA1_MASK (0x07)
98 /* PRTCSS_RTC_CTRL bit fields */
99 #define PRTCSS_RTC_CTRL_WDTBUS BIT(7)
100 #define PRTCSS_RTC_CTRL_WEN BIT(6)
101 #define PRTCSS_RTC_CTRL_WDRT BIT(5)
102 #define PRTCSS_RTC_CTRL_WDTFLG BIT(4)
103 #define PRTCSS_RTC_CTRL_TE BIT(3)
104 #define PRTCSS_RTC_CTRL_TIEN BIT(2)
105 #define PRTCSS_RTC_CTRL_TMRFLG BIT(1)
106 #define PRTCSS_RTC_CTRL_TMMD BIT(0)
108 /* PRTCSS_RTC_CCTRL bit fields */
109 #define PRTCSS_RTC_CCTRL_CALBUSY BIT(7)
110 #define PRTCSS_RTC_CCTRL_DAEN BIT(5)
111 #define PRTCSS_RTC_CCTRL_HAEN BIT(4)
112 #define PRTCSS_RTC_CCTRL_MAEN BIT(3)
113 #define PRTCSS_RTC_CCTRL_ALMFLG BIT(2)
114 #define PRTCSS_RTC_CCTRL_AIEN BIT(1)
115 #define PRTCSS_RTC_CCTRL_CAEN BIT(0)
117 static DEFINE_SPINLOCK(davinci_rtc_lock);
120 struct rtc_device *rtc;
122 resource_size_t pbase;
127 static inline void rtcif_write(struct davinci_rtc *davinci_rtc,
130 writel(val, davinci_rtc->base + addr);
133 static inline u32 rtcif_read(struct davinci_rtc *davinci_rtc, u32 addr)
135 return readl(davinci_rtc->base + addr);
138 static inline void rtcif_wait(struct davinci_rtc *davinci_rtc)
140 while (rtcif_read(davinci_rtc, PRTCIF_CTLR) & PRTCIF_CTLR_BUSY)
144 static inline void rtcss_write(struct davinci_rtc *davinci_rtc,
145 unsigned long val, u8 addr)
147 rtcif_wait(davinci_rtc);
149 rtcif_write(davinci_rtc, PRTCIF_CTLR_BENL_LSB | addr, PRTCIF_CTLR);
150 rtcif_write(davinci_rtc, val, PRTCIF_LDATA);
152 rtcif_wait(davinci_rtc);
155 static inline u8 rtcss_read(struct davinci_rtc *davinci_rtc, u8 addr)
157 rtcif_wait(davinci_rtc);
159 rtcif_write(davinci_rtc, PRTCIF_CTLR_DIR | PRTCIF_CTLR_BENL_LSB | addr,
162 rtcif_wait(davinci_rtc);
164 return rtcif_read(davinci_rtc, PRTCIF_LDATA);
167 static inline void davinci_rtcss_calendar_wait(struct davinci_rtc *davinci_rtc)
169 while (rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
170 PRTCSS_RTC_CCTRL_CALBUSY)
174 static irqreturn_t davinci_rtc_interrupt(int irq, void *class_dev)
176 struct davinci_rtc *davinci_rtc = class_dev;
177 unsigned long events = 0;
180 u8 rtc_ctrl, rtc_cctrl;
183 irq_flg = rtcif_read(davinci_rtc, PRTCIF_INTFLG) &
186 alm_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL) &
187 PRTCSS_RTC_CCTRL_ALMFLG;
189 tmr_irq = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL) &
190 PRTCSS_RTC_CTRL_TMRFLG;
194 events |= RTC_IRQF | RTC_AF;
195 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
196 rtc_cctrl |= PRTCSS_RTC_CCTRL_ALMFLG;
197 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
198 } else if (tmr_irq) {
199 events |= RTC_IRQF | RTC_PF;
200 rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
201 rtc_ctrl |= PRTCSS_RTC_CTRL_TMRFLG;
202 rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
205 rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS,
207 rtc_update_irq(davinci_rtc->rtc, 1, events);
216 davinci_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
218 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
223 spin_lock_irqsave(&davinci_rtc_lock, flags);
225 rtc_ctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CTRL);
229 rtc_ctrl |= PRTCSS_RTC_CTRL_WEN | PRTCSS_RTC_CTRL_WDTFLG;
232 rtc_ctrl &= ~PRTCSS_RTC_CTRL_WEN;
242 rtcss_write(davinci_rtc, rtc_ctrl, PRTCSS_RTC_CTRL);
244 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
249 static int convertfromdays(u16 days, struct rtc_time *tm)
251 int tmp_days, year, mon;
253 for (year = 2000;; year++) {
254 tmp_days = rtc_year_days(1, 12, year);
255 if (days >= tmp_days)
258 for (mon = 0;; mon++) {
259 tmp_days = rtc_month_days(mon, year);
260 if (days >= tmp_days) {
263 tm->tm_year = year - 1900;
265 tm->tm_mday = days + 1;
275 static int convert2days(u16 *days, struct rtc_time *tm)
281 if (tm->tm_year < 100 || tm->tm_year > 199)
284 for (i = 2000; i < 1900 + tm->tm_year; i++)
285 *days += rtc_year_days(1, 12, i);
287 *days += rtc_year_days(tm->tm_mday, tm->tm_mon, 1900 + tm->tm_year);
292 static int davinci_rtc_read_time(struct device *dev, struct rtc_time *tm)
294 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
299 spin_lock_irqsave(&davinci_rtc_lock, flags);
301 davinci_rtcss_calendar_wait(davinci_rtc);
302 tm->tm_sec = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_SEC));
304 davinci_rtcss_calendar_wait(davinci_rtc);
305 tm->tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_MIN));
307 davinci_rtcss_calendar_wait(davinci_rtc);
308 tm->tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_HOUR));
310 davinci_rtcss_calendar_wait(davinci_rtc);
311 day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY0);
313 davinci_rtcss_calendar_wait(davinci_rtc);
314 day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_DAY1);
316 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
322 if (convertfromdays(days, tm) < 0)
328 static int davinci_rtc_set_time(struct device *dev, struct rtc_time *tm)
330 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
335 if (convert2days(&days, tm) < 0)
338 spin_lock_irqsave(&davinci_rtc_lock, flags);
340 davinci_rtcss_calendar_wait(davinci_rtc);
341 rtcss_write(davinci_rtc, bin2bcd(tm->tm_sec), PRTCSS_RTC_SEC);
343 davinci_rtcss_calendar_wait(davinci_rtc);
344 rtcss_write(davinci_rtc, bin2bcd(tm->tm_min), PRTCSS_RTC_MIN);
346 davinci_rtcss_calendar_wait(davinci_rtc);
347 rtcss_write(davinci_rtc, bin2bcd(tm->tm_hour), PRTCSS_RTC_HOUR);
349 davinci_rtcss_calendar_wait(davinci_rtc);
350 rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_DAY0);
352 davinci_rtcss_calendar_wait(davinci_rtc);
353 rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_DAY1);
355 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
356 rtc_cctrl |= PRTCSS_RTC_CCTRL_CAEN;
357 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
359 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
364 static int davinci_rtc_alarm_irq_enable(struct device *dev,
365 unsigned int enabled)
367 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
369 u8 rtc_cctrl = rtcss_read(davinci_rtc, PRTCSS_RTC_CCTRL);
371 spin_lock_irqsave(&davinci_rtc_lock, flags);
374 rtc_cctrl |= PRTCSS_RTC_CCTRL_DAEN |
375 PRTCSS_RTC_CCTRL_HAEN |
376 PRTCSS_RTC_CCTRL_MAEN |
377 PRTCSS_RTC_CCTRL_ALMFLG |
378 PRTCSS_RTC_CCTRL_AIEN;
380 rtc_cctrl &= ~PRTCSS_RTC_CCTRL_AIEN;
382 davinci_rtcss_calendar_wait(davinci_rtc);
383 rtcss_write(davinci_rtc, rtc_cctrl, PRTCSS_RTC_CCTRL);
385 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
390 static int davinci_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
392 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
397 spin_lock_irqsave(&davinci_rtc_lock, flags);
399 davinci_rtcss_calendar_wait(davinci_rtc);
400 alm->time.tm_min = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AMIN));
402 davinci_rtcss_calendar_wait(davinci_rtc);
403 alm->time.tm_hour = bcd2bin(rtcss_read(davinci_rtc, PRTCSS_RTC_AHOUR));
405 davinci_rtcss_calendar_wait(davinci_rtc);
406 day0 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY0);
408 davinci_rtcss_calendar_wait(davinci_rtc);
409 day1 = rtcss_read(davinci_rtc, PRTCSS_RTC_ADAY1);
411 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
416 if (convertfromdays(days, &alm->time) < 0)
419 alm->pending = !!(rtcss_read(davinci_rtc,
421 PRTCSS_RTC_CCTRL_AIEN);
422 alm->enabled = alm->pending && device_may_wakeup(dev);
427 static int davinci_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
429 struct davinci_rtc *davinci_rtc = dev_get_drvdata(dev);
433 if (alm->time.tm_mday <= 0 && alm->time.tm_mon < 0
434 && alm->time.tm_year < 0) {
436 unsigned long now, then;
438 davinci_rtc_read_time(dev, &tm);
439 rtc_tm_to_time(&tm, &now);
441 alm->time.tm_mday = tm.tm_mday;
442 alm->time.tm_mon = tm.tm_mon;
443 alm->time.tm_year = tm.tm_year;
444 rtc_tm_to_time(&alm->time, &then);
447 rtc_time_to_tm(now + 24 * 60 * 60, &tm);
448 alm->time.tm_mday = tm.tm_mday;
449 alm->time.tm_mon = tm.tm_mon;
450 alm->time.tm_year = tm.tm_year;
454 if (convert2days(&days, &alm->time) < 0)
457 spin_lock_irqsave(&davinci_rtc_lock, flags);
459 davinci_rtcss_calendar_wait(davinci_rtc);
460 rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_min), PRTCSS_RTC_AMIN);
462 davinci_rtcss_calendar_wait(davinci_rtc);
463 rtcss_write(davinci_rtc, bin2bcd(alm->time.tm_hour), PRTCSS_RTC_AHOUR);
465 davinci_rtcss_calendar_wait(davinci_rtc);
466 rtcss_write(davinci_rtc, days & 0xFF, PRTCSS_RTC_ADAY0);
468 davinci_rtcss_calendar_wait(davinci_rtc);
469 rtcss_write(davinci_rtc, (days & 0xFF00) >> 8, PRTCSS_RTC_ADAY1);
471 spin_unlock_irqrestore(&davinci_rtc_lock, flags);
476 static struct rtc_class_ops davinci_rtc_ops = {
477 .ioctl = davinci_rtc_ioctl,
478 .read_time = davinci_rtc_read_time,
479 .set_time = davinci_rtc_set_time,
480 .alarm_irq_enable = davinci_rtc_alarm_irq_enable,
481 .read_alarm = davinci_rtc_read_alarm,
482 .set_alarm = davinci_rtc_set_alarm,
485 static int __init davinci_rtc_probe(struct platform_device *pdev)
487 struct device *dev = &pdev->dev;
488 struct davinci_rtc *davinci_rtc;
489 struct resource *res, *mem;
492 davinci_rtc = kzalloc(sizeof(struct davinci_rtc), GFP_KERNEL);
494 dev_dbg(dev, "could not allocate memory for private data\n");
498 davinci_rtc->irq = platform_get_irq(pdev, 0);
499 if (davinci_rtc->irq < 0) {
500 dev_err(dev, "no RTC irq\n");
501 ret = davinci_rtc->irq;
505 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
507 dev_err(dev, "no mem resource\n");
512 davinci_rtc->pbase = res->start;
513 davinci_rtc->base_size = resource_size(res);
515 mem = request_mem_region(davinci_rtc->pbase, davinci_rtc->base_size,
518 dev_err(dev, "RTC registers at %08x are not free\n",
524 davinci_rtc->base = ioremap(davinci_rtc->pbase, davinci_rtc->base_size);
525 if (!davinci_rtc->base) {
526 dev_err(dev, "unable to ioremap MEM resource\n");
531 davinci_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
532 &davinci_rtc_ops, THIS_MODULE);
533 if (IS_ERR(davinci_rtc->rtc)) {
534 dev_err(dev, "unable to register RTC device, err %ld\n",
535 PTR_ERR(davinci_rtc->rtc));
539 rtcif_write(davinci_rtc, PRTCIF_INTFLG_RTCSS, PRTCIF_INTFLG);
540 rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
541 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_INTC_EXTENA1);
543 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CTRL);
544 rtcss_write(davinci_rtc, 0, PRTCSS_RTC_CCTRL);
546 ret = request_irq(davinci_rtc->irq, davinci_rtc_interrupt,
547 IRQF_DISABLED, "davinci_rtc", davinci_rtc);
549 dev_err(dev, "unable to register davinci RTC interrupt\n");
553 /* Enable interrupts */
554 rtcif_write(davinci_rtc, PRTCIF_INTEN_RTCSS, PRTCIF_INTEN);
555 rtcss_write(davinci_rtc, PRTCSS_RTC_INTC_EXTENA1_MASK,
556 PRTCSS_RTC_INTC_EXTENA1);
558 rtcss_write(davinci_rtc, PRTCSS_RTC_CCTRL_CAEN, PRTCSS_RTC_CCTRL);
560 platform_set_drvdata(pdev, davinci_rtc);
562 device_init_wakeup(&pdev->dev, 0);
567 rtc_device_unregister(davinci_rtc->rtc);
569 iounmap(davinci_rtc->base);
571 release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
578 static int __devexit davinci_rtc_remove(struct platform_device *pdev)
580 struct davinci_rtc *davinci_rtc = platform_get_drvdata(pdev);
582 device_init_wakeup(&pdev->dev, 0);
584 rtcif_write(davinci_rtc, 0, PRTCIF_INTEN);
586 free_irq(davinci_rtc->irq, davinci_rtc);
588 rtc_device_unregister(davinci_rtc->rtc);
590 iounmap(davinci_rtc->base);
591 release_mem_region(davinci_rtc->pbase, davinci_rtc->base_size);
593 platform_set_drvdata(pdev, NULL);
600 static struct platform_driver davinci_rtc_driver = {
601 .probe = davinci_rtc_probe,
602 .remove = __devexit_p(davinci_rtc_remove),
604 .name = "rtc_davinci",
605 .owner = THIS_MODULE,
609 static int __init rtc_init(void)
611 return platform_driver_probe(&davinci_rtc_driver, davinci_rtc_probe);
613 module_init(rtc_init);
615 static void __exit rtc_exit(void)
617 platform_driver_unregister(&davinci_rtc_driver);
619 module_exit(rtc_exit);
621 MODULE_AUTHOR("Miguel Aguilar <miguel.aguilar@ridgerun.com>");
622 MODULE_DESCRIPTION("Texas Instruments DaVinci PRTC Driver");
623 MODULE_LICENSE("GPL");