1 // SPDX-License-Identifier: GPL-2.0+
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * based on a the Linux rtc-m41t80.c driver which is:
10 * Alexander Bigga <ab@mycable.de>, 2006 (c) mycable GmbH
14 * Date & Time support for STMicroelectronics M41T62
25 #include <linux/log2.h>
26 #include <linux/delay.h>
28 #define M41T62_REG_SSEC 0
29 #define M41T62_REG_SEC 1
30 #define M41T62_REG_MIN 2
31 #define M41T62_REG_HOUR 3
32 #define M41T62_REG_WDAY 4
33 #define M41T62_REG_DAY 5
34 #define M41T62_REG_MON 6
35 #define M41T62_REG_YEAR 7
36 #define M41T62_REG_ALARM_MON 0xa
37 #define M41T62_REG_ALARM_DAY 0xb
38 #define M41T62_REG_ALARM_HOUR 0xc
39 #define M41T62_REG_ALARM_MIN 0xd
40 #define M41T62_REG_ALARM_SEC 0xe
41 #define M41T62_REG_FLAGS 0xf
43 #define M41T62_DATETIME_REG_SIZE (M41T62_REG_YEAR + 1)
44 #define M41T62_ALARM_REG_SIZE \
45 (M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON)
47 #define M41T62_SEC_ST (1 << 7) /* ST: Stop Bit */
48 #define M41T62_ALMON_AFE (1 << 7) /* AFE: AF Enable Bit */
49 #define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */
50 #define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
51 #define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */
52 #define M41T62_FLAGS_OF (1 << 2) /* OF: Oscillator Flag Bit */
53 #define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */
55 #define M41T62_WDAY_SQW_FREQ_MASK 0xf0
56 #define M41T62_WDAY_SQW_FREQ_SHIFT 4
58 #define M41T62_SQW_MAX_FREQ 32768
60 #define M41T62_FEATURE_HT (1 << 0)
61 #define M41T62_FEATURE_BL (1 << 1)
63 #define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
65 static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf)
67 debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
68 "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
70 buf[0], buf[1], buf[2], buf[3],
71 buf[4], buf[5], buf[6], buf[7]);
73 tm->tm_sec = bcd2bin(buf[M41T62_REG_SEC] & 0x7f);
74 tm->tm_min = bcd2bin(buf[M41T62_REG_MIN] & 0x7f);
75 tm->tm_hour = bcd2bin(buf[M41T62_REG_HOUR] & 0x3f);
76 tm->tm_mday = bcd2bin(buf[M41T62_REG_DAY] & 0x3f);
77 tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07;
78 tm->tm_mon = bcd2bin(buf[M41T62_REG_MON] & 0x1f);
80 /* assume 20YY not 19YY, and ignore the Century Bit */
81 /* U-Boot needs to add 1900 here */
82 tm->tm_year = bcd2bin(buf[M41T62_REG_YEAR]) + 100 + 1900;
84 debug("%s: tm is secs=%d, mins=%d, hours=%d, "
85 "mday=%d, mon=%d, year=%d, wday=%d\n",
87 tm->tm_sec, tm->tm_min, tm->tm_hour,
88 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
91 static void m41t62_set_rtc_buf(const struct rtc_time *tm, u8 *buf)
93 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
94 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
95 tm->tm_hour, tm->tm_min, tm->tm_sec);
97 /* Merge time-data and register flags into buf[0..7] */
98 buf[M41T62_REG_SSEC] = 0;
100 bin2bcd(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f);
101 buf[M41T62_REG_MIN] =
102 bin2bcd(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f);
103 buf[M41T62_REG_HOUR] =
104 bin2bcd(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ;
105 buf[M41T62_REG_WDAY] =
106 (tm->tm_wday & 0x07) | (buf[M41T62_REG_WDAY] & ~0x07);
107 buf[M41T62_REG_DAY] =
108 bin2bcd(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f);
109 buf[M41T62_REG_MON] =
110 bin2bcd(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f);
111 /* assume 20YY not 19YY */
112 buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100);
116 static int m41t62_rtc_get(struct udevice *dev, struct rtc_time *tm)
118 u8 buf[M41T62_DATETIME_REG_SIZE];
121 ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
125 m41t62_update_rtc_time(tm, buf);
130 static int m41t62_rtc_set(struct udevice *dev, const struct rtc_time *tm)
132 u8 buf[M41T62_DATETIME_REG_SIZE];
135 ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
139 m41t62_set_rtc_buf(tm, buf);
141 ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
143 printf("I2C write failed in %s()\n", __func__);
150 static int m41t62_sqw_enable(struct udevice *dev, bool enable)
155 ret = dm_i2c_read(dev, M41T62_REG_ALARM_MON, &val, sizeof(val));
160 val |= M41T62_ALMON_SQWE;
162 val &= ~M41T62_ALMON_SQWE;
164 return dm_i2c_write(dev, M41T62_REG_ALARM_MON, &val, sizeof(val));
167 static int m41t62_sqw_set_rate(struct udevice *dev, unsigned int rate)
169 u8 val, newval, sqwrateval;
172 if (rate >= M41T62_SQW_MAX_FREQ)
174 else if (rate >= M41T62_SQW_MAX_FREQ / 4)
177 sqwrateval = 15 - ilog2(rate);
179 ret = dm_i2c_read(dev, M41T62_REG_WDAY, &val, sizeof(val));
184 newval &= ~M41T62_WDAY_SQW_FREQ_MASK;
185 newval |= (sqwrateval << M41T62_WDAY_SQW_FREQ_SHIFT);
188 * Try to avoid writing unchanged values. Writing to this register
189 * will reset the internal counter pipeline and thus affect system
195 return dm_i2c_write(dev, M41T62_REG_WDAY, &newval, sizeof(newval));
198 static int m41t62_rtc_restart_osc(struct udevice *dev)
203 /* 0. check if oscillator failure happened */
204 ret = dm_i2c_read(dev, M41T62_REG_FLAGS, &val, sizeof(val));
207 if (!(val & M41T62_FLAGS_OF))
210 ret = dm_i2c_read(dev, M41T62_REG_SEC, &val, sizeof(val));
214 /* 1. Set stop bit */
215 val |= M41T62_SEC_ST;
216 ret = dm_i2c_write(dev, M41T62_REG_SEC, &val, sizeof(val));
220 /* 2. Clear stop bit */
221 val &= ~M41T62_SEC_ST;
222 ret = dm_i2c_write(dev, M41T62_REG_SEC, &val, sizeof(val));
226 /* 3. wait 4 seconds */
229 ret = dm_i2c_read(dev, M41T62_REG_FLAGS, &val, sizeof(val));
233 /* 4. clear M41T62_FLAGS_OF bit */
234 val &= ~M41T62_FLAGS_OF;
235 ret = dm_i2c_write(dev, M41T62_REG_FLAGS, &val, sizeof(val));
242 static int m41t62_rtc_clear_ht(struct udevice *dev)
248 * M41T82: Make sure HT (Halt Update) bit is cleared.
249 * This bit is 0 in M41T62 so its save to clear it always.
252 ret = dm_i2c_read(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
255 val &= ~M41T80_ALHOUR_HT;
256 ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
263 static int m41t62_rtc_reset(struct udevice *dev)
267 ret = m41t62_rtc_restart_osc(dev);
271 ret = m41t62_rtc_clear_ht(dev);
276 * Some boards feed the square wave as clock input into
277 * the SoC. This enables a 32.768kHz square wave, which is
278 * also the hardware default after power-loss.
280 ret = m41t62_sqw_set_rate(dev, 32768);
283 return m41t62_sqw_enable(dev, true);
287 * Make sure HT bit is cleared. This bit is set on entering battery backup
288 * mode, so do this before the first read access.
290 static int m41t62_rtc_probe(struct udevice *dev)
292 return m41t62_rtc_clear_ht(dev);
295 static const struct rtc_ops m41t62_rtc_ops = {
296 .get = m41t62_rtc_get,
297 .set = m41t62_rtc_set,
298 .reset = m41t62_rtc_reset,
301 static const struct udevice_id m41t62_rtc_ids[] = {
302 { .compatible = "st,m41t62" },
303 { .compatible = "st,m41t82" },
304 { .compatible = "st,m41st87" },
305 { .compatible = "microcrystal,rv4162" },
309 U_BOOT_DRIVER(rtc_m41t62) = {
310 .name = "rtc-m41t62",
312 .of_match = m41t62_rtc_ids,
313 .ops = &m41t62_rtc_ops,
314 .probe = &m41t62_rtc_probe,
317 #else /* NON DM RTC code - will be removed */
318 int rtc_get(struct rtc_time *tm)
320 u8 buf[M41T62_DATETIME_REG_SIZE];
322 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
323 m41t62_update_rtc_time(tm, buf);
328 int rtc_set(struct rtc_time *tm)
330 u8 buf[M41T62_DATETIME_REG_SIZE];
332 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
333 m41t62_set_rtc_buf(tm, buf);
335 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf,
336 M41T62_DATETIME_REG_SIZE)) {
337 printf("I2C write failed in %s()\n", __func__);
349 * M41T82: Make sure HT (Halt Update) bit is cleared.
350 * This bit is 0 in M41T62 so its save to clear it always.
352 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
353 val &= ~M41T80_ALHOUR_HT;
354 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
356 #endif /* CONFIG_DM_RTC */