1 // SPDX-License-Identifier: GPL-2.0+
3 * PRNG driver for Qualcomm IPQ40xx
5 * Copyright (c) 2020 Sartura Ltd.
7 * Author: Robert Marko <robert.marko@sartura.hr>
9 * Based on Linux driver
16 #include <linux/bitops.h>
19 /* Device specific register offsets */
20 #define PRNG_DATA_OUT 0x0000
21 #define PRNG_STATUS 0x0004
22 #define PRNG_LFSR_CFG 0x0100
23 #define PRNG_CONFIG 0x0104
25 /* Device specific register masks and config values */
26 #define PRNG_LFSR_CFG_MASK 0x0000ffff
27 #define PRNG_LFSR_CFG_CLOCKS 0x0000dddd
28 #define PRNG_CONFIG_HW_ENABLE BIT(1)
29 #define PRNG_STATUS_DATA_AVAIL BIT(0)
31 #define MAX_HW_FIFO_DEPTH 16
32 #define MAX_HW_FIFO_SIZE (MAX_HW_FIFO_DEPTH * 4)
40 static int msm_rng_read(struct udevice *dev, void *data, size_t len)
42 struct msm_rng_priv *priv = dev_get_priv(dev);
48 /* calculate max size bytes to transfer back to caller */
49 maxsize = min_t(size_t, MAX_HW_FIFO_SIZE, len);
51 /* read random data from hardware */
53 val = readl_relaxed(priv->base + PRNG_STATUS);
54 if (!(val & PRNG_STATUS_DATA_AVAIL))
57 val = readl_relaxed(priv->base + PRNG_DATA_OUT);
64 /* make sure we stay on 32bit boundary */
65 if ((maxsize - currsize) < WORD_SZ)
67 } while (currsize < maxsize);
72 static int msm_rng_enable(struct msm_rng_priv *priv, int enable)
77 /* Enable PRNG only if it is not already enabled */
78 val = readl_relaxed(priv->base + PRNG_CONFIG);
79 if (val & PRNG_CONFIG_HW_ENABLE) {
80 val = readl_relaxed(priv->base + PRNG_LFSR_CFG);
81 val &= ~PRNG_LFSR_CFG_MASK;
82 val |= PRNG_LFSR_CFG_CLOCKS;
83 writel(val, priv->base + PRNG_LFSR_CFG);
85 val = readl_relaxed(priv->base + PRNG_CONFIG);
86 val |= PRNG_CONFIG_HW_ENABLE;
87 writel(val, priv->base + PRNG_CONFIG);
90 val = readl_relaxed(priv->base + PRNG_CONFIG);
91 val &= ~PRNG_CONFIG_HW_ENABLE;
92 writel(val, priv->base + PRNG_CONFIG);
98 static int msm_rng_probe(struct udevice *dev)
100 struct msm_rng_priv *priv = dev_get_priv(dev);
104 priv->base = dev_read_addr(dev);
105 if (priv->base == FDT_ADDR_T_NONE)
108 ret = clk_get_by_index(dev, 0, &priv->clk);
112 ret = clk_enable(&priv->clk);
116 return msm_rng_enable(priv, 1);
119 static int msm_rng_remove(struct udevice *dev)
121 struct msm_rng_priv *priv = dev_get_priv(dev);
123 return msm_rng_enable(priv, 0);
126 static const struct dm_rng_ops msm_rng_ops = {
127 .read = msm_rng_read,
130 static const struct udevice_id msm_rng_match[] = {
131 { .compatible = "qcom,prng", },
135 U_BOOT_DRIVER(msm_rng) = {
138 .of_match = msm_rng_match,
140 .probe = msm_rng_probe,
141 .remove = msm_rng_remove,
142 .priv_auto = sizeof(struct msm_rng_priv),