1 // SPDX-License-Identifier: GPL-2.0+
3 * Socfpga Reset Controller Driver
5 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
8 * Allwinner SoCs Reset Controller driver
10 * Copyright 2013 Maxime Ripard
12 * Maxime Ripard <maxime.ripard@free-electrons.com>
17 #include <dm/of_access.h>
18 #include <reset-uclass.h>
19 #include <linux/bitops.h>
21 #include <linux/sizes.h>
23 #define BANK_INCREMENT 4
26 struct socfpga_reset_data {
27 void __iomem *modrst_base;
31 * For compatibility with Kernels that don't support peripheral reset, this
32 * driver can keep the old behaviour of not asserting peripheral reset before
33 * starting the OS and deasserting all peripheral resets (enabling all
36 * For that, the reset driver checks the environment variable
37 * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not
38 * reset again once taken out of reset and all peripherals in 'permodrst' are
39 * taken out of reset before booting into the OS.
40 * Note that this should be required for gen5 systems only that are running
41 * Linux kernels without proper peripheral reset support for all drivers used.
43 static bool socfpga_reset_keep_enabled(void)
45 #if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
49 env_str = env_get("socfpga_legacy_reset_compat");
51 val = simple_strtol(env_str, NULL, 0);
60 static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
62 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
63 int id = reset_ctl->id;
64 int reg_width = sizeof(u32);
65 int bank = id / (reg_width * BITS_PER_BYTE);
66 int offset = id % (reg_width * BITS_PER_BYTE);
68 setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
72 static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
74 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
75 int id = reset_ctl->id;
76 int reg_width = sizeof(u32);
77 int bank = id / (reg_width * BITS_PER_BYTE);
78 int offset = id % (reg_width * BITS_PER_BYTE);
80 clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
84 static int socfpga_reset_request(struct reset_ctl *reset_ctl)
86 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
87 reset_ctl, reset_ctl->dev, reset_ctl->id);
92 static int socfpga_reset_free(struct reset_ctl *reset_ctl)
94 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
95 reset_ctl->dev, reset_ctl->id);
100 static const struct reset_ops socfpga_reset_ops = {
101 .request = socfpga_reset_request,
102 .free = socfpga_reset_free,
103 .rst_assert = socfpga_reset_assert,
104 .rst_deassert = socfpga_reset_deassert,
107 static int socfpga_reset_probe(struct udevice *dev)
109 struct socfpga_reset_data *data = dev_get_priv(dev);
111 void __iomem *membase;
113 membase = devfdt_get_addr_ptr(dev);
115 modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10);
116 data->modrst_base = membase + modrst_offset;
121 static int socfpga_reset_remove(struct udevice *dev)
123 struct socfpga_reset_data *data = dev_get_priv(dev);
125 if (socfpga_reset_keep_enabled()) {
126 puts("Deasserting all peripheral resets\n");
127 writel(0, data->modrst_base + 4);
133 static const struct udevice_id socfpga_reset_match[] = {
134 { .compatible = "altr,rst-mgr" },
138 U_BOOT_DRIVER(socfpga_reset) = {
139 .name = "socfpga-reset",
141 .of_match = socfpga_reset_match,
142 .probe = socfpga_reset_probe,
143 .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
144 .ops = &socfpga_reset_ops,
145 .remove = socfpga_reset_remove,
146 .flags = DM_FLAG_OS_PREPARE,