1 // SPDX-License-Identifier: GPL-2.0+
3 * Socfpga Reset Controller Driver
5 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
8 * Allwinner SoCs Reset Controller driver
10 * Copyright 2013 Maxime Ripard
12 * Maxime Ripard <maxime.ripard@free-electrons.com>
19 #include <dm/of_access.h>
21 #include <reset-uclass.h>
23 #include <linux/bitops.h>
25 #include <linux/sizes.h>
27 #define BANK_INCREMENT 4
30 struct socfpga_reset_data {
31 void __iomem *modrst_base;
35 * For compatibility with Kernels that don't support peripheral reset, this
36 * driver can keep the old behaviour of not asserting peripheral reset before
37 * starting the OS and deasserting all peripheral resets (enabling all
40 * For that, the reset driver checks the environment variable
41 * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not
42 * reset again once taken out of reset and all peripherals in 'permodrst' are
43 * taken out of reset before booting into the OS.
44 * Note that this should be required for gen5 systems only that are running
45 * Linux kernels without proper peripheral reset support for all drivers used.
47 static bool socfpga_reset_keep_enabled(void)
49 #if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
53 env_str = env_get("socfpga_legacy_reset_compat");
55 val = simple_strtol(env_str, NULL, 0);
64 static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
66 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
67 int id = reset_ctl->id;
68 int reg_width = sizeof(u32);
69 int bank = id / (reg_width * BITS_PER_BYTE);
70 int offset = id % (reg_width * BITS_PER_BYTE);
72 setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
76 static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
78 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
79 int id = reset_ctl->id;
80 int reg_width = sizeof(u32);
81 int bank = id / (reg_width * BITS_PER_BYTE);
82 int offset = id % (reg_width * BITS_PER_BYTE);
84 clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
86 return wait_for_bit_le32(data->modrst_base + (bank * BANK_INCREMENT),
91 static int socfpga_reset_request(struct reset_ctl *reset_ctl)
93 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
94 reset_ctl, reset_ctl->dev, reset_ctl->id);
99 static int socfpga_reset_free(struct reset_ctl *reset_ctl)
101 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
102 reset_ctl->dev, reset_ctl->id);
107 static const struct reset_ops socfpga_reset_ops = {
108 .request = socfpga_reset_request,
109 .rfree = socfpga_reset_free,
110 .rst_assert = socfpga_reset_assert,
111 .rst_deassert = socfpga_reset_deassert,
114 static int socfpga_reset_probe(struct udevice *dev)
116 struct socfpga_reset_data *data = dev_get_priv(dev);
118 void __iomem *membase;
120 membase = devfdt_get_addr_ptr(dev);
122 modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10);
123 data->modrst_base = membase + modrst_offset;
128 static int socfpga_reset_remove(struct udevice *dev)
130 struct socfpga_reset_data *data = dev_get_priv(dev);
132 if (socfpga_reset_keep_enabled()) {
133 puts("Deasserting all peripheral resets\n");
134 writel(0, data->modrst_base + 4);
140 static int socfpga_reset_bind(struct udevice *dev)
143 struct udevice *sys_child;
146 * The sysreset driver does not have a device node, so bind it here.
147 * Bind it to the node, too, so that it can get its base address.
149 ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
150 dev->node, &sys_child);
152 debug("Warning: No sysreset driver: ret=%d\n", ret);
157 static const struct udevice_id socfpga_reset_match[] = {
158 { .compatible = "altr,rst-mgr" },
162 U_BOOT_DRIVER(socfpga_reset) = {
163 .name = "socfpga-reset",
165 .of_match = socfpga_reset_match,
166 .bind = socfpga_reset_bind,
167 .probe = socfpga_reset_probe,
168 .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
169 .ops = &socfpga_reset_ops,
170 .remove = socfpga_reset_remove,
171 .flags = DM_FLAG_OS_PREPARE,