1 // SPDX-License-Identifier: GPL-2.0+
3 * Socfpga Reset Controller Driver
5 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
8 * Allwinner SoCs Reset Controller driver
10 * Copyright 2013 Maxime Ripard
12 * Maxime Ripard <maxime.ripard@free-electrons.com>
20 #include <dm/of_access.h>
22 #include <reset-uclass.h>
24 #include <linux/bitops.h>
26 #include <linux/sizes.h>
28 #define BANK_INCREMENT 4
31 struct socfpga_reset_data {
32 void __iomem *modrst_base;
36 * For compatibility with Kernels that don't support peripheral reset, this
37 * driver can keep the old behaviour of not asserting peripheral reset before
38 * starting the OS and deasserting all peripheral resets (enabling all
41 * For that, the reset driver checks the environment variable
42 * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not
43 * reset again once taken out of reset and all peripherals in 'permodrst' are
44 * taken out of reset before booting into the OS.
45 * Note that this should be required for gen5 systems only that are running
46 * Linux kernels without proper peripheral reset support for all drivers used.
48 static bool socfpga_reset_keep_enabled(void)
50 #if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
54 env_str = env_get("socfpga_legacy_reset_compat");
56 val = simple_strtol(env_str, NULL, 0);
65 static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
67 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
68 int id = reset_ctl->id;
69 int reg_width = sizeof(u32);
70 int bank = id / (reg_width * BITS_PER_BYTE);
71 int offset = id % (reg_width * BITS_PER_BYTE);
73 setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
77 static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
79 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
80 int id = reset_ctl->id;
81 int reg_width = sizeof(u32);
82 int bank = id / (reg_width * BITS_PER_BYTE);
83 int offset = id % (reg_width * BITS_PER_BYTE);
85 clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
87 return wait_for_bit_le32(data->modrst_base + (bank * BANK_INCREMENT),
92 static const struct reset_ops socfpga_reset_ops = {
93 .rst_assert = socfpga_reset_assert,
94 .rst_deassert = socfpga_reset_deassert,
97 static int socfpga_reset_probe(struct udevice *dev)
99 struct socfpga_reset_data *data = dev_get_priv(dev);
101 void __iomem *membase;
103 membase = dev_read_addr_ptr(dev);
105 modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10);
106 data->modrst_base = membase + modrst_offset;
111 static int socfpga_reset_remove(struct udevice *dev)
113 struct socfpga_reset_data *data = dev_get_priv(dev);
115 if (socfpga_reset_keep_enabled()) {
116 puts("Deasserting all peripheral resets\n");
117 writel(0, data->modrst_base + 4);
123 static int socfpga_reset_bind(struct udevice *dev)
126 struct udevice *sys_child;
129 * The sysreset driver does not have a device node, so bind it here.
130 * Bind it to the node, too, so that it can get its base address.
132 ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
133 dev_ofnode(dev), &sys_child);
135 debug("Warning: No sysreset driver: ret=%d\n", ret);
140 static const struct udevice_id socfpga_reset_match[] = {
141 { .compatible = "altr,rst-mgr" },
145 U_BOOT_DRIVER(socfpga_reset) = {
146 .name = "socfpga-reset",
148 .of_match = socfpga_reset_match,
149 .bind = socfpga_reset_bind,
150 .probe = socfpga_reset_probe,
151 .priv_auto = sizeof(struct socfpga_reset_data),
152 .ops = &socfpga_reset_ops,
153 .remove = socfpga_reset_remove,
154 .flags = DM_FLAG_OS_PREPARE,