drivers/reset/reset-qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2020 Sartura Ltd.
   4  * Copyright (c) 2022 Linaro Ltd.
   5  *
   6  * Author: Robert Marko <robert.marko@sartura.hr>
   7  *         Sumit Garg <sumit.garg@linaro.org>
   8  *
   9  * Based on Linux driver
  10  */
  11
  12 #include <asm/io.h>
  13 #include <common.h>
  14 #include <dm.h>
  15 #include <reset-uclass.h>
  16 #include <linux/bitops.h>
  17 #include <malloc.h>
  18
  19 struct qcom_reset_priv {
  20         phys_addr_t base;
  21 };
  22
  23 struct qcom_reset_map {
  24         unsigned int reg;
  25         u8 bit;
  26 };
  27
  28 #ifdef CONFIG_ARCH_IPQ40XX
  29 #include <dt-bindings/reset/qcom,ipq4019-reset.h>
  30 static const struct qcom_reset_map gcc_qcom_resets[] = {
  31         [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
  32         [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
  33         [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
  34         [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
  35         [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
  36         [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
  37         [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
  38         [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
  39         [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
  40         [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
  41         [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
  42         [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
  43         [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
  44         [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
  45         [USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
  46         [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
  47         [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
  48         [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
  49         [PCIE_AHB_ARES] = { 0x1d010, 10 },
  50         [PCIE_PWR_ARES] = { 0x1d010, 9 },
  51         [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
  52         [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
  53         [PCIE_PHY_ARES] = { 0x1d010, 6 },
  54         [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
  55         [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
  56         [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
  57         [PCIE_PIPE_ARES] = { 0x1d010, 2 },
  58         [PCIE_AXI_S_ARES] = { 0x1d010, 1 },
  59         [PCIE_AXI_M_ARES] = { 0x1d010, 0 },
  60         [ESS_RESET] = { 0x12008, 0},
  61         [GCC_BLSP1_BCR] = {0x01000, 0},
  62         [GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
  63         [GCC_BLSP1_UART1_BCR] = {0x02038, 0},
  64         [GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
  65         [GCC_BLSP1_UART2_BCR] = {0x03028, 0},
  66         [GCC_BIMC_BCR] = {0x04000, 0},
  67         [GCC_TLMM_BCR] = {0x05000, 0},
  68         [GCC_IMEM_BCR] = {0x0E000, 0},
  69         [GCC_ESS_BCR] = {0x12008, 0},
  70         [GCC_PRNG_BCR] = {0x13000, 0},
  71         [GCC_BOOT_ROM_BCR] = {0x13008, 0},
  72         [GCC_CRYPTO_BCR] = {0x16000, 0},
  73         [GCC_SDCC1_BCR] = {0x18000, 0},
  74         [GCC_SEC_CTRL_BCR] = {0x1A000, 0},
  75         [GCC_AUDIO_BCR] = {0x1B008, 0},
  76         [GCC_QPIC_BCR] = {0x1C000, 0},
  77         [GCC_PCIE_BCR] = {0x1D000, 0},
  78         [GCC_USB2_BCR] = {0x1E008, 0},
  79         [GCC_USB2_PHY_BCR] = {0x1E018, 0},
  80         [GCC_USB3_BCR] = {0x1E024, 0},
  81         [GCC_USB3_PHY_BCR] = {0x1E034, 0},
  82         [GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
  83         [GCC_PCNOC_BCR] = {0x2102C, 0},
  84         [GCC_DCD_BCR] = {0x21038, 0},
  85         [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
  86         [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
  87         [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
  88         [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
  89         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
  90         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
  91         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
  92         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
  93         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
  94         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
  95         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
  96         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
  97         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
  98         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
  99         [GCC_TCSR_BCR] = {0x22000, 0},
 100         [GCC_MPM_BCR] = {0x24000, 0},
 101         [GCC_SPDM_BCR] = {0x25000, 0},
 102 };
 103 #endif
 104
 105 #ifdef CONFIG_TARGET_QCS404EVB
 106 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
 107 static const struct qcom_reset_map gcc_qcom_resets[] = {
 108         [GCC_GENI_IR_BCR] = { 0x0F000 },
 109         [GCC_CDSP_RESTART] = { 0x18000 },
 110         [GCC_USB_HS_BCR] = { 0x41000 },
 111         [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
 112         [GCC_QUSB2_PHY_BCR] = { 0x4103c },
 113         [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
 114         [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
 115         [GCC_USB3_PHY_BCR] = { 0x39004 },
 116         [GCC_USB_30_BCR] = { 0x39000 },
 117         [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
 118         [GCC_PCIE_0_BCR] = { 0x3e000 },
 119         [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
 120         [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
 121         [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
 122         [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
 123         [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
 124         [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
 125         [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
 126         [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
 127         [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
 128         [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
 129         [GCC_EMAC_BCR] = { 0x4e000 },
 130         [GCC_WDSP_RESTART] = {0x19000},
 131 };
 132 #endif
 133
 134 static int qcom_reset_assert(struct reset_ctl *rst)
 135 {
 136         struct qcom_reset_priv *priv = dev_get_priv(rst->dev);
 137         const struct qcom_reset_map *reset_map = gcc_qcom_resets;
 138         const struct qcom_reset_map *map;
 139         u32 value;
 140
 141         map = &reset_map[rst->id];
 142
 143         value = readl(priv->base + map->reg);
 144         value |= BIT(map->bit);
 145         writel(value, priv->base + map->reg);
 146
 147         return 0;
 148 }
 149
 150 static int qcom_reset_deassert(struct reset_ctl *rst)
 151 {
 152         struct qcom_reset_priv *priv = dev_get_priv(rst->dev);
 153         const struct qcom_reset_map *reset_map = gcc_qcom_resets;
 154         const struct qcom_reset_map *map;
 155         u32 value;
 156
 157         map = &reset_map[rst->id];
 158
 159         value = readl(priv->base + map->reg);
 160         value &= ~BIT(map->bit);
 161         writel(value, priv->base + map->reg);
 162
 163         return 0;
 164 }
 165
 166 static const struct reset_ops qcom_reset_ops = {
 167         .rst_assert = qcom_reset_assert,
 168         .rst_deassert = qcom_reset_deassert,
 169 };
 170
 171 static const struct udevice_id qcom_reset_ids[] = {
 172         { .compatible = "qcom,gcc-reset-ipq4019" },
 173         { .compatible = "qcom,gcc-reset-qcs404" },
 174         { }
 175 };
 176
 177 static int qcom_reset_probe(struct udevice *dev)
 178 {
 179         struct qcom_reset_priv *priv = dev_get_priv(dev);
 180
 181         priv->base = dev_read_addr(dev);
 182         if (priv->base == FDT_ADDR_T_NONE)
 183                 return -EINVAL;
 184
 185         return 0;
 186 }
 187
 188 U_BOOT_DRIVER(qcom_reset) = {
 189         .name = "qcom_reset",
 190         .id = UCLASS_RESET,
 191         .of_match = qcom_reset_ids,
 192         .ops = &qcom_reset_ops,
 193         .probe = qcom_reset_probe,
 194         .priv_auto = sizeof(struct qcom_reset_priv),
 195 };