1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch Reset driver
4 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
9 #include <linux/mfd/syscon.h>
10 #include <linux/of_device.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
14 #include <linux/reset-controller.h>
16 #define PROTECT_REG 0x84
17 #define PROTECT_BIT BIT(10)
18 #define SOFT_RESET_REG 0x00
19 #define SOFT_RESET_BIT BIT(1)
21 struct mchp_reset_context {
22 struct regmap *cpu_ctrl;
23 struct regmap *gcb_ctrl;
24 struct reset_controller_dev rcdev;
27 static struct regmap_config sparx5_reset_regmap_config = {
33 static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
36 struct mchp_reset_context *ctx =
37 container_of(rcdev, struct mchp_reset_context, rcdev);
40 /* Make sure the core is PROTECTED from reset */
41 regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT);
43 /* Start soft reset */
44 regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
46 /* Wait for soft reset done */
47 return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
48 (val & SOFT_RESET_BIT) == 0,
52 static const struct reset_control_ops sparx5_reset_ops = {
53 .reset = sparx5_switch_reset,
56 static int mchp_sparx5_map_syscon(struct platform_device *pdev, char *name,
57 struct regmap **target)
59 struct device_node *syscon_np;
60 struct regmap *regmap;
63 syscon_np = of_parse_phandle(pdev->dev.of_node, name, 0);
66 regmap = syscon_node_to_regmap(syscon_np);
67 of_node_put(syscon_np);
69 err = PTR_ERR(regmap);
70 dev_err(&pdev->dev, "No '%s' map: %d\n", name, err);
77 static int mchp_sparx5_map_io(struct platform_device *pdev, int index,
78 struct regmap **target)
84 mem = devm_platform_get_and_ioremap_resource(pdev, index, &res);
86 dev_err(&pdev->dev, "Could not map resource %d\n", index);
89 sparx5_reset_regmap_config.name = res->name;
90 map = devm_regmap_init_mmio(&pdev->dev, mem, &sparx5_reset_regmap_config);
97 static int mchp_sparx5_reset_probe(struct platform_device *pdev)
99 struct device_node *dn = pdev->dev.of_node;
100 struct mchp_reset_context *ctx;
103 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
107 err = mchp_sparx5_map_syscon(pdev, "cpu-syscon", &ctx->cpu_ctrl);
110 err = mchp_sparx5_map_io(pdev, 0, &ctx->gcb_ctrl);
114 ctx->rcdev.owner = THIS_MODULE;
115 ctx->rcdev.nr_resets = 1;
116 ctx->rcdev.ops = &sparx5_reset_ops;
117 ctx->rcdev.of_node = dn;
119 return devm_reset_controller_register(&pdev->dev, &ctx->rcdev);
122 static const struct of_device_id mchp_sparx5_reset_of_match[] = {
124 .compatible = "microchip,sparx5-switch-reset",
129 static struct platform_driver mchp_sparx5_reset_driver = {
130 .probe = mchp_sparx5_reset_probe,
132 .name = "sparx5-switch-reset",
133 .of_match_table = mchp_sparx5_reset_of_match,
137 static int __init mchp_sparx5_reset_init(void)
139 return platform_driver_register(&mchp_sparx5_reset_driver);
142 postcore_initcall(mchp_sparx5_reset_init);
144 MODULE_DESCRIPTION("Microchip Sparx5 switch reset driver");
145 MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>");
146 MODULE_LICENSE("Dual MIT/GPL");