1 # SPDX-License-Identifier: GPL-2.0-only
2 config ARCH_HAS_RESET_CONTROLLER
5 menuconfig RESET_CONTROLLER
6 bool "Reset Controller Support"
7 default y if ARCH_HAS_RESET_CONTROLLER
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
20 depends on MFD_ALTERA_A10SR || COMPILE_TEST
22 This option enables support for the external reset functions for
23 peripheral PHYs on the Altera Arria10 System Resource Chip.
26 bool "AR71xx Reset Driver" if COMPILE_TEST
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
33 bool "AXS10x Reset Driver" if COMPILE_TEST
34 default ARC_PLAT_AXS10X
36 This enables the reset controller driver for AXS10x.
39 bool "BCM6345 Reset Controller"
40 depends on BMIPS_GENERIC || COMPILE_TEST
43 This enables the reset controller driver for BCM6345 SoCs.
46 tristate "Berlin Reset Driver"
47 depends on ARCH_BERLIN || COMPILE_TEST
48 default m if ARCH_BERLIN
50 This enables the reset controller driver for Marvell Berlin SoCs.
53 tristate "Broadcom STB reset controller"
54 depends on ARCH_BRCMSTB || COMPILE_TEST
57 This enables the reset controller driver for Broadcom STB SoCs using
58 a SUN_TOP_CTRL_SW_INIT style controller.
60 config RESET_BRCMSTB_RESCAL
61 tristate "Broadcom STB RESCAL reset controller"
63 depends on ARCH_BRCMSTB || COMPILE_TEST
66 This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
70 bool "Synopsys HSDK Reset Driver"
72 depends on ARC_SOC_HSDK || COMPILE_TEST
74 This enables the reset controller driver for HSDK board.
77 tristate "i.MX7/8 Reset Driver"
79 depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
80 default y if SOC_IMX7D
83 This enables the reset controller driver for i.MX7 SoCs.
86 bool "Intel Reset Controller Driver"
87 depends on X86 || COMPILE_TEST
88 depends on OF && HAS_IOMEM
91 This enables the reset controller driver for Intel Gateway SoCs.
92 Say Y to control the reset signals provided by reset controller.
96 bool "Reset controller driver for Canaan Kendryte K210 SoC"
97 depends on (SOC_CANAAN || COMPILE_TEST) && OF
101 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
102 Say Y if you want to control reset signals provided by this
106 bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
107 default SOC_TYPE_XWAY
109 This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
112 bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
115 This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
117 config RESET_MCHP_SPARX5
118 bool "Microchip Sparx5 reset driver"
119 depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST
120 default y if SPARX5_SWITCH
123 This driver supports switch core reset for the Microchip Sparx5 SoC.
126 tristate "Meson Reset Driver"
127 depends on ARCH_MESON || COMPILE_TEST
130 This enables the reset driver for Amlogic Meson SoCs.
132 config RESET_MESON_AUDIO_ARB
133 tristate "Meson Audio Memory Arbiter Reset Driver"
134 depends on ARCH_MESON || COMPILE_TEST
136 This enables the reset driver for Audio Memory Arbiter of
137 Amlogic's A113 based SoCs
140 bool "NPCM BMC Reset Driver" if COMPILE_TEST
143 This enables the reset controller driver for Nuvoton NPCM
146 config RESET_NUVOTON_MA35D1
147 bool "Nuvoton MA35D1 Reset Driver"
148 depends on ARCH_MA35 || COMPILE_TEST
151 This enables the reset controller driver for Nuvoton MA35D1 SoC.
153 config RESET_PISTACHIO
154 bool "Pistachio Reset Driver"
155 depends on MIPS || COMPILE_TEST
157 This enables the reset driver for ImgTec Pistachio SoCs.
159 config RESET_POLARFIRE_SOC
160 bool "Microchip PolarFire SoC (MPFS) Reset Driver"
161 depends on MCHP_CLK_MPFS
163 default MCHP_CLK_MPFS
165 This driver supports peripheral reset for the Microchip PolarFire SoC
167 config RESET_QCOM_AOSS
168 tristate "Qcom AOSS Reset Driver"
169 depends on ARCH_QCOM || COMPILE_TEST
171 This enables the AOSS (always on subsystem) reset driver
172 for Qualcomm SDM845 SoCs. Say Y if you want to control
173 reset signals provided by AOSS for Modem, Venus, ADSP,
174 GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
176 config RESET_QCOM_PDC
177 tristate "Qualcomm PDC Reset Driver"
178 depends on ARCH_QCOM || COMPILE_TEST
180 This enables the PDC (Power Domain Controller) reset driver
181 for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
182 to control reset signals provided by PDC for Modem, Compute,
183 Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
185 config RESET_RASPBERRYPI
186 tristate "Raspberry Pi 4 Firmware Reset Driver"
187 depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
190 Raspberry Pi 4's co-processor controls some of the board's HW
191 initialization process, but it's up to Linux to trigger it when
192 relevant. This driver provides a reset controller capable of
193 interfacing with RPi4's co-processor and model these firmware
194 initialization routines as reset lines.
196 config RESET_RZG2L_USBPHY_CTRL
197 tristate "Renesas RZ/G2L USBPHY control driver"
198 depends on ARCH_RZG2L || COMPILE_TEST
200 Support for USBPHY Control found on RZ/G2L family. It mainly
201 controls reset and power down of the USB/PHY.
204 tristate "Reset driver controlled via ARM SCMI interface"
205 depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
206 default ARM_SCMI_PROTOCOL
208 This driver provides support for reset signal/domains that are
209 controlled by firmware that implements the SCMI interface.
211 This driver uses SCMI Message Protocol to interact with the
212 firmware controlling all the reset signals.
215 bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
216 default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
219 This enables a simple reset controller driver for reset lines that
220 that can be asserted and deasserted by toggling bits in a contiguous,
221 exclusive register space.
223 Currently this driver supports:
228 - RCC reset controller in STM32 MCUs
233 bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
234 default ARM && ARCH_INTEL_SOCFPGA
237 This enables the reset driver for the SoCFPGA ARMv7 platforms. This
238 driver gets initialized early during platform init calls.
241 bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
244 This enables the reset driver support for Sunplus SoCs.
245 The reset lines that can be asserted and deasserted by toggling bits
246 in a contiguous, exclusive register space. The register is HIWORD_MASKED,
247 which means each register holds 16 reset lines.
250 bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
254 This enables the reset driver for Allwinner SoCs.
257 tristate "TI System Control Interface (TI-SCI) reset driver"
258 depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=n)
260 This enables the reset driver support over TI System Control Interface
261 available on some new TI's SoCs. If you wish to use reset resources
262 managed by the TI System Controller, say Y here. Otherwise, say N.
264 config RESET_TI_SYSCON
265 tristate "TI SYSCON Reset Driver"
269 This enables the reset driver support for TI devices with
270 memory-mapped reset registers as part of a syscon device node. If
271 you wish to use the reset framework for such memory-mapped devices,
272 say Y here. Otherwise, say N.
274 config RESET_TI_TPS380X
275 tristate "TI TPS380x Reset Driver"
278 This enables the reset driver support for TI TPS380x devices. If
279 you wish to use the reset framework for such devices, say Y here.
282 config RESET_TN48M_CPLD
283 tristate "Delta Networks TN48M switch CPLD reset controller"
284 depends on MFD_TN48M_CPLD || COMPILE_TEST
285 default MFD_TN48M_CPLD
287 This enables the reset controller driver for the Delta TN48M CPLD.
288 It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
289 switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
290 Microchip PD69200 PoE PSE controller.
292 This driver can also be built as a module. If so, the module will be
295 config RESET_UNIPHIER
296 tristate "Reset controller driver for UniPhier SoCs"
297 depends on ARCH_UNIPHIER || COMPILE_TEST
298 depends on OF && MFD_SYSCON
299 default ARCH_UNIPHIER
301 Support for reset controllers on UniPhier SoCs.
302 Say Y if you want to control reset signals provided by System Control
303 block, Media I/O block, Peripheral Block.
305 config RESET_UNIPHIER_GLUE
306 tristate "Reset driver in glue layer for UniPhier SoCs"
307 depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
308 default ARCH_UNIPHIER
311 Support for peripheral core reset included in its own glue layer
312 on UniPhier SoCs. Say Y if you want to control reset signals
313 provided by the glue layer.
316 bool "ZYNQ Reset Driver" if COMPILE_TEST
319 This enables the reset controller driver for Xilinx Zynq SoCs.
321 source "drivers/reset/starfive/Kconfig"
322 source "drivers/reset/sti/Kconfig"
323 source "drivers/reset/hisilicon/Kconfig"
324 source "drivers/reset/tegra/Kconfig"