drivers/remoteproc/qcom_wcnss.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
   4  *
   5  * Copyright (C) 2016 Linaro Ltd
   6  * Copyright (C) 2014 Sony Mobile Communications AB
   7  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/firmware.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/io.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_domain.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/qcom_scm.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/remoteproc.h>
  25 #include <linux/soc/qcom/mdt_loader.h>
  26 #include <linux/soc/qcom/smem.h>
  27 #include <linux/soc/qcom/smem_state.h>
  28
  29 #include "qcom_common.h"
  30 #include "remoteproc_internal.h"
  31 #include "qcom_pil_info.h"
  32 #include "qcom_wcnss.h"
  33
  34 #define WCNSS_CRASH_REASON_SMEM         422
  35 #define WCNSS_FIRMWARE_NAME             "wcnss.mdt"
  36 #define WCNSS_PAS_ID                    6
  37 #define WCNSS_SSCTL_ID                  0x13
  38
  39 #define WCNSS_SPARE_NVBIN_DLND          BIT(25)
  40
  41 #define WCNSS_PMU_IRIS_XO_CFG           BIT(3)
  42 #define WCNSS_PMU_IRIS_XO_EN            BIT(4)
  43 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP    BIT(5)
  44 #define WCNSS_PMU_IRIS_XO_CFG_STS       BIT(6) /* 1: in progress, 0: done */
  45
  46 #define WCNSS_PMU_IRIS_RESET            BIT(7)
  47 #define WCNSS_PMU_IRIS_RESET_STS        BIT(8) /* 1: in progress, 0: done */
  48 #define WCNSS_PMU_IRIS_XO_READ          BIT(9)
  49 #define WCNSS_PMU_IRIS_XO_READ_STS      BIT(10)
  50
  51 #define WCNSS_PMU_XO_MODE_MASK          GENMASK(2, 1)
  52 #define WCNSS_PMU_XO_MODE_19p2          0
  53 #define WCNSS_PMU_XO_MODE_48            3
  54
  55 #define WCNSS_MAX_PDS                   2
  56
  57 struct wcnss_data {
  58         size_t pmu_offset;
  59         size_t spare_offset;
  60
  61         const char *pd_names[WCNSS_MAX_PDS];
  62         const struct wcnss_vreg_info *vregs;
  63         size_t num_vregs, num_pd_vregs;
  64 };
  65
  66 struct qcom_wcnss {
  67         struct device *dev;
  68         struct rproc *rproc;
  69
  70         void __iomem *pmu_cfg;
  71         void __iomem *spare_out;
  72
  73         bool use_48mhz_xo;
  74
  75         int wdog_irq;
  76         int fatal_irq;
  77         int ready_irq;
  78         int handover_irq;
  79         int stop_ack_irq;
  80
  81         struct qcom_smem_state *state;
  82         unsigned stop_bit;
  83
  84         struct mutex iris_lock;
  85         struct qcom_iris *iris;
  86
  87         struct device *pds[WCNSS_MAX_PDS];
  88         size_t num_pds;
  89         struct regulator_bulk_data *vregs;
  90         size_t num_vregs;
  91
  92         struct completion start_done;
  93         struct completion stop_done;
  94
  95         phys_addr_t mem_phys;
  96         phys_addr_t mem_reloc;
  97         void *mem_region;
  98         size_t mem_size;
  99
 100         struct qcom_rproc_subdev smd_subdev;
 101         struct qcom_sysmon *sysmon;
 102 };
 103
 104 static const struct wcnss_data riva_data = {
 105         .pmu_offset = 0x28,
 106         .spare_offset = 0xb4,
 107
 108         .vregs = (struct wcnss_vreg_info[]) {
 109                 { "vddmx",  1050000, 1150000, 0 },
 110                 { "vddcx",  1050000, 1150000, 0 },
 111                 { "vddpx",  1800000, 1800000, 0 },
 112         },
 113         .num_vregs = 3,
 114 };
 115
 116 static const struct wcnss_data pronto_v1_data = {
 117         .pmu_offset = 0x1004,
 118         .spare_offset = 0x1088,
 119
 120         .pd_names = { "mx", "cx" },
 121         .vregs = (struct wcnss_vreg_info[]) {
 122                 { "vddmx", 950000, 1150000, 0 },
 123                 { "vddcx", .super_turbo = true},
 124                 { "vddpx", 1800000, 1800000, 0 },
 125         },
 126         .num_pd_vregs = 2,
 127         .num_vregs = 1,
 128 };
 129
 130 static const struct wcnss_data pronto_v2_data = {
 131         .pmu_offset = 0x1004,
 132         .spare_offset = 0x1088,
 133
 134         .pd_names = { "mx", "cx" },
 135         .vregs = (struct wcnss_vreg_info[]) {
 136                 { "vddmx", 1287500, 1287500, 0 },
 137                 { "vddcx", .super_turbo = true },
 138                 { "vddpx", 1800000, 1800000, 0 },
 139         },
 140         .num_pd_vregs = 2,
 141         .num_vregs = 1,
 142 };
 143
 144 static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
 145 {
 146         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 147         int ret;
 148
 149         ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
 150                             wcnss->mem_region, wcnss->mem_phys,
 151                             wcnss->mem_size, &wcnss->mem_reloc);
 152         if (ret)
 153                 return ret;
 154
 155         qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size);
 156
 157         return 0;
 158 }
 159
 160 static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
 161 {
 162         u32 val;
 163
 164         /* Indicate NV download capability */
 165         val = readl(wcnss->spare_out);
 166         val |= WCNSS_SPARE_NVBIN_DLND;
 167         writel(val, wcnss->spare_out);
 168 }
 169
 170 static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
 171 {
 172         u32 val;
 173
 174         /* Clear PMU cfg register */
 175         writel(0, wcnss->pmu_cfg);
 176
 177         val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
 178         writel(val, wcnss->pmu_cfg);
 179
 180         /* Clear XO_MODE */
 181         val &= ~WCNSS_PMU_XO_MODE_MASK;
 182         if (wcnss->use_48mhz_xo)
 183                 val |= WCNSS_PMU_XO_MODE_48 << 1;
 184         else
 185                 val |= WCNSS_PMU_XO_MODE_19p2 << 1;
 186         writel(val, wcnss->pmu_cfg);
 187
 188         /* Reset IRIS */
 189         val |= WCNSS_PMU_IRIS_RESET;
 190         writel(val, wcnss->pmu_cfg);
 191
 192         /* Wait for PMU.iris_reg_reset_sts */
 193         while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
 194                 cpu_relax();
 195
 196         /* Clear IRIS reset */
 197         val &= ~WCNSS_PMU_IRIS_RESET;
 198         writel(val, wcnss->pmu_cfg);
 199
 200         /* Start IRIS XO configuration */
 201         val |= WCNSS_PMU_IRIS_XO_CFG;
 202         writel(val, wcnss->pmu_cfg);
 203
 204         /* Wait for XO configuration to finish */
 205         while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
 206                 cpu_relax();
 207
 208         /* Stop IRIS XO configuration */
 209         val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
 210         val &= ~WCNSS_PMU_IRIS_XO_CFG;
 211         writel(val, wcnss->pmu_cfg);
 212
 213         /* Add some delay for XO to settle */
 214         msleep(20);
 215 }
 216
 217 static int wcnss_start(struct rproc *rproc)
 218 {
 219         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 220         int ret, i;
 221
 222         mutex_lock(&wcnss->iris_lock);
 223         if (!wcnss->iris) {
 224                 dev_err(wcnss->dev, "no iris registered\n");
 225                 ret = -EINVAL;
 226                 goto release_iris_lock;
 227         }
 228
 229         for (i = 0; i < wcnss->num_pds; i++) {
 230                 dev_pm_genpd_set_performance_state(wcnss->pds[i], INT_MAX);
 231                 ret = pm_runtime_get_sync(wcnss->pds[i]);
 232                 if (ret < 0) {
 233                         pm_runtime_put_noidle(wcnss->pds[i]);
 234                         goto disable_pds;
 235                 }
 236         }
 237
 238         ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
 239         if (ret)
 240                 goto disable_pds;
 241
 242         ret = qcom_iris_enable(wcnss->iris);
 243         if (ret)
 244                 goto disable_regulators;
 245
 246         wcnss_indicate_nv_download(wcnss);
 247         wcnss_configure_iris(wcnss);
 248
 249         ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
 250         if (ret) {
 251                 dev_err(wcnss->dev,
 252                         "failed to authenticate image and release reset\n");
 253                 goto disable_iris;
 254         }
 255
 256         ret = wait_for_completion_timeout(&wcnss->start_done,
 257                                           msecs_to_jiffies(5000));
 258         if (wcnss->ready_irq > 0 && ret == 0) {
 259                 /* We have a ready_irq, but it didn't fire in time. */
 260                 dev_err(wcnss->dev, "start timed out\n");
 261                 qcom_scm_pas_shutdown(WCNSS_PAS_ID);
 262                 ret = -ETIMEDOUT;
 263                 goto disable_iris;
 264         }
 265
 266         ret = 0;
 267
 268 disable_iris:
 269         qcom_iris_disable(wcnss->iris);
 270 disable_regulators:
 271         regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
 272 disable_pds:
 273         for (i--; i >= 0; i--) {
 274                 pm_runtime_put(wcnss->pds[i]);
 275                 dev_pm_genpd_set_performance_state(wcnss->pds[i], 0);
 276         }
 277 release_iris_lock:
 278         mutex_unlock(&wcnss->iris_lock);
 279
 280         return ret;
 281 }
 282
 283 static int wcnss_stop(struct rproc *rproc)
 284 {
 285         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 286         int ret;
 287
 288         if (wcnss->state) {
 289                 qcom_smem_state_update_bits(wcnss->state,
 290                                             BIT(wcnss->stop_bit),
 291                                             BIT(wcnss->stop_bit));
 292
 293                 ret = wait_for_completion_timeout(&wcnss->stop_done,
 294                                                   msecs_to_jiffies(5000));
 295                 if (ret == 0)
 296                         dev_err(wcnss->dev, "timed out on wait\n");
 297
 298                 qcom_smem_state_update_bits(wcnss->state,
 299                                             BIT(wcnss->stop_bit),
 300                                             0);
 301         }
 302
 303         ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
 304         if (ret)
 305                 dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
 306
 307         return ret;
 308 }
 309
 310 static void *wcnss_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
 311 {
 312         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 313         int offset;
 314
 315         offset = da - wcnss->mem_reloc;
 316         if (offset < 0 || offset + len > wcnss->mem_size)
 317                 return NULL;
 318
 319         return wcnss->mem_region + offset;
 320 }
 321
 322 static const struct rproc_ops wcnss_ops = {
 323         .start = wcnss_start,
 324         .stop = wcnss_stop,
 325         .da_to_va = wcnss_da_to_va,
 326         .parse_fw = qcom_register_dump_segments,
 327         .load = wcnss_load,
 328 };
 329
 330 static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
 331 {
 332         struct qcom_wcnss *wcnss = dev;
 333
 334         rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
 335
 336         return IRQ_HANDLED;
 337 }
 338
 339 static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
 340 {
 341         struct qcom_wcnss *wcnss = dev;
 342         size_t len;
 343         char *msg;
 344
 345         msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
 346         if (!IS_ERR(msg) && len > 0 && msg[0])
 347                 dev_err(wcnss->dev, "fatal error received: %s\n", msg);
 348
 349         rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
 350
 351         return IRQ_HANDLED;
 352 }
 353
 354 static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
 355 {
 356         struct qcom_wcnss *wcnss = dev;
 357
 358         complete(&wcnss->start_done);
 359
 360         return IRQ_HANDLED;
 361 }
 362
 363 static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
 364 {
 365         /*
 366          * XXX: At this point we're supposed to release the resources that we
 367          * have been holding on behalf of the WCNSS. Unfortunately this
 368          * interrupt comes way before the other side seems to be done.
 369          *
 370          * So we're currently relying on the ready interrupt firing later then
 371          * this and we just disable the resources at the end of wcnss_start().
 372          */
 373
 374         return IRQ_HANDLED;
 375 }
 376
 377 static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
 378 {
 379         struct qcom_wcnss *wcnss = dev;
 380
 381         complete(&wcnss->stop_done);
 382
 383         return IRQ_HANDLED;
 384 }
 385
 386 static int wcnss_init_pds(struct qcom_wcnss *wcnss,
 387                           const char * const pd_names[WCNSS_MAX_PDS])
 388 {
 389         int i, ret;
 390
 391         for (i = 0; i < WCNSS_MAX_PDS; i++) {
 392                 if (!pd_names[i])
 393                         break;
 394
 395                 wcnss->pds[i] = dev_pm_domain_attach_by_name(wcnss->dev, pd_names[i]);
 396                 if (IS_ERR_OR_NULL(wcnss->pds[i])) {
 397                         ret = PTR_ERR(wcnss->pds[i]) ? : -ENODATA;
 398                         for (i--; i >= 0; i--)
 399                                 dev_pm_domain_detach(wcnss->pds[i], false);
 400                         return ret;
 401                 }
 402         }
 403         wcnss->num_pds = i;
 404
 405         return 0;
 406 }
 407
 408 static void wcnss_release_pds(struct qcom_wcnss *wcnss)
 409 {
 410         int i;
 411
 412         for (i = 0; i < wcnss->num_pds; i++)
 413                 dev_pm_domain_detach(wcnss->pds[i], false);
 414 }
 415
 416 static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
 417                                  const struct wcnss_vreg_info *info,
 418                                  int num_vregs, int num_pd_vregs)
 419 {
 420         struct regulator_bulk_data *bulk;
 421         int ret;
 422         int i;
 423
 424         /*
 425          * If attaching the power domains suceeded we can skip requesting
 426          * the regulators for the power domains. For old device trees we need to
 427          * reserve extra space to manage them through the regulator interface.
 428          */
 429         if (wcnss->num_pds)
 430                 info += num_pd_vregs;
 431         else
 432                 num_vregs += num_pd_vregs;
 433
 434         bulk = devm_kcalloc(wcnss->dev,
 435                             num_vregs, sizeof(struct regulator_bulk_data),
 436                             GFP_KERNEL);
 437         if (!bulk)
 438                 return -ENOMEM;
 439
 440         for (i = 0; i < num_vregs; i++)
 441                 bulk[i].supply = info[i].name;
 442
 443         ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
 444         if (ret)
 445                 return ret;
 446
 447         for (i = 0; i < num_vregs; i++) {
 448                 if (info[i].max_voltage)
 449                         regulator_set_voltage(bulk[i].consumer,
 450                                               info[i].min_voltage,
 451                                               info[i].max_voltage);
 452
 453                 if (info[i].load_uA)
 454                         regulator_set_load(bulk[i].consumer, info[i].load_uA);
 455         }
 456
 457         wcnss->vregs = bulk;
 458         wcnss->num_vregs = num_vregs;
 459
 460         return 0;
 461 }
 462
 463 static int wcnss_request_irq(struct qcom_wcnss *wcnss,
 464                              struct platform_device *pdev,
 465                              const char *name,
 466                              bool optional,
 467                              irq_handler_t thread_fn)
 468 {
 469         int ret;
 470         int irq_number;
 471
 472         ret = platform_get_irq_byname(pdev, name);
 473         if (ret < 0 && optional) {
 474                 dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
 475                 return 0;
 476         } else if (ret < 0) {
 477                 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
 478                 return ret;
 479         }
 480
 481         irq_number = ret;
 482
 483         ret = devm_request_threaded_irq(&pdev->dev, ret,
 484                                         NULL, thread_fn,
 485                                         IRQF_TRIGGER_RISING | IRQF_ONESHOT,
 486                                         "wcnss", wcnss);
 487         if (ret) {
 488                 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
 489                 return ret;
 490         }
 491
 492         /* Return the IRQ number if the IRQ was successfully acquired */
 493         return irq_number;
 494 }
 495
 496 static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
 497 {
 498         struct device_node *node;
 499         struct resource r;
 500         int ret;
 501
 502         node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
 503         if (!node) {
 504                 dev_err(wcnss->dev, "no memory-region specified\n");
 505                 return -EINVAL;
 506         }
 507
 508         ret = of_address_to_resource(node, 0, &r);
 509         of_node_put(node);
 510         if (ret)
 511                 return ret;
 512
 513         wcnss->mem_phys = wcnss->mem_reloc = r.start;
 514         wcnss->mem_size = resource_size(&r);
 515         wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
 516         if (!wcnss->mem_region) {
 517                 dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
 518                         &r.start, wcnss->mem_size);
 519                 return -EBUSY;
 520         }
 521
 522         return 0;
 523 }
 524
 525 static int wcnss_probe(struct platform_device *pdev)
 526 {
 527         const char *fw_name = WCNSS_FIRMWARE_NAME;
 528         const struct wcnss_data *data;
 529         struct qcom_wcnss *wcnss;
 530         struct resource *res;
 531         struct rproc *rproc;
 532         void __iomem *mmio;
 533         int ret;
 534
 535         data = of_device_get_match_data(&pdev->dev);
 536
 537         if (!qcom_scm_is_available())
 538                 return -EPROBE_DEFER;
 539
 540         if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
 541                 dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
 542                 return -ENXIO;
 543         }
 544
 545         ret = of_property_read_string(pdev->dev.of_node, "firmware-name",
 546                                       &fw_name);
 547         if (ret < 0 && ret != -EINVAL)
 548                 return ret;
 549
 550         rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
 551                             fw_name, sizeof(*wcnss));
 552         if (!rproc) {
 553                 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
 554                 return -ENOMEM;
 555         }
 556         rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
 557
 558         wcnss = (struct qcom_wcnss *)rproc->priv;
 559         wcnss->dev = &pdev->dev;
 560         wcnss->rproc = rproc;
 561         platform_set_drvdata(pdev, wcnss);
 562
 563         init_completion(&wcnss->start_done);
 564         init_completion(&wcnss->stop_done);
 565
 566         mutex_init(&wcnss->iris_lock);
 567
 568         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
 569         mmio = devm_ioremap_resource(&pdev->dev, res);
 570         if (IS_ERR(mmio)) {
 571                 ret = PTR_ERR(mmio);
 572                 goto free_rproc;
 573         }
 574
 575         ret = wcnss_alloc_memory_region(wcnss);
 576         if (ret)
 577                 goto free_rproc;
 578
 579         wcnss->pmu_cfg = mmio + data->pmu_offset;
 580         wcnss->spare_out = mmio + data->spare_offset;
 581
 582         /*
 583          * We might need to fallback to regulators instead of power domains
 584          * for old device trees. Don't report an error in that case.
 585          */
 586         ret = wcnss_init_pds(wcnss, data->pd_names);
 587         if (ret && (ret != -ENODATA || !data->num_pd_vregs))
 588                 goto free_rproc;
 589
 590         ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs,
 591                                     data->num_pd_vregs);
 592         if (ret)
 593                 goto detach_pds;
 594
 595         ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
 596         if (ret < 0)
 597                 goto detach_pds;
 598         wcnss->wdog_irq = ret;
 599
 600         ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
 601         if (ret < 0)
 602                 goto detach_pds;
 603         wcnss->fatal_irq = ret;
 604
 605         ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
 606         if (ret < 0)
 607                 goto detach_pds;
 608         wcnss->ready_irq = ret;
 609
 610         ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
 611         if (ret < 0)
 612                 goto detach_pds;
 613         wcnss->handover_irq = ret;
 614
 615         ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
 616         if (ret < 0)
 617                 goto detach_pds;
 618         wcnss->stop_ack_irq = ret;
 619
 620         if (wcnss->stop_ack_irq) {
 621                 wcnss->state = devm_qcom_smem_state_get(&pdev->dev, "stop",
 622                                                         &wcnss->stop_bit);
 623                 if (IS_ERR(wcnss->state)) {
 624                         ret = PTR_ERR(wcnss->state);
 625                         goto detach_pds;
 626                 }
 627         }
 628
 629         qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
 630         wcnss->sysmon = qcom_add_sysmon_subdev(rproc, "wcnss", WCNSS_SSCTL_ID);
 631         if (IS_ERR(wcnss->sysmon)) {
 632                 ret = PTR_ERR(wcnss->sysmon);
 633                 goto detach_pds;
 634         }
 635
 636         wcnss->iris = qcom_iris_probe(&pdev->dev, &wcnss->use_48mhz_xo);
 637         if (IS_ERR(wcnss->iris)) {
 638                 ret = PTR_ERR(wcnss->iris);
 639                 goto detach_pds;
 640         }
 641
 642         ret = rproc_add(rproc);
 643         if (ret)
 644                 goto remove_iris;
 645
 646         return 0;
 647
 648 remove_iris:
 649         qcom_iris_remove(wcnss->iris);
 650 detach_pds:
 651         wcnss_release_pds(wcnss);
 652 free_rproc:
 653         rproc_free(rproc);
 654
 655         return ret;
 656 }
 657
 658 static int wcnss_remove(struct platform_device *pdev)
 659 {
 660         struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
 661
 662         qcom_iris_remove(wcnss->iris);
 663
 664         rproc_del(wcnss->rproc);
 665
 666         qcom_remove_sysmon_subdev(wcnss->sysmon);
 667         qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
 668         wcnss_release_pds(wcnss);
 669         rproc_free(wcnss->rproc);
 670
 671         return 0;
 672 }
 673
 674 static const struct of_device_id wcnss_of_match[] = {
 675         { .compatible = "qcom,riva-pil", &riva_data },
 676         { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
 677         { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
 678         { },
 679 };
 680 MODULE_DEVICE_TABLE(of, wcnss_of_match);
 681
 682 static struct platform_driver wcnss_driver = {
 683         .probe = wcnss_probe,
 684         .remove = wcnss_remove,
 685         .driver = {
 686                 .name = "qcom-wcnss-pil",
 687                 .of_match_table = wcnss_of_match,
 688         },
 689 };
 690
 691 module_platform_driver(wcnss_driver);
 692
 693 MODULE_DESCRIPTION("Qualcomm Peripheral Image Loader for Wireless Subsystem");
 694 MODULE_LICENSE("GPL v2");