drivers/remoteproc/qcom_wcnss.c

   1 /*
   2  * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
   3  *
   4  * Copyright (C) 2016 Linaro Ltd
   5  * Copyright (C) 2014 Sony Mobile Communications AB
   6  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * version 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/firmware.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/io.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/qcom_scm.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/remoteproc.h>
  31 #include <linux/soc/qcom/mdt_loader.h>
  32 #include <linux/soc/qcom/smem.h>
  33 #include <linux/soc/qcom/smem_state.h>
  34 #include <linux/rpmsg/qcom_smd.h>
  35
  36 #include "qcom_common.h"
  37 #include "remoteproc_internal.h"
  38 #include "qcom_wcnss.h"
  39
  40 #define WCNSS_CRASH_REASON_SMEM         422
  41 #define WCNSS_FIRMWARE_NAME             "wcnss.mdt"
  42 #define WCNSS_PAS_ID                    6
  43
  44 #define WCNSS_SPARE_NVBIN_DLND          BIT(25)
  45
  46 #define WCNSS_PMU_IRIS_XO_CFG           BIT(3)
  47 #define WCNSS_PMU_IRIS_XO_EN            BIT(4)
  48 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP    BIT(5)
  49 #define WCNSS_PMU_IRIS_XO_CFG_STS       BIT(6) /* 1: in progress, 0: done */
  50
  51 #define WCNSS_PMU_IRIS_RESET            BIT(7)
  52 #define WCNSS_PMU_IRIS_RESET_STS        BIT(8) /* 1: in progress, 0: done */
  53 #define WCNSS_PMU_IRIS_XO_READ          BIT(9)
  54 #define WCNSS_PMU_IRIS_XO_READ_STS      BIT(10)
  55
  56 #define WCNSS_PMU_XO_MODE_MASK          GENMASK(2, 1)
  57 #define WCNSS_PMU_XO_MODE_19p2          0
  58 #define WCNSS_PMU_XO_MODE_48            3
  59
  60 struct wcnss_data {
  61         size_t pmu_offset;
  62         size_t spare_offset;
  63
  64         const struct wcnss_vreg_info *vregs;
  65         size_t num_vregs;
  66 };
  67
  68 struct qcom_wcnss {
  69         struct device *dev;
  70         struct rproc *rproc;
  71
  72         void __iomem *pmu_cfg;
  73         void __iomem *spare_out;
  74
  75         bool use_48mhz_xo;
  76
  77         int wdog_irq;
  78         int fatal_irq;
  79         int ready_irq;
  80         int handover_irq;
  81         int stop_ack_irq;
  82
  83         struct qcom_smem_state *state;
  84         unsigned stop_bit;
  85
  86         struct mutex iris_lock;
  87         struct qcom_iris *iris;
  88
  89         struct regulator_bulk_data *vregs;
  90         size_t num_vregs;
  91
  92         struct completion start_done;
  93         struct completion stop_done;
  94
  95         phys_addr_t mem_phys;
  96         phys_addr_t mem_reloc;
  97         void *mem_region;
  98         size_t mem_size;
  99
 100         struct qcom_rproc_subdev smd_subdev;
 101 };
 102
 103 static const struct wcnss_data riva_data = {
 104         .pmu_offset = 0x28,
 105         .spare_offset = 0xb4,
 106
 107         .vregs = (struct wcnss_vreg_info[]) {
 108                 { "vddmx",  1050000, 1150000, 0 },
 109                 { "vddcx",  1050000, 1150000, 0 },
 110                 { "vddpx",  1800000, 1800000, 0 },
 111         },
 112         .num_vregs = 3,
 113 };
 114
 115 static const struct wcnss_data pronto_v1_data = {
 116         .pmu_offset = 0x1004,
 117         .spare_offset = 0x1088,
 118
 119         .vregs = (struct wcnss_vreg_info[]) {
 120                 { "vddmx", 950000, 1150000, 0 },
 121                 { "vddcx", .super_turbo = true},
 122                 { "vddpx", 1800000, 1800000, 0 },
 123         },
 124         .num_vregs = 3,
 125 };
 126
 127 static const struct wcnss_data pronto_v2_data = {
 128         .pmu_offset = 0x1004,
 129         .spare_offset = 0x1088,
 130
 131         .vregs = (struct wcnss_vreg_info[]) {
 132                 { "vddmx", 1287500, 1287500, 0 },
 133                 { "vddcx", .super_turbo = true },
 134                 { "vddpx", 1800000, 1800000, 0 },
 135         },
 136         .num_vregs = 3,
 137 };
 138
 139 void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
 140                             struct qcom_iris *iris,
 141                             bool use_48mhz_xo)
 142 {
 143         mutex_lock(&wcnss->iris_lock);
 144
 145         wcnss->iris = iris;
 146         wcnss->use_48mhz_xo = use_48mhz_xo;
 147
 148         mutex_unlock(&wcnss->iris_lock);
 149 }
 150
 151 static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
 152 {
 153         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 154
 155         return qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
 156                              wcnss->mem_region, wcnss->mem_phys, wcnss->mem_size);
 157 }
 158
 159 static const struct rproc_fw_ops wcnss_fw_ops = {
 160         .find_rsc_table = qcom_mdt_find_rsc_table,
 161         .load = wcnss_load,
 162 };
 163
 164 static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
 165 {
 166         u32 val;
 167
 168         /* Indicate NV download capability */
 169         val = readl(wcnss->spare_out);
 170         val |= WCNSS_SPARE_NVBIN_DLND;
 171         writel(val, wcnss->spare_out);
 172 }
 173
 174 static void wcnss_configure_iris(struct qcom_wcnss *wcnss)
 175 {
 176         u32 val;
 177
 178         /* Clear PMU cfg register */
 179         writel(0, wcnss->pmu_cfg);
 180
 181         val = WCNSS_PMU_GC_BUS_MUX_SEL_TOP | WCNSS_PMU_IRIS_XO_EN;
 182         writel(val, wcnss->pmu_cfg);
 183
 184         /* Clear XO_MODE */
 185         val &= ~WCNSS_PMU_XO_MODE_MASK;
 186         if (wcnss->use_48mhz_xo)
 187                 val |= WCNSS_PMU_XO_MODE_48 << 1;
 188         else
 189                 val |= WCNSS_PMU_XO_MODE_19p2 << 1;
 190         writel(val, wcnss->pmu_cfg);
 191
 192         /* Reset IRIS */
 193         val |= WCNSS_PMU_IRIS_RESET;
 194         writel(val, wcnss->pmu_cfg);
 195
 196         /* Wait for PMU.iris_reg_reset_sts */
 197         while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_RESET_STS)
 198                 cpu_relax();
 199
 200         /* Clear IRIS reset */
 201         val &= ~WCNSS_PMU_IRIS_RESET;
 202         writel(val, wcnss->pmu_cfg);
 203
 204         /* Start IRIS XO configuration */
 205         val |= WCNSS_PMU_IRIS_XO_CFG;
 206         writel(val, wcnss->pmu_cfg);
 207
 208         /* Wait for XO configuration to finish */
 209         while (readl(wcnss->pmu_cfg) & WCNSS_PMU_IRIS_XO_CFG_STS)
 210                 cpu_relax();
 211
 212         /* Stop IRIS XO configuration */
 213         val &= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP;
 214         val &= ~WCNSS_PMU_IRIS_XO_CFG;
 215         writel(val, wcnss->pmu_cfg);
 216
 217         /* Add some delay for XO to settle */
 218         msleep(20);
 219 }
 220
 221 static int wcnss_start(struct rproc *rproc)
 222 {
 223         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 224         int ret;
 225
 226         mutex_lock(&wcnss->iris_lock);
 227         if (!wcnss->iris) {
 228                 dev_err(wcnss->dev, "no iris registered\n");
 229                 ret = -EINVAL;
 230                 goto release_iris_lock;
 231         }
 232
 233         ret = regulator_bulk_enable(wcnss->num_vregs, wcnss->vregs);
 234         if (ret)
 235                 goto release_iris_lock;
 236
 237         ret = qcom_iris_enable(wcnss->iris);
 238         if (ret)
 239                 goto disable_regulators;
 240
 241         wcnss_indicate_nv_download(wcnss);
 242         wcnss_configure_iris(wcnss);
 243
 244         ret = qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID);
 245         if (ret) {
 246                 dev_err(wcnss->dev,
 247                         "failed to authenticate image and release reset\n");
 248                 goto disable_iris;
 249         }
 250
 251         ret = wait_for_completion_timeout(&wcnss->start_done,
 252                                           msecs_to_jiffies(5000));
 253         if (wcnss->ready_irq > 0 && ret == 0) {
 254                 /* We have a ready_irq, but it didn't fire in time. */
 255                 dev_err(wcnss->dev, "start timed out\n");
 256                 qcom_scm_pas_shutdown(WCNSS_PAS_ID);
 257                 ret = -ETIMEDOUT;
 258                 goto disable_iris;
 259         }
 260
 261         ret = 0;
 262
 263 disable_iris:
 264         qcom_iris_disable(wcnss->iris);
 265 disable_regulators:
 266         regulator_bulk_disable(wcnss->num_vregs, wcnss->vregs);
 267 release_iris_lock:
 268         mutex_unlock(&wcnss->iris_lock);
 269
 270         return ret;
 271 }
 272
 273 static int wcnss_stop(struct rproc *rproc)
 274 {
 275         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 276         int ret;
 277
 278         if (wcnss->state) {
 279                 qcom_smem_state_update_bits(wcnss->state,
 280                                             BIT(wcnss->stop_bit),
 281                                             BIT(wcnss->stop_bit));
 282
 283                 ret = wait_for_completion_timeout(&wcnss->stop_done,
 284                                                   msecs_to_jiffies(5000));
 285                 if (ret == 0)
 286                         dev_err(wcnss->dev, "timed out on wait\n");
 287
 288                 qcom_smem_state_update_bits(wcnss->state,
 289                                             BIT(wcnss->stop_bit),
 290                                             0);
 291         }
 292
 293         ret = qcom_scm_pas_shutdown(WCNSS_PAS_ID);
 294         if (ret)
 295                 dev_err(wcnss->dev, "failed to shutdown: %d\n", ret);
 296
 297         return ret;
 298 }
 299
 300 static void *wcnss_da_to_va(struct rproc *rproc, u64 da, int len)
 301 {
 302         struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
 303         int offset;
 304
 305         offset = da - wcnss->mem_reloc;
 306         if (offset < 0 || offset + len > wcnss->mem_size)
 307                 return NULL;
 308
 309         return wcnss->mem_region + offset;
 310 }
 311
 312 static const struct rproc_ops wcnss_ops = {
 313         .start = wcnss_start,
 314         .stop = wcnss_stop,
 315         .da_to_va = wcnss_da_to_va,
 316 };
 317
 318 static irqreturn_t wcnss_wdog_interrupt(int irq, void *dev)
 319 {
 320         struct qcom_wcnss *wcnss = dev;
 321
 322         rproc_report_crash(wcnss->rproc, RPROC_WATCHDOG);
 323
 324         return IRQ_HANDLED;
 325 }
 326
 327 static irqreturn_t wcnss_fatal_interrupt(int irq, void *dev)
 328 {
 329         struct qcom_wcnss *wcnss = dev;
 330         size_t len;
 331         char *msg;
 332
 333         msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, WCNSS_CRASH_REASON_SMEM, &len);
 334         if (!IS_ERR(msg) && len > 0 && msg[0])
 335                 dev_err(wcnss->dev, "fatal error received: %s\n", msg);
 336
 337         rproc_report_crash(wcnss->rproc, RPROC_FATAL_ERROR);
 338
 339         if (!IS_ERR(msg))
 340                 msg[0] = '\0';
 341
 342         return IRQ_HANDLED;
 343 }
 344
 345 static irqreturn_t wcnss_ready_interrupt(int irq, void *dev)
 346 {
 347         struct qcom_wcnss *wcnss = dev;
 348
 349         complete(&wcnss->start_done);
 350
 351         return IRQ_HANDLED;
 352 }
 353
 354 static irqreturn_t wcnss_handover_interrupt(int irq, void *dev)
 355 {
 356         /*
 357          * XXX: At this point we're supposed to release the resources that we
 358          * have been holding on behalf of the WCNSS. Unfortunately this
 359          * interrupt comes way before the other side seems to be done.
 360          *
 361          * So we're currently relying on the ready interrupt firing later then
 362          * this and we just disable the resources at the end of wcnss_start().
 363          */
 364
 365         return IRQ_HANDLED;
 366 }
 367
 368 static irqreturn_t wcnss_stop_ack_interrupt(int irq, void *dev)
 369 {
 370         struct qcom_wcnss *wcnss = dev;
 371
 372         complete(&wcnss->stop_done);
 373
 374         return IRQ_HANDLED;
 375 }
 376
 377 static int wcnss_init_regulators(struct qcom_wcnss *wcnss,
 378                                  const struct wcnss_vreg_info *info,
 379                                  int num_vregs)
 380 {
 381         struct regulator_bulk_data *bulk;
 382         int ret;
 383         int i;
 384
 385         bulk = devm_kcalloc(wcnss->dev,
 386                             num_vregs, sizeof(struct regulator_bulk_data),
 387                             GFP_KERNEL);
 388         if (!bulk)
 389                 return -ENOMEM;
 390
 391         for (i = 0; i < num_vregs; i++)
 392                 bulk[i].supply = info[i].name;
 393
 394         ret = devm_regulator_bulk_get(wcnss->dev, num_vregs, bulk);
 395         if (ret)
 396                 return ret;
 397
 398         for (i = 0; i < num_vregs; i++) {
 399                 if (info[i].max_voltage)
 400                         regulator_set_voltage(bulk[i].consumer,
 401                                               info[i].min_voltage,
 402                                               info[i].max_voltage);
 403
 404                 if (info[i].load_uA)
 405                         regulator_set_load(bulk[i].consumer, info[i].load_uA);
 406         }
 407
 408         wcnss->vregs = bulk;
 409         wcnss->num_vregs = num_vregs;
 410
 411         return 0;
 412 }
 413
 414 static int wcnss_request_irq(struct qcom_wcnss *wcnss,
 415                              struct platform_device *pdev,
 416                              const char *name,
 417                              bool optional,
 418                              irq_handler_t thread_fn)
 419 {
 420         int ret;
 421
 422         ret = platform_get_irq_byname(pdev, name);
 423         if (ret < 0 && optional) {
 424                 dev_dbg(&pdev->dev, "no %s IRQ defined, ignoring\n", name);
 425                 return 0;
 426         } else if (ret < 0) {
 427                 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
 428                 return ret;
 429         }
 430
 431         ret = devm_request_threaded_irq(&pdev->dev, ret,
 432                                         NULL, thread_fn,
 433                                         IRQF_TRIGGER_RISING | IRQF_ONESHOT,
 434                                         "wcnss", wcnss);
 435         if (ret)
 436                 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
 437
 438         return ret;
 439 }
 440
 441 static int wcnss_alloc_memory_region(struct qcom_wcnss *wcnss)
 442 {
 443         struct device_node *node;
 444         struct resource r;
 445         int ret;
 446
 447         node = of_parse_phandle(wcnss->dev->of_node, "memory-region", 0);
 448         if (!node) {
 449                 dev_err(wcnss->dev, "no memory-region specified\n");
 450                 return -EINVAL;
 451         }
 452
 453         ret = of_address_to_resource(node, 0, &r);
 454         if (ret)
 455                 return ret;
 456
 457         wcnss->mem_phys = wcnss->mem_reloc = r.start;
 458         wcnss->mem_size = resource_size(&r);
 459         wcnss->mem_region = devm_ioremap_wc(wcnss->dev, wcnss->mem_phys, wcnss->mem_size);
 460         if (!wcnss->mem_region) {
 461                 dev_err(wcnss->dev, "unable to map memory region: %pa+%zx\n",
 462                         &r.start, wcnss->mem_size);
 463                 return -EBUSY;
 464         }
 465
 466         return 0;
 467 }
 468
 469 static int wcnss_probe(struct platform_device *pdev)
 470 {
 471         const struct wcnss_data *data;
 472         struct qcom_wcnss *wcnss;
 473         struct resource *res;
 474         struct rproc *rproc;
 475         void __iomem *mmio;
 476         int ret;
 477
 478         data = of_device_get_match_data(&pdev->dev);
 479
 480         if (!qcom_scm_is_available())
 481                 return -EPROBE_DEFER;
 482
 483         if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) {
 484                 dev_err(&pdev->dev, "PAS is not available for WCNSS\n");
 485                 return -ENXIO;
 486         }
 487
 488         rproc = rproc_alloc(&pdev->dev, pdev->name, &wcnss_ops,
 489                             WCNSS_FIRMWARE_NAME, sizeof(*wcnss));
 490         if (!rproc) {
 491                 dev_err(&pdev->dev, "unable to allocate remoteproc\n");
 492                 return -ENOMEM;
 493         }
 494
 495         rproc->fw_ops = &wcnss_fw_ops;
 496
 497         wcnss = (struct qcom_wcnss *)rproc->priv;
 498         wcnss->dev = &pdev->dev;
 499         wcnss->rproc = rproc;
 500         platform_set_drvdata(pdev, wcnss);
 501
 502         init_completion(&wcnss->start_done);
 503         init_completion(&wcnss->stop_done);
 504
 505         mutex_init(&wcnss->iris_lock);
 506
 507         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmu");
 508         mmio = devm_ioremap_resource(&pdev->dev, res);
 509         if (IS_ERR(mmio)) {
 510                 ret = PTR_ERR(mmio);
 511                 goto free_rproc;
 512         };
 513
 514         ret = wcnss_alloc_memory_region(wcnss);
 515         if (ret)
 516                 goto free_rproc;
 517
 518         wcnss->pmu_cfg = mmio + data->pmu_offset;
 519         wcnss->spare_out = mmio + data->spare_offset;
 520
 521         ret = wcnss_init_regulators(wcnss, data->vregs, data->num_vregs);
 522         if (ret)
 523                 goto free_rproc;
 524
 525         ret = wcnss_request_irq(wcnss, pdev, "wdog", false, wcnss_wdog_interrupt);
 526         if (ret < 0)
 527                 goto free_rproc;
 528         wcnss->wdog_irq = ret;
 529
 530         ret = wcnss_request_irq(wcnss, pdev, "fatal", false, wcnss_fatal_interrupt);
 531         if (ret < 0)
 532                 goto free_rproc;
 533         wcnss->fatal_irq = ret;
 534
 535         ret = wcnss_request_irq(wcnss, pdev, "ready", true, wcnss_ready_interrupt);
 536         if (ret < 0)
 537                 goto free_rproc;
 538         wcnss->ready_irq = ret;
 539
 540         ret = wcnss_request_irq(wcnss, pdev, "handover", true, wcnss_handover_interrupt);
 541         if (ret < 0)
 542                 goto free_rproc;
 543         wcnss->handover_irq = ret;
 544
 545         ret = wcnss_request_irq(wcnss, pdev, "stop-ack", true, wcnss_stop_ack_interrupt);
 546         if (ret < 0)
 547                 goto free_rproc;
 548         wcnss->stop_ack_irq = ret;
 549
 550         if (wcnss->stop_ack_irq) {
 551                 wcnss->state = qcom_smem_state_get(&pdev->dev, "stop",
 552                                                    &wcnss->stop_bit);
 553                 if (IS_ERR(wcnss->state)) {
 554                         ret = PTR_ERR(wcnss->state);
 555                         goto free_rproc;
 556                 }
 557         }
 558
 559         qcom_add_smd_subdev(rproc, &wcnss->smd_subdev);
 560
 561         ret = rproc_add(rproc);
 562         if (ret)
 563                 goto free_rproc;
 564
 565         return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
 566
 567 free_rproc:
 568         rproc_free(rproc);
 569
 570         return ret;
 571 }
 572
 573 static int wcnss_remove(struct platform_device *pdev)
 574 {
 575         struct qcom_wcnss *wcnss = platform_get_drvdata(pdev);
 576
 577         of_platform_depopulate(&pdev->dev);
 578
 579         qcom_smem_state_put(wcnss->state);
 580         rproc_del(wcnss->rproc);
 581
 582         qcom_remove_smd_subdev(wcnss->rproc, &wcnss->smd_subdev);
 583         rproc_free(wcnss->rproc);
 584
 585         return 0;
 586 }
 587
 588 static const struct of_device_id wcnss_of_match[] = {
 589         { .compatible = "qcom,riva-pil", &riva_data },
 590         { .compatible = "qcom,pronto-v1-pil", &pronto_v1_data },
 591         { .compatible = "qcom,pronto-v2-pil", &pronto_v2_data },
 592         { },
 593 };
 594 MODULE_DEVICE_TABLE(of, wcnss_of_match);
 595
 596 static struct platform_driver wcnss_driver = {
 597         .probe = wcnss_probe,
 598         .remove = wcnss_remove,
 599         .driver = {
 600                 .name = "qcom-wcnss-pil",
 601                 .of_match_table = wcnss_of_match,
 602         },
 603 };
 604
 605 static int __init wcnss_init(void)
 606 {
 607         int ret;
 608
 609         ret = platform_driver_register(&wcnss_driver);
 610         if (ret)
 611                 return ret;
 612
 613         ret = platform_driver_register(&qcom_iris_driver);
 614         if (ret)
 615                 platform_driver_unregister(&wcnss_driver);
 616
 617         return ret;
 618 }
 619 module_init(wcnss_init);
 620
 621 static void __exit wcnss_exit(void)
 622 {
 623         platform_driver_unregister(&qcom_iris_driver);
 624         platform_driver_unregister(&wcnss_driver);
 625 }
 626 module_exit(wcnss_exit);
 627
 628 MODULE_DESCRIPTION("Qualcomm Peripherial Image Loader for Wireless Subsystem");
 629 MODULE_LICENSE("GPL v2");