drivers/remoteproc/qcom_q6v5_wcss.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Linaro Ltd.
   4  * Copyright (C) 2014 Sony Mobile Communications AB
   5  * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
   6  */
   7 #include <linux/clk.h>
   8 #include <linux/delay.h>
   9 #include <linux/io.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/kernel.h>
  12 #include <linux/mfd/syscon.h>
  13 #include <linux/module.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_reserved_mem.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/regmap.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/soc/qcom/mdt_loader.h>
  21 #include "qcom_common.h"
  22 #include "qcom_pil_info.h"
  23 #include "qcom_q6v5.h"
  24
  25 #define WCSS_CRASH_REASON               421
  26
  27 /* Q6SS Register Offsets */
  28 #define Q6SS_RESET_REG          0x014
  29 #define Q6SS_GFMUX_CTL_REG              0x020
  30 #define Q6SS_PWR_CTL_REG                0x030
  31 #define Q6SS_MEM_PWR_CTL                0x0B0
  32 #define Q6SS_STRAP_ACC                  0x110
  33 #define Q6SS_CGC_OVERRIDE               0x034
  34 #define Q6SS_BCR_REG                    0x6000
  35
  36 /* AXI Halt Register Offsets */
  37 #define AXI_HALTREQ_REG                 0x0
  38 #define AXI_HALTACK_REG                 0x4
  39 #define AXI_IDLE_REG                    0x8
  40
  41 #define HALT_ACK_TIMEOUT_MS             100
  42
  43 /* Q6SS_RESET */
  44 #define Q6SS_STOP_CORE                  BIT(0)
  45 #define Q6SS_CORE_ARES                  BIT(1)
  46 #define Q6SS_BUS_ARES_ENABLE            BIT(2)
  47
  48 /* Q6SS_BRC_RESET */
  49 #define Q6SS_BRC_BLK_ARES               BIT(0)
  50
  51 /* Q6SS_GFMUX_CTL */
  52 #define Q6SS_CLK_ENABLE                 BIT(1)
  53 #define Q6SS_SWITCH_CLK_SRC             BIT(8)
  54
  55 /* Q6SS_PWR_CTL */
  56 #define Q6SS_L2DATA_STBY_N              BIT(18)
  57 #define Q6SS_SLP_RET_N                  BIT(19)
  58 #define Q6SS_CLAMP_IO                   BIT(20)
  59 #define QDSS_BHS_ON                     BIT(21)
  60 #define QDSS_Q6_MEMORIES                GENMASK(15, 0)
  61
  62 /* Q6SS parameters */
  63 #define Q6SS_LDO_BYP            BIT(25)
  64 #define Q6SS_BHS_ON             BIT(24)
  65 #define Q6SS_CLAMP_WL           BIT(21)
  66 #define Q6SS_CLAMP_QMC_MEM              BIT(22)
  67 #define HALT_CHECK_MAX_LOOPS            200
  68 #define Q6SS_XO_CBCR            GENMASK(5, 3)
  69 #define Q6SS_SLEEP_CBCR         GENMASK(5, 2)
  70
  71 /* Q6SS config/status registers */
  72 #define TCSR_GLOBAL_CFG0        0x0
  73 #define TCSR_GLOBAL_CFG1        0x4
  74 #define SSCAON_CONFIG           0x8
  75 #define SSCAON_STATUS           0xc
  76 #define Q6SS_BHS_STATUS         0x78
  77 #define Q6SS_RST_EVB            0x10
  78
  79 #define BHS_EN_REST_ACK         BIT(0)
  80 #define SSCAON_ENABLE           BIT(13)
  81 #define SSCAON_BUS_EN           BIT(15)
  82 #define SSCAON_BUS_MUX_MASK     GENMASK(18, 16)
  83
  84 #define MEM_BANKS               19
  85 #define TCSR_WCSS_CLK_MASK      0x1F
  86 #define TCSR_WCSS_CLK_ENABLE    0x14
  87
  88 #define MAX_HALT_REG            3
  89 enum {
  90         WCSS_IPQ8074,
  91         WCSS_QCS404,
  92 };
  93
  94 struct wcss_data {
  95         const char *firmware_name;
  96         unsigned int crash_reason_smem;
  97         u32 version;
  98         bool aon_reset_required;
  99         bool wcss_q6_reset_required;
 100         const char *ssr_name;
 101         const char *sysmon_name;
 102         int ssctl_id;
 103         const struct rproc_ops *ops;
 104         bool requires_force_stop;
 105 };
 106
 107 struct q6v5_wcss {
 108         struct device *dev;
 109
 110         void __iomem *reg_base;
 111         void __iomem *rmb_base;
 112
 113         struct regmap *halt_map;
 114         u32 halt_q6;
 115         u32 halt_wcss;
 116         u32 halt_nc;
 117
 118         struct clk *xo;
 119         struct clk *ahbfabric_cbcr_clk;
 120         struct clk *gcc_abhs_cbcr;
 121         struct clk *gcc_axim_cbcr;
 122         struct clk *lcc_csr_cbcr;
 123         struct clk *ahbs_cbcr;
 124         struct clk *tcm_slave_cbcr;
 125         struct clk *qdsp6ss_abhm_cbcr;
 126         struct clk *qdsp6ss_sleep_cbcr;
 127         struct clk *qdsp6ss_axim_cbcr;
 128         struct clk *qdsp6ss_xo_cbcr;
 129         struct clk *qdsp6ss_core_gfmux;
 130         struct clk *lcc_bcr_sleep;
 131         struct regulator *cx_supply;
 132         struct qcom_sysmon *sysmon;
 133
 134         struct reset_control *wcss_aon_reset;
 135         struct reset_control *wcss_reset;
 136         struct reset_control *wcss_q6_reset;
 137         struct reset_control *wcss_q6_bcr_reset;
 138
 139         struct qcom_q6v5 q6v5;
 140
 141         phys_addr_t mem_phys;
 142         phys_addr_t mem_reloc;
 143         void *mem_region;
 144         size_t mem_size;
 145
 146         unsigned int crash_reason_smem;
 147         u32 version;
 148         bool requires_force_stop;
 149
 150         struct qcom_rproc_glink glink_subdev;
 151         struct qcom_rproc_ssr ssr_subdev;
 152 };
 153
 154 static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
 155 {
 156         int ret;
 157         u32 val;
 158         int i;
 159
 160         /* Assert resets, stop core */
 161         val = readl(wcss->reg_base + Q6SS_RESET_REG);
 162         val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 163         writel(val, wcss->reg_base + Q6SS_RESET_REG);
 164
 165         /* BHS require xo cbcr to be enabled */
 166         val = readl(wcss->reg_base + Q6SS_XO_CBCR);
 167         val |= 0x1;
 168         writel(val, wcss->reg_base + Q6SS_XO_CBCR);
 169
 170         /* Read CLKOFF bit to go low indicating CLK is enabled */
 171         ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR,
 172                                  val, !(val & BIT(31)), 1,
 173                                  HALT_CHECK_MAX_LOOPS);
 174         if (ret) {
 175                 dev_err(wcss->dev,
 176                         "xo cbcr enabling timed out (rc:%d)\n", ret);
 177                 return ret;
 178         }
 179         /* Enable power block headswitch and wait for it to stabilize */
 180         val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
 181         val |= Q6SS_BHS_ON;
 182         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 183         udelay(1);
 184
 185         /* Put LDO in bypass mode */
 186         val |= Q6SS_LDO_BYP;
 187         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 188
 189         /* Deassert Q6 compiler memory clamp */
 190         val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
 191         val &= ~Q6SS_CLAMP_QMC_MEM;
 192         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 193
 194         /* Deassert memory peripheral sleep and L2 memory standby */
 195         val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
 196         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 197
 198         /* Turn on L1, L2, ETB and JU memories 1 at a time */
 199         val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
 200         for (i = MEM_BANKS; i >= 0; i--) {
 201                 val |= BIT(i);
 202                 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
 203                 /*
 204                  * Read back value to ensure the write is done then
 205                  * wait for 1us for both memory peripheral and data
 206                  * array to turn on.
 207                  */
 208                 val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
 209                 udelay(1);
 210         }
 211         /* Remove word line clamp */
 212         val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
 213         val &= ~Q6SS_CLAMP_WL;
 214         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 215
 216         /* Remove IO clamp */
 217         val &= ~Q6SS_CLAMP_IO;
 218         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 219
 220         /* Bring core out of reset */
 221         val = readl(wcss->reg_base + Q6SS_RESET_REG);
 222         val &= ~Q6SS_CORE_ARES;
 223         writel(val, wcss->reg_base + Q6SS_RESET_REG);
 224
 225         /* Turn on core clock */
 226         val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
 227         val |= Q6SS_CLK_ENABLE;
 228         writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
 229
 230         /* Start core execution */
 231         val = readl(wcss->reg_base + Q6SS_RESET_REG);
 232         val &= ~Q6SS_STOP_CORE;
 233         writel(val, wcss->reg_base + Q6SS_RESET_REG);
 234
 235         return 0;
 236 }
 237
 238 static int q6v5_wcss_start(struct rproc *rproc)
 239 {
 240         struct q6v5_wcss *wcss = rproc->priv;
 241         int ret;
 242
 243         qcom_q6v5_prepare(&wcss->q6v5);
 244
 245         /* Release Q6 and WCSS reset */
 246         ret = reset_control_deassert(wcss->wcss_reset);
 247         if (ret) {
 248                 dev_err(wcss->dev, "wcss_reset failed\n");
 249                 return ret;
 250         }
 251
 252         ret = reset_control_deassert(wcss->wcss_q6_reset);
 253         if (ret) {
 254                 dev_err(wcss->dev, "wcss_q6_reset failed\n");
 255                 goto wcss_reset;
 256         }
 257
 258         /* Lithium configuration - clock gating and bus arbitration */
 259         ret = regmap_update_bits(wcss->halt_map,
 260                                  wcss->halt_nc + TCSR_GLOBAL_CFG0,
 261                                  TCSR_WCSS_CLK_MASK,
 262                                  TCSR_WCSS_CLK_ENABLE);
 263         if (ret)
 264                 goto wcss_q6_reset;
 265
 266         ret = regmap_update_bits(wcss->halt_map,
 267                                  wcss->halt_nc + TCSR_GLOBAL_CFG1,
 268                                  1, 0);
 269         if (ret)
 270                 goto wcss_q6_reset;
 271
 272         /* Write bootaddr to EVB so that Q6WCSS will jump there after reset */
 273         writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);
 274
 275         ret = q6v5_wcss_reset(wcss);
 276         if (ret)
 277                 goto wcss_q6_reset;
 278
 279         ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
 280         if (ret == -ETIMEDOUT)
 281                 dev_err(wcss->dev, "start timed out\n");
 282
 283         return ret;
 284
 285 wcss_q6_reset:
 286         reset_control_assert(wcss->wcss_q6_reset);
 287
 288 wcss_reset:
 289         reset_control_assert(wcss->wcss_reset);
 290
 291         return ret;
 292 }
 293
 294 static int q6v5_wcss_qcs404_power_on(struct q6v5_wcss *wcss)
 295 {
 296         unsigned long val;
 297         int ret, idx;
 298
 299         /* Toggle the restart */
 300         reset_control_assert(wcss->wcss_reset);
 301         usleep_range(200, 300);
 302         reset_control_deassert(wcss->wcss_reset);
 303         usleep_range(200, 300);
 304
 305         /* Enable GCC_WDSP_Q6SS_AHBS_CBCR clock */
 306         ret = clk_prepare_enable(wcss->gcc_abhs_cbcr);
 307         if (ret)
 308                 return ret;
 309
 310         /* Remove reset to the WCNSS QDSP6SS */
 311         reset_control_deassert(wcss->wcss_q6_bcr_reset);
 312
 313         /* Enable Q6SSTOP_AHBFABRIC_CBCR clock */
 314         ret = clk_prepare_enable(wcss->ahbfabric_cbcr_clk);
 315         if (ret)
 316                 goto disable_gcc_abhs_cbcr_clk;
 317
 318         /* Enable the LCCCSR CBC clock, Q6SSTOP_Q6SSTOP_LCC_CSR_CBCR clock */
 319         ret = clk_prepare_enable(wcss->lcc_csr_cbcr);
 320         if (ret)
 321                 goto disable_ahbfabric_cbcr_clk;
 322
 323         /* Enable the Q6AHBS CBC, Q6SSTOP_Q6SS_AHBS_CBCR clock */
 324         ret = clk_prepare_enable(wcss->ahbs_cbcr);
 325         if (ret)
 326                 goto disable_csr_cbcr_clk;
 327
 328         /* Enable the TCM slave CBC, Q6SSTOP_Q6SS_TCM_SLAVE_CBCR clock */
 329         ret = clk_prepare_enable(wcss->tcm_slave_cbcr);
 330         if (ret)
 331                 goto disable_ahbs_cbcr_clk;
 332
 333         /* Enable the Q6SS AHB master CBC, Q6SSTOP_Q6SS_AHBM_CBCR clock */
 334         ret = clk_prepare_enable(wcss->qdsp6ss_abhm_cbcr);
 335         if (ret)
 336                 goto disable_tcm_slave_cbcr_clk;
 337
 338         /* Enable the Q6SS AXI master CBC, Q6SSTOP_Q6SS_AXIM_CBCR clock */
 339         ret = clk_prepare_enable(wcss->qdsp6ss_axim_cbcr);
 340         if (ret)
 341                 goto disable_abhm_cbcr_clk;
 342
 343         /* Enable the Q6SS XO CBC */
 344         val = readl(wcss->reg_base + Q6SS_XO_CBCR);
 345         val |= BIT(0);
 346         writel(val, wcss->reg_base + Q6SS_XO_CBCR);
 347         /* Read CLKOFF bit to go low indicating CLK is enabled */
 348         ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR,
 349                                  val, !(val & BIT(31)), 1,
 350                                  HALT_CHECK_MAX_LOOPS);
 351         if (ret) {
 352                 dev_err(wcss->dev,
 353                         "xo cbcr enabling timed out (rc:%d)\n", ret);
 354                 return ret;
 355         }
 356
 357         writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE);
 358
 359         /* Enable QDSP6 sleep clock clock */
 360         val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
 361         val |= BIT(0);
 362         writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
 363
 364         /* Enable the Enable the Q6 AXI clock, GCC_WDSP_Q6SS_AXIM_CBCR*/
 365         ret = clk_prepare_enable(wcss->gcc_axim_cbcr);
 366         if (ret)
 367                 goto disable_sleep_cbcr_clk;
 368
 369         /* Assert resets, stop core */
 370         val = readl(wcss->reg_base + Q6SS_RESET_REG);
 371         val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 372         writel(val, wcss->reg_base + Q6SS_RESET_REG);
 373
 374         /* Program the QDSP6SS PWR_CTL register */
 375         writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
 376
 377         writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
 378
 379         writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG);
 380
 381         writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
 382
 383         /*
 384          * Enable memories by turning on the QDSP6 memory foot/head switch, one
 385          * bank at a time to avoid in-rush current
 386          */
 387         for (idx = 28; idx >= 0; idx--) {
 388                 writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) |
 389                         (1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL);
 390         }
 391
 392         writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
 393         writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
 394
 395         val = readl(wcss->reg_base + Q6SS_RESET_REG);
 396         val &= ~Q6SS_CORE_ARES;
 397         writel(val, wcss->reg_base + Q6SS_RESET_REG);
 398
 399         /* Enable the Q6 core clock at the GFM, Q6SSTOP_QDSP6SS_GFMUX_CTL */
 400         val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
 401         val |= Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC;
 402         writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
 403
 404         /* Enable sleep clock branch needed for BCR circuit */
 405         ret = clk_prepare_enable(wcss->lcc_bcr_sleep);
 406         if (ret)
 407                 goto disable_core_gfmux_clk;
 408
 409         return 0;
 410
 411 disable_core_gfmux_clk:
 412         val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
 413         val &= ~(Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC);
 414         writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
 415         clk_disable_unprepare(wcss->gcc_axim_cbcr);
 416 disable_sleep_cbcr_clk:
 417         val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
 418         val &= ~Q6SS_CLK_ENABLE;
 419         writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
 420         val = readl(wcss->reg_base + Q6SS_XO_CBCR);
 421         val &= ~Q6SS_CLK_ENABLE;
 422         writel(val, wcss->reg_base + Q6SS_XO_CBCR);
 423         clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr);
 424 disable_abhm_cbcr_clk:
 425         clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr);
 426 disable_tcm_slave_cbcr_clk:
 427         clk_disable_unprepare(wcss->tcm_slave_cbcr);
 428 disable_ahbs_cbcr_clk:
 429         clk_disable_unprepare(wcss->ahbs_cbcr);
 430 disable_csr_cbcr_clk:
 431         clk_disable_unprepare(wcss->lcc_csr_cbcr);
 432 disable_ahbfabric_cbcr_clk:
 433         clk_disable_unprepare(wcss->ahbfabric_cbcr_clk);
 434 disable_gcc_abhs_cbcr_clk:
 435         clk_disable_unprepare(wcss->gcc_abhs_cbcr);
 436
 437         return ret;
 438 }
 439
 440 static inline int q6v5_wcss_qcs404_reset(struct q6v5_wcss *wcss)
 441 {
 442         unsigned long val;
 443
 444         writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC);
 445
 446         /* Start core execution */
 447         val = readl(wcss->reg_base + Q6SS_RESET_REG);
 448         val &= ~Q6SS_STOP_CORE;
 449         writel(val, wcss->reg_base + Q6SS_RESET_REG);
 450
 451         return 0;
 452 }
 453
 454 static int q6v5_qcs404_wcss_start(struct rproc *rproc)
 455 {
 456         struct q6v5_wcss *wcss = rproc->priv;
 457         int ret;
 458
 459         ret = clk_prepare_enable(wcss->xo);
 460         if (ret)
 461                 return ret;
 462
 463         ret = regulator_enable(wcss->cx_supply);
 464         if (ret)
 465                 goto disable_xo_clk;
 466
 467         qcom_q6v5_prepare(&wcss->q6v5);
 468
 469         ret = q6v5_wcss_qcs404_power_on(wcss);
 470         if (ret) {
 471                 dev_err(wcss->dev, "wcss clk_enable failed\n");
 472                 goto disable_cx_supply;
 473         }
 474
 475         writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);
 476
 477         q6v5_wcss_qcs404_reset(wcss);
 478
 479         ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
 480         if (ret == -ETIMEDOUT) {
 481                 dev_err(wcss->dev, "start timed out\n");
 482                 goto disable_cx_supply;
 483         }
 484
 485         return 0;
 486
 487 disable_cx_supply:
 488         regulator_disable(wcss->cx_supply);
 489 disable_xo_clk:
 490         clk_disable_unprepare(wcss->xo);
 491
 492         return ret;
 493 }
 494
 495 static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss,
 496                                     struct regmap *halt_map,
 497                                     u32 offset)
 498 {
 499         unsigned long timeout;
 500         unsigned int val;
 501         int ret;
 502
 503         /* Check if we're already idle */
 504         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 505         if (!ret && val)
 506                 return;
 507
 508         /* Assert halt request */
 509         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
 510
 511         /* Wait for halt */
 512         timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
 513         for (;;) {
 514                 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
 515                 if (ret || val || time_after(jiffies, timeout))
 516                         break;
 517
 518                 msleep(1);
 519         }
 520
 521         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 522         if (ret || !val)
 523                 dev_err(wcss->dev, "port failed halt\n");
 524
 525         /* Clear halt request (port will remain halted until reset) */
 526         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 527 }
 528
 529 static int q6v5_qcs404_wcss_shutdown(struct q6v5_wcss *wcss)
 530 {
 531         unsigned long val;
 532         int ret;
 533
 534         q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss);
 535
 536         /* assert clamps to avoid MX current inrush */
 537         val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
 538         val |= (Q6SS_CLAMP_IO | Q6SS_CLAMP_WL | Q6SS_CLAMP_QMC_MEM);
 539         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 540
 541         /* Disable memories by turning off memory foot/headswitch */
 542         writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) &
 543                 ~QDSS_Q6_MEMORIES),
 544                 wcss->reg_base + Q6SS_MEM_PWR_CTL);
 545
 546         /* Clear the BHS_ON bit */
 547         val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
 548         val &= ~Q6SS_BHS_ON;
 549         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 550
 551         clk_disable_unprepare(wcss->ahbfabric_cbcr_clk);
 552         clk_disable_unprepare(wcss->lcc_csr_cbcr);
 553         clk_disable_unprepare(wcss->tcm_slave_cbcr);
 554         clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr);
 555         clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr);
 556
 557         val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR);
 558         val &= ~BIT(0);
 559         writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR);
 560
 561         val = readl(wcss->reg_base + Q6SS_XO_CBCR);
 562         val &= ~BIT(0);
 563         writel(val, wcss->reg_base + Q6SS_XO_CBCR);
 564
 565         clk_disable_unprepare(wcss->ahbs_cbcr);
 566         clk_disable_unprepare(wcss->lcc_bcr_sleep);
 567
 568         val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
 569         val &= ~(Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC);
 570         writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
 571
 572         clk_disable_unprepare(wcss->gcc_abhs_cbcr);
 573
 574         ret = reset_control_assert(wcss->wcss_reset);
 575         if (ret) {
 576                 dev_err(wcss->dev, "wcss_reset failed\n");
 577                 return ret;
 578         }
 579         usleep_range(200, 300);
 580
 581         ret = reset_control_deassert(wcss->wcss_reset);
 582         if (ret) {
 583                 dev_err(wcss->dev, "wcss_reset failed\n");
 584                 return ret;
 585         }
 586         usleep_range(200, 300);
 587
 588         clk_disable_unprepare(wcss->gcc_axim_cbcr);
 589
 590         return 0;
 591 }
 592
 593 static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss)
 594 {
 595         int ret;
 596         u32 val;
 597
 598         /* 1 - Assert WCSS/Q6 HALTREQ */
 599         q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss);
 600
 601         /* 2 - Enable WCSSAON_CONFIG */
 602         val = readl(wcss->rmb_base + SSCAON_CONFIG);
 603         val |= SSCAON_ENABLE;
 604         writel(val, wcss->rmb_base + SSCAON_CONFIG);
 605
 606         /* 3 - Set SSCAON_CONFIG */
 607         val |= SSCAON_BUS_EN;
 608         val &= ~SSCAON_BUS_MUX_MASK;
 609         writel(val, wcss->rmb_base + SSCAON_CONFIG);
 610
 611         /* 4 - SSCAON_CONFIG 1 */
 612         val |= BIT(1);
 613         writel(val, wcss->rmb_base + SSCAON_CONFIG);
 614
 615         /* 5 - wait for SSCAON_STATUS */
 616         ret = readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS,
 617                                  val, (val & 0xffff) == 0x400, 1000,
 618                                  HALT_CHECK_MAX_LOOPS);
 619         if (ret) {
 620                 dev_err(wcss->dev,
 621                         "can't get SSCAON_STATUS rc:%d)\n", ret);
 622                 return ret;
 623         }
 624
 625         /* 6 - De-assert WCSS_AON reset */
 626         reset_control_assert(wcss->wcss_aon_reset);
 627
 628         /* 7 - Disable WCSSAON_CONFIG 13 */
 629         val = readl(wcss->rmb_base + SSCAON_CONFIG);
 630         val &= ~SSCAON_ENABLE;
 631         writel(val, wcss->rmb_base + SSCAON_CONFIG);
 632
 633         /* 8 - De-assert WCSS/Q6 HALTREQ */
 634         reset_control_assert(wcss->wcss_reset);
 635
 636         return 0;
 637 }
 638
 639 static int q6v5_q6_powerdown(struct q6v5_wcss *wcss)
 640 {
 641         int ret;
 642         u32 val;
 643         int i;
 644
 645         /* 1 - Halt Q6 bus interface */
 646         q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6);
 647
 648         /* 2 - Disable Q6 Core clock */
 649         val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG);
 650         val &= ~Q6SS_CLK_ENABLE;
 651         writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG);
 652
 653         /* 3 - Clamp I/O */
 654         val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
 655         val |= Q6SS_CLAMP_IO;
 656         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 657
 658         /* 4 - Clamp WL */
 659         val |= QDSS_BHS_ON;
 660         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 661
 662         /* 5 - Clear Erase standby */
 663         val &= ~Q6SS_L2DATA_STBY_N;
 664         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 665
 666         /* 6 - Clear Sleep RTN */
 667         val &= ~Q6SS_SLP_RET_N;
 668         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 669
 670         /* 7 - turn off Q6 memory foot/head switch one bank at a time */
 671         for (i = 0; i < 20; i++) {
 672                 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL);
 673                 val &= ~BIT(i);
 674                 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL);
 675                 mdelay(1);
 676         }
 677
 678         /* 8 - Assert QMC memory RTN */
 679         val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
 680         val |= Q6SS_CLAMP_QMC_MEM;
 681         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 682
 683         /* 9 - Turn off BHS */
 684         val &= ~Q6SS_BHS_ON;
 685         writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
 686         udelay(1);
 687
 688         /* 10 - Wait till BHS Reset is done */
 689         ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS,
 690                                  val, !(val & BHS_EN_REST_ACK), 1000,
 691                                  HALT_CHECK_MAX_LOOPS);
 692         if (ret) {
 693                 dev_err(wcss->dev, "BHS_STATUS not OFF (rc:%d)\n", ret);
 694                 return ret;
 695         }
 696
 697         /* 11 -  Assert WCSS reset */
 698         reset_control_assert(wcss->wcss_reset);
 699
 700         /* 12 - Assert Q6 reset */
 701         reset_control_assert(wcss->wcss_q6_reset);
 702
 703         return 0;
 704 }
 705
 706 static int q6v5_wcss_stop(struct rproc *rproc)
 707 {
 708         struct q6v5_wcss *wcss = rproc->priv;
 709         int ret;
 710
 711         /* WCSS powerdown */
 712         if (wcss->requires_force_stop) {
 713                 ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL);
 714                 if (ret == -ETIMEDOUT) {
 715                         dev_err(wcss->dev, "timed out on wait\n");
 716                         return ret;
 717                 }
 718         }
 719
 720         if (wcss->version == WCSS_QCS404) {
 721                 ret = q6v5_qcs404_wcss_shutdown(wcss);
 722                 if (ret)
 723                         return ret;
 724         } else {
 725                 ret = q6v5_wcss_powerdown(wcss);
 726                 if (ret)
 727                         return ret;
 728
 729                 /* Q6 Power down */
 730                 ret = q6v5_q6_powerdown(wcss);
 731                 if (ret)
 732                         return ret;
 733         }
 734
 735         qcom_q6v5_unprepare(&wcss->q6v5);
 736
 737         return 0;
 738 }
 739
 740 static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem)
 741 {
 742         struct q6v5_wcss *wcss = rproc->priv;
 743         int offset;
 744
 745         offset = da - wcss->mem_reloc;
 746         if (offset < 0 || offset + len > wcss->mem_size)
 747                 return NULL;
 748
 749         return wcss->mem_region + offset;
 750 }
 751
 752 static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
 753 {
 754         struct q6v5_wcss *wcss = rproc->priv;
 755         int ret;
 756
 757         ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
 758                                     0, wcss->mem_region, wcss->mem_phys,
 759                                     wcss->mem_size, &wcss->mem_reloc);
 760         if (ret)
 761                 return ret;
 762
 763         qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size);
 764
 765         return ret;
 766 }
 767
 768 static const struct rproc_ops q6v5_wcss_ipq8074_ops = {
 769         .start = q6v5_wcss_start,
 770         .stop = q6v5_wcss_stop,
 771         .da_to_va = q6v5_wcss_da_to_va,
 772         .load = q6v5_wcss_load,
 773         .get_boot_addr = rproc_elf_get_boot_addr,
 774 };
 775
 776 static const struct rproc_ops q6v5_wcss_qcs404_ops = {
 777         .start = q6v5_qcs404_wcss_start,
 778         .stop = q6v5_wcss_stop,
 779         .da_to_va = q6v5_wcss_da_to_va,
 780         .load = q6v5_wcss_load,
 781         .get_boot_addr = rproc_elf_get_boot_addr,
 782         .parse_fw = qcom_register_dump_segments,
 783 };
 784
 785 static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss,
 786                                 const struct wcss_data *desc)
 787 {
 788         struct device *dev = wcss->dev;
 789
 790         if (desc->aon_reset_required) {
 791                 wcss->wcss_aon_reset = devm_reset_control_get_exclusive(dev, "wcss_aon_reset");
 792                 if (IS_ERR(wcss->wcss_aon_reset)) {
 793                         dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n");
 794                         return PTR_ERR(wcss->wcss_aon_reset);
 795                 }
 796         }
 797
 798         wcss->wcss_reset = devm_reset_control_get_exclusive(dev, "wcss_reset");
 799         if (IS_ERR(wcss->wcss_reset)) {
 800                 dev_err(wcss->dev, "unable to acquire wcss_reset\n");
 801                 return PTR_ERR(wcss->wcss_reset);
 802         }
 803
 804         if (desc->wcss_q6_reset_required) {
 805                 wcss->wcss_q6_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_reset");
 806                 if (IS_ERR(wcss->wcss_q6_reset)) {
 807                         dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n");
 808                         return PTR_ERR(wcss->wcss_q6_reset);
 809                 }
 810         }
 811
 812         wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset");
 813         if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
 814                 dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
 815                 return PTR_ERR(wcss->wcss_q6_bcr_reset);
 816         }
 817
 818         return 0;
 819 }
 820
 821 static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss,
 822                                struct platform_device *pdev)
 823 {
 824         unsigned int halt_reg[MAX_HALT_REG] = {0};
 825         struct device_node *syscon;
 826         struct resource *res;
 827         int ret;
 828
 829         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
 830         wcss->reg_base = devm_ioremap(&pdev->dev, res->start,
 831                                       resource_size(res));
 832         if (!wcss->reg_base)
 833                 return -ENOMEM;
 834
 835         if (wcss->version == WCSS_IPQ8074) {
 836                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
 837                 wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
 838                 if (IS_ERR(wcss->rmb_base))
 839                         return PTR_ERR(wcss->rmb_base);
 840         }
 841
 842         syscon = of_parse_phandle(pdev->dev.of_node,
 843                                   "qcom,halt-regs", 0);
 844         if (!syscon) {
 845                 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
 846                 return -EINVAL;
 847         }
 848
 849         wcss->halt_map = syscon_node_to_regmap(syscon);
 850         of_node_put(syscon);
 851         if (IS_ERR(wcss->halt_map))
 852                 return PTR_ERR(wcss->halt_map);
 853
 854         ret = of_property_read_variable_u32_array(pdev->dev.of_node,
 855                                                   "qcom,halt-regs",
 856                                                   halt_reg, 0,
 857                                                   MAX_HALT_REG);
 858         if (ret < 0) {
 859                 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
 860                 return -EINVAL;
 861         }
 862
 863         wcss->halt_q6 = halt_reg[0];
 864         wcss->halt_wcss = halt_reg[1];
 865         wcss->halt_nc = halt_reg[2];
 866
 867         return 0;
 868 }
 869
 870 static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)
 871 {
 872         struct reserved_mem *rmem = NULL;
 873         struct device_node *node;
 874         struct device *dev = wcss->dev;
 875
 876         node = of_parse_phandle(dev->of_node, "memory-region", 0);
 877         if (node)
 878                 rmem = of_reserved_mem_lookup(node);
 879         of_node_put(node);
 880
 881         if (!rmem) {
 882                 dev_err(dev, "unable to acquire memory-region\n");
 883                 return -EINVAL;
 884         }
 885
 886         wcss->mem_phys = rmem->base;
 887         wcss->mem_reloc = rmem->base;
 888         wcss->mem_size = rmem->size;
 889         wcss->mem_region = devm_ioremap_wc(dev, wcss->mem_phys, wcss->mem_size);
 890         if (!wcss->mem_region) {
 891                 dev_err(dev, "unable to map memory region: %pa+%pa\n",
 892                         &rmem->base, &rmem->size);
 893                 return -EBUSY;
 894         }
 895
 896         return 0;
 897 }
 898
 899 static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
 900 {
 901         int ret;
 902
 903         wcss->xo = devm_clk_get(wcss->dev, "xo");
 904         if (IS_ERR(wcss->xo)) {
 905                 ret = PTR_ERR(wcss->xo);
 906                 if (ret != -EPROBE_DEFER)
 907                         dev_err(wcss->dev, "failed to get xo clock");
 908                 return ret;
 909         }
 910
 911         wcss->gcc_abhs_cbcr = devm_clk_get(wcss->dev, "gcc_abhs_cbcr");
 912         if (IS_ERR(wcss->gcc_abhs_cbcr)) {
 913                 ret = PTR_ERR(wcss->gcc_abhs_cbcr);
 914                 if (ret != -EPROBE_DEFER)
 915                         dev_err(wcss->dev, "failed to get gcc abhs clock");
 916                 return ret;
 917         }
 918
 919         wcss->gcc_axim_cbcr = devm_clk_get(wcss->dev, "gcc_axim_cbcr");
 920         if (IS_ERR(wcss->gcc_axim_cbcr)) {
 921                 ret = PTR_ERR(wcss->gcc_axim_cbcr);
 922                 if (ret != -EPROBE_DEFER)
 923                         dev_err(wcss->dev, "failed to get gcc axim clock\n");
 924                 return ret;
 925         }
 926
 927         wcss->ahbfabric_cbcr_clk = devm_clk_get(wcss->dev,
 928                                                 "lcc_ahbfabric_cbc");
 929         if (IS_ERR(wcss->ahbfabric_cbcr_clk)) {
 930                 ret = PTR_ERR(wcss->ahbfabric_cbcr_clk);
 931                 if (ret != -EPROBE_DEFER)
 932                         dev_err(wcss->dev, "failed to get ahbfabric clock\n");
 933                 return ret;
 934         }
 935
 936         wcss->lcc_csr_cbcr = devm_clk_get(wcss->dev, "tcsr_lcc_cbc");
 937         if (IS_ERR(wcss->lcc_csr_cbcr)) {
 938                 ret = PTR_ERR(wcss->lcc_csr_cbcr);
 939                 if (ret != -EPROBE_DEFER)
 940                         dev_err(wcss->dev, "failed to get csr cbcr clk\n");
 941                 return ret;
 942         }
 943
 944         wcss->ahbs_cbcr = devm_clk_get(wcss->dev,
 945                                        "lcc_abhs_cbc");
 946         if (IS_ERR(wcss->ahbs_cbcr)) {
 947                 ret = PTR_ERR(wcss->ahbs_cbcr);
 948                 if (ret != -EPROBE_DEFER)
 949                         dev_err(wcss->dev, "failed to get ahbs_cbcr clk\n");
 950                 return ret;
 951         }
 952
 953         wcss->tcm_slave_cbcr = devm_clk_get(wcss->dev,
 954                                             "lcc_tcm_slave_cbc");
 955         if (IS_ERR(wcss->tcm_slave_cbcr)) {
 956                 ret = PTR_ERR(wcss->tcm_slave_cbcr);
 957                 if (ret != -EPROBE_DEFER)
 958                         dev_err(wcss->dev, "failed to get tcm cbcr clk\n");
 959                 return ret;
 960         }
 961
 962         wcss->qdsp6ss_abhm_cbcr = devm_clk_get(wcss->dev, "lcc_abhm_cbc");
 963         if (IS_ERR(wcss->qdsp6ss_abhm_cbcr)) {
 964                 ret = PTR_ERR(wcss->qdsp6ss_abhm_cbcr);
 965                 if (ret != -EPROBE_DEFER)
 966                         dev_err(wcss->dev, "failed to get abhm cbcr clk\n");
 967                 return ret;
 968         }
 969
 970         wcss->qdsp6ss_axim_cbcr = devm_clk_get(wcss->dev, "lcc_axim_cbc");
 971         if (IS_ERR(wcss->qdsp6ss_axim_cbcr)) {
 972                 ret = PTR_ERR(wcss->qdsp6ss_axim_cbcr);
 973                 if (ret != -EPROBE_DEFER)
 974                         dev_err(wcss->dev, "failed to get axim cbcr clk\n");
 975                 return ret;
 976         }
 977
 978         wcss->lcc_bcr_sleep = devm_clk_get(wcss->dev, "lcc_bcr_sleep");
 979         if (IS_ERR(wcss->lcc_bcr_sleep)) {
 980                 ret = PTR_ERR(wcss->lcc_bcr_sleep);
 981                 if (ret != -EPROBE_DEFER)
 982                         dev_err(wcss->dev, "failed to get bcr cbcr clk\n");
 983                 return ret;
 984         }
 985
 986         return 0;
 987 }
 988
 989 static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
 990 {
 991         wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
 992         if (IS_ERR(wcss->cx_supply))
 993                 return PTR_ERR(wcss->cx_supply);
 994
 995         regulator_set_load(wcss->cx_supply, 100000);
 996
 997         return 0;
 998 }
 999
1000 static int q6v5_wcss_probe(struct platform_device *pdev)
1001 {
1002         const struct wcss_data *desc;
1003         struct q6v5_wcss *wcss;
1004         struct rproc *rproc;
1005         int ret;
1006
1007         desc = device_get_match_data(&pdev->dev);
1008         if (!desc)
1009                 return -EINVAL;
1010
1011         rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
1012                             desc->firmware_name, sizeof(*wcss));
1013         if (!rproc) {
1014                 dev_err(&pdev->dev, "failed to allocate rproc\n");
1015                 return -ENOMEM;
1016         }
1017
1018         wcss = rproc->priv;
1019         wcss->dev = &pdev->dev;
1020         wcss->version = desc->version;
1021
1022         wcss->version = desc->version;
1023         wcss->requires_force_stop = desc->requires_force_stop;
1024
1025         ret = q6v5_wcss_init_mmio(wcss, pdev);
1026         if (ret)
1027                 goto free_rproc;
1028
1029         ret = q6v5_alloc_memory_region(wcss);
1030         if (ret)
1031                 goto free_rproc;
1032
1033         if (wcss->version == WCSS_QCS404) {
1034                 ret = q6v5_wcss_init_clock(wcss);
1035                 if (ret)
1036                         goto free_rproc;
1037
1038                 ret = q6v5_wcss_init_regulator(wcss);
1039                 if (ret)
1040                         goto free_rproc;
1041         }
1042
1043         ret = q6v5_wcss_init_reset(wcss, desc);
1044         if (ret)
1045                 goto free_rproc;
1046
1047         ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, NULL);
1048         if (ret)
1049                 goto free_rproc;
1050
1051         qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss");
1052         qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss");
1053
1054         if (desc->ssctl_id)
1055                 wcss->sysmon = qcom_add_sysmon_subdev(rproc,
1056                                                       desc->sysmon_name,
1057                                                       desc->ssctl_id);
1058
1059         ret = rproc_add(rproc);
1060         if (ret)
1061                 goto free_rproc;
1062
1063         platform_set_drvdata(pdev, rproc);
1064
1065         return 0;
1066
1067 free_rproc:
1068         rproc_free(rproc);
1069
1070         return ret;
1071 }
1072
1073 static int q6v5_wcss_remove(struct platform_device *pdev)
1074 {
1075         struct rproc *rproc = platform_get_drvdata(pdev);
1076         struct q6v5_wcss *wcss = rproc->priv;
1077
1078         qcom_q6v5_deinit(&wcss->q6v5);
1079         rproc_del(rproc);
1080         rproc_free(rproc);
1081
1082         return 0;
1083 }
1084
1085 static const struct wcss_data wcss_ipq8074_res_init = {
1086         .firmware_name = "IPQ8074/q6_fw.mdt",
1087         .crash_reason_smem = WCSS_CRASH_REASON,
1088         .aon_reset_required = true,
1089         .wcss_q6_reset_required = true,
1090         .ops = &q6v5_wcss_ipq8074_ops,
1091         .requires_force_stop = true,
1092 };
1093
1094 static const struct wcss_data wcss_qcs404_res_init = {
1095         .crash_reason_smem = WCSS_CRASH_REASON,
1096         .firmware_name = "wcnss.mdt",
1097         .version = WCSS_QCS404,
1098         .aon_reset_required = false,
1099         .wcss_q6_reset_required = false,
1100         .ssr_name = "mpss",
1101         .sysmon_name = "wcnss",
1102         .ssctl_id = 0x12,
1103         .ops = &q6v5_wcss_qcs404_ops,
1104         .requires_force_stop = false,
1105 };
1106
1107 static const struct of_device_id q6v5_wcss_of_match[] = {
1108         { .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
1109         { .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init },
1110         { },
1111 };
1112 MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match);
1113
1114 static struct platform_driver q6v5_wcss_driver = {
1115         .probe = q6v5_wcss_probe,
1116         .remove = q6v5_wcss_remove,
1117         .driver = {
1118                 .name = "qcom-q6v5-wcss-pil",
1119                 .of_match_table = q6v5_wcss_of_match,
1120         },
1121 };
1122 module_platform_driver(q6v5_wcss_driver);
1123
1124 MODULE_DESCRIPTION("Hexagon WCSS Peripheral Image Loader");
1125 MODULE_LICENSE("GPL v2");