drivers/remoteproc/qcom_q6v5_mss.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Qualcomm self-authenticating modem subsystem remoteproc driver
   4  *
   5  * Copyright (C) 2016 Linaro Ltd.
   6  * Copyright (C) 2014 Sony Mobile Communications AB
   7  * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/devcoredump.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/module.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_device.h>
  20 #include <linux/of_reserved_mem.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_domain.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/regmap.h>
  25 #include <linux/regulator/consumer.h>
  26 #include <linux/remoteproc.h>
  27 #include <linux/reset.h>
  28 #include <linux/soc/qcom/mdt_loader.h>
  29 #include <linux/iopoll.h>
  30 #include <linux/slab.h>
  31
  32 #include "remoteproc_internal.h"
  33 #include "qcom_common.h"
  34 #include "qcom_pil_info.h"
  35 #include "qcom_q6v5.h"
  36
  37 #include <linux/qcom_scm.h>
  38
  39 #define MPSS_CRASH_REASON_SMEM          421
  40
  41 #define MBA_LOG_SIZE                    SZ_4K
  42
  43 /* RMB Status Register Values */
  44 #define RMB_PBL_SUCCESS                 0x1
  45
  46 #define RMB_MBA_XPU_UNLOCKED            0x1
  47 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED  0x2
  48 #define RMB_MBA_META_DATA_AUTH_SUCCESS  0x3
  49 #define RMB_MBA_AUTH_COMPLETE           0x4
  50
  51 /* PBL/MBA interface registers */
  52 #define RMB_MBA_IMAGE_REG               0x00
  53 #define RMB_PBL_STATUS_REG              0x04
  54 #define RMB_MBA_COMMAND_REG             0x08
  55 #define RMB_MBA_STATUS_REG              0x0C
  56 #define RMB_PMI_META_DATA_REG           0x10
  57 #define RMB_PMI_CODE_START_REG          0x14
  58 #define RMB_PMI_CODE_LENGTH_REG         0x18
  59 #define RMB_MBA_MSS_STATUS              0x40
  60 #define RMB_MBA_ALT_RESET               0x44
  61
  62 #define RMB_CMD_META_DATA_READY         0x1
  63 #define RMB_CMD_LOAD_READY              0x2
  64
  65 /* QDSP6SS Register Offsets */
  66 #define QDSP6SS_RESET_REG               0x014
  67 #define QDSP6SS_GFMUX_CTL_REG           0x020
  68 #define QDSP6SS_PWR_CTL_REG             0x030
  69 #define QDSP6SS_MEM_PWR_CTL             0x0B0
  70 #define QDSP6V6SS_MEM_PWR_CTL           0x034
  71 #define QDSP6SS_STRAP_ACC               0x110
  72
  73 /* AXI Halt Register Offsets */
  74 #define AXI_HALTREQ_REG                 0x0
  75 #define AXI_HALTACK_REG                 0x4
  76 #define AXI_IDLE_REG                    0x8
  77 #define AXI_GATING_VALID_OVERRIDE       BIT(0)
  78
  79 #define HALT_ACK_TIMEOUT_US             100000
  80
  81 /* QACCEPT Register Offsets */
  82 #define QACCEPT_ACCEPT_REG              0x0
  83 #define QACCEPT_ACTIVE_REG              0x4
  84 #define QACCEPT_DENY_REG                0x8
  85 #define QACCEPT_REQ_REG                 0xC
  86
  87 #define QACCEPT_TIMEOUT_US              50
  88
  89 /* QDSP6SS_RESET */
  90 #define Q6SS_STOP_CORE                  BIT(0)
  91 #define Q6SS_CORE_ARES                  BIT(1)
  92 #define Q6SS_BUS_ARES_ENABLE            BIT(2)
  93
  94 /* QDSP6SS CBCR */
  95 #define Q6SS_CBCR_CLKEN                 BIT(0)
  96 #define Q6SS_CBCR_CLKOFF                BIT(31)
  97 #define Q6SS_CBCR_TIMEOUT_US            200
  98
  99 /* QDSP6SS_GFMUX_CTL */
 100 #define Q6SS_CLK_ENABLE                 BIT(1)
 101
 102 /* QDSP6SS_PWR_CTL */
 103 #define Q6SS_L2DATA_SLP_NRET_N_0        BIT(0)
 104 #define Q6SS_L2DATA_SLP_NRET_N_1        BIT(1)
 105 #define Q6SS_L2DATA_SLP_NRET_N_2        BIT(2)
 106 #define Q6SS_L2TAG_SLP_NRET_N           BIT(16)
 107 #define Q6SS_ETB_SLP_NRET_N             BIT(17)
 108 #define Q6SS_L2DATA_STBY_N              BIT(18)
 109 #define Q6SS_SLP_RET_N                  BIT(19)
 110 #define Q6SS_CLAMP_IO                   BIT(20)
 111 #define QDSS_BHS_ON                     BIT(21)
 112 #define QDSS_LDO_BYP                    BIT(22)
 113
 114 /* QDSP6v56 parameters */
 115 #define QDSP6v56_LDO_BYP                BIT(25)
 116 #define QDSP6v56_BHS_ON         BIT(24)
 117 #define QDSP6v56_CLAMP_WL               BIT(21)
 118 #define QDSP6v56_CLAMP_QMC_MEM          BIT(22)
 119 #define QDSP6SS_XO_CBCR         0x0038
 120 #define QDSP6SS_ACC_OVERRIDE_VAL                0x20
 121
 122 /* QDSP6v65 parameters */
 123 #define QDSP6SS_CORE_CBCR               0x20
 124 #define QDSP6SS_SLEEP                   0x3C
 125 #define QDSP6SS_BOOT_CORE_START         0x400
 126 #define QDSP6SS_BOOT_CMD                0x404
 127 #define BOOT_FSM_TIMEOUT                10000
 128
 129 struct reg_info {
 130         struct regulator *reg;
 131         int uV;
 132         int uA;
 133 };
 134
 135 struct qcom_mss_reg_res {
 136         const char *supply;
 137         int uV;
 138         int uA;
 139 };
 140
 141 struct rproc_hexagon_res {
 142         const char *hexagon_mba_image;
 143         struct qcom_mss_reg_res *proxy_supply;
 144         struct qcom_mss_reg_res *fallback_proxy_supply;
 145         struct qcom_mss_reg_res *active_supply;
 146         char **proxy_clk_names;
 147         char **reset_clk_names;
 148         char **active_clk_names;
 149         char **proxy_pd_names;
 150         int version;
 151         bool need_mem_protection;
 152         bool has_alt_reset;
 153         bool has_mba_logs;
 154         bool has_spare_reg;
 155         bool has_qaccept_regs;
 156         bool has_ext_cntl_regs;
 157         bool has_vq6;
 158 };
 159
 160 struct q6v5 {
 161         struct device *dev;
 162         struct rproc *rproc;
 163
 164         void __iomem *reg_base;
 165         void __iomem *rmb_base;
 166
 167         struct regmap *halt_map;
 168         struct regmap *conn_map;
 169
 170         u32 halt_q6;
 171         u32 halt_modem;
 172         u32 halt_nc;
 173         u32 halt_vq6;
 174         u32 conn_box;
 175
 176         u32 qaccept_mdm;
 177         u32 qaccept_cx;
 178         u32 qaccept_axi;
 179
 180         u32 axim1_clk_off;
 181         u32 crypto_clk_off;
 182         u32 force_clk_on;
 183         u32 rscc_disable;
 184
 185         struct reset_control *mss_restart;
 186         struct reset_control *pdc_reset;
 187
 188         struct qcom_q6v5 q6v5;
 189
 190         struct clk *active_clks[8];
 191         struct clk *reset_clks[4];
 192         struct clk *proxy_clks[4];
 193         struct device *proxy_pds[3];
 194         int active_clk_count;
 195         int reset_clk_count;
 196         int proxy_clk_count;
 197         int proxy_pd_count;
 198
 199         struct reg_info active_regs[1];
 200         struct reg_info proxy_regs[1];
 201         struct reg_info fallback_proxy_regs[2];
 202         int active_reg_count;
 203         int proxy_reg_count;
 204         int fallback_proxy_reg_count;
 205
 206         bool dump_mba_loaded;
 207         size_t current_dump_size;
 208         size_t total_dump_size;
 209
 210         phys_addr_t mba_phys;
 211         size_t mba_size;
 212         size_t dp_size;
 213
 214         phys_addr_t mdata_phys;
 215         size_t mdata_size;
 216
 217         phys_addr_t mpss_phys;
 218         phys_addr_t mpss_reloc;
 219         size_t mpss_size;
 220
 221         struct qcom_rproc_glink glink_subdev;
 222         struct qcom_rproc_subdev smd_subdev;
 223         struct qcom_rproc_ssr ssr_subdev;
 224         struct qcom_sysmon *sysmon;
 225         struct platform_device *bam_dmux;
 226         bool need_mem_protection;
 227         bool has_alt_reset;
 228         bool has_mba_logs;
 229         bool has_spare_reg;
 230         bool has_qaccept_regs;
 231         bool has_ext_cntl_regs;
 232         bool has_vq6;
 233         int mpss_perm;
 234         int mba_perm;
 235         const char *hexagon_mdt_image;
 236         int version;
 237 };
 238
 239 enum {
 240         MSS_MSM8916,
 241         MSS_MSM8974,
 242         MSS_MSM8996,
 243         MSS_MSM8998,
 244         MSS_SC7180,
 245         MSS_SC7280,
 246         MSS_SDM845,
 247 };
 248
 249 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
 250                                const struct qcom_mss_reg_res *reg_res)
 251 {
 252         int rc;
 253         int i;
 254
 255         if (!reg_res)
 256                 return 0;
 257
 258         for (i = 0; reg_res[i].supply; i++) {
 259                 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
 260                 if (IS_ERR(regs[i].reg)) {
 261                         rc = PTR_ERR(regs[i].reg);
 262                         if (rc != -EPROBE_DEFER)
 263                                 dev_err(dev, "Failed to get %s\n regulator",
 264                                         reg_res[i].supply);
 265                         return rc;
 266                 }
 267
 268                 regs[i].uV = reg_res[i].uV;
 269                 regs[i].uA = reg_res[i].uA;
 270         }
 271
 272         return i;
 273 }
 274
 275 static int q6v5_regulator_enable(struct q6v5 *qproc,
 276                                  struct reg_info *regs, int count)
 277 {
 278         int ret;
 279         int i;
 280
 281         for (i = 0; i < count; i++) {
 282                 if (regs[i].uV > 0) {
 283                         ret = regulator_set_voltage(regs[i].reg,
 284                                         regs[i].uV, INT_MAX);
 285                         if (ret) {
 286                                 dev_err(qproc->dev,
 287                                         "Failed to request voltage for %d.\n",
 288                                                 i);
 289                                 goto err;
 290                         }
 291                 }
 292
 293                 if (regs[i].uA > 0) {
 294                         ret = regulator_set_load(regs[i].reg,
 295                                                  regs[i].uA);
 296                         if (ret < 0) {
 297                                 dev_err(qproc->dev,
 298                                         "Failed to set regulator mode\n");
 299                                 goto err;
 300                         }
 301                 }
 302
 303                 ret = regulator_enable(regs[i].reg);
 304                 if (ret) {
 305                         dev_err(qproc->dev, "Regulator enable failed\n");
 306                         goto err;
 307                 }
 308         }
 309
 310         return 0;
 311 err:
 312         for (; i >= 0; i--) {
 313                 if (regs[i].uV > 0)
 314                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 315
 316                 if (regs[i].uA > 0)
 317                         regulator_set_load(regs[i].reg, 0);
 318
 319                 regulator_disable(regs[i].reg);
 320         }
 321
 322         return ret;
 323 }
 324
 325 static void q6v5_regulator_disable(struct q6v5 *qproc,
 326                                    struct reg_info *regs, int count)
 327 {
 328         int i;
 329
 330         for (i = 0; i < count; i++) {
 331                 if (regs[i].uV > 0)
 332                         regulator_set_voltage(regs[i].reg, 0, INT_MAX);
 333
 334                 if (regs[i].uA > 0)
 335                         regulator_set_load(regs[i].reg, 0);
 336
 337                 regulator_disable(regs[i].reg);
 338         }
 339 }
 340
 341 static int q6v5_clk_enable(struct device *dev,
 342                            struct clk **clks, int count)
 343 {
 344         int rc;
 345         int i;
 346
 347         for (i = 0; i < count; i++) {
 348                 rc = clk_prepare_enable(clks[i]);
 349                 if (rc) {
 350                         dev_err(dev, "Clock enable failed\n");
 351                         goto err;
 352                 }
 353         }
 354
 355         return 0;
 356 err:
 357         for (i--; i >= 0; i--)
 358                 clk_disable_unprepare(clks[i]);
 359
 360         return rc;
 361 }
 362
 363 static void q6v5_clk_disable(struct device *dev,
 364                              struct clk **clks, int count)
 365 {
 366         int i;
 367
 368         for (i = 0; i < count; i++)
 369                 clk_disable_unprepare(clks[i]);
 370 }
 371
 372 static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
 373                            size_t pd_count)
 374 {
 375         int ret;
 376         int i;
 377
 378         for (i = 0; i < pd_count; i++) {
 379                 dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
 380                 ret = pm_runtime_get_sync(pds[i]);
 381                 if (ret < 0) {
 382                         pm_runtime_put_noidle(pds[i]);
 383                         dev_pm_genpd_set_performance_state(pds[i], 0);
 384                         goto unroll_pd_votes;
 385                 }
 386         }
 387
 388         return 0;
 389
 390 unroll_pd_votes:
 391         for (i--; i >= 0; i--) {
 392                 dev_pm_genpd_set_performance_state(pds[i], 0);
 393                 pm_runtime_put(pds[i]);
 394         }
 395
 396         return ret;
 397 }
 398
 399 static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
 400                              size_t pd_count)
 401 {
 402         int i;
 403
 404         for (i = 0; i < pd_count; i++) {
 405                 dev_pm_genpd_set_performance_state(pds[i], 0);
 406                 pm_runtime_put(pds[i]);
 407         }
 408 }
 409
 410 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
 411                                    bool local, bool remote, phys_addr_t addr,
 412                                    size_t size)
 413 {
 414         struct qcom_scm_vmperm next[2];
 415         int perms = 0;
 416
 417         if (!qproc->need_mem_protection)
 418                 return 0;
 419
 420         if (local == !!(*current_perm & BIT(QCOM_SCM_VMID_HLOS)) &&
 421             remote == !!(*current_perm & BIT(QCOM_SCM_VMID_MSS_MSA)))
 422                 return 0;
 423
 424         if (local) {
 425                 next[perms].vmid = QCOM_SCM_VMID_HLOS;
 426                 next[perms].perm = QCOM_SCM_PERM_RWX;
 427                 perms++;
 428         }
 429
 430         if (remote) {
 431                 next[perms].vmid = QCOM_SCM_VMID_MSS_MSA;
 432                 next[perms].perm = QCOM_SCM_PERM_RW;
 433                 perms++;
 434         }
 435
 436         return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
 437                                    current_perm, next, perms);
 438 }
 439
 440 static void q6v5_debug_policy_load(struct q6v5 *qproc, void *mba_region)
 441 {
 442         const struct firmware *dp_fw;
 443
 444         if (request_firmware_direct(&dp_fw, "msadp", qproc->dev))
 445                 return;
 446
 447         if (SZ_1M + dp_fw->size <= qproc->mba_size) {
 448                 memcpy(mba_region + SZ_1M, dp_fw->data, dp_fw->size);
 449                 qproc->dp_size = dp_fw->size;
 450         }
 451
 452         release_firmware(dp_fw);
 453 }
 454
 455 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
 456 {
 457         struct q6v5 *qproc = rproc->priv;
 458         void *mba_region;
 459
 460         /* MBA is restricted to a maximum size of 1M */
 461         if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
 462                 dev_err(qproc->dev, "MBA firmware load failed\n");
 463                 return -EINVAL;
 464         }
 465
 466         mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
 467         if (!mba_region) {
 468                 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
 469                         &qproc->mba_phys, qproc->mba_size);
 470                 return -EBUSY;
 471         }
 472
 473         memcpy(mba_region, fw->data, fw->size);
 474         q6v5_debug_policy_load(qproc, mba_region);
 475         memunmap(mba_region);
 476
 477         return 0;
 478 }
 479
 480 static int q6v5_reset_assert(struct q6v5 *qproc)
 481 {
 482         int ret;
 483
 484         if (qproc->has_alt_reset) {
 485                 reset_control_assert(qproc->pdc_reset);
 486                 ret = reset_control_reset(qproc->mss_restart);
 487                 reset_control_deassert(qproc->pdc_reset);
 488         } else if (qproc->has_spare_reg) {
 489                 /*
 490                  * When the AXI pipeline is being reset with the Q6 modem partly
 491                  * operational there is possibility of AXI valid signal to
 492                  * glitch, leading to spurious transactions and Q6 hangs. A work
 493                  * around is employed by asserting the AXI_GATING_VALID_OVERRIDE
 494                  * BIT before triggering Q6 MSS reset. AXI_GATING_VALID_OVERRIDE
 495                  * is withdrawn post MSS assert followed by a MSS deassert,
 496                  * while holding the PDC reset.
 497                  */
 498                 reset_control_assert(qproc->pdc_reset);
 499                 regmap_update_bits(qproc->conn_map, qproc->conn_box,
 500                                    AXI_GATING_VALID_OVERRIDE, 1);
 501                 reset_control_assert(qproc->mss_restart);
 502                 reset_control_deassert(qproc->pdc_reset);
 503                 regmap_update_bits(qproc->conn_map, qproc->conn_box,
 504                                    AXI_GATING_VALID_OVERRIDE, 0);
 505                 ret = reset_control_deassert(qproc->mss_restart);
 506         } else if (qproc->has_ext_cntl_regs) {
 507                 regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
 508                 reset_control_assert(qproc->pdc_reset);
 509                 reset_control_assert(qproc->mss_restart);
 510                 reset_control_deassert(qproc->pdc_reset);
 511                 ret = reset_control_deassert(qproc->mss_restart);
 512         } else {
 513                 ret = reset_control_assert(qproc->mss_restart);
 514         }
 515
 516         return ret;
 517 }
 518
 519 static int q6v5_reset_deassert(struct q6v5 *qproc)
 520 {
 521         int ret;
 522
 523         if (qproc->has_alt_reset) {
 524                 reset_control_assert(qproc->pdc_reset);
 525                 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
 526                 ret = reset_control_reset(qproc->mss_restart);
 527                 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
 528                 reset_control_deassert(qproc->pdc_reset);
 529         } else if (qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
 530                 ret = reset_control_reset(qproc->mss_restart);
 531         } else {
 532                 ret = reset_control_deassert(qproc->mss_restart);
 533         }
 534
 535         return ret;
 536 }
 537
 538 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
 539 {
 540         unsigned long timeout;
 541         s32 val;
 542
 543         timeout = jiffies + msecs_to_jiffies(ms);
 544         for (;;) {
 545                 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
 546                 if (val)
 547                         break;
 548
 549                 if (time_after(jiffies, timeout))
 550                         return -ETIMEDOUT;
 551
 552                 msleep(1);
 553         }
 554
 555         return val;
 556 }
 557
 558 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
 559 {
 560
 561         unsigned long timeout;
 562         s32 val;
 563
 564         timeout = jiffies + msecs_to_jiffies(ms);
 565         for (;;) {
 566                 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
 567                 if (val < 0)
 568                         break;
 569
 570                 if (!status && val)
 571                         break;
 572                 else if (status && val == status)
 573                         break;
 574
 575                 if (time_after(jiffies, timeout))
 576                         return -ETIMEDOUT;
 577
 578                 msleep(1);
 579         }
 580
 581         return val;
 582 }
 583
 584 static void q6v5_dump_mba_logs(struct q6v5 *qproc)
 585 {
 586         struct rproc *rproc = qproc->rproc;
 587         void *data;
 588         void *mba_region;
 589
 590         if (!qproc->has_mba_logs)
 591                 return;
 592
 593         if (q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false, qproc->mba_phys,
 594                                     qproc->mba_size))
 595                 return;
 596
 597         mba_region = memremap(qproc->mba_phys, qproc->mba_size, MEMREMAP_WC);
 598         if (!mba_region)
 599                 return;
 600
 601         data = vmalloc(MBA_LOG_SIZE);
 602         if (data) {
 603                 memcpy(data, mba_region, MBA_LOG_SIZE);
 604                 dev_coredumpv(&rproc->dev, data, MBA_LOG_SIZE, GFP_KERNEL);
 605         }
 606         memunmap(mba_region);
 607 }
 608
 609 static int q6v5proc_reset(struct q6v5 *qproc)
 610 {
 611         u32 val;
 612         int ret;
 613         int i;
 614
 615         if (qproc->version == MSS_SDM845) {
 616                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 617                 val |= Q6SS_CBCR_CLKEN;
 618                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 619
 620                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 621                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 622                                          Q6SS_CBCR_TIMEOUT_US);
 623                 if (ret) {
 624                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 625                         return -ETIMEDOUT;
 626                 }
 627
 628                 /* De-assert QDSP6 stop core */
 629                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 630                 /* Trigger boot FSM */
 631                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 632
 633                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 634                                 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 635                 if (ret) {
 636                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 637                         /* Reset the modem so that boot FSM is in reset state */
 638                         q6v5_reset_deassert(qproc);
 639                         return ret;
 640                 }
 641
 642                 goto pbl_wait;
 643         } else if (qproc->version == MSS_SC7180 || qproc->version == MSS_SC7280) {
 644                 val = readl(qproc->reg_base + QDSP6SS_SLEEP);
 645                 val |= Q6SS_CBCR_CLKEN;
 646                 writel(val, qproc->reg_base + QDSP6SS_SLEEP);
 647
 648                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
 649                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 650                                          Q6SS_CBCR_TIMEOUT_US);
 651                 if (ret) {
 652                         dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
 653                         return -ETIMEDOUT;
 654                 }
 655
 656                 /* Turn on the XO clock needed for PLL setup */
 657                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 658                 val |= Q6SS_CBCR_CLKEN;
 659                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 660
 661                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 662                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 663                                          Q6SS_CBCR_TIMEOUT_US);
 664                 if (ret) {
 665                         dev_err(qproc->dev, "QDSP6SS XO clock timed out\n");
 666                         return -ETIMEDOUT;
 667                 }
 668
 669                 /* Configure Q6 core CBCR to auto-enable after reset sequence */
 670                 val = readl(qproc->reg_base + QDSP6SS_CORE_CBCR);
 671                 val |= Q6SS_CBCR_CLKEN;
 672                 writel(val, qproc->reg_base + QDSP6SS_CORE_CBCR);
 673
 674                 /* De-assert the Q6 stop core signal */
 675                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
 676
 677                 /* Wait for 10 us for any staggering logic to settle */
 678                 usleep_range(10, 20);
 679
 680                 /* Trigger the boot FSM to start the Q6 out-of-reset sequence */
 681                 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
 682
 683                 /* Poll the MSS_STATUS for FSM completion */
 684                 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
 685                                          val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
 686                 if (ret) {
 687                         dev_err(qproc->dev, "Boot FSM failed to complete.\n");
 688                         /* Reset the modem so that boot FSM is in reset state */
 689                         q6v5_reset_deassert(qproc);
 690                         return ret;
 691                 }
 692                 goto pbl_wait;
 693         } else if (qproc->version == MSS_MSM8996 ||
 694                    qproc->version == MSS_MSM8998) {
 695                 int mem_pwr_ctl;
 696
 697                 /* Override the ACC value if required */
 698                 writel(QDSP6SS_ACC_OVERRIDE_VAL,
 699                        qproc->reg_base + QDSP6SS_STRAP_ACC);
 700
 701                 /* Assert resets, stop core */
 702                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 703                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 704                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 705
 706                 /* BHS require xo cbcr to be enabled */
 707                 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
 708                 val |= Q6SS_CBCR_CLKEN;
 709                 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
 710
 711                 /* Read CLKOFF bit to go low indicating CLK is enabled */
 712                 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
 713                                          val, !(val & Q6SS_CBCR_CLKOFF), 1,
 714                                          Q6SS_CBCR_TIMEOUT_US);
 715                 if (ret) {
 716                         dev_err(qproc->dev,
 717                                 "xo cbcr enabling timed out (rc:%d)\n", ret);
 718                         return ret;
 719                 }
 720                 /* Enable power block headswitch and wait for it to stabilize */
 721                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 722                 val |= QDSP6v56_BHS_ON;
 723                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 724                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 725                 udelay(1);
 726
 727                 /* Put LDO in bypass mode */
 728                 val |= QDSP6v56_LDO_BYP;
 729                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 730
 731                 /* Deassert QDSP6 compiler memory clamp */
 732                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 733                 val &= ~QDSP6v56_CLAMP_QMC_MEM;
 734                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 735
 736                 /* Deassert memory peripheral sleep and L2 memory standby */
 737                 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
 738                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 739
 740                 /* Turn on L1, L2, ETB and JU memories 1 at a time */
 741                 if (qproc->version == MSS_MSM8996) {
 742                         mem_pwr_ctl = QDSP6SS_MEM_PWR_CTL;
 743                         i = 19;
 744                 } else {
 745                         /* MSS_MSM8998 */
 746                         mem_pwr_ctl = QDSP6V6SS_MEM_PWR_CTL;
 747                         i = 28;
 748                 }
 749                 val = readl(qproc->reg_base + mem_pwr_ctl);
 750                 for (; i >= 0; i--) {
 751                         val |= BIT(i);
 752                         writel(val, qproc->reg_base + mem_pwr_ctl);
 753                         /*
 754                          * Read back value to ensure the write is done then
 755                          * wait for 1us for both memory peripheral and data
 756                          * array to turn on.
 757                          */
 758                         val |= readl(qproc->reg_base + mem_pwr_ctl);
 759                         udelay(1);
 760                 }
 761                 /* Remove word line clamp */
 762                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 763                 val &= ~QDSP6v56_CLAMP_WL;
 764                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 765         } else {
 766                 /* Assert resets, stop core */
 767                 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 768                 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
 769                 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 770
 771                 /* Enable power block headswitch and wait for it to stabilize */
 772                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 773                 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
 774                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 775                 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 776                 udelay(1);
 777                 /*
 778                  * Turn on memories. L2 banks should be done individually
 779                  * to minimize inrush current.
 780                  */
 781                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 782                 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
 783                         Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
 784                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 785                 val |= Q6SS_L2DATA_SLP_NRET_N_2;
 786                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 787                 val |= Q6SS_L2DATA_SLP_NRET_N_1;
 788                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 789                 val |= Q6SS_L2DATA_SLP_NRET_N_0;
 790                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 791         }
 792         /* Remove IO clamp */
 793         val &= ~Q6SS_CLAMP_IO;
 794         writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
 795
 796         /* Bring core out of reset */
 797         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 798         val &= ~Q6SS_CORE_ARES;
 799         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 800
 801         /* Turn on core clock */
 802         val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 803         val |= Q6SS_CLK_ENABLE;
 804         writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
 805
 806         /* Start core execution */
 807         val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
 808         val &= ~Q6SS_STOP_CORE;
 809         writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
 810
 811 pbl_wait:
 812         /* Wait for PBL status */
 813         ret = q6v5_rmb_pbl_wait(qproc, 1000);
 814         if (ret == -ETIMEDOUT) {
 815                 dev_err(qproc->dev, "PBL boot timed out\n");
 816         } else if (ret != RMB_PBL_SUCCESS) {
 817                 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
 818                 ret = -EINVAL;
 819         } else {
 820                 ret = 0;
 821         }
 822
 823         return ret;
 824 }
 825
 826 static int q6v5proc_enable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
 827 {
 828         unsigned int val;
 829         int ret;
 830
 831         if (!qproc->has_qaccept_regs)
 832                 return 0;
 833
 834         if (qproc->has_ext_cntl_regs) {
 835                 regmap_write(qproc->conn_map, qproc->rscc_disable, 0);
 836                 regmap_write(qproc->conn_map, qproc->force_clk_on, 1);
 837
 838                 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
 839                                                !val, 1, Q6SS_CBCR_TIMEOUT_US);
 840                 if (ret) {
 841                         dev_err(qproc->dev, "failed to enable axim1 clock\n");
 842                         return -ETIMEDOUT;
 843                 }
 844         }
 845
 846         regmap_write(map, offset + QACCEPT_REQ_REG, 1);
 847
 848         /* Wait for accept */
 849         ret = regmap_read_poll_timeout(map, offset + QACCEPT_ACCEPT_REG, val, val, 5,
 850                                        QACCEPT_TIMEOUT_US);
 851         if (ret) {
 852                 dev_err(qproc->dev, "qchannel enable failed\n");
 853                 return -ETIMEDOUT;
 854         }
 855
 856         return 0;
 857 }
 858
 859 static void q6v5proc_disable_qchannel(struct q6v5 *qproc, struct regmap *map, u32 offset)
 860 {
 861         int ret;
 862         unsigned int val, retry;
 863         unsigned int nretry = 10;
 864         bool takedown_complete = false;
 865
 866         if (!qproc->has_qaccept_regs)
 867                 return;
 868
 869         while (!takedown_complete && nretry) {
 870                 nretry--;
 871
 872                 /* Wait for active transactions to complete */
 873                 regmap_read_poll_timeout(map, offset + QACCEPT_ACTIVE_REG, val, !val, 5,
 874                                          QACCEPT_TIMEOUT_US);
 875
 876                 /* Request Q-channel transaction takedown */
 877                 regmap_write(map, offset + QACCEPT_REQ_REG, 0);
 878
 879                 /*
 880                  * If the request is denied, reset the Q-channel takedown request,
 881                  * wait for active transactions to complete and retry takedown.
 882                  */
 883                 retry = 10;
 884                 while (retry) {
 885                         usleep_range(5, 10);
 886                         retry--;
 887                         ret = regmap_read(map, offset + QACCEPT_DENY_REG, &val);
 888                         if (!ret && val) {
 889                                 regmap_write(map, offset + QACCEPT_REQ_REG, 1);
 890                                 break;
 891                         }
 892
 893                         ret = regmap_read(map, offset + QACCEPT_ACCEPT_REG, &val);
 894                         if (!ret && !val) {
 895                                 takedown_complete = true;
 896                                 break;
 897                         }
 898                 }
 899
 900                 if (!retry)
 901                         break;
 902         }
 903
 904         /* Rely on mss_restart to clear out pending transactions on takedown failure */
 905         if (!takedown_complete)
 906                 dev_err(qproc->dev, "qchannel takedown failed\n");
 907 }
 908
 909 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
 910                                    struct regmap *halt_map,
 911                                    u32 offset)
 912 {
 913         unsigned int val;
 914         int ret;
 915
 916         /* Check if we're already idle */
 917         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 918         if (!ret && val)
 919                 return;
 920
 921         /* Assert halt request */
 922         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
 923
 924         /* Wait for halt */
 925         regmap_read_poll_timeout(halt_map, offset + AXI_HALTACK_REG, val,
 926                                  val, 1000, HALT_ACK_TIMEOUT_US);
 927
 928         ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
 929         if (ret || !val)
 930                 dev_err(qproc->dev, "port failed halt\n");
 931
 932         /* Clear halt request (port will remain halted until reset) */
 933         regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 934 }
 935
 936 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw,
 937                                 const char *fw_name)
 938 {
 939         unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
 940         dma_addr_t phys;
 941         void *metadata;
 942         int mdata_perm;
 943         int xferop_ret;
 944         size_t size;
 945         void *ptr;
 946         int ret;
 947
 948         metadata = qcom_mdt_read_metadata(fw, &size, fw_name, qproc->dev);
 949         if (IS_ERR(metadata))
 950                 return PTR_ERR(metadata);
 951
 952         if (qproc->mdata_phys) {
 953                 if (size > qproc->mdata_size) {
 954                         ret = -EINVAL;
 955                         dev_err(qproc->dev, "metadata size outside memory range\n");
 956                         goto free_metadata;
 957                 }
 958
 959                 phys = qproc->mdata_phys;
 960                 ptr = memremap(qproc->mdata_phys, size, MEMREMAP_WC);
 961                 if (!ptr) {
 962                         ret = -EBUSY;
 963                         dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
 964                                 &qproc->mdata_phys, size);
 965                         goto free_metadata;
 966                 }
 967         } else {
 968                 ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
 969                 if (!ptr) {
 970                         ret = -ENOMEM;
 971                         dev_err(qproc->dev, "failed to allocate mdt buffer\n");
 972                         goto free_metadata;
 973                 }
 974         }
 975
 976         memcpy(ptr, metadata, size);
 977
 978         if (qproc->mdata_phys)
 979                 memunmap(ptr);
 980
 981         /* Hypervisor mapping to access metadata by modem */
 982         mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
 983         ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, true,
 984                                       phys, size);
 985         if (ret) {
 986                 dev_err(qproc->dev,
 987                         "assigning Q6 access to metadata failed: %d\n", ret);
 988                 ret = -EAGAIN;
 989                 goto free_dma_attrs;
 990         }
 991
 992         writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
 993         writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
 994
 995         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
 996         if (ret == -ETIMEDOUT)
 997                 dev_err(qproc->dev, "MPSS header authentication timed out\n");
 998         else if (ret < 0)
 999                 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
1000
1001         /* Metadata authentication done, remove modem access */
1002         xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, false,
1003                                              phys, size);
1004         if (xferop_ret)
1005                 dev_warn(qproc->dev,
1006                          "mdt buffer not reclaimed system may become unstable\n");
1007
1008 free_dma_attrs:
1009         if (!qproc->mdata_phys)
1010                 dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
1011 free_metadata:
1012         kfree(metadata);
1013
1014         return ret < 0 ? ret : 0;
1015 }
1016
1017 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
1018 {
1019         if (phdr->p_type != PT_LOAD)
1020                 return false;
1021
1022         if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
1023                 return false;
1024
1025         if (!phdr->p_memsz)
1026                 return false;
1027
1028         return true;
1029 }
1030
1031 static int q6v5_mba_load(struct q6v5 *qproc)
1032 {
1033         int ret;
1034         int xfermemop_ret;
1035         bool mba_load_err = false;
1036
1037         ret = qcom_q6v5_prepare(&qproc->q6v5);
1038         if (ret)
1039                 return ret;
1040
1041         ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1042         if (ret < 0) {
1043                 dev_err(qproc->dev, "failed to enable proxy power domains\n");
1044                 goto disable_irqs;
1045         }
1046
1047         ret = q6v5_regulator_enable(qproc, qproc->fallback_proxy_regs,
1048                                     qproc->fallback_proxy_reg_count);
1049         if (ret) {
1050                 dev_err(qproc->dev, "failed to enable fallback proxy supplies\n");
1051                 goto disable_proxy_pds;
1052         }
1053
1054         ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
1055                                     qproc->proxy_reg_count);
1056         if (ret) {
1057                 dev_err(qproc->dev, "failed to enable proxy supplies\n");
1058                 goto disable_fallback_proxy_reg;
1059         }
1060
1061         ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
1062                               qproc->proxy_clk_count);
1063         if (ret) {
1064                 dev_err(qproc->dev, "failed to enable proxy clocks\n");
1065                 goto disable_proxy_reg;
1066         }
1067
1068         ret = q6v5_regulator_enable(qproc, qproc->active_regs,
1069                                     qproc->active_reg_count);
1070         if (ret) {
1071                 dev_err(qproc->dev, "failed to enable supplies\n");
1072                 goto disable_proxy_clk;
1073         }
1074
1075         ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
1076                               qproc->reset_clk_count);
1077         if (ret) {
1078                 dev_err(qproc->dev, "failed to enable reset clocks\n");
1079                 goto disable_vdd;
1080         }
1081
1082         ret = q6v5_reset_deassert(qproc);
1083         if (ret) {
1084                 dev_err(qproc->dev, "failed to deassert mss restart\n");
1085                 goto disable_reset_clks;
1086         }
1087
1088         ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
1089                               qproc->active_clk_count);
1090         if (ret) {
1091                 dev_err(qproc->dev, "failed to enable clocks\n");
1092                 goto assert_reset;
1093         }
1094
1095         ret = q6v5proc_enable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1096         if (ret) {
1097                 dev_err(qproc->dev, "failed to enable axi bridge\n");
1098                 goto disable_active_clks;
1099         }
1100
1101         /*
1102          * Some versions of the MBA firmware will upon boot wipe the MPSS region as well, so provide
1103          * the Q6 access to this region.
1104          */
1105         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1106                                       qproc->mpss_phys, qproc->mpss_size);
1107         if (ret) {
1108                 dev_err(qproc->dev, "assigning Q6 access to mpss memory failed: %d\n", ret);
1109                 goto disable_active_clks;
1110         }
1111
1112         /* Assign MBA image access in DDR to q6 */
1113         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, true,
1114                                       qproc->mba_phys, qproc->mba_size);
1115         if (ret) {
1116                 dev_err(qproc->dev,
1117                         "assigning Q6 access to mba memory failed: %d\n", ret);
1118                 goto disable_active_clks;
1119         }
1120
1121         writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
1122         if (qproc->dp_size) {
1123                 writel(qproc->mba_phys + SZ_1M, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1124                 writel(qproc->dp_size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1125         }
1126
1127         ret = q6v5proc_reset(qproc);
1128         if (ret)
1129                 goto reclaim_mba;
1130
1131         if (qproc->has_mba_logs)
1132                 qcom_pil_info_store("mba", qproc->mba_phys, MBA_LOG_SIZE);
1133
1134         ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
1135         if (ret == -ETIMEDOUT) {
1136                 dev_err(qproc->dev, "MBA boot timed out\n");
1137                 goto halt_axi_ports;
1138         } else if (ret != RMB_MBA_XPU_UNLOCKED &&
1139                    ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
1140                 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
1141                 ret = -EINVAL;
1142                 goto halt_axi_ports;
1143         }
1144
1145         qproc->dump_mba_loaded = true;
1146         return 0;
1147
1148 halt_axi_ports:
1149         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1150         if (qproc->has_vq6)
1151                 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1152         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1153         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1154         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1155         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1156         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1157         mba_load_err = true;
1158 reclaim_mba:
1159         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1160                                                 false, qproc->mba_phys,
1161                                                 qproc->mba_size);
1162         if (xfermemop_ret) {
1163                 dev_err(qproc->dev,
1164                         "Failed to reclaim mba buffer, system may become unstable\n");
1165         } else if (mba_load_err) {
1166                 q6v5_dump_mba_logs(qproc);
1167         }
1168
1169 disable_active_clks:
1170         q6v5_clk_disable(qproc->dev, qproc->active_clks,
1171                          qproc->active_clk_count);
1172 assert_reset:
1173         q6v5_reset_assert(qproc);
1174 disable_reset_clks:
1175         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1176                          qproc->reset_clk_count);
1177 disable_vdd:
1178         q6v5_regulator_disable(qproc, qproc->active_regs,
1179                                qproc->active_reg_count);
1180 disable_proxy_clk:
1181         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1182                          qproc->proxy_clk_count);
1183 disable_proxy_reg:
1184         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1185                                qproc->proxy_reg_count);
1186 disable_fallback_proxy_reg:
1187         q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1188                                qproc->fallback_proxy_reg_count);
1189 disable_proxy_pds:
1190         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1191 disable_irqs:
1192         qcom_q6v5_unprepare(&qproc->q6v5);
1193
1194         return ret;
1195 }
1196
1197 static void q6v5_mba_reclaim(struct q6v5 *qproc)
1198 {
1199         int ret;
1200         u32 val;
1201
1202         qproc->dump_mba_loaded = false;
1203         qproc->dp_size = 0;
1204
1205         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
1206         if (qproc->has_vq6)
1207                 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_vq6);
1208         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
1209         q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
1210         if (qproc->version == MSS_MSM8996) {
1211                 /*
1212                  * To avoid high MX current during LPASS/MSS restart.
1213                  */
1214                 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1215                 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
1216                         QDSP6v56_CLAMP_QMC_MEM;
1217                 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
1218         }
1219
1220         if (qproc->has_ext_cntl_regs) {
1221                 regmap_write(qproc->conn_map, qproc->rscc_disable, 1);
1222
1223                 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->axim1_clk_off, val,
1224                                                !val, 1, Q6SS_CBCR_TIMEOUT_US);
1225                 if (ret)
1226                         dev_err(qproc->dev, "failed to enable axim1 clock\n");
1227
1228                 ret = regmap_read_poll_timeout(qproc->halt_map, qproc->crypto_clk_off, val,
1229                                                !val, 1, Q6SS_CBCR_TIMEOUT_US);
1230                 if (ret)
1231                         dev_err(qproc->dev, "failed to enable crypto clock\n");
1232         }
1233
1234         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_mdm);
1235         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_cx);
1236         q6v5proc_disable_qchannel(qproc, qproc->halt_map, qproc->qaccept_axi);
1237
1238         q6v5_reset_assert(qproc);
1239
1240         q6v5_clk_disable(qproc->dev, qproc->reset_clks,
1241                          qproc->reset_clk_count);
1242         q6v5_clk_disable(qproc->dev, qproc->active_clks,
1243                          qproc->active_clk_count);
1244         q6v5_regulator_disable(qproc, qproc->active_regs,
1245                                qproc->active_reg_count);
1246
1247         /* In case of failure or coredump scenario where reclaiming MBA memory
1248          * could not happen reclaim it here.
1249          */
1250         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, false,
1251                                       qproc->mba_phys,
1252                                       qproc->mba_size);
1253         WARN_ON(ret);
1254
1255         ret = qcom_q6v5_unprepare(&qproc->q6v5);
1256         if (ret) {
1257                 q6v5_pds_disable(qproc, qproc->proxy_pds,
1258                                  qproc->proxy_pd_count);
1259                 q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1260                                  qproc->proxy_clk_count);
1261                 q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1262                                        qproc->fallback_proxy_reg_count);
1263                 q6v5_regulator_disable(qproc, qproc->proxy_regs,
1264                                        qproc->proxy_reg_count);
1265         }
1266 }
1267
1268 static int q6v5_reload_mba(struct rproc *rproc)
1269 {
1270         struct q6v5 *qproc = rproc->priv;
1271         const struct firmware *fw;
1272         int ret;
1273
1274         ret = request_firmware(&fw, rproc->firmware, qproc->dev);
1275         if (ret < 0)
1276                 return ret;
1277
1278         q6v5_load(rproc, fw);
1279         ret = q6v5_mba_load(qproc);
1280         release_firmware(fw);
1281
1282         return ret;
1283 }
1284
1285 static int q6v5_mpss_load(struct q6v5 *qproc)
1286 {
1287         const struct elf32_phdr *phdrs;
1288         const struct elf32_phdr *phdr;
1289         const struct firmware *seg_fw;
1290         const struct firmware *fw;
1291         struct elf32_hdr *ehdr;
1292         phys_addr_t mpss_reloc;
1293         phys_addr_t boot_addr;
1294         phys_addr_t min_addr = PHYS_ADDR_MAX;
1295         phys_addr_t max_addr = 0;
1296         u32 code_length;
1297         bool relocate = false;
1298         char *fw_name;
1299         size_t fw_name_len;
1300         ssize_t offset;
1301         size_t size = 0;
1302         void *ptr;
1303         int ret;
1304         int i;
1305
1306         fw_name_len = strlen(qproc->hexagon_mdt_image);
1307         if (fw_name_len <= 4)
1308                 return -EINVAL;
1309
1310         fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
1311         if (!fw_name)
1312                 return -ENOMEM;
1313
1314         ret = request_firmware(&fw, fw_name, qproc->dev);
1315         if (ret < 0) {
1316                 dev_err(qproc->dev, "unable to load %s\n", fw_name);
1317                 goto out;
1318         }
1319
1320         /* Initialize the RMB validator */
1321         writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1322
1323         ret = q6v5_mpss_init_image(qproc, fw, qproc->hexagon_mdt_image);
1324         if (ret)
1325                 goto release_firmware;
1326
1327         ehdr = (struct elf32_hdr *)fw->data;
1328         phdrs = (struct elf32_phdr *)(ehdr + 1);
1329
1330         for (i = 0; i < ehdr->e_phnum; i++) {
1331                 phdr = &phdrs[i];
1332
1333                 if (!q6v5_phdr_valid(phdr))
1334                         continue;
1335
1336                 if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
1337                         relocate = true;
1338
1339                 if (phdr->p_paddr < min_addr)
1340                         min_addr = phdr->p_paddr;
1341
1342                 if (phdr->p_paddr + phdr->p_memsz > max_addr)
1343                         max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
1344         }
1345
1346         /*
1347          * In case of a modem subsystem restart on secure devices, the modem
1348          * memory can be reclaimed only after MBA is loaded.
1349          */
1350         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, false,
1351                                 qproc->mpss_phys, qproc->mpss_size);
1352
1353         /* Share ownership between Linux and MSS, during segment loading */
1354         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, true,
1355                                       qproc->mpss_phys, qproc->mpss_size);
1356         if (ret) {
1357                 dev_err(qproc->dev,
1358                         "assigning Q6 access to mpss memory failed: %d\n", ret);
1359                 ret = -EAGAIN;
1360                 goto release_firmware;
1361         }
1362
1363         mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
1364         qproc->mpss_reloc = mpss_reloc;
1365         /* Load firmware segments */
1366         for (i = 0; i < ehdr->e_phnum; i++) {
1367                 phdr = &phdrs[i];
1368
1369                 if (!q6v5_phdr_valid(phdr))
1370                         continue;
1371
1372                 offset = phdr->p_paddr - mpss_reloc;
1373                 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
1374                         dev_err(qproc->dev, "segment outside memory range\n");
1375                         ret = -EINVAL;
1376                         goto release_firmware;
1377                 }
1378
1379                 if (phdr->p_filesz > phdr->p_memsz) {
1380                         dev_err(qproc->dev,
1381                                 "refusing to load segment %d with p_filesz > p_memsz\n",
1382                                 i);
1383                         ret = -EINVAL;
1384                         goto release_firmware;
1385                 }
1386
1387                 ptr = memremap(qproc->mpss_phys + offset, phdr->p_memsz, MEMREMAP_WC);
1388                 if (!ptr) {
1389                         dev_err(qproc->dev,
1390                                 "unable to map memory region: %pa+%zx-%x\n",
1391                                 &qproc->mpss_phys, offset, phdr->p_memsz);
1392                         goto release_firmware;
1393                 }
1394
1395                 if (phdr->p_filesz && phdr->p_offset < fw->size) {
1396                         /* Firmware is large enough to be non-split */
1397                         if (phdr->p_offset + phdr->p_filesz > fw->size) {
1398                                 dev_err(qproc->dev,
1399                                         "failed to load segment %d from truncated file %s\n",
1400                                         i, fw_name);
1401                                 ret = -EINVAL;
1402                                 memunmap(ptr);
1403                                 goto release_firmware;
1404                         }
1405
1406                         memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
1407                 } else if (phdr->p_filesz) {
1408                         /* Replace "xxx.xxx" with "xxx.bxx" */
1409                         sprintf(fw_name + fw_name_len - 3, "b%02d", i);
1410                         ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
1411                                                         ptr, phdr->p_filesz);
1412                         if (ret) {
1413                                 dev_err(qproc->dev, "failed to load %s\n", fw_name);
1414                                 memunmap(ptr);
1415                                 goto release_firmware;
1416                         }
1417
1418                         if (seg_fw->size != phdr->p_filesz) {
1419                                 dev_err(qproc->dev,
1420                                         "failed to load segment %d from truncated file %s\n",
1421                                         i, fw_name);
1422                                 ret = -EINVAL;
1423                                 release_firmware(seg_fw);
1424                                 memunmap(ptr);
1425                                 goto release_firmware;
1426                         }
1427
1428                         release_firmware(seg_fw);
1429                 }
1430
1431                 if (phdr->p_memsz > phdr->p_filesz) {
1432                         memset(ptr + phdr->p_filesz, 0,
1433                                phdr->p_memsz - phdr->p_filesz);
1434                 }
1435                 memunmap(ptr);
1436                 size += phdr->p_memsz;
1437
1438                 code_length = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1439                 if (!code_length) {
1440                         boot_addr = relocate ? qproc->mpss_phys : min_addr;
1441                         writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
1442                         writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
1443                 }
1444                 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
1445
1446                 ret = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
1447                 if (ret < 0) {
1448                         dev_err(qproc->dev, "MPSS authentication failed: %d\n",
1449                                 ret);
1450                         goto release_firmware;
1451                 }
1452         }
1453
1454         /* Transfer ownership of modem ddr region to q6 */
1455         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, true,
1456                                       qproc->mpss_phys, qproc->mpss_size);
1457         if (ret) {
1458                 dev_err(qproc->dev,
1459                         "assigning Q6 access to mpss memory failed: %d\n", ret);
1460                 ret = -EAGAIN;
1461                 goto release_firmware;
1462         }
1463
1464         ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
1465         if (ret == -ETIMEDOUT)
1466                 dev_err(qproc->dev, "MPSS authentication timed out\n");
1467         else if (ret < 0)
1468                 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
1469
1470         qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
1471
1472 release_firmware:
1473         release_firmware(fw);
1474 out:
1475         kfree(fw_name);
1476
1477         return ret < 0 ? ret : 0;
1478 }
1479
1480 static void qcom_q6v5_dump_segment(struct rproc *rproc,
1481                                    struct rproc_dump_segment *segment,
1482                                    void *dest, size_t cp_offset, size_t size)
1483 {
1484         int ret = 0;
1485         struct q6v5 *qproc = rproc->priv;
1486         int offset = segment->da - qproc->mpss_reloc;
1487         void *ptr = NULL;
1488
1489         /* Unlock mba before copying segments */
1490         if (!qproc->dump_mba_loaded) {
1491                 ret = q6v5_reload_mba(rproc);
1492                 if (!ret) {
1493                         /* Reset ownership back to Linux to copy segments */
1494                         ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1495                                                       true, false,
1496                                                       qproc->mpss_phys,
1497                                                       qproc->mpss_size);
1498                 }
1499         }
1500
1501         if (!ret)
1502                 ptr = memremap(qproc->mpss_phys + offset + cp_offset, size, MEMREMAP_WC);
1503
1504         if (ptr) {
1505                 memcpy(dest, ptr, size);
1506                 memunmap(ptr);
1507         } else {
1508                 memset(dest, 0xff, size);
1509         }
1510
1511         qproc->current_dump_size += size;
1512
1513         /* Reclaim mba after copying segments */
1514         if (qproc->current_dump_size == qproc->total_dump_size) {
1515                 if (qproc->dump_mba_loaded) {
1516                         /* Try to reset ownership back to Q6 */
1517                         q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
1518                                                 false, true,
1519                                                 qproc->mpss_phys,
1520                                                 qproc->mpss_size);
1521                         q6v5_mba_reclaim(qproc);
1522                 }
1523         }
1524 }
1525
1526 static int q6v5_start(struct rproc *rproc)
1527 {
1528         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1529         int xfermemop_ret;
1530         int ret;
1531
1532         ret = q6v5_mba_load(qproc);
1533         if (ret)
1534                 return ret;
1535
1536         dev_info(qproc->dev, "MBA booted with%s debug policy, loading mpss\n",
1537                  qproc->dp_size ? "" : "out");
1538
1539         ret = q6v5_mpss_load(qproc);
1540         if (ret)
1541                 goto reclaim_mpss;
1542
1543         ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
1544         if (ret == -ETIMEDOUT) {
1545                 dev_err(qproc->dev, "start timed out\n");
1546                 goto reclaim_mpss;
1547         }
1548
1549         xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
1550                                                 false, qproc->mba_phys,
1551                                                 qproc->mba_size);
1552         if (xfermemop_ret)
1553                 dev_err(qproc->dev,
1554                         "Failed to reclaim mba buffer system may become unstable\n");
1555
1556         /* Reset Dump Segment Mask */
1557         qproc->current_dump_size = 0;
1558
1559         return 0;
1560
1561 reclaim_mpss:
1562         q6v5_mba_reclaim(qproc);
1563         q6v5_dump_mba_logs(qproc);
1564
1565         return ret;
1566 }
1567
1568 static int q6v5_stop(struct rproc *rproc)
1569 {
1570         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1571         int ret;
1572
1573         ret = qcom_q6v5_request_stop(&qproc->q6v5, qproc->sysmon);
1574         if (ret == -ETIMEDOUT)
1575                 dev_err(qproc->dev, "timed out on wait\n");
1576
1577         q6v5_mba_reclaim(qproc);
1578
1579         return 0;
1580 }
1581
1582 static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
1583                                             const struct firmware *mba_fw)
1584 {
1585         const struct firmware *fw;
1586         const struct elf32_phdr *phdrs;
1587         const struct elf32_phdr *phdr;
1588         const struct elf32_hdr *ehdr;
1589         struct q6v5 *qproc = rproc->priv;
1590         unsigned long i;
1591         int ret;
1592
1593         ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
1594         if (ret < 0) {
1595                 dev_err(qproc->dev, "unable to load %s\n",
1596                         qproc->hexagon_mdt_image);
1597                 return ret;
1598         }
1599
1600         rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1601
1602         ehdr = (struct elf32_hdr *)fw->data;
1603         phdrs = (struct elf32_phdr *)(ehdr + 1);
1604         qproc->total_dump_size = 0;
1605
1606         for (i = 0; i < ehdr->e_phnum; i++) {
1607                 phdr = &phdrs[i];
1608
1609                 if (!q6v5_phdr_valid(phdr))
1610                         continue;
1611
1612                 ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
1613                                                         phdr->p_memsz,
1614                                                         qcom_q6v5_dump_segment,
1615                                                         NULL);
1616                 if (ret)
1617                         break;
1618
1619                 qproc->total_dump_size += phdr->p_memsz;
1620         }
1621
1622         release_firmware(fw);
1623         return ret;
1624 }
1625
1626 static unsigned long q6v5_panic(struct rproc *rproc)
1627 {
1628         struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
1629
1630         return qcom_q6v5_panic(&qproc->q6v5);
1631 }
1632
1633 static const struct rproc_ops q6v5_ops = {
1634         .start = q6v5_start,
1635         .stop = q6v5_stop,
1636         .parse_fw = qcom_q6v5_register_dump_segments,
1637         .load = q6v5_load,
1638         .panic = q6v5_panic,
1639 };
1640
1641 static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
1642 {
1643         struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
1644
1645         q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
1646                          qproc->proxy_clk_count);
1647         q6v5_regulator_disable(qproc, qproc->proxy_regs,
1648                                qproc->proxy_reg_count);
1649         q6v5_regulator_disable(qproc, qproc->fallback_proxy_regs,
1650                                qproc->fallback_proxy_reg_count);
1651         q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
1652 }
1653
1654 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
1655 {
1656         struct of_phandle_args args;
1657         int halt_cell_cnt = 3;
1658         int ret;
1659
1660         qproc->reg_base = devm_platform_ioremap_resource_byname(pdev, "qdsp6");
1661         if (IS_ERR(qproc->reg_base))
1662                 return PTR_ERR(qproc->reg_base);
1663
1664         qproc->rmb_base = devm_platform_ioremap_resource_byname(pdev, "rmb");
1665         if (IS_ERR(qproc->rmb_base))
1666                 return PTR_ERR(qproc->rmb_base);
1667
1668         if (qproc->has_vq6)
1669                 halt_cell_cnt++;
1670
1671         ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1672                                                "qcom,halt-regs", halt_cell_cnt, 0, &args);
1673         if (ret < 0) {
1674                 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
1675                 return -EINVAL;
1676         }
1677
1678         qproc->halt_map = syscon_node_to_regmap(args.np);
1679         of_node_put(args.np);
1680         if (IS_ERR(qproc->halt_map))
1681                 return PTR_ERR(qproc->halt_map);
1682
1683         qproc->halt_q6 = args.args[0];
1684         qproc->halt_modem = args.args[1];
1685         qproc->halt_nc = args.args[2];
1686
1687         if (qproc->has_vq6)
1688                 qproc->halt_vq6 = args.args[3];
1689
1690         if (qproc->has_qaccept_regs) {
1691                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1692                                                        "qcom,qaccept-regs",
1693                                                        3, 0, &args);
1694                 if (ret < 0) {
1695                         dev_err(&pdev->dev, "failed to parse qaccept-regs\n");
1696                         return -EINVAL;
1697                 }
1698
1699                 qproc->qaccept_mdm = args.args[0];
1700                 qproc->qaccept_cx = args.args[1];
1701                 qproc->qaccept_axi = args.args[2];
1702         }
1703
1704         if (qproc->has_ext_cntl_regs) {
1705                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1706                                                        "qcom,ext-regs",
1707                                                        2, 0, &args);
1708                 if (ret < 0) {
1709                         dev_err(&pdev->dev, "failed to parse ext-regs index 0\n");
1710                         return -EINVAL;
1711                 }
1712
1713                 qproc->conn_map = syscon_node_to_regmap(args.np);
1714                 of_node_put(args.np);
1715                 if (IS_ERR(qproc->conn_map))
1716                         return PTR_ERR(qproc->conn_map);
1717
1718                 qproc->force_clk_on = args.args[0];
1719                 qproc->rscc_disable = args.args[1];
1720
1721                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1722                                                        "qcom,ext-regs",
1723                                                        2, 1, &args);
1724                 if (ret < 0) {
1725                         dev_err(&pdev->dev, "failed to parse ext-regs index 1\n");
1726                         return -EINVAL;
1727                 }
1728
1729                 qproc->axim1_clk_off = args.args[0];
1730                 qproc->crypto_clk_off = args.args[1];
1731         }
1732
1733         if (qproc->has_spare_reg) {
1734                 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
1735                                                        "qcom,spare-regs",
1736                                                        1, 0, &args);
1737                 if (ret < 0) {
1738                         dev_err(&pdev->dev, "failed to parse spare-regs\n");
1739                         return -EINVAL;
1740                 }
1741
1742                 qproc->conn_map = syscon_node_to_regmap(args.np);
1743                 of_node_put(args.np);
1744                 if (IS_ERR(qproc->conn_map))
1745                         return PTR_ERR(qproc->conn_map);
1746
1747                 qproc->conn_box = args.args[0];
1748         }
1749
1750         return 0;
1751 }
1752
1753 static int q6v5_init_clocks(struct device *dev, struct clk **clks,
1754                 char **clk_names)
1755 {
1756         int i;
1757
1758         if (!clk_names)
1759                 return 0;
1760
1761         for (i = 0; clk_names[i]; i++) {
1762                 clks[i] = devm_clk_get(dev, clk_names[i]);
1763                 if (IS_ERR(clks[i])) {
1764                         int rc = PTR_ERR(clks[i]);
1765
1766                         if (rc != -EPROBE_DEFER)
1767                                 dev_err(dev, "Failed to get %s clock\n",
1768                                         clk_names[i]);
1769                         return rc;
1770                 }
1771         }
1772
1773         return i;
1774 }
1775
1776 static int q6v5_pds_attach(struct device *dev, struct device **devs,
1777                            char **pd_names)
1778 {
1779         size_t num_pds = 0;
1780         int ret;
1781         int i;
1782
1783         if (!pd_names)
1784                 return 0;
1785
1786         while (pd_names[num_pds])
1787                 num_pds++;
1788
1789         for (i = 0; i < num_pds; i++) {
1790                 devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
1791                 if (IS_ERR_OR_NULL(devs[i])) {
1792                         ret = PTR_ERR(devs[i]) ? : -ENODATA;
1793                         goto unroll_attach;
1794                 }
1795         }
1796
1797         return num_pds;
1798
1799 unroll_attach:
1800         for (i--; i >= 0; i--)
1801                 dev_pm_domain_detach(devs[i], false);
1802
1803         return ret;
1804 }
1805
1806 static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
1807                             size_t pd_count)
1808 {
1809         int i;
1810
1811         for (i = 0; i < pd_count; i++)
1812                 dev_pm_domain_detach(pds[i], false);
1813 }
1814
1815 static int q6v5_init_reset(struct q6v5 *qproc)
1816 {
1817         qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
1818                                                               "mss_restart");
1819         if (IS_ERR(qproc->mss_restart)) {
1820                 dev_err(qproc->dev, "failed to acquire mss restart\n");
1821                 return PTR_ERR(qproc->mss_restart);
1822         }
1823
1824         if (qproc->has_alt_reset || qproc->has_spare_reg || qproc->has_ext_cntl_regs) {
1825                 qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
1826                                                                     "pdc_reset");
1827                 if (IS_ERR(qproc->pdc_reset)) {
1828                         dev_err(qproc->dev, "failed to acquire pdc reset\n");
1829                         return PTR_ERR(qproc->pdc_reset);
1830                 }
1831         }
1832
1833         return 0;
1834 }
1835
1836 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
1837 {
1838         struct device_node *child;
1839         struct reserved_mem *rmem;
1840         struct device_node *node;
1841         struct resource r;
1842         int ret;
1843
1844         /*
1845          * In the absence of mba/mpss sub-child, extract the mba and mpss
1846          * reserved memory regions from device's memory-region property.
1847          */
1848         child = of_get_child_by_name(qproc->dev->of_node, "mba");
1849         if (!child) {
1850                 node = of_parse_phandle(qproc->dev->of_node,
1851                                         "memory-region", 0);
1852         } else {
1853                 node = of_parse_phandle(child, "memory-region", 0);
1854                 of_node_put(child);
1855         }
1856
1857         ret = of_address_to_resource(node, 0, &r);
1858         of_node_put(node);
1859         if (ret) {
1860                 dev_err(qproc->dev, "unable to resolve mba region\n");
1861                 return ret;
1862         }
1863
1864         qproc->mba_phys = r.start;
1865         qproc->mba_size = resource_size(&r);
1866
1867         if (!child) {
1868                 node = of_parse_phandle(qproc->dev->of_node,
1869                                         "memory-region", 1);
1870         } else {
1871                 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
1872                 node = of_parse_phandle(child, "memory-region", 0);
1873                 of_node_put(child);
1874         }
1875
1876         ret = of_address_to_resource(node, 0, &r);
1877         of_node_put(node);
1878         if (ret) {
1879                 dev_err(qproc->dev, "unable to resolve mpss region\n");
1880                 return ret;
1881         }
1882
1883         qproc->mpss_phys = qproc->mpss_reloc = r.start;
1884         qproc->mpss_size = resource_size(&r);
1885
1886         if (!child) {
1887                 node = of_parse_phandle(qproc->dev->of_node, "memory-region", 2);
1888         } else {
1889                 child = of_get_child_by_name(qproc->dev->of_node, "metadata");
1890                 node = of_parse_phandle(child, "memory-region", 0);
1891                 of_node_put(child);
1892         }
1893
1894         if (!node)
1895                 return 0;
1896
1897         rmem = of_reserved_mem_lookup(node);
1898         if (!rmem) {
1899                 dev_err(qproc->dev, "unable to resolve metadata region\n");
1900                 return -EINVAL;
1901         }
1902
1903         qproc->mdata_phys = rmem->base;
1904         qproc->mdata_size = rmem->size;
1905
1906         return 0;
1907 }
1908
1909 static int q6v5_probe(struct platform_device *pdev)
1910 {
1911         const struct rproc_hexagon_res *desc;
1912         struct device_node *node;
1913         struct q6v5 *qproc;
1914         struct rproc *rproc;
1915         const char *mba_image;
1916         int ret;
1917
1918         desc = of_device_get_match_data(&pdev->dev);
1919         if (!desc)
1920                 return -EINVAL;
1921
1922         if (desc->need_mem_protection && !qcom_scm_is_available())
1923                 return -EPROBE_DEFER;
1924
1925         mba_image = desc->hexagon_mba_image;
1926         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1927                                             0, &mba_image);
1928         if (ret < 0 && ret != -EINVAL) {
1929                 dev_err(&pdev->dev, "unable to read mba firmware-name\n");
1930                 return ret;
1931         }
1932
1933         rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
1934                             mba_image, sizeof(*qproc));
1935         if (!rproc) {
1936                 dev_err(&pdev->dev, "failed to allocate rproc\n");
1937                 return -ENOMEM;
1938         }
1939
1940         rproc->auto_boot = false;
1941         rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE);
1942
1943         qproc = (struct q6v5 *)rproc->priv;
1944         qproc->dev = &pdev->dev;
1945         qproc->rproc = rproc;
1946         qproc->hexagon_mdt_image = "modem.mdt";
1947         ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
1948                                             1, &qproc->hexagon_mdt_image);
1949         if (ret < 0 && ret != -EINVAL) {
1950                 dev_err(&pdev->dev, "unable to read mpss firmware-name\n");
1951                 goto free_rproc;
1952         }
1953
1954         platform_set_drvdata(pdev, qproc);
1955
1956         qproc->has_qaccept_regs = desc->has_qaccept_regs;
1957         qproc->has_ext_cntl_regs = desc->has_ext_cntl_regs;
1958         qproc->has_vq6 = desc->has_vq6;
1959         qproc->has_spare_reg = desc->has_spare_reg;
1960         ret = q6v5_init_mem(qproc, pdev);
1961         if (ret)
1962                 goto free_rproc;
1963
1964         ret = q6v5_alloc_memory_region(qproc);
1965         if (ret)
1966                 goto free_rproc;
1967
1968         ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
1969                                desc->proxy_clk_names);
1970         if (ret < 0) {
1971                 dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
1972                 goto free_rproc;
1973         }
1974         qproc->proxy_clk_count = ret;
1975
1976         ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
1977                                desc->reset_clk_names);
1978         if (ret < 0) {
1979                 dev_err(&pdev->dev, "Failed to get reset clocks.\n");
1980                 goto free_rproc;
1981         }
1982         qproc->reset_clk_count = ret;
1983
1984         ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
1985                                desc->active_clk_names);
1986         if (ret < 0) {
1987                 dev_err(&pdev->dev, "Failed to get active clocks.\n");
1988                 goto free_rproc;
1989         }
1990         qproc->active_clk_count = ret;
1991
1992         ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
1993                                   desc->proxy_supply);
1994         if (ret < 0) {
1995                 dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
1996                 goto free_rproc;
1997         }
1998         qproc->proxy_reg_count = ret;
1999
2000         ret = q6v5_regulator_init(&pdev->dev,  qproc->active_regs,
2001                                   desc->active_supply);
2002         if (ret < 0) {
2003                 dev_err(&pdev->dev, "Failed to get active regulators.\n");
2004                 goto free_rproc;
2005         }
2006         qproc->active_reg_count = ret;
2007
2008         ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
2009                               desc->proxy_pd_names);
2010         /* Fallback to regulators for old device trees */
2011         if (ret == -ENODATA && desc->fallback_proxy_supply) {
2012                 ret = q6v5_regulator_init(&pdev->dev,
2013                                           qproc->fallback_proxy_regs,
2014                                           desc->fallback_proxy_supply);
2015                 if (ret < 0) {
2016                         dev_err(&pdev->dev, "Failed to get fallback proxy regulators.\n");
2017                         goto free_rproc;
2018                 }
2019                 qproc->fallback_proxy_reg_count = ret;
2020         } else if (ret < 0) {
2021                 dev_err(&pdev->dev, "Failed to init power domains\n");
2022                 goto free_rproc;
2023         } else {
2024                 qproc->proxy_pd_count = ret;
2025         }
2026
2027         qproc->has_alt_reset = desc->has_alt_reset;
2028         ret = q6v5_init_reset(qproc);
2029         if (ret)
2030                 goto detach_proxy_pds;
2031
2032         qproc->version = desc->version;
2033         qproc->need_mem_protection = desc->need_mem_protection;
2034         qproc->has_mba_logs = desc->has_mba_logs;
2035
2036         ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, "modem",
2037                              qcom_msa_handover);
2038         if (ret)
2039                 goto detach_proxy_pds;
2040
2041         qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
2042         qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
2043         qcom_add_glink_subdev(rproc, &qproc->glink_subdev, "mpss");
2044         qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
2045         qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
2046         qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
2047         if (IS_ERR(qproc->sysmon)) {
2048                 ret = PTR_ERR(qproc->sysmon);
2049                 goto remove_subdevs;
2050         }
2051
2052         ret = rproc_add(rproc);
2053         if (ret)
2054                 goto remove_sysmon_subdev;
2055
2056         node = of_get_compatible_child(pdev->dev.of_node, "qcom,bam-dmux");
2057         qproc->bam_dmux = of_platform_device_create(node, NULL, &pdev->dev);
2058         of_node_put(node);
2059
2060         return 0;
2061
2062 remove_sysmon_subdev:
2063         qcom_remove_sysmon_subdev(qproc->sysmon);
2064 remove_subdevs:
2065         qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
2066         qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
2067         qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2068 detach_proxy_pds:
2069         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2070 free_rproc:
2071         rproc_free(rproc);
2072
2073         return ret;
2074 }
2075
2076 static int q6v5_remove(struct platform_device *pdev)
2077 {
2078         struct q6v5 *qproc = platform_get_drvdata(pdev);
2079         struct rproc *rproc = qproc->rproc;
2080
2081         if (qproc->bam_dmux)
2082                 of_platform_device_destroy(&qproc->bam_dmux->dev, NULL);
2083         rproc_del(rproc);
2084
2085         qcom_q6v5_deinit(&qproc->q6v5);
2086         qcom_remove_sysmon_subdev(qproc->sysmon);
2087         qcom_remove_ssr_subdev(rproc, &qproc->ssr_subdev);
2088         qcom_remove_smd_subdev(rproc, &qproc->smd_subdev);
2089         qcom_remove_glink_subdev(rproc, &qproc->glink_subdev);
2090
2091         q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
2092
2093         rproc_free(rproc);
2094
2095         return 0;
2096 }
2097
2098 static const struct rproc_hexagon_res sc7180_mss = {
2099         .hexagon_mba_image = "mba.mbn",
2100         .proxy_clk_names = (char*[]){
2101                 "xo",
2102                 NULL
2103         },
2104         .reset_clk_names = (char*[]){
2105                 "iface",
2106                 "bus",
2107                 "snoc_axi",
2108                 NULL
2109         },
2110         .active_clk_names = (char*[]){
2111                 "mnoc_axi",
2112                 "nav",
2113                 NULL
2114         },
2115         .proxy_pd_names = (char*[]){
2116                 "cx",
2117                 "mx",
2118                 "mss",
2119                 NULL
2120         },
2121         .need_mem_protection = true,
2122         .has_alt_reset = false,
2123         .has_mba_logs = true,
2124         .has_spare_reg = true,
2125         .has_qaccept_regs = false,
2126         .has_ext_cntl_regs = false,
2127         .has_vq6 = false,
2128         .version = MSS_SC7180,
2129 };
2130
2131 static const struct rproc_hexagon_res sc7280_mss = {
2132         .hexagon_mba_image = "mba.mbn",
2133         .proxy_clk_names = (char*[]){
2134                 "xo",
2135                 "pka",
2136                 NULL
2137         },
2138         .active_clk_names = (char*[]){
2139                 "iface",
2140                 "offline",
2141                 "snoc_axi",
2142                 NULL
2143         },
2144         .proxy_pd_names = (char*[]){
2145                 "cx",
2146                 "mss",
2147                 NULL
2148         },
2149         .need_mem_protection = true,
2150         .has_alt_reset = false,
2151         .has_mba_logs = true,
2152         .has_spare_reg = false,
2153         .has_qaccept_regs = true,
2154         .has_ext_cntl_regs = true,
2155         .has_vq6 = true,
2156         .version = MSS_SC7280,
2157 };
2158
2159 static const struct rproc_hexagon_res sdm845_mss = {
2160         .hexagon_mba_image = "mba.mbn",
2161         .proxy_clk_names = (char*[]){
2162                         "xo",
2163                         "prng",
2164                         NULL
2165         },
2166         .reset_clk_names = (char*[]){
2167                         "iface",
2168                         "snoc_axi",
2169                         NULL
2170         },
2171         .active_clk_names = (char*[]){
2172                         "bus",
2173                         "mem",
2174                         "gpll0_mss",
2175                         "mnoc_axi",
2176                         NULL
2177         },
2178         .proxy_pd_names = (char*[]){
2179                         "cx",
2180                         "mx",
2181                         "mss",
2182                         NULL
2183         },
2184         .need_mem_protection = true,
2185         .has_alt_reset = true,
2186         .has_mba_logs = false,
2187         .has_spare_reg = false,
2188         .has_qaccept_regs = false,
2189         .has_ext_cntl_regs = false,
2190         .has_vq6 = false,
2191         .version = MSS_SDM845,
2192 };
2193
2194 static const struct rproc_hexagon_res msm8998_mss = {
2195         .hexagon_mba_image = "mba.mbn",
2196         .proxy_clk_names = (char*[]){
2197                         "xo",
2198                         "qdss",
2199                         "mem",
2200                         NULL
2201         },
2202         .active_clk_names = (char*[]){
2203                         "iface",
2204                         "bus",
2205                         "gpll0_mss",
2206                         "mnoc_axi",
2207                         "snoc_axi",
2208                         NULL
2209         },
2210         .proxy_pd_names = (char*[]){
2211                         "cx",
2212                         "mx",
2213                         NULL
2214         },
2215         .need_mem_protection = true,
2216         .has_alt_reset = false,
2217         .has_mba_logs = false,
2218         .has_spare_reg = false,
2219         .has_qaccept_regs = false,
2220         .has_ext_cntl_regs = false,
2221         .has_vq6 = false,
2222         .version = MSS_MSM8998,
2223 };
2224
2225 static const struct rproc_hexagon_res msm8996_mss = {
2226         .hexagon_mba_image = "mba.mbn",
2227         .proxy_supply = (struct qcom_mss_reg_res[]) {
2228                 {
2229                         .supply = "pll",
2230                         .uA = 100000,
2231                 },
2232                 {}
2233         },
2234         .proxy_clk_names = (char*[]){
2235                         "xo",
2236                         "pnoc",
2237                         "qdss",
2238                         NULL
2239         },
2240         .active_clk_names = (char*[]){
2241                         "iface",
2242                         "bus",
2243                         "mem",
2244                         "gpll0_mss",
2245                         "snoc_axi",
2246                         "mnoc_axi",
2247                         NULL
2248         },
2249         .proxy_pd_names = (char*[]){
2250                         "mx",
2251                         "cx",
2252                         NULL
2253         },
2254         .need_mem_protection = true,
2255         .has_alt_reset = false,
2256         .has_mba_logs = false,
2257         .has_spare_reg = false,
2258         .has_qaccept_regs = false,
2259         .has_ext_cntl_regs = false,
2260         .has_vq6 = false,
2261         .version = MSS_MSM8996,
2262 };
2263
2264 static const struct rproc_hexagon_res msm8916_mss = {
2265         .hexagon_mba_image = "mba.mbn",
2266         .proxy_supply = (struct qcom_mss_reg_res[]) {
2267                 {
2268                         .supply = "pll",
2269                         .uA = 100000,
2270                 },
2271                 {}
2272         },
2273         .fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
2274                 {
2275                         .supply = "mx",
2276                         .uV = 1050000,
2277                 },
2278                 {
2279                         .supply = "cx",
2280                         .uA = 100000,
2281                 },
2282                 {}
2283         },
2284         .proxy_clk_names = (char*[]){
2285                 "xo",
2286                 NULL
2287         },
2288         .active_clk_names = (char*[]){
2289                 "iface",
2290                 "bus",
2291                 "mem",
2292                 NULL
2293         },
2294         .proxy_pd_names = (char*[]){
2295                 "mx",
2296                 "cx",
2297                 NULL
2298         },
2299         .need_mem_protection = false,
2300         .has_alt_reset = false,
2301         .has_mba_logs = false,
2302         .has_spare_reg = false,
2303         .has_qaccept_regs = false,
2304         .has_ext_cntl_regs = false,
2305         .has_vq6 = false,
2306         .version = MSS_MSM8916,
2307 };
2308
2309 static const struct rproc_hexagon_res msm8974_mss = {
2310         .hexagon_mba_image = "mba.b00",
2311         .proxy_supply = (struct qcom_mss_reg_res[]) {
2312                 {
2313                         .supply = "pll",
2314                         .uA = 100000,
2315                 },
2316                 {}
2317         },
2318         .fallback_proxy_supply = (struct qcom_mss_reg_res[]) {
2319                 {
2320                         .supply = "mx",
2321                         .uV = 1050000,
2322                 },
2323                 {
2324                         .supply = "cx",
2325                         .uA = 100000,
2326                 },
2327                 {}
2328         },
2329         .active_supply = (struct qcom_mss_reg_res[]) {
2330                 {
2331                         .supply = "mss",
2332                         .uV = 1050000,
2333                         .uA = 100000,
2334                 },
2335                 {}
2336         },
2337         .proxy_clk_names = (char*[]){
2338                 "xo",
2339                 NULL
2340         },
2341         .active_clk_names = (char*[]){
2342                 "iface",
2343                 "bus",
2344                 "mem",
2345                 NULL
2346         },
2347         .proxy_pd_names = (char*[]){
2348                 "mx",
2349                 "cx",
2350                 NULL
2351         },
2352         .need_mem_protection = false,
2353         .has_alt_reset = false,
2354         .has_mba_logs = false,
2355         .has_spare_reg = false,
2356         .has_qaccept_regs = false,
2357         .has_ext_cntl_regs = false,
2358         .has_vq6 = false,
2359         .version = MSS_MSM8974,
2360 };
2361
2362 static const struct of_device_id q6v5_of_match[] = {
2363         { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
2364         { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
2365         { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
2366         { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
2367         { .compatible = "qcom,msm8998-mss-pil", .data = &msm8998_mss},
2368         { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss},
2369         { .compatible = "qcom,sc7280-mss-pil", .data = &sc7280_mss},
2370         { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
2371         { },
2372 };
2373 MODULE_DEVICE_TABLE(of, q6v5_of_match);
2374
2375 static struct platform_driver q6v5_driver = {
2376         .probe = q6v5_probe,
2377         .remove = q6v5_remove,
2378         .driver = {
2379                 .name = "qcom-q6v5-mss",
2380                 .of_match_table = q6v5_of_match,
2381         },
2382 };
2383 module_platform_driver(q6v5_driver);
2384
2385 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
2386 MODULE_LICENSE("GPL v2");