drivers/regulator/wm8350-regulator.c

   1 /*
   2  * wm8350.c  --  Voltage and current regulation for the Wolfson WM8350 PMIC
   3  *
   4  * Copyright 2007, 2008 Wolfson Microelectronics PLC.
   5  *
   6  * Author: Liam Girdwood
   7  *         linux@wolfsonmicro.com
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/moduleparam.h>
  17 #include <linux/init.h>
  18 #include <linux/bitops.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/mfd/wm8350/core.h>
  22 #include <linux/mfd/wm8350/pmic.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regulator/driver.h>
  25 #include <linux/regulator/machine.h>
  26
  27 /* Maximum value possible for VSEL */
  28 #define WM8350_DCDC_MAX_VSEL 0x66
  29
  30 /* Microamps */
  31 static const int isink_cur[] = {
  32         4,
  33         5,
  34         6,
  35         7,
  36         8,
  37         10,
  38         11,
  39         14,
  40         16,
  41         19,
  42         23,
  43         27,
  44         32,
  45         39,
  46         46,
  47         54,
  48         65,
  49         77,
  50         92,
  51         109,
  52         130,
  53         154,
  54         183,
  55         218,
  56         259,
  57         308,
  58         367,
  59         436,
  60         518,
  61         616,
  62         733,
  63         872,
  64         1037,
  65         1233,
  66         1466,
  67         1744,
  68         2073,
  69         2466,
  70         2933,
  71         3487,
  72         4147,
  73         4932,
  74         5865,
  75         6975,
  76         8294,
  77         9864,
  78         11730,
  79         13949,
  80         16589,
  81         19728,
  82         23460,
  83         27899,
  84         33178,
  85         39455,
  86         46920,
  87         55798,
  88         66355,
  89         78910,
  90         93840,
  91         111596,
  92         132710,
  93         157820,
  94         187681,
  95         223191
  96 };
  97
  98 static int get_isink_val(int min_uA, int max_uA, u16 *setting)
  99 {
 100         int i;
 101
 102         for (i = 0; i < ARRAY_SIZE(isink_cur); i++) {
 103                 if (min_uA <= isink_cur[i] && max_uA >= isink_cur[i]) {
 104                         *setting = i;
 105                         return 0;
 106                 }
 107         }
 108         return -EINVAL;
 109 }
 110
 111 static int wm8350_isink_set_current(struct regulator_dev *rdev, int min_uA,
 112         int max_uA)
 113 {
 114         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 115         int isink = rdev_get_id(rdev);
 116         u16 val, setting;
 117         int ret;
 118
 119         ret = get_isink_val(min_uA, max_uA, &setting);
 120         if (ret != 0)
 121                 return ret;
 122
 123         switch (isink) {
 124         case WM8350_ISINK_A:
 125                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 126                     ~WM8350_CS1_ISEL_MASK;
 127                 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_A,
 128                                  val | setting);
 129                 break;
 130         case WM8350_ISINK_B:
 131                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 132                     ~WM8350_CS1_ISEL_MASK;
 133                 wm8350_reg_write(wm8350, WM8350_CURRENT_SINK_DRIVER_B,
 134                                  val | setting);
 135                 break;
 136         default:
 137                 return -EINVAL;
 138         }
 139
 140         return 0;
 141 }
 142
 143 static int wm8350_isink_get_current(struct regulator_dev *rdev)
 144 {
 145         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 146         int isink = rdev_get_id(rdev);
 147         u16 val;
 148
 149         switch (isink) {
 150         case WM8350_ISINK_A:
 151                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 152                     WM8350_CS1_ISEL_MASK;
 153                 break;
 154         case WM8350_ISINK_B:
 155                 val = wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 156                     WM8350_CS1_ISEL_MASK;
 157                 break;
 158         default:
 159                 return 0;
 160         }
 161
 162         return isink_cur[val];
 163 }
 164
 165 /* turn on ISINK followed by DCDC */
 166 static int wm8350_isink_enable(struct regulator_dev *rdev)
 167 {
 168         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 169         int isink = rdev_get_id(rdev);
 170
 171         switch (isink) {
 172         case WM8350_ISINK_A:
 173                 switch (wm8350->pmic.isink_A_dcdc) {
 174                 case WM8350_DCDC_2:
 175                 case WM8350_DCDC_5:
 176                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
 177                                         WM8350_CS1_ENA);
 178                         wm8350_set_bits(wm8350, WM8350_CSA_FLASH_CONTROL,
 179                                         WM8350_CS1_DRIVE);
 180                         wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 181                                         1 << (wm8350->pmic.isink_A_dcdc -
 182                                               WM8350_DCDC_1));
 183                         break;
 184                 default:
 185                         return -EINVAL;
 186                 }
 187                 break;
 188         case WM8350_ISINK_B:
 189                 switch (wm8350->pmic.isink_B_dcdc) {
 190                 case WM8350_DCDC_2:
 191                 case WM8350_DCDC_5:
 192                         wm8350_set_bits(wm8350, WM8350_POWER_MGMT_7,
 193                                         WM8350_CS2_ENA);
 194                         wm8350_set_bits(wm8350, WM8350_CSB_FLASH_CONTROL,
 195                                         WM8350_CS2_DRIVE);
 196                         wm8350_set_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 197                                         1 << (wm8350->pmic.isink_B_dcdc -
 198                                               WM8350_DCDC_1));
 199                         break;
 200                 default:
 201                         return -EINVAL;
 202                 }
 203                 break;
 204         default:
 205                 return -EINVAL;
 206         }
 207         return 0;
 208 }
 209
 210 static int wm8350_isink_disable(struct regulator_dev *rdev)
 211 {
 212         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 213         int isink = rdev_get_id(rdev);
 214
 215         switch (isink) {
 216         case WM8350_ISINK_A:
 217                 switch (wm8350->pmic.isink_A_dcdc) {
 218                 case WM8350_DCDC_2:
 219                 case WM8350_DCDC_5:
 220                         wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 221                                           1 << (wm8350->pmic.isink_A_dcdc -
 222                                                 WM8350_DCDC_1));
 223                         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
 224                                           WM8350_CS1_ENA);
 225                         break;
 226                 default:
 227                         return -EINVAL;
 228                 }
 229                 break;
 230         case WM8350_ISINK_B:
 231                 switch (wm8350->pmic.isink_B_dcdc) {
 232                 case WM8350_DCDC_2:
 233                 case WM8350_DCDC_5:
 234                         wm8350_clear_bits(wm8350, WM8350_DCDC_LDO_REQUESTED,
 235                                           1 << (wm8350->pmic.isink_B_dcdc -
 236                                                 WM8350_DCDC_1));
 237                         wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_7,
 238                                           WM8350_CS2_ENA);
 239                         break;
 240                 default:
 241                         return -EINVAL;
 242                 }
 243                 break;
 244         default:
 245                 return -EINVAL;
 246         }
 247         return 0;
 248 }
 249
 250 static int wm8350_isink_is_enabled(struct regulator_dev *rdev)
 251 {
 252         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 253         int isink = rdev_get_id(rdev);
 254
 255         switch (isink) {
 256         case WM8350_ISINK_A:
 257                 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_A) &
 258                     0x8000;
 259         case WM8350_ISINK_B:
 260                 return wm8350_reg_read(wm8350, WM8350_CURRENT_SINK_DRIVER_B) &
 261                     0x8000;
 262         }
 263         return -EINVAL;
 264 }
 265
 266 static int wm8350_isink_enable_time(struct regulator_dev *rdev)
 267 {
 268         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 269         int isink = rdev_get_id(rdev);
 270         int reg;
 271
 272         switch (isink) {
 273         case WM8350_ISINK_A:
 274                 reg = wm8350_reg_read(wm8350, WM8350_CSA_FLASH_CONTROL);
 275                 break;
 276         case WM8350_ISINK_B:
 277                 reg = wm8350_reg_read(wm8350, WM8350_CSB_FLASH_CONTROL);
 278                 break;
 279         default:
 280                 return -EINVAL;
 281         }
 282
 283         if (reg & WM8350_CS1_FLASH_MODE) {
 284                 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
 285                 case 0:
 286                         return 0;
 287                 case 1:
 288                         return 1950;
 289                 case 2:
 290                         return 3910;
 291                 case 3:
 292                         return 7800;
 293                 }
 294         } else {
 295                 switch (reg & WM8350_CS1_ON_RAMP_MASK) {
 296                 case 0:
 297                         return 0;
 298                 case 1:
 299                         return 250000;
 300                 case 2:
 301                         return 500000;
 302                 case 3:
 303                         return 1000000;
 304                 }
 305         }
 306
 307         return -EINVAL;
 308 }
 309
 310
 311 int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
 312                            u16 trigger, u16 duration, u16 on_ramp, u16 off_ramp,
 313                            u16 drive)
 314 {
 315         switch (isink) {
 316         case WM8350_ISINK_A:
 317                 wm8350_reg_write(wm8350, WM8350_CSA_FLASH_CONTROL,
 318                                  (mode ? WM8350_CS1_FLASH_MODE : 0) |
 319                                  (trigger ? WM8350_CS1_TRIGSRC : 0) |
 320                                  duration | on_ramp | off_ramp | drive);
 321                 break;
 322         case WM8350_ISINK_B:
 323                 wm8350_reg_write(wm8350, WM8350_CSB_FLASH_CONTROL,
 324                                  (mode ? WM8350_CS2_FLASH_MODE : 0) |
 325                                  (trigger ? WM8350_CS2_TRIGSRC : 0) |
 326                                  duration | on_ramp | off_ramp | drive);
 327                 break;
 328         default:
 329                 return -EINVAL;
 330         }
 331         return 0;
 332 }
 333 EXPORT_SYMBOL_GPL(wm8350_isink_set_flash);
 334
 335 static int wm8350_dcdc_set_suspend_voltage(struct regulator_dev *rdev, int uV)
 336 {
 337         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 338         int sel, volt_reg, dcdc = rdev_get_id(rdev);
 339         u16 val;
 340
 341         dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, dcdc, uV / 1000);
 342
 343         switch (dcdc) {
 344         case WM8350_DCDC_1:
 345                 volt_reg = WM8350_DCDC1_LOW_POWER;
 346                 break;
 347         case WM8350_DCDC_3:
 348                 volt_reg = WM8350_DCDC3_LOW_POWER;
 349                 break;
 350         case WM8350_DCDC_4:
 351                 volt_reg = WM8350_DCDC4_LOW_POWER;
 352                 break;
 353         case WM8350_DCDC_6:
 354                 volt_reg = WM8350_DCDC6_LOW_POWER;
 355                 break;
 356         case WM8350_DCDC_2:
 357         case WM8350_DCDC_5:
 358         default:
 359                 return -EINVAL;
 360         }
 361
 362         sel = regulator_map_voltage_linear(rdev, uV, uV);
 363         if (sel < 0)
 364                 return -EINVAL;
 365
 366         /* all DCDCs have same mV bits */
 367         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_DC1_VSEL_MASK;
 368         wm8350_reg_write(wm8350, volt_reg, val | sel);
 369         return 0;
 370 }
 371
 372 static int wm8350_dcdc_set_suspend_enable(struct regulator_dev *rdev)
 373 {
 374         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 375         int dcdc = rdev_get_id(rdev);
 376         u16 val;
 377
 378         switch (dcdc) {
 379         case WM8350_DCDC_1:
 380                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER)
 381                         & ~WM8350_DCDC_HIB_MODE_MASK;
 382                 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
 383                         val | wm8350->pmic.dcdc1_hib_mode);
 384                 break;
 385         case WM8350_DCDC_3:
 386                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER)
 387                         & ~WM8350_DCDC_HIB_MODE_MASK;
 388                 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
 389                         val | wm8350->pmic.dcdc3_hib_mode);
 390                 break;
 391         case WM8350_DCDC_4:
 392                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER)
 393                         & ~WM8350_DCDC_HIB_MODE_MASK;
 394                 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
 395                         val | wm8350->pmic.dcdc4_hib_mode);
 396                 break;
 397         case WM8350_DCDC_6:
 398                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER)
 399                         & ~WM8350_DCDC_HIB_MODE_MASK;
 400                 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
 401                         val | wm8350->pmic.dcdc6_hib_mode);
 402                 break;
 403         case WM8350_DCDC_2:
 404         case WM8350_DCDC_5:
 405         default:
 406                 return -EINVAL;
 407         }
 408
 409         return 0;
 410 }
 411
 412 static int wm8350_dcdc_set_suspend_disable(struct regulator_dev *rdev)
 413 {
 414         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 415         int dcdc = rdev_get_id(rdev);
 416         u16 val;
 417
 418         switch (dcdc) {
 419         case WM8350_DCDC_1:
 420                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
 421                 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 422                 wm8350_reg_write(wm8350, WM8350_DCDC1_LOW_POWER,
 423                                  val | WM8350_DCDC_HIB_MODE_DIS);
 424                 break;
 425         case WM8350_DCDC_3:
 426                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
 427                 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 428                 wm8350_reg_write(wm8350, WM8350_DCDC3_LOW_POWER,
 429                                  val | WM8350_DCDC_HIB_MODE_DIS);
 430                 break;
 431         case WM8350_DCDC_4:
 432                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
 433                 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 434                 wm8350_reg_write(wm8350, WM8350_DCDC4_LOW_POWER,
 435                                  val | WM8350_DCDC_HIB_MODE_DIS);
 436                 break;
 437         case WM8350_DCDC_6:
 438                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
 439                 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
 440                 wm8350_reg_write(wm8350, WM8350_DCDC6_LOW_POWER,
 441                                  val | WM8350_DCDC_HIB_MODE_DIS);
 442                 break;
 443         case WM8350_DCDC_2:
 444         case WM8350_DCDC_5:
 445         default:
 446                 return -EINVAL;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int wm8350_dcdc25_set_suspend_enable(struct regulator_dev *rdev)
 453 {
 454         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 455         int dcdc = rdev_get_id(rdev);
 456         u16 val;
 457
 458         switch (dcdc) {
 459         case WM8350_DCDC_2:
 460                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 461                     & ~WM8350_DC2_HIB_MODE_MASK;
 462                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 463                     (WM8350_DC2_HIB_MODE_ACTIVE << WM8350_DC2_HIB_MODE_SHIFT));
 464                 break;
 465         case WM8350_DCDC_5:
 466                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 467                     & ~WM8350_DC5_HIB_MODE_MASK;
 468                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 469                     (WM8350_DC5_HIB_MODE_ACTIVE << WM8350_DC5_HIB_MODE_SHIFT));
 470                 break;
 471         default:
 472                 return -EINVAL;
 473         }
 474         return 0;
 475 }
 476
 477 static int wm8350_dcdc25_set_suspend_disable(struct regulator_dev *rdev)
 478 {
 479         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 480         int dcdc = rdev_get_id(rdev);
 481         u16 val;
 482
 483         switch (dcdc) {
 484         case WM8350_DCDC_2:
 485                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 486                     & ~WM8350_DC2_HIB_MODE_MASK;
 487                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 488                     (WM8350_DC2_HIB_MODE_DISABLE << WM8350_DC2_HIB_MODE_SHIFT));
 489                 break;
 490         case WM8350_DCDC_5:
 491                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 492                     & ~WM8350_DC5_HIB_MODE_MASK;
 493                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 494                     (WM8350_DC5_HIB_MODE_DISABLE << WM8350_DC5_HIB_MODE_SHIFT));
 495                 break;
 496         default:
 497                 return -EINVAL;
 498         }
 499         return 0;
 500 }
 501
 502 static int wm8350_dcdc_set_suspend_mode(struct regulator_dev *rdev,
 503         unsigned int mode)
 504 {
 505         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 506         int dcdc = rdev_get_id(rdev);
 507         u16 *hib_mode;
 508
 509         switch (dcdc) {
 510         case WM8350_DCDC_1:
 511                 hib_mode = &wm8350->pmic.dcdc1_hib_mode;
 512                 break;
 513         case WM8350_DCDC_3:
 514                 hib_mode = &wm8350->pmic.dcdc3_hib_mode;
 515                 break;
 516         case WM8350_DCDC_4:
 517                 hib_mode = &wm8350->pmic.dcdc4_hib_mode;
 518                 break;
 519         case WM8350_DCDC_6:
 520                 hib_mode = &wm8350->pmic.dcdc6_hib_mode;
 521                 break;
 522         case WM8350_DCDC_2:
 523         case WM8350_DCDC_5:
 524         default:
 525                 return -EINVAL;
 526         }
 527
 528         switch (mode) {
 529         case REGULATOR_MODE_NORMAL:
 530                 *hib_mode = WM8350_DCDC_HIB_MODE_IMAGE;
 531                 break;
 532         case REGULATOR_MODE_IDLE:
 533                 *hib_mode = WM8350_DCDC_HIB_MODE_STANDBY;
 534                 break;
 535         case REGULATOR_MODE_STANDBY:
 536                 *hib_mode = WM8350_DCDC_HIB_MODE_LDO_IM;
 537                 break;
 538         default:
 539                 return -EINVAL;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static int wm8350_ldo_list_voltage(struct regulator_dev *rdev,
 546                                     unsigned selector)
 547 {
 548         if (selector > WM8350_LDO1_VSEL_MASK)
 549                 return -EINVAL;
 550
 551         if (selector < 16)
 552                 return (selector * 50000) + 900000;
 553         else
 554                 return ((selector - 16) * 100000) + 1800000;
 555 }
 556
 557 static int wm8350_ldo_map_voltage(struct regulator_dev *rdev, int min_uV,
 558                                   int max_uV)
 559 {
 560         int volt, sel;
 561         int min_mV = min_uV / 1000;
 562         int max_mV = max_uV / 1000;
 563
 564         if (min_mV < 900 || min_mV > 3300)
 565                 return -EINVAL;
 566         if (max_mV < 900 || max_mV > 3300)
 567                 return -EINVAL;
 568
 569         if (min_mV < 1800) /* step size is 50mV < 1800mV */
 570                 sel = DIV_ROUND_UP(min_uV - 900, 50);
 571         else /* step size is 100mV > 1800mV */
 572                 sel = DIV_ROUND_UP(min_uV - 1800, 100) + 16;
 573
 574         volt = wm8350_ldo_list_voltage(rdev, sel);
 575         if (volt < min_uV || volt > max_uV)
 576                 return -EINVAL;
 577
 578         return sel;
 579 }
 580
 581 static int wm8350_ldo_set_suspend_voltage(struct regulator_dev *rdev, int uV)
 582 {
 583         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 584         int sel, volt_reg, ldo = rdev_get_id(rdev);
 585         u16 val;
 586
 587         dev_dbg(wm8350->dev, "%s %d mV %d\n", __func__, ldo, uV / 1000);
 588
 589         switch (ldo) {
 590         case WM8350_LDO_1:
 591                 volt_reg = WM8350_LDO1_LOW_POWER;
 592                 break;
 593         case WM8350_LDO_2:
 594                 volt_reg = WM8350_LDO2_LOW_POWER;
 595                 break;
 596         case WM8350_LDO_3:
 597                 volt_reg = WM8350_LDO3_LOW_POWER;
 598                 break;
 599         case WM8350_LDO_4:
 600                 volt_reg = WM8350_LDO4_LOW_POWER;
 601                 break;
 602         default:
 603                 return -EINVAL;
 604         }
 605
 606         sel = wm8350_ldo_map_voltage(rdev, uV, uV);
 607         if (sel < 0)
 608                 return -EINVAL;
 609
 610         /* all LDOs have same mV bits */
 611         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_VSEL_MASK;
 612         wm8350_reg_write(wm8350, volt_reg, val | sel);
 613         return 0;
 614 }
 615
 616 static int wm8350_ldo_set_suspend_enable(struct regulator_dev *rdev)
 617 {
 618         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 619         int volt_reg, ldo = rdev_get_id(rdev);
 620         u16 val;
 621
 622         switch (ldo) {
 623         case WM8350_LDO_1:
 624                 volt_reg = WM8350_LDO1_LOW_POWER;
 625                 break;
 626         case WM8350_LDO_2:
 627                 volt_reg = WM8350_LDO2_LOW_POWER;
 628                 break;
 629         case WM8350_LDO_3:
 630                 volt_reg = WM8350_LDO3_LOW_POWER;
 631                 break;
 632         case WM8350_LDO_4:
 633                 volt_reg = WM8350_LDO4_LOW_POWER;
 634                 break;
 635         default:
 636                 return -EINVAL;
 637         }
 638
 639         /* all LDOs have same mV bits */
 640         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
 641         wm8350_reg_write(wm8350, volt_reg, val);
 642         return 0;
 643 }
 644
 645 static int wm8350_ldo_set_suspend_disable(struct regulator_dev *rdev)
 646 {
 647         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 648         int volt_reg, ldo = rdev_get_id(rdev);
 649         u16 val;
 650
 651         switch (ldo) {
 652         case WM8350_LDO_1:
 653                 volt_reg = WM8350_LDO1_LOW_POWER;
 654                 break;
 655         case WM8350_LDO_2:
 656                 volt_reg = WM8350_LDO2_LOW_POWER;
 657                 break;
 658         case WM8350_LDO_3:
 659                 volt_reg = WM8350_LDO3_LOW_POWER;
 660                 break;
 661         case WM8350_LDO_4:
 662                 volt_reg = WM8350_LDO4_LOW_POWER;
 663                 break;
 664         default:
 665                 return -EINVAL;
 666         }
 667
 668         /* all LDOs have same mV bits */
 669         val = wm8350_reg_read(wm8350, volt_reg) & ~WM8350_LDO1_HIB_MODE_MASK;
 670         wm8350_reg_write(wm8350, volt_reg, val | WM8350_LDO1_HIB_MODE_DIS);
 671         return 0;
 672 }
 673
 674 int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
 675                          u16 stop, u16 fault)
 676 {
 677         int slot_reg;
 678         u16 val;
 679
 680         dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
 681                 __func__, dcdc, start, stop);
 682
 683         /* slot valid ? */
 684         if (start > 15 || stop > 15)
 685                 return -EINVAL;
 686
 687         switch (dcdc) {
 688         case WM8350_DCDC_1:
 689                 slot_reg = WM8350_DCDC1_TIMEOUTS;
 690                 break;
 691         case WM8350_DCDC_2:
 692                 slot_reg = WM8350_DCDC2_TIMEOUTS;
 693                 break;
 694         case WM8350_DCDC_3:
 695                 slot_reg = WM8350_DCDC3_TIMEOUTS;
 696                 break;
 697         case WM8350_DCDC_4:
 698                 slot_reg = WM8350_DCDC4_TIMEOUTS;
 699                 break;
 700         case WM8350_DCDC_5:
 701                 slot_reg = WM8350_DCDC5_TIMEOUTS;
 702                 break;
 703         case WM8350_DCDC_6:
 704                 slot_reg = WM8350_DCDC6_TIMEOUTS;
 705                 break;
 706         default:
 707                 return -EINVAL;
 708         }
 709
 710         val = wm8350_reg_read(wm8350, slot_reg) &
 711             ~(WM8350_DC1_ENSLOT_MASK | WM8350_DC1_SDSLOT_MASK |
 712               WM8350_DC1_ERRACT_MASK);
 713         wm8350_reg_write(wm8350, slot_reg,
 714                          val | (start << WM8350_DC1_ENSLOT_SHIFT) |
 715                          (stop << WM8350_DC1_SDSLOT_SHIFT) |
 716                          (fault << WM8350_DC1_ERRACT_SHIFT));
 717
 718         return 0;
 719 }
 720 EXPORT_SYMBOL_GPL(wm8350_dcdc_set_slot);
 721
 722 int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop)
 723 {
 724         int slot_reg;
 725         u16 val;
 726
 727         dev_dbg(wm8350->dev, "%s %d start %d stop %d\n",
 728                 __func__, ldo, start, stop);
 729
 730         /* slot valid ? */
 731         if (start > 15 || stop > 15)
 732                 return -EINVAL;
 733
 734         switch (ldo) {
 735         case WM8350_LDO_1:
 736                 slot_reg = WM8350_LDO1_TIMEOUTS;
 737                 break;
 738         case WM8350_LDO_2:
 739                 slot_reg = WM8350_LDO2_TIMEOUTS;
 740                 break;
 741         case WM8350_LDO_3:
 742                 slot_reg = WM8350_LDO3_TIMEOUTS;
 743                 break;
 744         case WM8350_LDO_4:
 745                 slot_reg = WM8350_LDO4_TIMEOUTS;
 746                 break;
 747         default:
 748                 return -EINVAL;
 749         }
 750
 751         val = wm8350_reg_read(wm8350, slot_reg) & ~WM8350_LDO1_SDSLOT_MASK;
 752         wm8350_reg_write(wm8350, slot_reg, val | ((start << 10) | (stop << 6)));
 753         return 0;
 754 }
 755 EXPORT_SYMBOL_GPL(wm8350_ldo_set_slot);
 756
 757 int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
 758                            u16 ilim, u16 ramp, u16 feedback)
 759 {
 760         u16 val;
 761
 762         dev_dbg(wm8350->dev, "%s %d mode: %s %s\n", __func__, dcdc,
 763                 mode ? "normal" : "boost", ilim ? "low" : "normal");
 764
 765         switch (dcdc) {
 766         case WM8350_DCDC_2:
 767                 val = wm8350_reg_read(wm8350, WM8350_DCDC2_CONTROL)
 768                     & ~(WM8350_DC2_MODE_MASK | WM8350_DC2_ILIM_MASK |
 769                         WM8350_DC2_RMP_MASK | WM8350_DC2_FBSRC_MASK);
 770                 wm8350_reg_write(wm8350, WM8350_DCDC2_CONTROL, val |
 771                                  (mode << WM8350_DC2_MODE_SHIFT) |
 772                                  (ilim << WM8350_DC2_ILIM_SHIFT) |
 773                                  (ramp << WM8350_DC2_RMP_SHIFT) |
 774                                  (feedback << WM8350_DC2_FBSRC_SHIFT));
 775                 break;
 776         case WM8350_DCDC_5:
 777                 val = wm8350_reg_read(wm8350, WM8350_DCDC5_CONTROL)
 778                     & ~(WM8350_DC5_MODE_MASK | WM8350_DC5_ILIM_MASK |
 779                         WM8350_DC5_RMP_MASK | WM8350_DC5_FBSRC_MASK);
 780                 wm8350_reg_write(wm8350, WM8350_DCDC5_CONTROL, val |
 781                                  (mode << WM8350_DC5_MODE_SHIFT) |
 782                                  (ilim << WM8350_DC5_ILIM_SHIFT) |
 783                                  (ramp << WM8350_DC5_RMP_SHIFT) |
 784                                  (feedback << WM8350_DC5_FBSRC_SHIFT));
 785                 break;
 786         default:
 787                 return -EINVAL;
 788         }
 789
 790         return 0;
 791 }
 792 EXPORT_SYMBOL_GPL(wm8350_dcdc25_set_mode);
 793
 794 static int force_continuous_enable(struct wm8350 *wm8350, int dcdc, int enable)
 795 {
 796         int reg = 0, ret;
 797
 798         switch (dcdc) {
 799         case WM8350_DCDC_1:
 800                 reg = WM8350_DCDC1_FORCE_PWM;
 801                 break;
 802         case WM8350_DCDC_3:
 803                 reg = WM8350_DCDC3_FORCE_PWM;
 804                 break;
 805         case WM8350_DCDC_4:
 806                 reg = WM8350_DCDC4_FORCE_PWM;
 807                 break;
 808         case WM8350_DCDC_6:
 809                 reg = WM8350_DCDC6_FORCE_PWM;
 810                 break;
 811         default:
 812                 return -EINVAL;
 813         }
 814
 815         if (enable)
 816                 ret = wm8350_set_bits(wm8350, reg,
 817                         WM8350_DCDC1_FORCE_PWM_ENA);
 818         else
 819                 ret = wm8350_clear_bits(wm8350, reg,
 820                         WM8350_DCDC1_FORCE_PWM_ENA);
 821         return ret;
 822 }
 823
 824 static int wm8350_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
 825 {
 826         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 827         int dcdc = rdev_get_id(rdev);
 828         u16 val;
 829
 830         if (dcdc < WM8350_DCDC_1 || dcdc > WM8350_DCDC_6)
 831                 return -EINVAL;
 832
 833         if (dcdc == WM8350_DCDC_2 || dcdc == WM8350_DCDC_5)
 834                 return -EINVAL;
 835
 836         val = 1 << (dcdc - WM8350_DCDC_1);
 837
 838         switch (mode) {
 839         case REGULATOR_MODE_FAST:
 840                 /* force continuous mode */
 841                 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
 842                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 843                 force_continuous_enable(wm8350, dcdc, 1);
 844                 break;
 845         case REGULATOR_MODE_NORMAL:
 846                 /* active / pulse skipping */
 847                 wm8350_set_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
 848                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 849                 force_continuous_enable(wm8350, dcdc, 0);
 850                 break;
 851         case REGULATOR_MODE_IDLE:
 852                 /* standby mode */
 853                 force_continuous_enable(wm8350, dcdc, 0);
 854                 wm8350_clear_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 855                 wm8350_clear_bits(wm8350, WM8350_DCDC_ACTIVE_OPTIONS, val);
 856                 break;
 857         case REGULATOR_MODE_STANDBY:
 858                 /* LDO mode */
 859                 force_continuous_enable(wm8350, dcdc, 0);
 860                 wm8350_set_bits(wm8350, WM8350_DCDC_SLEEP_OPTIONS, val);
 861                 break;
 862         }
 863
 864         return 0;
 865 }
 866
 867 static unsigned int wm8350_dcdc_get_mode(struct regulator_dev *rdev)
 868 {
 869         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
 870         int dcdc = rdev_get_id(rdev);
 871         u16 mask, sleep, active, force;
 872         int mode = REGULATOR_MODE_NORMAL;
 873         int reg;
 874
 875         switch (dcdc) {
 876         case WM8350_DCDC_1:
 877                 reg = WM8350_DCDC1_FORCE_PWM;
 878                 break;
 879         case WM8350_DCDC_3:
 880                 reg = WM8350_DCDC3_FORCE_PWM;
 881                 break;
 882         case WM8350_DCDC_4:
 883                 reg = WM8350_DCDC4_FORCE_PWM;
 884                 break;
 885         case WM8350_DCDC_6:
 886                 reg = WM8350_DCDC6_FORCE_PWM;
 887                 break;
 888         default:
 889                 return -EINVAL;
 890         }
 891
 892         mask = 1 << (dcdc - WM8350_DCDC_1);
 893         active = wm8350_reg_read(wm8350, WM8350_DCDC_ACTIVE_OPTIONS) & mask;
 894         force = wm8350_reg_read(wm8350, reg) & WM8350_DCDC1_FORCE_PWM_ENA;
 895         sleep = wm8350_reg_read(wm8350, WM8350_DCDC_SLEEP_OPTIONS) & mask;
 896
 897         dev_dbg(wm8350->dev, "mask %x active %x sleep %x force %x",
 898                 mask, active, sleep, force);
 899
 900         if (active && !sleep) {
 901                 if (force)
 902                         mode = REGULATOR_MODE_FAST;
 903                 else
 904                         mode = REGULATOR_MODE_NORMAL;
 905         } else if (!active && !sleep)
 906                 mode = REGULATOR_MODE_IDLE;
 907         else if (sleep)
 908                 mode = REGULATOR_MODE_STANDBY;
 909
 910         return mode;
 911 }
 912
 913 static unsigned int wm8350_ldo_get_mode(struct regulator_dev *rdev)
 914 {
 915         return REGULATOR_MODE_NORMAL;
 916 }
 917
 918 struct wm8350_dcdc_efficiency {
 919         int uA_load_min;
 920         int uA_load_max;
 921         unsigned int mode;
 922 };
 923
 924 static const struct wm8350_dcdc_efficiency dcdc1_6_efficiency[] = {
 925         {0, 10000, REGULATOR_MODE_STANDBY},       /* 0 - 10mA - LDO */
 926         {10000, 100000, REGULATOR_MODE_IDLE},     /* 10mA - 100mA - Standby */
 927         {100000, 1000000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
 928         {-1, -1, REGULATOR_MODE_NORMAL},
 929 };
 930
 931 static const struct wm8350_dcdc_efficiency dcdc3_4_efficiency[] = {
 932         {0, 10000, REGULATOR_MODE_STANDBY},      /* 0 - 10mA - LDO */
 933         {10000, 100000, REGULATOR_MODE_IDLE},    /* 10mA - 100mA - Standby */
 934         {100000, 800000, REGULATOR_MODE_NORMAL}, /* > 100mA - Active */
 935         {-1, -1, REGULATOR_MODE_NORMAL},
 936 };
 937
 938 static unsigned int get_mode(int uA, const struct wm8350_dcdc_efficiency *eff)
 939 {
 940         int i = 0;
 941
 942         while (eff[i].uA_load_min != -1) {
 943                 if (uA >= eff[i].uA_load_min && uA <= eff[i].uA_load_max)
 944                         return eff[i].mode;
 945         }
 946         return REGULATOR_MODE_NORMAL;
 947 }
 948
 949 /* Query the regulator for it's most efficient mode @ uV,uA
 950  * WM8350 regulator efficiency is pretty similar over
 951  * different input and output uV.
 952  */
 953 static unsigned int wm8350_dcdc_get_optimum_mode(struct regulator_dev *rdev,
 954                                                  int input_uV, int output_uV,
 955                                                  int output_uA)
 956 {
 957         int dcdc = rdev_get_id(rdev), mode;
 958
 959         switch (dcdc) {
 960         case WM8350_DCDC_1:
 961         case WM8350_DCDC_6:
 962                 mode = get_mode(output_uA, dcdc1_6_efficiency);
 963                 break;
 964         case WM8350_DCDC_3:
 965         case WM8350_DCDC_4:
 966                 mode = get_mode(output_uA, dcdc3_4_efficiency);
 967                 break;
 968         default:
 969                 mode = REGULATOR_MODE_NORMAL;
 970                 break;
 971         }
 972         return mode;
 973 }
 974
 975 static struct regulator_ops wm8350_dcdc_ops = {
 976         .set_voltage_sel = regulator_set_voltage_sel_regmap,
 977         .get_voltage_sel = regulator_get_voltage_sel_regmap,
 978         .list_voltage = regulator_list_voltage_linear,
 979         .map_voltage = regulator_map_voltage_linear,
 980         .enable = regulator_enable_regmap,
 981         .disable = regulator_disable_regmap,
 982         .is_enabled = regulator_is_enabled_regmap,
 983         .get_mode = wm8350_dcdc_get_mode,
 984         .set_mode = wm8350_dcdc_set_mode,
 985         .get_optimum_mode = wm8350_dcdc_get_optimum_mode,
 986         .set_suspend_voltage = wm8350_dcdc_set_suspend_voltage,
 987         .set_suspend_enable = wm8350_dcdc_set_suspend_enable,
 988         .set_suspend_disable = wm8350_dcdc_set_suspend_disable,
 989         .set_suspend_mode = wm8350_dcdc_set_suspend_mode,
 990 };
 991
 992 static struct regulator_ops wm8350_dcdc2_5_ops = {
 993         .enable = regulator_enable_regmap,
 994         .disable = regulator_disable_regmap,
 995         .is_enabled = regulator_is_enabled_regmap,
 996         .set_suspend_enable = wm8350_dcdc25_set_suspend_enable,
 997         .set_suspend_disable = wm8350_dcdc25_set_suspend_disable,
 998 };
 999
1000 static struct regulator_ops wm8350_ldo_ops = {
1001         .map_voltage = wm8350_ldo_map_voltage,
1002         .set_voltage_sel = regulator_set_voltage_sel_regmap,
1003         .get_voltage_sel = regulator_get_voltage_sel_regmap,
1004         .list_voltage = wm8350_ldo_list_voltage,
1005         .enable = regulator_enable_regmap,
1006         .disable = regulator_disable_regmap,
1007         .is_enabled = regulator_is_enabled_regmap,
1008         .get_mode = wm8350_ldo_get_mode,
1009         .set_suspend_voltage = wm8350_ldo_set_suspend_voltage,
1010         .set_suspend_enable = wm8350_ldo_set_suspend_enable,
1011         .set_suspend_disable = wm8350_ldo_set_suspend_disable,
1012 };
1013
1014 static struct regulator_ops wm8350_isink_ops = {
1015         .set_current_limit = wm8350_isink_set_current,
1016         .get_current_limit = wm8350_isink_get_current,
1017         .enable = wm8350_isink_enable,
1018         .disable = wm8350_isink_disable,
1019         .is_enabled = wm8350_isink_is_enabled,
1020         .enable_time = wm8350_isink_enable_time,
1021 };
1022
1023 static const struct regulator_desc wm8350_reg[NUM_WM8350_REGULATORS] = {
1024         {
1025                 .name = "DCDC1",
1026                 .id = WM8350_DCDC_1,
1027                 .ops = &wm8350_dcdc_ops,
1028                 .irq = WM8350_IRQ_UV_DC1,
1029                 .type = REGULATOR_VOLTAGE,
1030                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1031                 .min_uV = 850000,
1032                 .uV_step = 25000,
1033                 .vsel_reg = WM8350_DCDC1_CONTROL,
1034                 .vsel_mask = WM8350_DC1_VSEL_MASK,
1035                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1036                 .enable_mask = WM8350_DC1_ENA,
1037                 .owner = THIS_MODULE,
1038         },
1039         {
1040                 .name = "DCDC2",
1041                 .id = WM8350_DCDC_2,
1042                 .ops = &wm8350_dcdc2_5_ops,
1043                 .irq = WM8350_IRQ_UV_DC2,
1044                 .type = REGULATOR_VOLTAGE,
1045                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1046                 .enable_mask = WM8350_DC2_ENA,
1047                 .owner = THIS_MODULE,
1048         },
1049         {
1050                 .name = "DCDC3",
1051                 .id = WM8350_DCDC_3,
1052                 .ops = &wm8350_dcdc_ops,
1053                 .irq = WM8350_IRQ_UV_DC3,
1054                 .type = REGULATOR_VOLTAGE,
1055                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1056                 .min_uV = 850000,
1057                 .uV_step = 25000,
1058                 .vsel_reg = WM8350_DCDC3_CONTROL,
1059                 .vsel_mask = WM8350_DC3_VSEL_MASK,
1060                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1061                 .enable_mask = WM8350_DC3_ENA,
1062                 .owner = THIS_MODULE,
1063         },
1064         {
1065                 .name = "DCDC4",
1066                 .id = WM8350_DCDC_4,
1067                 .ops = &wm8350_dcdc_ops,
1068                 .irq = WM8350_IRQ_UV_DC4,
1069                 .type = REGULATOR_VOLTAGE,
1070                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1071                 .min_uV = 850000,
1072                 .uV_step = 25000,
1073                 .vsel_reg = WM8350_DCDC4_CONTROL,
1074                 .vsel_mask = WM8350_DC4_VSEL_MASK,
1075                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1076                 .enable_mask = WM8350_DC4_ENA,
1077                 .owner = THIS_MODULE,
1078         },
1079         {
1080                 .name = "DCDC5",
1081                 .id = WM8350_DCDC_5,
1082                 .ops = &wm8350_dcdc2_5_ops,
1083                 .irq = WM8350_IRQ_UV_DC5,
1084                 .type = REGULATOR_VOLTAGE,
1085                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1086                 .enable_mask = WM8350_DC5_ENA,
1087                 .owner = THIS_MODULE,
1088          },
1089         {
1090                 .name = "DCDC6",
1091                 .id = WM8350_DCDC_6,
1092                 .ops = &wm8350_dcdc_ops,
1093                 .irq = WM8350_IRQ_UV_DC6,
1094                 .type = REGULATOR_VOLTAGE,
1095                 .n_voltages = WM8350_DCDC_MAX_VSEL + 1,
1096                 .min_uV = 850000,
1097                 .uV_step = 25000,
1098                 .vsel_reg = WM8350_DCDC6_CONTROL,
1099                 .vsel_mask = WM8350_DC6_VSEL_MASK,
1100                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1101                 .enable_mask = WM8350_DC6_ENA,
1102                 .owner = THIS_MODULE,
1103         },
1104         {
1105                 .name = "LDO1",
1106                 .id = WM8350_LDO_1,
1107                 .ops = &wm8350_ldo_ops,
1108                 .irq = WM8350_IRQ_UV_LDO1,
1109                 .type = REGULATOR_VOLTAGE,
1110                 .n_voltages = WM8350_LDO1_VSEL_MASK + 1,
1111                 .vsel_reg = WM8350_LDO1_CONTROL,
1112                 .vsel_mask = WM8350_LDO1_VSEL_MASK,
1113                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1114                 .enable_mask = WM8350_LDO1_ENA,
1115                 .owner = THIS_MODULE,
1116         },
1117         {
1118                 .name = "LDO2",
1119                 .id = WM8350_LDO_2,
1120                 .ops = &wm8350_ldo_ops,
1121                 .irq = WM8350_IRQ_UV_LDO2,
1122                 .type = REGULATOR_VOLTAGE,
1123                 .n_voltages = WM8350_LDO2_VSEL_MASK + 1,
1124                 .vsel_reg = WM8350_LDO2_CONTROL,
1125                 .vsel_mask = WM8350_LDO2_VSEL_MASK,
1126                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1127                 .enable_mask = WM8350_LDO2_ENA,
1128                 .owner = THIS_MODULE,
1129         },
1130         {
1131                 .name = "LDO3",
1132                 .id = WM8350_LDO_3,
1133                 .ops = &wm8350_ldo_ops,
1134                 .irq = WM8350_IRQ_UV_LDO3,
1135                 .type = REGULATOR_VOLTAGE,
1136                 .n_voltages = WM8350_LDO3_VSEL_MASK + 1,
1137                 .vsel_reg = WM8350_LDO3_CONTROL,
1138                 .vsel_mask = WM8350_LDO3_VSEL_MASK,
1139                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1140                 .enable_mask = WM8350_LDO3_ENA,
1141                 .owner = THIS_MODULE,
1142         },
1143         {
1144                 .name = "LDO4",
1145                 .id = WM8350_LDO_4,
1146                 .ops = &wm8350_ldo_ops,
1147                 .irq = WM8350_IRQ_UV_LDO4,
1148                 .type = REGULATOR_VOLTAGE,
1149                 .n_voltages = WM8350_LDO4_VSEL_MASK + 1,
1150                 .vsel_reg = WM8350_LDO4_CONTROL,
1151                 .vsel_mask = WM8350_LDO4_VSEL_MASK,
1152                 .enable_reg = WM8350_DCDC_LDO_REQUESTED,
1153                 .enable_mask = WM8350_LDO4_ENA,
1154                 .owner = THIS_MODULE,
1155         },
1156         {
1157                 .name = "ISINKA",
1158                 .id = WM8350_ISINK_A,
1159                 .ops = &wm8350_isink_ops,
1160                 .irq = WM8350_IRQ_CS1,
1161                 .type = REGULATOR_CURRENT,
1162                 .owner = THIS_MODULE,
1163          },
1164         {
1165                 .name = "ISINKB",
1166                 .id = WM8350_ISINK_B,
1167                 .ops = &wm8350_isink_ops,
1168                 .irq = WM8350_IRQ_CS2,
1169                 .type = REGULATOR_CURRENT,
1170                 .owner = THIS_MODULE,
1171          },
1172 };
1173
1174 static irqreturn_t pmic_uv_handler(int irq, void *data)
1175 {
1176         struct regulator_dev *rdev = (struct regulator_dev *)data;
1177         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1178
1179         mutex_lock(&rdev->mutex);
1180         if (irq == WM8350_IRQ_CS1 || irq == WM8350_IRQ_CS2)
1181                 regulator_notifier_call_chain(rdev,
1182                                               REGULATOR_EVENT_REGULATION_OUT,
1183                                               wm8350);
1184         else
1185                 regulator_notifier_call_chain(rdev,
1186                                               REGULATOR_EVENT_UNDER_VOLTAGE,
1187                                               wm8350);
1188         mutex_unlock(&rdev->mutex);
1189
1190         return IRQ_HANDLED;
1191 }
1192
1193 static int wm8350_regulator_probe(struct platform_device *pdev)
1194 {
1195         struct wm8350 *wm8350 = dev_get_drvdata(&pdev->dev);
1196         struct regulator_config config = { };
1197         struct regulator_dev *rdev;
1198         int ret;
1199         u16 val;
1200
1201         if (pdev->id < WM8350_DCDC_1 || pdev->id > WM8350_ISINK_B)
1202                 return -ENODEV;
1203
1204         /* do any regulatior specific init */
1205         switch (pdev->id) {
1206         case WM8350_DCDC_1:
1207                 val = wm8350_reg_read(wm8350, WM8350_DCDC1_LOW_POWER);
1208                 wm8350->pmic.dcdc1_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1209                 break;
1210         case WM8350_DCDC_3:
1211                 val = wm8350_reg_read(wm8350, WM8350_DCDC3_LOW_POWER);
1212                 wm8350->pmic.dcdc3_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1213                 break;
1214         case WM8350_DCDC_4:
1215                 val = wm8350_reg_read(wm8350, WM8350_DCDC4_LOW_POWER);
1216                 wm8350->pmic.dcdc4_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1217                 break;
1218         case WM8350_DCDC_6:
1219                 val = wm8350_reg_read(wm8350, WM8350_DCDC6_LOW_POWER);
1220                 wm8350->pmic.dcdc6_hib_mode = val & WM8350_DCDC_HIB_MODE_MASK;
1221                 break;
1222         }
1223
1224         config.dev = &pdev->dev;
1225         config.init_data = pdev->dev.platform_data;
1226         config.driver_data = dev_get_drvdata(&pdev->dev);
1227         config.regmap = wm8350->regmap;
1228
1229         /* register regulator */
1230         rdev = regulator_register(&wm8350_reg[pdev->id], &config);
1231         if (IS_ERR(rdev)) {
1232                 dev_err(&pdev->dev, "failed to register %s\n",
1233                         wm8350_reg[pdev->id].name);
1234                 return PTR_ERR(rdev);
1235         }
1236
1237         /* register regulator IRQ */
1238         ret = wm8350_register_irq(wm8350, wm8350_reg[pdev->id].irq,
1239                                   pmic_uv_handler, 0, "UV", rdev);
1240         if (ret < 0) {
1241                 regulator_unregister(rdev);
1242                 dev_err(&pdev->dev, "failed to register regulator %s IRQ\n",
1243                         wm8350_reg[pdev->id].name);
1244                 return ret;
1245         }
1246
1247         return 0;
1248 }
1249
1250 static int wm8350_regulator_remove(struct platform_device *pdev)
1251 {
1252         struct regulator_dev *rdev = platform_get_drvdata(pdev);
1253         struct wm8350 *wm8350 = rdev_get_drvdata(rdev);
1254
1255         wm8350_free_irq(wm8350, wm8350_reg[pdev->id].irq, rdev);
1256
1257         regulator_unregister(rdev);
1258
1259         return 0;
1260 }
1261
1262 int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
1263                               struct regulator_init_data *initdata)
1264 {
1265         struct platform_device *pdev;
1266         int ret;
1267         if (reg < 0 || reg >= NUM_WM8350_REGULATORS)
1268                 return -EINVAL;
1269
1270         if (wm8350->pmic.pdev[reg])
1271                 return -EBUSY;
1272
1273         if (reg >= WM8350_DCDC_1 && reg <= WM8350_DCDC_6 &&
1274             reg > wm8350->pmic.max_dcdc)
1275                 return -ENODEV;
1276         if (reg >= WM8350_ISINK_A && reg <= WM8350_ISINK_B &&
1277             reg > wm8350->pmic.max_isink)
1278                 return -ENODEV;
1279
1280         pdev = platform_device_alloc("wm8350-regulator", reg);
1281         if (!pdev)
1282                 return -ENOMEM;
1283
1284         wm8350->pmic.pdev[reg] = pdev;
1285
1286         initdata->driver_data = wm8350;
1287
1288         pdev->dev.platform_data = initdata;
1289         pdev->dev.parent = wm8350->dev;
1290         platform_set_drvdata(pdev, wm8350);
1291
1292         ret = platform_device_add(pdev);
1293
1294         if (ret != 0) {
1295                 dev_err(wm8350->dev, "Failed to register regulator %d: %d\n",
1296                         reg, ret);
1297                 platform_device_put(pdev);
1298                 wm8350->pmic.pdev[reg] = NULL;
1299         }
1300
1301         return ret;
1302 }
1303 EXPORT_SYMBOL_GPL(wm8350_register_regulator);
1304
1305 /**
1306  * wm8350_register_led - Register a WM8350 LED output
1307  *
1308  * @param wm8350 The WM8350 device to configure.
1309  * @param lednum LED device index to create.
1310  * @param dcdc The DCDC to use for the LED.
1311  * @param isink The ISINK to use for the LED.
1312  * @param pdata Configuration for the LED.
1313  *
1314  * The WM8350 supports the use of an ISINK together with a DCDC to
1315  * provide a power-efficient LED driver.  This function registers the
1316  * regulators and instantiates the platform device for a LED.  The
1317  * operating modes for the LED regulators must be configured using
1318  * wm8350_isink_set_flash(), wm8350_dcdc25_set_mode() and
1319  * wm8350_dcdc_set_slot() prior to calling this function.
1320  */
1321 int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
1322                         struct wm8350_led_platform_data *pdata)
1323 {
1324         struct wm8350_led *led;
1325         struct platform_device *pdev;
1326         int ret;
1327
1328         if (lednum >= ARRAY_SIZE(wm8350->pmic.led) || lednum < 0) {
1329                 dev_err(wm8350->dev, "Invalid LED index %d\n", lednum);
1330                 return -ENODEV;
1331         }
1332
1333         led = &wm8350->pmic.led[lednum];
1334
1335         if (led->pdev) {
1336                 dev_err(wm8350->dev, "LED %d already allocated\n", lednum);
1337                 return -EINVAL;
1338         }
1339
1340         pdev = platform_device_alloc("wm8350-led", lednum);
1341         if (pdev == NULL) {
1342                 dev_err(wm8350->dev, "Failed to allocate LED %d\n", lednum);
1343                 return -ENOMEM;
1344         }
1345
1346         led->isink_consumer.dev_name = dev_name(&pdev->dev);
1347         led->isink_consumer.supply = "led_isink";
1348         led->isink_init.num_consumer_supplies = 1;
1349         led->isink_init.consumer_supplies = &led->isink_consumer;
1350         led->isink_init.constraints.min_uA = 0;
1351         led->isink_init.constraints.max_uA = pdata->max_uA;
1352         led->isink_init.constraints.valid_ops_mask
1353                 = REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_STATUS;
1354         led->isink_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1355         ret = wm8350_register_regulator(wm8350, isink, &led->isink_init);
1356         if (ret != 0) {
1357                 platform_device_put(pdev);
1358                 return ret;
1359         }
1360
1361         led->dcdc_consumer.dev_name = dev_name(&pdev->dev);
1362         led->dcdc_consumer.supply = "led_vcc";
1363         led->dcdc_init.num_consumer_supplies = 1;
1364         led->dcdc_init.consumer_supplies = &led->dcdc_consumer;
1365         led->dcdc_init.constraints.valid_modes_mask = REGULATOR_MODE_NORMAL;
1366         led->dcdc_init.constraints.valid_ops_mask =  REGULATOR_CHANGE_STATUS;
1367         ret = wm8350_register_regulator(wm8350, dcdc, &led->dcdc_init);
1368         if (ret != 0) {
1369                 platform_device_put(pdev);
1370                 return ret;
1371         }
1372
1373         switch (isink) {
1374         case WM8350_ISINK_A:
1375                 wm8350->pmic.isink_A_dcdc = dcdc;
1376                 break;
1377         case WM8350_ISINK_B:
1378                 wm8350->pmic.isink_B_dcdc = dcdc;
1379                 break;
1380         }
1381
1382         pdev->dev.platform_data = pdata;
1383         pdev->dev.parent = wm8350->dev;
1384         ret = platform_device_add(pdev);
1385         if (ret != 0) {
1386                 dev_err(wm8350->dev, "Failed to register LED %d: %d\n",
1387                         lednum, ret);
1388                 platform_device_put(pdev);
1389                 return ret;
1390         }
1391
1392         led->pdev = pdev;
1393
1394         return 0;
1395 }
1396 EXPORT_SYMBOL_GPL(wm8350_register_led);
1397
1398 static struct platform_driver wm8350_regulator_driver = {
1399         .probe = wm8350_regulator_probe,
1400         .remove = wm8350_regulator_remove,
1401         .driver         = {
1402                 .name   = "wm8350-regulator",
1403         },
1404 };
1405
1406 static int __init wm8350_regulator_init(void)
1407 {
1408         return platform_driver_register(&wm8350_regulator_driver);
1409 }
1410 subsys_initcall(wm8350_regulator_init);
1411
1412 static void __exit wm8350_regulator_exit(void)
1413 {
1414         platform_driver_unregister(&wm8350_regulator_driver);
1415 }
1416 module_exit(wm8350_regulator_exit);
1417
1418 /* Module information */
1419 MODULE_AUTHOR("Liam Girdwood");
1420 MODULE_DESCRIPTION("WM8350 voltage and current regulator driver");
1421 MODULE_LICENSE("GPL");
1422 MODULE_ALIAS("platform:wm8350-regulator");