drivers/regulator/slg51000-regulator.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // SLG51000 High PSRR, Multi-Output Regulators
   4 // Copyright (C) 2019  Dialog Semiconductor
   5 //
   6 // Author: Eric Jeong <eric.jeong.opensource@diasemi.com>
   7
   8 #include <linux/err.h>
   9 #include <linux/gpio/consumer.h>
  10 #include <linux/i2c.h>
  11 #include <linux/init.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/irq.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/regmap.h>
  17 #include <linux/regulator/driver.h>
  18 #include <linux/regulator/machine.h>
  19 #include <linux/regulator/of_regulator.h>
  20 #include "slg51000-regulator.h"
  21
  22 #define SLG51000_SCTL_EVT               7
  23 #define SLG51000_MAX_EVT_REGISTER       8
  24 #define SLG51000_LDOHP_LV_MIN           1200000
  25 #define SLG51000_LDOHP_HV_MIN           2400000
  26
  27 enum slg51000_regulators {
  28         SLG51000_REGULATOR_LDO1 = 0,
  29         SLG51000_REGULATOR_LDO2,
  30         SLG51000_REGULATOR_LDO3,
  31         SLG51000_REGULATOR_LDO4,
  32         SLG51000_REGULATOR_LDO5,
  33         SLG51000_REGULATOR_LDO6,
  34         SLG51000_REGULATOR_LDO7,
  35         SLG51000_MAX_REGULATORS,
  36 };
  37
  38 struct slg51000_pdata {
  39         struct gpio_desc *ena_gpiod;
  40 };
  41
  42 struct slg51000 {
  43         struct device *dev;
  44         struct regmap *regmap;
  45         struct slg51000_pdata regl_pdata[SLG51000_MAX_REGULATORS];
  46         struct regulator_desc *rdesc[SLG51000_MAX_REGULATORS];
  47         struct regulator_dev *rdev[SLG51000_MAX_REGULATORS];
  48         struct gpio_desc *cs_gpiod;
  49         int chip_irq;
  50 };
  51
  52 struct slg51000_evt_sta {
  53         unsigned int ereg;
  54         unsigned int sreg;
  55 };
  56
  57 static const struct slg51000_evt_sta es_reg[SLG51000_MAX_EVT_REGISTER] = {
  58         {SLG51000_LDO1_EVENT, SLG51000_LDO1_STATUS},
  59         {SLG51000_LDO2_EVENT, SLG51000_LDO2_STATUS},
  60         {SLG51000_LDO3_EVENT, SLG51000_LDO3_STATUS},
  61         {SLG51000_LDO4_EVENT, SLG51000_LDO4_STATUS},
  62         {SLG51000_LDO5_EVENT, SLG51000_LDO5_STATUS},
  63         {SLG51000_LDO6_EVENT, SLG51000_LDO6_STATUS},
  64         {SLG51000_LDO7_EVENT, SLG51000_LDO7_STATUS},
  65         {SLG51000_SYSCTL_EVENT, SLG51000_SYSCTL_STATUS},
  66 };
  67
  68 static const struct regmap_range slg51000_writeable_ranges[] = {
  69         regmap_reg_range(SLG51000_SYSCTL_MATRIX_CONF_A,
  70                          SLG51000_SYSCTL_MATRIX_CONF_A),
  71         regmap_reg_range(SLG51000_LDO1_VSEL, SLG51000_LDO1_VSEL),
  72         regmap_reg_range(SLG51000_LDO1_MINV, SLG51000_LDO1_MAXV),
  73         regmap_reg_range(SLG51000_LDO1_IRQ_MASK, SLG51000_LDO1_IRQ_MASK),
  74         regmap_reg_range(SLG51000_LDO2_VSEL, SLG51000_LDO2_VSEL),
  75         regmap_reg_range(SLG51000_LDO2_MINV, SLG51000_LDO2_MAXV),
  76         regmap_reg_range(SLG51000_LDO2_IRQ_MASK, SLG51000_LDO2_IRQ_MASK),
  77         regmap_reg_range(SLG51000_LDO3_VSEL, SLG51000_LDO3_VSEL),
  78         regmap_reg_range(SLG51000_LDO3_MINV, SLG51000_LDO3_MAXV),
  79         regmap_reg_range(SLG51000_LDO3_IRQ_MASK, SLG51000_LDO3_IRQ_MASK),
  80         regmap_reg_range(SLG51000_LDO4_VSEL, SLG51000_LDO4_VSEL),
  81         regmap_reg_range(SLG51000_LDO4_MINV, SLG51000_LDO4_MAXV),
  82         regmap_reg_range(SLG51000_LDO4_IRQ_MASK, SLG51000_LDO4_IRQ_MASK),
  83         regmap_reg_range(SLG51000_LDO5_VSEL, SLG51000_LDO5_VSEL),
  84         regmap_reg_range(SLG51000_LDO5_MINV, SLG51000_LDO5_MAXV),
  85         regmap_reg_range(SLG51000_LDO5_IRQ_MASK, SLG51000_LDO5_IRQ_MASK),
  86         regmap_reg_range(SLG51000_LDO6_VSEL, SLG51000_LDO6_VSEL),
  87         regmap_reg_range(SLG51000_LDO6_MINV, SLG51000_LDO6_MAXV),
  88         regmap_reg_range(SLG51000_LDO6_IRQ_MASK, SLG51000_LDO6_IRQ_MASK),
  89         regmap_reg_range(SLG51000_LDO7_VSEL, SLG51000_LDO7_VSEL),
  90         regmap_reg_range(SLG51000_LDO7_MINV, SLG51000_LDO7_MAXV),
  91         regmap_reg_range(SLG51000_LDO7_IRQ_MASK, SLG51000_LDO7_IRQ_MASK),
  92         regmap_reg_range(SLG51000_OTP_IRQ_MASK, SLG51000_OTP_IRQ_MASK),
  93 };
  94
  95 static const struct regmap_range slg51000_readable_ranges[] = {
  96         regmap_reg_range(SLG51000_SYSCTL_PATN_ID_B0,
  97                          SLG51000_SYSCTL_PATN_ID_B2),
  98         regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_A,
  99                          SLG51000_SYSCTL_SYS_CONF_A),
 100         regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_D,
 101                          SLG51000_SYSCTL_MATRIX_CONF_B),
 102         regmap_reg_range(SLG51000_SYSCTL_REFGEN_CONF_C,
 103                          SLG51000_SYSCTL_UVLO_CONF_A),
 104         regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1, SLG51000_SYSCTL_IRQ_MASK),
 105         regmap_reg_range(SLG51000_IO_GPIO1_CONF, SLG51000_IO_GPIO_STATUS),
 106         regmap_reg_range(SLG51000_LUTARRAY_LUT_VAL_0,
 107                          SLG51000_LUTARRAY_LUT_VAL_11),
 108         regmap_reg_range(SLG51000_MUXARRAY_INPUT_SEL_0,
 109                          SLG51000_MUXARRAY_INPUT_SEL_63),
 110         regmap_reg_range(SLG51000_PWRSEQ_RESOURCE_EN_0,
 111                          SLG51000_PWRSEQ_INPUT_SENSE_CONF_B),
 112         regmap_reg_range(SLG51000_LDO1_VSEL, SLG51000_LDO1_VSEL),
 113         regmap_reg_range(SLG51000_LDO1_MINV, SLG51000_LDO1_MAXV),
 114         regmap_reg_range(SLG51000_LDO1_MISC1, SLG51000_LDO1_VSEL_ACTUAL),
 115         regmap_reg_range(SLG51000_LDO1_EVENT, SLG51000_LDO1_IRQ_MASK),
 116         regmap_reg_range(SLG51000_LDO2_VSEL, SLG51000_LDO2_VSEL),
 117         regmap_reg_range(SLG51000_LDO2_MINV, SLG51000_LDO2_MAXV),
 118         regmap_reg_range(SLG51000_LDO2_MISC1, SLG51000_LDO2_VSEL_ACTUAL),
 119         regmap_reg_range(SLG51000_LDO2_EVENT, SLG51000_LDO2_IRQ_MASK),
 120         regmap_reg_range(SLG51000_LDO3_VSEL, SLG51000_LDO3_VSEL),
 121         regmap_reg_range(SLG51000_LDO3_MINV, SLG51000_LDO3_MAXV),
 122         regmap_reg_range(SLG51000_LDO3_CONF1, SLG51000_LDO3_VSEL_ACTUAL),
 123         regmap_reg_range(SLG51000_LDO3_EVENT, SLG51000_LDO3_IRQ_MASK),
 124         regmap_reg_range(SLG51000_LDO4_VSEL, SLG51000_LDO4_VSEL),
 125         regmap_reg_range(SLG51000_LDO4_MINV, SLG51000_LDO4_MAXV),
 126         regmap_reg_range(SLG51000_LDO4_CONF1, SLG51000_LDO4_VSEL_ACTUAL),
 127         regmap_reg_range(SLG51000_LDO4_EVENT, SLG51000_LDO4_IRQ_MASK),
 128         regmap_reg_range(SLG51000_LDO5_VSEL, SLG51000_LDO5_VSEL),
 129         regmap_reg_range(SLG51000_LDO5_MINV, SLG51000_LDO5_MAXV),
 130         regmap_reg_range(SLG51000_LDO5_TRIM2, SLG51000_LDO5_TRIM2),
 131         regmap_reg_range(SLG51000_LDO5_CONF1, SLG51000_LDO5_VSEL_ACTUAL),
 132         regmap_reg_range(SLG51000_LDO5_EVENT, SLG51000_LDO5_IRQ_MASK),
 133         regmap_reg_range(SLG51000_LDO6_VSEL, SLG51000_LDO6_VSEL),
 134         regmap_reg_range(SLG51000_LDO6_MINV, SLG51000_LDO6_MAXV),
 135         regmap_reg_range(SLG51000_LDO6_TRIM2, SLG51000_LDO6_TRIM2),
 136         regmap_reg_range(SLG51000_LDO6_CONF1, SLG51000_LDO6_VSEL_ACTUAL),
 137         regmap_reg_range(SLG51000_LDO6_EVENT, SLG51000_LDO6_IRQ_MASK),
 138         regmap_reg_range(SLG51000_LDO7_VSEL, SLG51000_LDO7_VSEL),
 139         regmap_reg_range(SLG51000_LDO7_MINV, SLG51000_LDO7_MAXV),
 140         regmap_reg_range(SLG51000_LDO7_CONF1, SLG51000_LDO7_VSEL_ACTUAL),
 141         regmap_reg_range(SLG51000_LDO7_EVENT, SLG51000_LDO7_IRQ_MASK),
 142         regmap_reg_range(SLG51000_OTP_EVENT, SLG51000_OTP_EVENT),
 143         regmap_reg_range(SLG51000_OTP_IRQ_MASK, SLG51000_OTP_IRQ_MASK),
 144         regmap_reg_range(SLG51000_OTP_LOCK_OTP_PROG, SLG51000_OTP_LOCK_CTRL),
 145         regmap_reg_range(SLG51000_LOCK_GLOBAL_LOCK_CTRL1,
 146                          SLG51000_LOCK_GLOBAL_LOCK_CTRL1),
 147 };
 148
 149 static const struct regmap_range slg51000_volatile_ranges[] = {
 150         regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1, SLG51000_SYSCTL_STATUS),
 151         regmap_reg_range(SLG51000_IO_GPIO_STATUS, SLG51000_IO_GPIO_STATUS),
 152         regmap_reg_range(SLG51000_LDO1_EVENT, SLG51000_LDO1_STATUS),
 153         regmap_reg_range(SLG51000_LDO2_EVENT, SLG51000_LDO2_STATUS),
 154         regmap_reg_range(SLG51000_LDO3_EVENT, SLG51000_LDO3_STATUS),
 155         regmap_reg_range(SLG51000_LDO4_EVENT, SLG51000_LDO4_STATUS),
 156         regmap_reg_range(SLG51000_LDO5_EVENT, SLG51000_LDO5_STATUS),
 157         regmap_reg_range(SLG51000_LDO6_EVENT, SLG51000_LDO6_STATUS),
 158         regmap_reg_range(SLG51000_LDO7_EVENT, SLG51000_LDO7_STATUS),
 159         regmap_reg_range(SLG51000_OTP_EVENT, SLG51000_OTP_EVENT),
 160 };
 161
 162 static const struct regmap_access_table slg51000_writeable_table = {
 163         .yes_ranges     = slg51000_writeable_ranges,
 164         .n_yes_ranges   = ARRAY_SIZE(slg51000_writeable_ranges),
 165 };
 166
 167 static const struct regmap_access_table slg51000_readable_table = {
 168         .yes_ranges     = slg51000_readable_ranges,
 169         .n_yes_ranges   = ARRAY_SIZE(slg51000_readable_ranges),
 170 };
 171
 172 static const struct regmap_access_table slg51000_volatile_table = {
 173         .yes_ranges     = slg51000_volatile_ranges,
 174         .n_yes_ranges   = ARRAY_SIZE(slg51000_volatile_ranges),
 175 };
 176
 177 static const struct regmap_config slg51000_regmap_config = {
 178         .reg_bits = 16,
 179         .val_bits = 8,
 180         .max_register = 0x8000,
 181         .wr_table = &slg51000_writeable_table,
 182         .rd_table = &slg51000_readable_table,
 183         .volatile_table = &slg51000_volatile_table,
 184 };
 185
 186 static struct regulator_ops slg51000_regl_ops = {
 187         .enable = regulator_enable_regmap,
 188         .disable = regulator_disable_regmap,
 189         .is_enabled = regulator_is_enabled_regmap,
 190         .list_voltage = regulator_list_voltage_linear,
 191         .map_voltage = regulator_map_voltage_linear,
 192         .get_voltage_sel = regulator_get_voltage_sel_regmap,
 193         .set_voltage_sel = regulator_set_voltage_sel_regmap,
 194 };
 195
 196 static struct regulator_ops slg51000_switch_ops = {
 197         .enable = regulator_enable_regmap,
 198         .disable = regulator_disable_regmap,
 199         .is_enabled = regulator_is_enabled_regmap,
 200 };
 201
 202 static int slg51000_of_parse_cb(struct device_node *np,
 203                                 const struct regulator_desc *desc,
 204                                 struct regulator_config *config)
 205 {
 206         struct slg51000 *chip = config->driver_data;
 207         struct slg51000_pdata *rpdata = &chip->regl_pdata[desc->id];
 208         enum gpiod_flags gflags = GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE;
 209
 210         rpdata->ena_gpiod = devm_gpiod_get_from_of_node(chip->dev, np,
 211                                                         "enable-gpios", 0,
 212                                                         gflags, "gpio-en-ldo");
 213         if (rpdata->ena_gpiod) {
 214                 config->ena_gpiod = rpdata->ena_gpiod;
 215                 devm_gpiod_unhinge(chip->dev, config->ena_gpiod);
 216         }
 217
 218         return 0;
 219 }
 220
 221 #define SLG51000_REGL_DESC(_id, _name, _s_name, _min, _step) \
 222         [SLG51000_REGULATOR_##_id] = {                             \
 223                 .name = #_name,                                    \
 224                 .supply_name = _s_name,                            \
 225                 .id = SLG51000_REGULATOR_##_id,                    \
 226                 .of_match = of_match_ptr(#_name),                  \
 227                 .of_parse_cb = slg51000_of_parse_cb,               \
 228                 .ops = &slg51000_regl_ops,                         \
 229                 .regulators_node = of_match_ptr("regulators"),     \
 230                 .n_voltages = 256,                                 \
 231                 .min_uV = _min,                                    \
 232                 .uV_step = _step,                                  \
 233                 .linear_min_sel = 0,                               \
 234                 .vsel_mask = SLG51000_VSEL_MASK,                   \
 235                 .vsel_reg = SLG51000_##_id##_VSEL,                 \
 236                 .enable_reg = SLG51000_SYSCTL_MATRIX_CONF_A,       \
 237                 .enable_mask = BIT(SLG51000_REGULATOR_##_id),      \
 238                 .type = REGULATOR_VOLTAGE,                         \
 239                 .owner = THIS_MODULE,                              \
 240         }
 241
 242 static struct regulator_desc regls_desc[SLG51000_MAX_REGULATORS] = {
 243         SLG51000_REGL_DESC(LDO1, ldo1, NULL,   2400000,  5000),
 244         SLG51000_REGL_DESC(LDO2, ldo2, NULL,   2400000,  5000),
 245         SLG51000_REGL_DESC(LDO3, ldo3, "vin3", 1200000, 10000),
 246         SLG51000_REGL_DESC(LDO4, ldo4, "vin4", 1200000, 10000),
 247         SLG51000_REGL_DESC(LDO5, ldo5, "vin5",  400000,  5000),
 248         SLG51000_REGL_DESC(LDO6, ldo6, "vin6",  400000,  5000),
 249         SLG51000_REGL_DESC(LDO7, ldo7, "vin7", 1200000, 10000),
 250 };
 251
 252 static int slg51000_regulator_init(struct slg51000 *chip)
 253 {
 254         struct regulator_config config = { };
 255         struct regulator_desc *rdesc;
 256         unsigned int reg, val;
 257         u8 vsel_range[2];
 258         int id, ret = 0;
 259         const unsigned int min_regs[SLG51000_MAX_REGULATORS] = {
 260                 SLG51000_LDO1_MINV, SLG51000_LDO2_MINV, SLG51000_LDO3_MINV,
 261                 SLG51000_LDO4_MINV, SLG51000_LDO5_MINV, SLG51000_LDO6_MINV,
 262                 SLG51000_LDO7_MINV,
 263         };
 264
 265         for (id = 0; id < SLG51000_MAX_REGULATORS; id++) {
 266                 chip->rdesc[id] = &regls_desc[id];
 267                 rdesc = chip->rdesc[id];
 268                 config.regmap = chip->regmap;
 269                 config.dev = chip->dev;
 270                 config.driver_data = chip;
 271
 272                 ret = regmap_bulk_read(chip->regmap, min_regs[id],
 273                                        vsel_range, 2);
 274                 if (ret < 0) {
 275                         dev_err(chip->dev,
 276                                 "Failed to read the MIN register\n");
 277                         return ret;
 278                 }
 279
 280                 switch (id) {
 281                 case SLG51000_REGULATOR_LDO1:
 282                 case SLG51000_REGULATOR_LDO2:
 283                         if (id == SLG51000_REGULATOR_LDO1)
 284                                 reg = SLG51000_LDO1_MISC1;
 285                         else
 286                                 reg = SLG51000_LDO2_MISC1;
 287
 288                         ret = regmap_read(chip->regmap, reg, &val);
 289                         if (ret < 0) {
 290                                 dev_err(chip->dev,
 291                                         "Failed to read voltage range of ldo%d\n",
 292                                         id + 1);
 293                                 return ret;
 294                         }
 295
 296                         rdesc->linear_min_sel = vsel_range[0];
 297                         rdesc->n_voltages = vsel_range[1] + 1;
 298                         if (val & SLG51000_SEL_VRANGE_MASK)
 299                                 rdesc->min_uV = SLG51000_LDOHP_HV_MIN
 300                                                 + (vsel_range[0]
 301                                                    * rdesc->uV_step);
 302                         else
 303                                 rdesc->min_uV = SLG51000_LDOHP_LV_MIN
 304                                                 + (vsel_range[0]
 305                                                    * rdesc->uV_step);
 306                         break;
 307
 308                 case SLG51000_REGULATOR_LDO5:
 309                 case SLG51000_REGULATOR_LDO6:
 310                         if (id == SLG51000_REGULATOR_LDO5)
 311                                 reg = SLG51000_LDO5_TRIM2;
 312                         else
 313                                 reg = SLG51000_LDO6_TRIM2;
 314
 315                         ret = regmap_read(chip->regmap, reg, &val);
 316                         if (ret < 0) {
 317                                 dev_err(chip->dev,
 318                                         "Failed to read LDO mode register\n");
 319                                 return ret;
 320                         }
 321
 322                         if (val & SLG51000_SEL_BYP_MODE_MASK) {
 323                                 rdesc->ops = &slg51000_switch_ops;
 324                                 rdesc->n_voltages = 0;
 325                                 rdesc->min_uV = 0;
 326                                 rdesc->uV_step = 0;
 327                                 rdesc->linear_min_sel = 0;
 328                                 break;
 329                         }
 330                         /* Fall through - to the check below.*/
 331
 332                 default:
 333                         rdesc->linear_min_sel = vsel_range[0];
 334                         rdesc->n_voltages = vsel_range[1] + 1;
 335                         rdesc->min_uV = rdesc->min_uV
 336                                         + (vsel_range[0] * rdesc->uV_step);
 337                         break;
 338                 }
 339
 340                 chip->rdev[id] = devm_regulator_register(chip->dev, rdesc,
 341                                                          &config);
 342                 if (IS_ERR(chip->rdev[id])) {
 343                         ret = PTR_ERR(chip->rdev[id]);
 344                         dev_err(chip->dev,
 345                                 "Failed to register regulator(%s):%d\n",
 346                                 chip->rdesc[id]->name, ret);
 347                         return ret;
 348                 }
 349         }
 350
 351         return 0;
 352 }
 353
 354 static irqreturn_t slg51000_irq_handler(int irq, void *data)
 355 {
 356         struct slg51000 *chip = data;
 357         struct regmap *regmap = chip->regmap;
 358         enum { R0 = 0, R1, R2, REG_MAX };
 359         u8 evt[SLG51000_MAX_EVT_REGISTER][REG_MAX];
 360         int ret, i, handled = IRQ_NONE;
 361         unsigned int evt_otp, mask_otp;
 362
 363         /* Read event[R0], status[R1] and mask[R2] register */
 364         for (i = 0; i < SLG51000_MAX_EVT_REGISTER; i++) {
 365                 ret = regmap_bulk_read(regmap, es_reg[i].ereg, evt[i], REG_MAX);
 366                 if (ret < 0) {
 367                         dev_err(chip->dev,
 368                                 "Failed to read event registers(%d)\n", ret);
 369                         return IRQ_NONE;
 370                 }
 371         }
 372
 373         ret = regmap_read(regmap, SLG51000_OTP_EVENT, &evt_otp);
 374         if (ret < 0) {
 375                 dev_err(chip->dev,
 376                         "Failed to read otp event registers(%d)\n", ret);
 377                 return IRQ_NONE;
 378         }
 379
 380         ret = regmap_read(regmap, SLG51000_OTP_IRQ_MASK, &mask_otp);
 381         if (ret < 0) {
 382                 dev_err(chip->dev,
 383                         "Failed to read otp mask register(%d)\n", ret);
 384                 return IRQ_NONE;
 385         }
 386
 387         if ((evt_otp & SLG51000_EVT_CRC_MASK) &&
 388             !(mask_otp & SLG51000_IRQ_CRC_MASK)) {
 389                 dev_info(chip->dev,
 390                          "OTP has been read or OTP crc is not zero\n");
 391                 handled = IRQ_HANDLED;
 392         }
 393
 394         for (i = 0; i < SLG51000_MAX_REGULATORS; i++) {
 395                 if (!(evt[i][R2] & SLG51000_IRQ_ILIM_FLAG_MASK) &&
 396                     (evt[i][R0] & SLG51000_EVT_ILIM_FLAG_MASK)) {
 397                         regulator_lock(chip->rdev[i]);
 398                         regulator_notifier_call_chain(chip->rdev[i],
 399                                             REGULATOR_EVENT_OVER_CURRENT, NULL);
 400                         regulator_unlock(chip->rdev[i]);
 401
 402                         if (evt[i][R1] & SLG51000_STA_ILIM_FLAG_MASK)
 403                                 dev_warn(chip->dev,
 404                                          "Over-current limit(ldo%d)\n", i + 1);
 405                         handled = IRQ_HANDLED;
 406                 }
 407         }
 408
 409         if (!(evt[SLG51000_SCTL_EVT][R2] & SLG51000_IRQ_HIGH_TEMP_WARN_MASK) &&
 410             (evt[SLG51000_SCTL_EVT][R0] & SLG51000_EVT_HIGH_TEMP_WARN_MASK)) {
 411                 for (i = 0; i < SLG51000_MAX_REGULATORS; i++) {
 412                         if (!(evt[i][R1] & SLG51000_STA_ILIM_FLAG_MASK) &&
 413                             (evt[i][R1] & SLG51000_STA_VOUT_OK_FLAG_MASK)) {
 414                                 regulator_lock(chip->rdev[i]);
 415                                 regulator_notifier_call_chain(chip->rdev[i],
 416                                                REGULATOR_EVENT_OVER_TEMP, NULL);
 417                                 regulator_unlock(chip->rdev[i]);
 418                         }
 419                 }
 420                 handled = IRQ_HANDLED;
 421                 if (evt[SLG51000_SCTL_EVT][R1] &
 422                     SLG51000_STA_HIGH_TEMP_WARN_MASK)
 423                         dev_warn(chip->dev, "High temperature warning!\n");
 424         }
 425
 426         return handled;
 427 }
 428
 429 static void slg51000_clear_fault_log(struct slg51000 *chip)
 430 {
 431         unsigned int val = 0;
 432         int ret = 0;
 433
 434         ret = regmap_read(chip->regmap, SLG51000_SYSCTL_FAULT_LOG1, &val);
 435         if (ret < 0) {
 436                 dev_err(chip->dev, "Failed to read Fault log register\n");
 437                 return;
 438         }
 439
 440         if (val & SLG51000_FLT_OVER_TEMP_MASK)
 441                 dev_dbg(chip->dev, "Fault log: FLT_OVER_TEMP\n");
 442         if (val & SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK)
 443                 dev_dbg(chip->dev, "Fault log: FLT_POWER_SEQ_CRASH_REQ\n");
 444         if (val & SLG51000_FLT_RST_MASK)
 445                 dev_dbg(chip->dev, "Fault log: FLT_RST\n");
 446         if (val & SLG51000_FLT_POR_MASK)
 447                 dev_dbg(chip->dev, "Fault log: FLT_POR\n");
 448 }
 449
 450 static int slg51000_i2c_probe(struct i2c_client *client,
 451                               const struct i2c_device_id *id)
 452 {
 453         struct device *dev = &client->dev;
 454         struct slg51000 *chip;
 455         struct gpio_desc *cs_gpiod = NULL;
 456         int error, ret;
 457
 458         chip = devm_kzalloc(dev, sizeof(struct slg51000), GFP_KERNEL);
 459         if (!chip)
 460                 return -ENOMEM;
 461
 462         cs_gpiod = devm_gpiod_get_from_of_node(dev, dev->of_node,
 463                                                "dlg,cs-gpios", 0,
 464                                                GPIOD_OUT_HIGH
 465                                                | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
 466                                                "slg51000-cs");
 467         if (cs_gpiod) {
 468                 dev_info(dev, "Found chip selector property\n");
 469                 chip->cs_gpiod = cs_gpiod;
 470         }
 471
 472         i2c_set_clientdata(client, chip);
 473         chip->chip_irq = client->irq;
 474         chip->dev = dev;
 475         chip->regmap = devm_regmap_init_i2c(client, &slg51000_regmap_config);
 476         if (IS_ERR(chip->regmap)) {
 477                 error = PTR_ERR(chip->regmap);
 478                 dev_err(dev, "Failed to allocate register map: %d\n",
 479                         error);
 480                 return error;
 481         }
 482
 483         ret = slg51000_regulator_init(chip);
 484         if (ret < 0) {
 485                 dev_err(chip->dev, "Failed to init regulator(%d)\n", ret);
 486                 return ret;
 487         }
 488
 489         slg51000_clear_fault_log(chip);
 490
 491         if (chip->chip_irq) {
 492                 ret = devm_request_threaded_irq(dev, chip->chip_irq, NULL,
 493                                                 slg51000_irq_handler,
 494                                                 (IRQF_TRIGGER_HIGH |
 495                                                 IRQF_ONESHOT),
 496                                                 "slg51000-irq", chip);
 497                 if (ret != 0) {
 498                         dev_err(dev, "Failed to request IRQ: %d\n",
 499                                 chip->chip_irq);
 500                         return ret;
 501                 }
 502         } else {
 503                 dev_info(dev, "No IRQ configured\n");
 504         }
 505
 506         return ret;
 507 }
 508
 509 static const struct i2c_device_id slg51000_i2c_id[] = {
 510         {"slg51000", 0},
 511         {},
 512 };
 513 MODULE_DEVICE_TABLE(i2c, slg51000_i2c_id);
 514
 515 static struct i2c_driver slg51000_regulator_driver = {
 516         .driver = {
 517                 .name = "slg51000-regulator",
 518         },
 519         .probe = slg51000_i2c_probe,
 520         .id_table = slg51000_i2c_id,
 521 };
 522
 523 module_i2c_driver(slg51000_regulator_driver);
 524
 525 MODULE_AUTHOR("Eric Jeong <eric.jeong.opensource@diasemi.com>");
 526 MODULE_DESCRIPTION("SLG51000 regulator driver");
 527 MODULE_LICENSE("GPL");
 528