drivers/ram/stm32mp1/stm32mp1_tuning.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
   4  */
   5 #include <common.h>
   6 #include <console.h>
   7 #include <clk.h>
   8 #include <ram.h>
   9 #include <reset.h>
  10 #include <asm/io.h>
  11
  12 #include "stm32mp1_ddr_regs.h"
  13 #include "stm32mp1_ddr.h"
  14 #include "stm32mp1_tests.h"
  15
  16 #define MAX_DQS_PHASE_IDX _144deg
  17 #define MAX_DQS_UNIT_IDX 7
  18 #define MAX_GSL_IDX 5
  19 #define MAX_GPS_IDX 3
  20
  21 /* Number of bytes used in this SW. ( min 1--> max 4). */
  22 #define NUM_BYTES 4
  23
  24 enum dqs_phase_enum {
  25         _36deg = 0,
  26         _54deg = 1,
  27         _72deg = 2,
  28         _90deg = 3,
  29         _108deg = 4,
  30         _126deg = 5,
  31         _144deg = 6
  32 };
  33
  34 /* BIST Result struct */
  35 struct BIST_result {
  36         /* Overall test result:
  37          * 0 Fail (any bit failed) ,
  38          * 1 Success (All bits success)
  39          */
  40         bool test_result;
  41         /* 1: true, all fail /  0: False, not all bits fail */
  42         bool all_bits_fail;
  43         bool bit_i_test_result[8];  /* 0 fail / 1 success */
  44 };
  45
  46 /* a struct that defines tuning parameters of a byte. */
  47 struct tuning_position {
  48         u8 phase; /* DQS phase */
  49         u8 unit; /* DQS unit delay */
  50         u32 bits_delay; /* Bits deskew in this byte */
  51 };
  52
  53 /* 36deg, 54deg, 72deg, 90deg, 108deg, 126deg, 144deg */
  54 const u8 dx_dll_phase[7] = {3, 2, 1, 0, 14, 13, 12};
  55
  56 static u8 BIST_error_max = 1;
  57 static u32 BIST_seed = 0x1234ABCD;
  58
  59 static u8 get_nb_bytes(struct stm32mp1_ddrctl *ctl)
  60 {
  61         u32 data_bus = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
  62         u8 nb_bytes = NUM_BYTES;
  63
  64         switch (data_bus) {
  65         case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
  66                 nb_bytes /= 2;
  67                 break;
  68         case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
  69                 nb_bytes /= 4;
  70                 break;
  71         default:
  72                 break;
  73         }
  74
  75         return nb_bytes;
  76 }
  77
  78 static void itm_soft_reset(struct stm32mp1_ddrphy *phy)
  79 {
  80         stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
  81 }
  82
  83 /* Read DQ unit delay register and provides the retrieved value for DQS
  84  * We are assuming that we have the same delay when clocking
  85  * by DQS and when clocking by DQSN
  86  */
  87 static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit)
  88 {
  89         u32 index;
  90         u32 addr = DXNDQTR(phy, byte);
  91
  92         /* We are assuming that we have the same delay when clocking by DQS
  93          * and when clocking by DQSN : use only the low bits
  94          */
  95         index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
  96                 & DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
  97
  98         pr_debug("%s: [%x]: %x => DQ unit index = %x\n",
  99                  __func__, addr, readl(addr), index);
 100
 101         return index;
 102 }
 103
 104 /* Sets the DQS phase delay for a byte lane.
 105  *phase delay is specified by giving the index of the desired delay
 106  * in the dx_dll_phase array.
 107  */
 108 static void DQS_phase_delay(struct stm32mp1_ddrphy *phy, u8 byte, u8 phase_idx)
 109 {
 110         u8 sdphase_val = 0;
 111
 112         /*      Write DXNDLLCR.SDPHASE = dx_dll_phase(phase_index); */
 113         sdphase_val = dx_dll_phase[phase_idx];
 114         clrsetbits_le32(DXNDLLCR(phy, byte),
 115                         DDRPHYC_DXNDLLCR_SDPHASE_MASK,
 116                         sdphase_val << DDRPHYC_DXNDLLCR_SDPHASE_SHIFT);
 117 }
 118
 119 /* Sets the DQS unit delay for a byte lane.
 120  * unit delay is specified by giving the index of the desired delay
 121  * for dgsdly and dqsndly (same value).
 122  */
 123 static void DQS_unit_delay(struct stm32mp1_ddrphy *phy,
 124                            u8 byte, u8 unit_dly_idx)
 125 {
 126         /* Write the same value in DXNDQSTR.DQSDLY and DXNDQSTR.DQSNDLY */
 127         clrsetbits_le32(DXNDQSTR(phy, byte),
 128                         DDRPHYC_DXNDQSTR_DQSDLY_MASK |
 129                         DDRPHYC_DXNDQSTR_DQSNDLY_MASK,
 130                         (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSDLY_SHIFT) |
 131                         (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT));
 132
 133         /* After changing this value, an ITM soft reset (PIR.ITMSRST=1,
 134          * plus PIR.INIT=1) must be issued.
 135          */
 136         stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
 137 }
 138
 139 /* Sets the DQ unit delay for a bit line in particular byte lane.
 140  * unit delay is specified by giving the desired delay
 141  */
 142 static void set_DQ_unit_delay(struct stm32mp1_ddrphy *phy,
 143                               u8 byte, u8 bit,
 144                               u8 dq_delay_index)
 145 {
 146         u8 dq_bit_delay_val = dq_delay_index | (dq_delay_index << 2);
 147
 148         /* same value on delay for clock DQ an DQS_b */
 149         clrsetbits_le32(DXNDQTR(phy, byte),
 150                         DDRPHYC_DXNDQTR_DQDLY_MASK
 151                         << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit),
 152                         dq_bit_delay_val << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit));
 153 }
 154
 155 static void set_r0dgsl_delay(struct stm32mp1_ddrphy *phy,
 156                              u8 byte, u8 r0dgsl_idx)
 157 {
 158         clrsetbits_le32(DXNDQSTR(phy, byte),
 159                         DDRPHYC_DXNDQSTR_R0DGSL_MASK,
 160                         r0dgsl_idx << DDRPHYC_DXNDQSTR_R0DGSL_SHIFT);
 161 }
 162
 163 static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy,
 164                              u8 byte, u8 r0dgps_idx)
 165 {
 166         clrsetbits_le32(DXNDQSTR(phy, byte),
 167                         DDRPHYC_DXNDQSTR_R0DGPS_MASK,
 168                         r0dgps_idx << DDRPHYC_DXNDQSTR_R0DGPS_SHIFT);
 169 }
 170
 171 /* Basic BIST configuration for data lane tests. */
 172 static void config_BIST(struct stm32mp1_ddrphy *phy)
 173 {
 174         /* Selects the SDRAM bank address to be used during BIST. */
 175         u32 bbank = 0;
 176         /* Selects the SDRAM row address to be used during BIST. */
 177         u32 brow = 0;
 178         /* Selects the SDRAM column address to be used during BIST. */
 179         u32 bcol = 0;
 180         /* Selects the value by which the SDRAM address is incremented
 181          * for each write/read access.
 182          */
 183         u32 bainc = 0x00000008;
 184         /* Specifies the maximum SDRAM rank to be used during BIST.
 185          * The default value is set to maximum ranks minus 1.
 186          * must be 0 with single rank
 187          */
 188         u32 bmrank = 0;
 189         /* Selects the SDRAM rank to be used during BIST.
 190          * must be 0 with single rank
 191          */
 192         u32 brank = 0;
 193         /* Specifies the maximum SDRAM bank address to be used during
 194          * BIST before the address & increments to the next rank.
 195          */
 196         u32 bmbank = 1;
 197         /* Specifies the maximum SDRAM row address to be used during
 198          * BIST before the address & increments to the next bank.
 199          */
 200         u32 bmrow = 0x7FFF; /* To check */
 201         /* Specifies the maximum SDRAM column address to be used during
 202          * BIST before the address & increments to the next row.
 203          */
 204         u32 bmcol = 0x3FF;  /* To check */
 205         u32 bmode_conf = 0x00000001;  /* DRam mode */
 206         u32 bdxen_conf = 0x00000001;  /* BIST on Data byte */
 207         u32 bdpat_conf = 0x00000002;  /* Select LFSR pattern */
 208
 209         /*Setup BIST for DRAM mode,  and LFSR-random data pattern.*/
 210         /*Write BISTRR.BMODE = 1?b1;*/
 211         /*Write BISTRR.BDXEN = 1?b1;*/
 212         /*Write BISTRR.BDPAT = 2?b10;*/
 213
 214         /* reset BIST */
 215         writel(0x3, &phy->bistrr);
 216
 217         writel((bmode_conf << 3) | (bdxen_conf << 14) | (bdpat_conf << 17),
 218                &phy->bistrr);
 219
 220         /*Setup BIST Word Count*/
 221         /*Write BISTWCR.BWCNT = 16?b0008;*/
 222         writel(0x00000200, &phy->bistwcr); /* A multiple of BL/2 */
 223
 224         writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0);
 225         writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1);
 226
 227         /* To check this line : */
 228         writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2);
 229 }
 230
 231 /* Select the Byte lane to be tested by BIST. */
 232 static void BIST_datx8_sel(struct stm32mp1_ddrphy *phy, u8 datx8)
 233 {
 234         clrsetbits_le32(&phy->bistrr,
 235                         DDRPHYC_BISTRR_BDXSEL_MASK,
 236                         datx8 << DDRPHYC_BISTRR_BDXSEL_SHIFT);
 237
 238         /*(For example, selecting Byte Lane 3, BISTRR.BDXSEL = 4?b0011)*/
 239         /* Write BISTRR.BDXSEL = datx8; */
 240 }
 241
 242 /* Perform BIST Write_Read test on a byte lane and return test result. */
 243 static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte,
 244                       struct BIST_result *bist)
 245 {
 246         bool result = true; /* BIST_SUCCESS */
 247         u32 cnt = 0;
 248         u32 error = 0;
 249
 250         bist->test_result = true;
 251
 252 run:
 253         itm_soft_reset(phy);
 254
 255         /*Perform BIST Reset*/
 256         /* Write BISTRR.BINST = 3?b011; */
 257         clrsetbits_le32(&phy->bistrr,
 258                         0x00000007,
 259                         0x00000003);
 260
 261         /*Re-seed LFSR*/
 262         /* Write BISTLSR.SEED = 32'h1234ABCD; */
 263         if (BIST_seed)
 264                 writel(BIST_seed, &phy->bistlsr);
 265         else
 266                 writel(rand(), &phy->bistlsr);
 267
 268         /* some delay to reset BIST */
 269         mdelay(1);
 270
 271         /*Perform BIST Run*/
 272         clrsetbits_le32(&phy->bistrr,
 273                         0x00000007,
 274                         0x00000001);
 275         /* Write BISTRR.BINST = 3?b001; */
 276
 277         /* Wait for a number of CTL clocks before reading BIST register*/
 278         /* Wait 300 ctl_clk cycles;  ... IS it really needed?? */
 279         /* Perform BIST Instruction Stop*/
 280         /* Write BISTRR.BINST = 3?b010;*/
 281
 282         /* poll on BISTGSR.BDONE. If 0, wait.  ++TODO Add timeout */
 283         while (!(readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDDONE))
 284                 ;
 285
 286         /*Check if received correct number of words*/
 287         /* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */
 288         if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT) ==
 289             readl(&phy->bistwcr)) {
 290                 /*Determine if there is a data comparison error*/
 291                 /* if (Read BISTGSR.BDXERR = 1?b0) */
 292                 if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR)
 293                         result = false; /* BIST_FAIL; */
 294                 else
 295                         result = true; /* BIST_SUCCESS; */
 296         } else {
 297                 result = false; /* BIST_FAIL; */
 298         }
 299
 300         /* loop while success */
 301         cnt++;
 302         if (result && cnt != 1000)
 303                 goto run;
 304
 305         if (!result)
 306                 error++;
 307
 308         if (error < BIST_error_max) {
 309                 if (cnt != 1000)
 310                         goto run;
 311                 bist->test_result = true;
 312         } else {
 313                 bist->test_result = false;
 314         }
 315 }
 316
 317 /* After running the deskew algo, this function applies the new DQ delays
 318  * by reading them from the array "deskew_delay"and writing in PHY registers.
 319  * The bits that are not deskewed parfectly (too much skew on them,
 320  * or data eye very wide) are marked in the array deskew_non_converge.
 321  */
 322 static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte,
 323                                  u8 deskew_delay[NUM_BYTES][8],
 324                                  u8 deskew_non_converge[NUM_BYTES][8])
 325 {
 326         u8  bit_i;
 327         u8  index;
 328
 329         for (bit_i = 0; bit_i < 8; bit_i++) {
 330                 set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
 331                 index = DQ_unit_index(phy, byte, bit_i);
 332                 pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
 333                          byte, bit_i, deskew_delay[byte][bit_i],
 334                          index, index - 3);
 335                 printf("Byte %d, bit %d, DQ delay = %d",
 336                        byte, bit_i, deskew_delay[byte][bit_i]);
 337                 if (deskew_non_converge[byte][bit_i] == 1)
 338                         pr_debug(" - not converged : still more skew");
 339                 printf("\n");
 340         }
 341 }
 342
 343 /* DQ Bit de-skew algorithm.
 344  * Deskews data lines as much as possible.
 345  * 1. Add delay to DQS line until finding the failure
 346  *    (normally a hold time violation)
 347  * 2. Reduce DQS line by small steps until finding the very first time
 348  *    we go back to "Pass" condition.
 349  * 3. For each DQ line, Reduce DQ delay until finding the very first failure
 350  *    (normally a hold time fail)
 351  * 4. When all bits are at their first failure delay, we can consider them
 352  *    aligned.
 353  * Handle conrer situation (Can't find Pass-fail, or fail-pass transitions
 354  * at any step)
 355  * TODO Provide a return Status. Improve doc
 356  */
 357 static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
 358                                    struct stm32mp1_ddrphy *phy, char *string)
 359 {
 360         /* New DQ delay value (index), set during Deskew algo */
 361         u8 deskew_delay[NUM_BYTES][8];
 362         /*If there is still skew on a bit, mark this bit. */
 363         u8 deskew_non_converge[NUM_BYTES][8];
 364         struct BIST_result result;
 365         s8 dqs_unit_delay_index = 0;
 366         u8 datx8 = 0;
 367         u8 bit_i = 0;
 368         s8 phase_idx = 0;
 369         s8 bit_i_delay_index = 0;
 370         u8 success = 0;
 371         struct tuning_position last_right_ok;
 372         u8 force_stop = 0;
 373         u8 fail_found;
 374         u8 error = 0;
 375         u8 nb_bytes = get_nb_bytes(ctl);
 376         /* u8 last_pass_dqs_unit = 0; */
 377
 378         memset(deskew_delay, 0, sizeof(deskew_delay));
 379         memset(deskew_non_converge, 0, sizeof(deskew_non_converge));
 380
 381         /*Disable DQS Drift Compensation*/
 382         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
 383         /*Disable all bytes*/
 384         /* Disable automatic power down of DLL and IOs when disabling
 385          * a byte (To avoid having to add programming and  delay
 386          * for a DLL re-lock when later re-enabling a disabled Byte Lane)
 387          */
 388         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
 389
 390         /* Disable all data bytes */
 391         clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
 392         clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
 393         clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
 394         clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
 395
 396         /* Config the BIST block */
 397         config_BIST(phy);
 398         pr_debug("BIST Config done.\n");
 399
 400         /* Train each byte */
 401         for (datx8 = 0; datx8 < nb_bytes; datx8++) {
 402                 if (ctrlc()) {
 403                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 404                                 datx8 + 1, nb_bytes, error);
 405                         return TEST_FAILED;
 406                 }
 407                 pr_debug("\n======================\n");
 408                 pr_debug("Start deskew byte %d .\n", datx8);
 409                 pr_debug("======================\n");
 410                 /* Enable Byte (DXNGCR, bit DXEN) */
 411                 setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
 412
 413                 /* Select the byte lane for comparison of read data */
 414                 BIST_datx8_sel(phy, datx8);
 415
 416                 /* Set all DQDLYn to maximum value. All bits within the byte
 417                  * will be delayed with DQSTR = 2 instead of max = 3
 418                  * to avoid inter bits fail influence
 419                  */
 420                 writel(0xAAAAAAAA, DXNDQTR(phy, datx8));
 421
 422                 /* Set the DQS phase delay to 90 DEG (default).
 423                  * What is defined here is the index of the desired config
 424                  * in the PHASE array.
 425                  */
 426                 phase_idx = _90deg;
 427
 428                 /* Set DQS unit delay to the max value. */
 429                 dqs_unit_delay_index = MAX_DQS_UNIT_IDX;
 430                 DQS_unit_delay(phy, datx8, dqs_unit_delay_index);
 431                 DQS_phase_delay(phy, datx8, phase_idx);
 432
 433                 /* Issue a DLL soft reset */
 434                 clrbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
 435                 setbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
 436
 437                 /* Test this typical init condition */
 438                 BIST_test(phy, datx8, &result);
 439                 success = result.test_result;
 440
 441                 /* If the test pass in this typical condition,
 442                  * start the algo with it.
 443                  * Else, look for Pass init condition
 444                  */
 445                 if (!success) {
 446                         pr_debug("Fail at init condtion. Let's look for a good init condition.\n");
 447                         success = 0; /* init */
 448                         /* Make sure we start with a PASS condition before
 449                          * looking for a fail condition.
 450                          * Find the first PASS PHASE condition
 451                          */
 452
 453                         /* escape if we find a PASS */
 454                         pr_debug("increase Phase idx\n");
 455                         while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
 456                                 DQS_phase_delay(phy, datx8, phase_idx);
 457                                 BIST_test(phy, datx8, &result);
 458                                 success = result.test_result;
 459                                 phase_idx++;
 460                         }
 461                         /* if ended with success
 462                          * ==>> Restore the fist success condition
 463                          */
 464                         if (success)
 465                                 phase_idx--; /* because it ended with ++ */
 466                 }
 467                 if (ctrlc()) {
 468                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 469                                 datx8 + 1, nb_bytes, error);
 470                         return TEST_FAILED;
 471                 }
 472                 /* We couldn't find a successful condition, its seems
 473                  * we have hold violation, lets try reduce DQS_unit Delay
 474                  */
 475                 if (!success) {
 476                         /* We couldn't find a successful condition, its seems
 477                          * we have hold violation, lets try reduce DQS_unit
 478                          * Delay
 479                          */
 480                         pr_debug("Still fail. Try decrease DQS Unit delay\n");
 481
 482                         phase_idx = 0;
 483                         dqs_unit_delay_index = 0;
 484                         DQS_phase_delay(phy, datx8, phase_idx);
 485
 486                         /* escape if we find a PASS */
 487                         while (!success &&
 488                                (dqs_unit_delay_index <=
 489                                 MAX_DQS_UNIT_IDX)) {
 490                                 DQS_unit_delay(phy, datx8,
 491                                                dqs_unit_delay_index);
 492                                 BIST_test(phy, datx8, &result);
 493                                 success = result.test_result;
 494                                 dqs_unit_delay_index++;
 495                         }
 496                         if (success) {
 497                                 /* Restore the first success condition*/
 498                                 dqs_unit_delay_index--;
 499                                 /* last_pass_dqs_unit = dqs_unit_delay_index;*/
 500                                 DQS_unit_delay(phy, datx8,
 501                                                dqs_unit_delay_index);
 502                         } else {
 503                                 /* No need to continue,
 504                                  * there is no pass region.
 505                                  */
 506                                 force_stop = 1;
 507                         }
 508                 }
 509
 510                 /* There is an initial PASS condition
 511                  * Look for the first failing condition by PHASE stepping.
 512                  * This part of the algo can finish without converging.
 513                  */
 514                 if (force_stop) {
 515                         printf("Result: Failed ");
 516                         printf("[Cannot Deskew lines, ");
 517                         printf("there is no PASS region]\n");
 518                         error++;
 519                         continue;
 520                 }
 521                 if (ctrlc()) {
 522                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 523                                 datx8 + 1, nb_bytes, error);
 524                         return TEST_FAILED;
 525                 }
 526
 527                 pr_debug("there is a pass region for phase idx %d\n",
 528                          phase_idx);
 529                 pr_debug("Step1: Find the first failing condition\n");
 530                 /* Look for the first failing condition by PHASE stepping.
 531                  * This part of the algo can finish without converging.
 532                  */
 533
 534                 /* escape if we find a fail (hold time violation)
 535                  * condition at any bit or if out of delay range.
 536                  */
 537                 while (success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
 538                         DQS_phase_delay(phy, datx8, phase_idx);
 539                         BIST_test(phy, datx8, &result);
 540                         success = result.test_result;
 541                         phase_idx++;
 542                 }
 543                 if (ctrlc()) {
 544                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 545                                 datx8 + 1, nb_bytes, error);
 546                         return TEST_FAILED;
 547                 }
 548
 549                 /* if the loop ended with a failing condition at any bit,
 550                  * lets look for the first previous success condition by unit
 551                  * stepping (minimal delay)
 552                  */
 553                 if (!success) {
 554                         pr_debug("Fail region (PHASE) found phase idx %d\n",
 555                                  phase_idx);
 556                         pr_debug("Let's look for first success by DQS Unit steps\n");
 557                         /* This part, the algo always converge */
 558                         phase_idx--;
 559
 560                         /* escape if we find a success condition
 561                          * or if out of delay range.
 562                          */
 563                         while (!success && dqs_unit_delay_index >= 0) {
 564                                 DQS_unit_delay(phy, datx8,
 565                                                dqs_unit_delay_index);
 566                                 BIST_test(phy, datx8, &result);
 567                                 success = result.test_result;
 568                                 dqs_unit_delay_index--;
 569                         }
 570                         /* if the loop ended with a success condition,
 571                          * the last delay Right OK (before hold violation)
 572                          *  condition is then defined as following:
 573                          */
 574                         if (success) {
 575                                 /* Hold the dely parameters of the the last
 576                                  * delay Right OK condition.
 577                                  * -1 to get back to current condition
 578                                  */
 579                                 last_right_ok.phase = phase_idx;
 580                                 /*+1 to get back to current condition */
 581                                 last_right_ok.unit = dqs_unit_delay_index + 1;
 582                                 last_right_ok.bits_delay = 0xFFFFFFFF;
 583                                 pr_debug("Found %d\n", dqs_unit_delay_index);
 584                         } else {
 585                                 /* the last OK condition is then with the
 586                                  * previous phase_idx.
 587                                  * -2 instead of -1 because at the last
 588                                  * iteration of the while(),
 589                                  * we incremented phase_idx
 590                                  */
 591                                 last_right_ok.phase = phase_idx - 1;
 592                                 /* Nominal+1. Because we want the previous
 593                                  * delay after reducing the phase delay.
 594                                  */
 595                                 last_right_ok.unit = 1;
 596                                 last_right_ok.bits_delay = 0xFFFFFFFF;
 597                                 pr_debug("Not Found : try previous phase %d\n",
 598                                          phase_idx - 1);
 599
 600                                 DQS_phase_delay(phy, datx8, phase_idx - 1);
 601                                 dqs_unit_delay_index = 0;
 602                                 success = true;
 603                                 while (success &&
 604                                        (dqs_unit_delay_index <
 605                                         MAX_DQS_UNIT_IDX)) {
 606                                         DQS_unit_delay(phy, datx8,
 607                                                        dqs_unit_delay_index);
 608                                         BIST_test(phy, datx8, &result);
 609                                         success = result.test_result;
 610                                         dqs_unit_delay_index++;
 611                                         pr_debug("dqs_unit_delay_index = %d, result = %d\n",
 612                                                  dqs_unit_delay_index, success);
 613                                 }
 614
 615                                 if (!success) {
 616                                         last_right_ok.unit =
 617                                                  dqs_unit_delay_index - 1;
 618                                 } else {
 619                                         last_right_ok.unit = 0;
 620                                         pr_debug("ERROR: failed region not FOUND");
 621                                 }
 622                         }
 623                 } else {
 624                         /* we can't find a failing  condition at all bits
 625                          * ==> Just hold the last test condition
 626                          * (the max DQS delay)
 627                          * which is the most likely,
 628                          * the closest to a hold violation
 629                          * If we can't find a Fail condition after
 630                          * the Pass region, stick at this position
 631                          * In order to have max chances to find a fail
 632                          * when reducing DQ delays.
 633                          */
 634                         last_right_ok.phase = MAX_DQS_PHASE_IDX;
 635                         last_right_ok.unit = MAX_DQS_UNIT_IDX;
 636                         last_right_ok.bits_delay = 0xFFFFFFFF;
 637                         pr_debug("Can't find the a fail condition\n");
 638                 }
 639
 640                 /* step 2:
 641                  * if we arrive at this stage, it means that we found the last
 642                  * Right OK condition (by tweeking the DQS delay). Or we simply
 643                  * pushed DQS delay to the max
 644                  * This means that by reducing the delay on some DQ bits,
 645                  * we should find a failing condition.
 646                  */
 647                 printf("Byte %d, DQS unit = %d, phase = %d\n",
 648                        datx8, last_right_ok.unit, last_right_ok.phase);
 649                 pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
 650                          last_right_ok.unit, last_right_ok.phase,
 651                          last_right_ok.bits_delay);
 652
 653                 /* Restore the last_right_ok condtion. */
 654                 DQS_unit_delay(phy, datx8, last_right_ok.unit);
 655                 DQS_phase_delay(phy, datx8, last_right_ok.phase);
 656                 writel(last_right_ok.bits_delay, DXNDQTR(phy, datx8));
 657
 658                 /* train each bit
 659                  * reduce delay on each bit, and perform a write/read test
 660                  * and stop at the very first time it fails.
 661                  * the goal is the find the first failing condition
 662                  * for each bit.
 663                  * When we achieve this condition<  for all the bits,
 664                  * we are sure they are aligned (+/- step resolution)
 665                  */
 666                 fail_found = 0;
 667                 for (bit_i = 0; bit_i < 8; bit_i++) {
 668                         if (ctrlc()) {
 669                                 sprintf(string,
 670                                         "interrupted at byte %d/%d, error=%d",
 671                                         datx8 + 1, nb_bytes, error);
 672                                 return error;
 673                         }
 674                         pr_debug("deskewing bit %d:\n", bit_i);
 675                         success = 1; /* init */
 676                         /* Set all DQDLYn to maximum value.
 677                          * Only bit_i will be down-delayed
 678                          * ==> if we have a fail, it will be definitely
 679                          *     from bit_i
 680                          */
 681                         writel(0xFFFFFFFF, DXNDQTR(phy, datx8));
 682                         /* Arriving at this stage,
 683                          * we have a success condition with delay = 3;
 684                          */
 685                         bit_i_delay_index = 3;
 686
 687                         /* escape if bit delay is out of range or
 688                          * if a fatil occurs
 689                          */
 690                         while ((bit_i_delay_index >= 0) && success) {
 691                                 set_DQ_unit_delay(phy, datx8,
 692                                                   bit_i,
 693                                                   bit_i_delay_index);
 694                                 BIST_test(phy, datx8, &result);
 695                                 success = result.test_result;
 696                                 bit_i_delay_index--;
 697                         }
 698
 699                         /* if escape with a fail condition
 700                          * ==> save this position for bit_i
 701                          */
 702                         if (!success) {
 703                                 /* save the delay position.
 704                                  * Add 1 because the while loop ended with a --,
 705                                  * and that we need to hold the last success
 706                                  *  delay
 707                                  */
 708                                 deskew_delay[datx8][bit_i] =
 709                                         bit_i_delay_index + 2;
 710                                 if (deskew_delay[datx8][bit_i] > 3)
 711                                         deskew_delay[datx8][bit_i] = 3;
 712
 713                                 /* A flag that states we found at least a fail
 714                                  * at one bit.
 715                                  */
 716                                 fail_found = 1;
 717                                 pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
 718                                          bit_i, bit_i_delay_index + 1,
 719                                          datx8, bit_i,
 720                                          deskew_delay[datx8][bit_i]);
 721                         } else {
 722                                 /* if we can find a success condition by
 723                                  * back-delaying this bit, just set the delay
 724                                  * to 0 (the best deskew
 725                                  * possible) and mark the bit.
 726                                  */
 727                                 deskew_delay[datx8][bit_i] = 0;
 728                                 /* set a flag that will be used later
 729                                  * in the report.
 730                                  */
 731                                 deskew_non_converge[datx8][bit_i] = 1;
 732                                 pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
 733                                          bit_i, datx8, bit_i,
 734                                          deskew_delay[datx8][bit_i]);
 735                         }
 736                 }
 737                 pr_debug("**********byte %d tuning complete************\n",
 738                          datx8);
 739                 /* If we can't find any failure by back delaying DQ lines,
 740                  * hold the default values
 741                  */
 742                 if (!fail_found) {
 743                         for (bit_i = 0; bit_i < 8; bit_i++)
 744                                 deskew_delay[datx8][bit_i] = 0;
 745                         pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
 746                 }
 747
 748                 apply_deskew_results(phy, datx8, deskew_delay,
 749                                      deskew_non_converge);
 750                 /* Restore nominal value for DQS delay */
 751                 DQS_phase_delay(phy, datx8, 3);
 752                 DQS_unit_delay(phy, datx8, 3);
 753                 /* disable byte after byte bits deskew */
 754                 clrbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
 755         }  /* end of byte deskew */
 756
 757         /* re-enable all data bytes */
 758         setbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
 759         setbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
 760         setbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
 761         setbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
 762
 763         if (error) {
 764                 sprintf(string, "error = %d", error);
 765                 return TEST_FAILED;
 766         }
 767
 768         return TEST_PASSED;
 769 } /* end function */
 770
 771 /* Trim DQS timings and set it in the centre of data eye.
 772  * Look for a PPPPF region, then look for a FPPP region and finally select
 773  * the mid of the FPPPPPF region
 774  */
 775 static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
 776                                      struct stm32mp1_ddrphy *phy, char *string)
 777 {
 778         /*Stores the DQS trim values (PHASE index, unit index) */
 779         u8 eye_training_val[NUM_BYTES][2];
 780         u8 byte = 0;
 781         struct BIST_result result;
 782         s8 dqs_unit_delay_index = 0;
 783         s8 phase_idx = 0;
 784         s8 dqs_unit_delay_index_pass = 0;
 785         s8 phase_idx_pass = 0;
 786         u8 success = 0;
 787         u8 left_phase_bound_found, right_phase_bound_found;
 788         u8 left_unit_bound_found, right_unit_bound_found;
 789         u8 left_bound_found, right_bound_found;
 790         struct tuning_position left_bound, right_bound;
 791         u8 error = 0;
 792         u8 nb_bytes = get_nb_bytes(ctl);
 793
 794         /*Disable DQS Drift Compensation*/
 795         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
 796         /*Disable all bytes*/
 797         /* Disable automatic power down of DLL and IOs when disabling a byte
 798          * (To avoid having to add programming and  delay
 799          * for a DLL re-lock when later re-enabling a disabled Byte Lane)
 800          */
 801         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
 802
 803         /*Disable all data bytes */
 804         clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
 805         clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
 806         clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
 807         clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
 808
 809         /* Config the BIST block */
 810         config_BIST(phy);
 811
 812         for (byte = 0; byte < nb_bytes; byte++) {
 813                 if (ctrlc()) {
 814                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 815                                 byte + 1, nb_bytes, error);
 816                         return TEST_FAILED;
 817                 }
 818                 right_bound.phase = 0;
 819                 right_bound.unit = 0;
 820
 821                 left_bound.phase = 0;
 822                 left_bound.unit = 0;
 823
 824                 left_phase_bound_found = 0;
 825                 right_phase_bound_found = 0;
 826
 827                 left_unit_bound_found = 0;
 828                 right_unit_bound_found = 0;
 829
 830                 left_bound_found = 0;
 831                 right_bound_found = 0;
 832
 833                 /* Enable Byte (DXNGCR, bit DXEN) */
 834                 setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
 835
 836                 /* Select the byte lane for comparison of read data */
 837                 BIST_datx8_sel(phy, byte);
 838
 839                 /* Set DQS phase delay to the nominal value. */
 840                 phase_idx = _90deg;
 841                 phase_idx_pass = phase_idx;
 842
 843                 /* Set DQS unit delay to the nominal value. */
 844                 dqs_unit_delay_index = 3;
 845                 dqs_unit_delay_index_pass = dqs_unit_delay_index;
 846                 success = 0;
 847
 848                 pr_debug("STEP0: Find Init delay\n");
 849                 /* STEP0: Find Init delay: a delay that put the system
 850                  * in a "Pass" condition then (TODO) update
 851                  * dqs_unit_delay_index_pass & phase_idx_pass
 852                  */
 853                 DQS_unit_delay(phy, byte, dqs_unit_delay_index);
 854                 DQS_phase_delay(phy, byte, phase_idx);
 855                 BIST_test(phy, byte, &result);
 856                 success = result.test_result;
 857                 /* If we have a fail in the nominal condition */
 858                 if (!success) {
 859                         /* Look at the left */
 860                         while (phase_idx >= 0 && !success) {
 861                                 phase_idx--;
 862                                 DQS_phase_delay(phy, byte, phase_idx);
 863                                 BIST_test(phy, byte, &result);
 864                                 success = result.test_result;
 865                         }
 866                 }
 867                 if (!success) {
 868                         /* if we can't find pass condition,
 869                          * then look at the right
 870                          */
 871                         phase_idx = _90deg;
 872                         while (phase_idx <= MAX_DQS_PHASE_IDX &&
 873                                !success) {
 874                                 phase_idx++;
 875                                 DQS_phase_delay(phy, byte,
 876                                                 phase_idx);
 877                                 BIST_test(phy, byte, &result);
 878                                 success = result.test_result;
 879                         }
 880                 }
 881                 /* save the pass condition */
 882                 if (success) {
 883                         phase_idx_pass = phase_idx;
 884                 } else {
 885                         printf("Result: Failed ");
 886                         printf("[Cannot DQS timings, ");
 887                         printf("there is no PASS region]\n");
 888                         error++;
 889                         continue;
 890                 }
 891
 892                 if (ctrlc()) {
 893                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 894                                 byte + 1, nb_bytes, error);
 895                         return TEST_FAILED;
 896                 }
 897                 pr_debug("STEP1: Find LEFT PHASE DQS Bound\n");
 898                 /* STEP1: Find LEFT PHASE DQS Bound */
 899                 while ((phase_idx >= 0) &&
 900                        (phase_idx <= MAX_DQS_PHASE_IDX) &&
 901                        !left_phase_bound_found) {
 902                         DQS_unit_delay(phy, byte,
 903                                        dqs_unit_delay_index);
 904                         DQS_phase_delay(phy, byte,
 905                                         phase_idx);
 906                         BIST_test(phy, byte, &result);
 907                         success = result.test_result;
 908
 909                         /*TODO: Manage the case were at the beginning
 910                          * there is already a fail
 911                          */
 912                         if (!success) {
 913                                 /* the last pass condition */
 914                                 left_bound.phase = ++phase_idx;
 915                                 left_phase_bound_found = 1;
 916                         } else if (success) {
 917                                 phase_idx--;
 918                         }
 919                 }
 920                 if (!left_phase_bound_found) {
 921                         left_bound.phase = 0;
 922                         phase_idx = 0;
 923                 }
 924                 /* If not found, lets take 0 */
 925
 926                 if (ctrlc()) {
 927                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 928                                 byte + 1, nb_bytes, error);
 929                         return TEST_FAILED;
 930                 }
 931                 pr_debug("STEP2: Find UNIT left bound\n");
 932                 /* STEP2: Find UNIT left bound */
 933                 while ((dqs_unit_delay_index >= 0) &&
 934                        !left_unit_bound_found) {
 935                         DQS_unit_delay(phy, byte,
 936                                        dqs_unit_delay_index);
 937                         DQS_phase_delay(phy, byte, phase_idx);
 938                         BIST_test(phy, byte, &result);
 939                         success = result.test_result;
 940                         if (!success) {
 941                                 left_bound.unit =
 942                                         ++dqs_unit_delay_index;
 943                                 left_unit_bound_found = 1;
 944                                 left_bound_found = 1;
 945                         } else if (success) {
 946                                 dqs_unit_delay_index--;
 947                         }
 948                 }
 949
 950                 /* If not found, lets take 0 */
 951                 if (!left_unit_bound_found)
 952                         left_bound.unit = 0;
 953
 954                 if (ctrlc()) {
 955                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 956                                 byte + 1, nb_bytes, error);
 957                         return TEST_FAILED;
 958                 }
 959                 pr_debug("STEP3: Find PHase right bound\n");
 960                 /* STEP3: Find PHase right bound, start with "pass"
 961                  * condition
 962                  */
 963
 964                 /* Set DQS phase delay to the pass value. */
 965                 phase_idx = phase_idx_pass;
 966
 967                 /* Set DQS unit delay to the pass value. */
 968                 dqs_unit_delay_index = dqs_unit_delay_index_pass;
 969
 970                 while ((phase_idx <= MAX_DQS_PHASE_IDX) &&
 971                        !right_phase_bound_found) {
 972                         DQS_unit_delay(phy, byte,
 973                                        dqs_unit_delay_index);
 974                         DQS_phase_delay(phy, byte, phase_idx);
 975                         BIST_test(phy, byte, &result);
 976                         success = result.test_result;
 977                         if (!success) {
 978                                 /* the last pass condition */
 979                                 right_bound.phase = --phase_idx;
 980                                 right_phase_bound_found = 1;
 981                         } else if (success) {
 982                                 phase_idx++;
 983                         }
 984                 }
 985
 986                 /* If not found, lets take the max value */
 987                 if (!right_phase_bound_found) {
 988                         right_bound.phase = MAX_DQS_PHASE_IDX;
 989                         phase_idx = MAX_DQS_PHASE_IDX;
 990                 }
 991
 992                 if (ctrlc()) {
 993                         sprintf(string, "interrupted at byte %d/%d, error=%d",
 994                                 byte + 1, nb_bytes, error);
 995                         return TEST_FAILED;
 996                 }
 997                 pr_debug("STEP4: Find UNIT right bound\n");
 998                 /* STEP4: Find UNIT right bound */
 999                 while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
1000                        !right_unit_bound_found) {
1001                         DQS_unit_delay(phy, byte,
1002                                        dqs_unit_delay_index);
1003                         DQS_phase_delay(phy, byte, phase_idx);
1004                         BIST_test(phy, byte, &result);
1005                         success = result.test_result;
1006                         if (!success) {
1007                                 right_bound.unit =
1008                                         --dqs_unit_delay_index;
1009                                 right_unit_bound_found = 1;
1010                                 right_bound_found = 1;
1011                         } else if (success) {
1012                                 dqs_unit_delay_index++;
1013                         }
1014                 }
1015                 /* If not found, lets take the max value */
1016                 if (!right_unit_bound_found)
1017                         right_bound.unit = MAX_DQS_UNIT_IDX;
1018
1019                 /* If we found a regular FAil Pass FAil pattern
1020                  * FFPPPPPPFF
1021                  * OR PPPPPFF  Or FFPPPPP
1022                  */
1023
1024                 if (left_bound_found || right_bound_found) {
1025                         eye_training_val[byte][0] = (right_bound.phase +
1026                                                  left_bound.phase) / 2;
1027                         eye_training_val[byte][1] = (right_bound.unit +
1028                                                  left_bound.unit) / 2;
1029
1030                         /* If we already lost 1/2PHASE Tuning,
1031                          * let's try to recover by ++ on unit
1032                          */
1033                         if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
1034                             eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
1035                                 eye_training_val[byte][1]++;
1036                         pr_debug("** found phase : %d -  %d & unit %d - %d\n",
1037                                  right_bound.phase, left_bound.phase,
1038                                  right_bound.unit, left_bound.unit);
1039                         pr_debug("** calculating mid region: phase: %d  unit: %d (nominal is 3)\n",
1040                                  eye_training_val[byte][0],
1041                                  eye_training_val[byte][1]);
1042                 } else {
1043                         /* PPPPPPPPPP, we're already good.
1044                          * Set nominal values.
1045                          */
1046                         eye_training_val[byte][0] = 3;
1047                         eye_training_val[byte][1] = 3;
1048                 }
1049                 DQS_phase_delay(phy, byte, eye_training_val[byte][0]);
1050                 DQS_unit_delay(phy, byte, eye_training_val[byte][1]);
1051
1052                 printf("Byte %d, DQS unit = %d, phase = %d\n",
1053                        byte,
1054                        eye_training_val[byte][1],
1055                        eye_training_val[byte][0]);
1056         }
1057
1058         if (error) {
1059                 sprintf(string, "error = %d", error);
1060                 return TEST_FAILED;
1061         }
1062
1063         return TEST_PASSED;
1064 }
1065
1066 static void display_reg_results(struct stm32mp1_ddrphy *phy, u8 byte)
1067 {
1068         u8 i = 0;
1069
1070         printf("Byte %d Dekew result, bit0 delay, bit1 delay...bit8 delay\n  ",
1071                byte);
1072
1073         for (i = 0; i < 8; i++)
1074                 printf("%d ", DQ_unit_index(phy, byte, i));
1075         printf("\n");
1076
1077         printf("dxndllcr: [%08x] val:%08x\n",
1078                DXNDLLCR(phy, byte),
1079                readl(DXNDLLCR(phy, byte)));
1080         printf("dxnqdstr: [%08x] val:%08x\n",
1081                DXNDQSTR(phy, byte),
1082                readl(DXNDQSTR(phy, byte)));
1083         printf("dxndqtr: [%08x] val:%08x\n",
1084                DXNDQTR(phy, byte),
1085                readl(DXNDQTR(phy, byte)));
1086 }
1087
1088 /* analyse the dgs gating log table, and determine the midpoint.*/
1089 static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
1090                                        u8 dqs_gating[NUM_BYTES]
1091                                                     [MAX_GSL_IDX + 1]
1092                                                     [MAX_GPS_IDX + 1])
1093 {
1094         /* stores the dqs gate values (gsl index, gps index) */
1095         u8 dqs_gate_values[NUM_BYTES][2];
1096         u8 gsl_idx, gps_idx = 0;
1097         u8 left_bound_idx[2] = {0, 0};
1098         u8 right_bound_idx[2] = {0, 0};
1099         u8 left_bound_found = 0;
1100         u8 right_bound_found = 0;
1101         u8 intermittent = 0;
1102         u8 value;
1103
1104         for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
1105                 for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
1106                         value = dqs_gating[byte][gsl_idx][gps_idx];
1107                         if (value == 1 && left_bound_found == 0) {
1108                                 left_bound_idx[0] = gsl_idx;
1109                                 left_bound_idx[1] = gps_idx;
1110                                 left_bound_found = 1;
1111                         } else if (value == 0 &&
1112                                    left_bound_found == 1 &&
1113                                    !right_bound_found) {
1114                                 if (gps_idx == 0) {
1115                                         right_bound_idx[0] = gsl_idx - 1;
1116                                         right_bound_idx[1] = MAX_GPS_IDX;
1117                                 } else {
1118                                         right_bound_idx[0] = gsl_idx;
1119                                         right_bound_idx[1] = gps_idx - 1;
1120                                 }
1121                                 right_bound_found = 1;
1122                         } else if (value == 1 &&
1123                                    right_bound_found == 1) {
1124                                 intermittent = 1;
1125                         }
1126                 }
1127         }
1128
1129         /* if only ppppppp is found, there is no mid region. */
1130         if (left_bound_idx[0] == 0 && left_bound_idx[1] == 0 &&
1131             right_bound_idx[0] == 0 && right_bound_idx[1] == 0)
1132                 intermittent = 1;
1133
1134         /*if we found a regular fail pass fail pattern ffppppppff
1135          * or pppppff  or ffppppp
1136          */
1137         if (!intermittent) {
1138                 /*if we found a regular fail pass fail pattern ffppppppff
1139                  * or pppppff  or ffppppp
1140                  */
1141                 if (left_bound_found || right_bound_found) {
1142                         pr_debug("idx0(%d): %d %d      idx1(%d) : %d %d\n",
1143                                  left_bound_found,
1144                                  right_bound_idx[0], left_bound_idx[0],
1145                                  right_bound_found,
1146                                  right_bound_idx[1], left_bound_idx[1]);
1147                         dqs_gate_values[byte][0] =
1148                                 (right_bound_idx[0] + left_bound_idx[0]) / 2;
1149                         dqs_gate_values[byte][1] =
1150                                 (right_bound_idx[1] + left_bound_idx[1]) / 2;
1151                         /* if we already lost 1/2gsl tuning,
1152                          * let's try to recover by ++ on gps
1153                          */
1154                         if (((right_bound_idx[0] +
1155                               left_bound_idx[0]) % 2 == 1) &&
1156                             dqs_gate_values[byte][1] != MAX_GPS_IDX)
1157                                 dqs_gate_values[byte][1]++;
1158                         /* if we already lost 1/2gsl tuning and gps is on max*/
1159                         else if (((right_bound_idx[0] +
1160                                    left_bound_idx[0]) % 2 == 1) &&
1161                                  dqs_gate_values[byte][1] == MAX_GPS_IDX) {
1162                                 dqs_gate_values[byte][1] = 0;
1163                                 dqs_gate_values[byte][0]++;
1164                         }
1165                         /* if we have gsl left and write limit too close
1166                          * (difference=1)
1167                          */
1168                         if (((right_bound_idx[0] - left_bound_idx[0]) == 1)) {
1169                                 dqs_gate_values[byte][1] = (left_bound_idx[1] +
1170                                                             right_bound_idx[1] +
1171                                                             4) / 2;
1172                                 if (dqs_gate_values[byte][1] >= 4) {
1173                                         dqs_gate_values[byte][0] =
1174                                                 right_bound_idx[0];
1175                                         dqs_gate_values[byte][1] -= 4;
1176                                 } else {
1177                                         dqs_gate_values[byte][0] =
1178                                                 left_bound_idx[0];
1179                                 }
1180                         }
1181                         pr_debug("*******calculating mid region: system latency: %d  phase: %d********\n",
1182                                  dqs_gate_values[byte][0],
1183                                  dqs_gate_values[byte][1]);
1184                         pr_debug("*******the nominal values were system latency: 0  phase: 2*******\n");
1185                         set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]);
1186                         set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]);
1187                 }
1188         } else {
1189                 /* if intermitant, restore defaut values */
1190                 pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
1191                 set_r0dgsl_delay(phy, byte, 0);
1192                 set_r0dgps_delay(phy, byte, 2);
1193         }
1194
1195         /* return 0 if intermittent or if both left_bound
1196          * and right_bound are not found
1197          */
1198         return !(intermittent || (left_bound_found && right_bound_found));
1199 }
1200
1201 static enum test_result read_dqs_gating(struct stm32mp1_ddrctl *ctl,
1202                                         struct stm32mp1_ddrphy *phy,
1203                                         char *string)
1204 {
1205         /* stores the log of pass/fail */
1206         u8 dqs_gating[NUM_BYTES][MAX_GSL_IDX + 1][MAX_GPS_IDX + 1];
1207         u8 byte, gsl_idx, gps_idx = 0;
1208         struct BIST_result result;
1209         u8 success = 0;
1210         u8 nb_bytes = get_nb_bytes(ctl);
1211
1212         memset(dqs_gating, 0x0, sizeof(dqs_gating));
1213
1214         /*disable dqs drift compensation*/
1215         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
1216         /*disable all bytes*/
1217         /* disable automatic power down of dll and ios when disabling a byte
1218          * (to avoid having to add programming and  delay
1219          * for a dll re-lock when later re-enabling a disabled byte lane)
1220          */
1221         clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
1222
1223         /* disable all data bytes */
1224         clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
1225         clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
1226         clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
1227         clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
1228
1229         /* config the bist block */
1230         config_BIST(phy);
1231
1232         for (byte = 0; byte < nb_bytes; byte++) {
1233                 if (ctrlc()) {
1234                         sprintf(string, "interrupted at byte %d/%d",
1235                                 byte + 1, nb_bytes);
1236                         return TEST_FAILED;
1237                 }
1238                 /* enable byte x (dxngcr, bit dxen) */
1239                 setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
1240
1241                 /* select the byte lane for comparison of read data */
1242                 BIST_datx8_sel(phy, byte);
1243                 for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
1244                         for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
1245                                 if (ctrlc()) {
1246                                         sprintf(string,
1247                                                 "interrupted at byte %d/%d",
1248                                                 byte + 1, nb_bytes);
1249                                         return TEST_FAILED;
1250                                 }
1251                                 /* write cfg to dxndqstr */
1252                                 set_r0dgsl_delay(phy, byte, gsl_idx);
1253                                 set_r0dgps_delay(phy, byte, gps_idx);
1254
1255                                 BIST_test(phy, byte, &result);
1256                                 success = result.test_result;
1257                                 if (success)
1258                                         dqs_gating[byte][gsl_idx][gps_idx] = 1;
1259                                 itm_soft_reset(phy);
1260                         }
1261                 }
1262                 set_midpoint_read_dqs_gating(phy, byte, dqs_gating);
1263                 /* dummy reads */
1264                 readl(0xc0000000);
1265                 readl(0xc0000000);
1266         }
1267
1268         /* re-enable drift compensation */
1269         /* setbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); */
1270         return TEST_PASSED;
1271 }
1272
1273 /****************************************************************
1274  * TEST
1275  ****************************************************************
1276  */
1277 static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl,
1278                                            struct stm32mp1_ddrphy *phy,
1279                                            char *string, int argc,
1280                                            char *argv[])
1281 {
1282         u32 rfshctl3 = readl(&ctl->rfshctl3);
1283         u32 pwrctl = readl(&ctl->pwrctl);
1284         enum test_result res;
1285
1286         stm32mp1_refresh_disable(ctl);
1287         res = read_dqs_gating(ctl, phy, string);
1288         stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
1289
1290         return res;
1291 }
1292
1293 static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl,
1294                                       struct stm32mp1_ddrphy *phy,
1295                                       char *string, int argc, char *argv[])
1296 {
1297         u32 rfshctl3 = readl(&ctl->rfshctl3);
1298         u32 pwrctl = readl(&ctl->pwrctl);
1299         enum test_result res;
1300
1301         stm32mp1_refresh_disable(ctl);
1302         res = bit_deskew(ctl, phy, string);
1303         stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
1304
1305         return res;
1306 }
1307
1308 static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl,
1309                                         struct stm32mp1_ddrphy *phy,
1310                                         char *string, int argc, char *argv[])
1311 {
1312         u32 rfshctl3 = readl(&ctl->rfshctl3);
1313         u32 pwrctl = readl(&ctl->pwrctl);
1314         enum test_result res;
1315
1316         stm32mp1_refresh_disable(ctl);
1317         res = eye_training(ctl, phy, string);
1318         stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
1319
1320         return res;
1321 }
1322
1323 static enum test_result do_display(struct stm32mp1_ddrctl *ctl,
1324                                    struct stm32mp1_ddrphy *phy,
1325                                    char *string, int argc, char *argv[])
1326 {
1327         int byte;
1328         u8 nb_bytes = get_nb_bytes(ctl);
1329
1330         for (byte = 0; byte < nb_bytes; byte++)
1331                 display_reg_results(phy, byte);
1332
1333         return TEST_PASSED;
1334 }
1335
1336 static enum test_result do_bist_config(struct stm32mp1_ddrctl *ctl,
1337                                        struct stm32mp1_ddrphy *phy,
1338                                        char *string, int argc, char *argv[])
1339 {
1340         unsigned long value;
1341
1342         if (argc > 0) {
1343                 if (strict_strtoul(argv[0], 0, &value) < 0) {
1344                         sprintf(string, "invalid nbErr %s", argv[0]);
1345                         return TEST_FAILED;
1346                 }
1347                 BIST_error_max = value;
1348         }
1349         if (argc > 1) {
1350                 if (strict_strtoul(argv[1], 0, &value) < 0) {
1351                         sprintf(string, "invalid Seed %s", argv[1]);
1352                         return TEST_FAILED;
1353                 }
1354                 BIST_seed = value;
1355         }
1356         printf("Bist.nbErr = %d\n", BIST_error_max);
1357         if (BIST_seed)
1358                 printf("Bist.Seed = 0x%x\n", BIST_seed);
1359         else
1360                 printf("Bist.Seed = random\n");
1361
1362         return TEST_PASSED;
1363 }
1364
1365 /****************************************************************
1366  * TEST Description
1367  ****************************************************************
1368  */
1369
1370 const struct test_desc tuning[] = {
1371         {do_read_dqs_gating, "Read DQS gating",
1372                 "software read DQS Gating", "", 0 },
1373         {do_bit_deskew, "Bit de-skew", "", "", 0 },
1374         {do_eye_training, "Eye Training", "or DQS training", "", 0 },
1375         {do_display, "Display registers", "", "", 0 },
1376         {do_bist_config, "Bist config", "[nbErr] [seed]",
1377          "configure Bist test", 2},
1378 };
1379
1380 const int tuning_nb = ARRAY_SIZE(tuning);