drivers/ram/stm32mp1/stm32mp1_ram.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <ram.h>
  11 #include <regmap.h>
  12 #include <syscon.h>
  13 #include <asm/io.h>
  14 #include "stm32mp1_ddr.h"
  15
  16 static const char *const clkname[] = {
  17         "ddrc1",
  18         "ddrc2",
  19         "ddrcapb",
  20         "ddrphycapb",
  21         "ddrphyc" /* LAST clock => used for get_rate() */
  22 };
  23
  24 int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
  25 {
  26         unsigned long ddrphy_clk;
  27         unsigned long ddr_clk;
  28         struct clk clk;
  29         int ret;
  30         unsigned int idx;
  31
  32         for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
  33                 ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
  34
  35                 if (!ret)
  36                         ret = clk_enable(&clk);
  37
  38                 if (ret) {
  39                         printf("error for %s : %d\n", clkname[idx], ret);
  40                         return ret;
  41                 }
  42         }
  43
  44         priv->clk = clk;
  45         ddrphy_clk = clk_get_rate(&priv->clk);
  46
  47         debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
  48               mem_speed, (u32)(ddrphy_clk / 1000));
  49         /* max 10% frequency delta */
  50         ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
  51         if (ddr_clk > (mem_speed * 100)) {
  52                 pr_err("DDR expected freq %d kHz, current is %d kHz\n",
  53                        mem_speed, (u32)(ddrphy_clk / 1000));
  54                 return -EINVAL;
  55         }
  56
  57         return 0;
  58 }
  59
  60 static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
  61 {
  62         struct ddr_info *priv = dev_get_priv(dev);
  63         int ret;
  64         unsigned int idx;
  65         struct clk axidcg;
  66         struct stm32mp1_ddr_config config;
  67
  68 #define PARAM(x, y) \
  69         { x,\
  70           offsetof(struct stm32mp1_ddr_config, y),\
  71           sizeof(config.y) / sizeof(u32)}
  72
  73 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x)
  74 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x)
  75
  76         const struct {
  77                 const char *name; /* name in DT */
  78                 const u32 offset; /* offset in config struct */
  79                 const u32 size;   /* size of parameters */
  80         } param[] = {
  81                 CTL_PARAM(reg),
  82                 CTL_PARAM(timing),
  83                 CTL_PARAM(map),
  84                 CTL_PARAM(perf),
  85                 PHY_PARAM(reg),
  86                 PHY_PARAM(timing),
  87                 PHY_PARAM(cal)
  88         };
  89
  90         config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
  91         config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
  92         config.info.name = dev_read_string(dev, "st,mem-name");
  93         if (!config.info.name) {
  94                 debug("%s: no st,mem-name\n", __func__);
  95                 return -EINVAL;
  96         }
  97         printf("RAM: %s\n", config.info.name);
  98
  99         for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
 100                 ret = dev_read_u32_array(dev, param[idx].name,
 101                                          (void *)((u32)&config +
 102                                                   param[idx].offset),
 103                                          param[idx].size);
 104                 debug("%s: %s[0x%x] = %d\n", __func__,
 105                       param[idx].name, param[idx].size, ret);
 106                 if (ret) {
 107                         pr_err("%s: Cannot read %s, error=%d\n",
 108                                __func__, param[idx].name, ret);
 109                         return -EINVAL;
 110                 }
 111         }
 112
 113         ret = clk_get_by_name(dev, "axidcg", &axidcg);
 114         if (ret) {
 115                 debug("%s: Cannot found axidcg\n", __func__);
 116                 return -EINVAL;
 117         }
 118         clk_disable(&axidcg); /* disable clock gating during init */
 119
 120         stm32mp1_ddr_init(priv, &config);
 121
 122         clk_enable(&axidcg); /* enable clock gating */
 123
 124         /* check size */
 125         debug("%s : get_ram_size(%x, %x)\n", __func__,
 126               (u32)priv->info.base, (u32)STM32_DDR_SIZE);
 127
 128         priv->info.size = get_ram_size((long *)priv->info.base,
 129                                        STM32_DDR_SIZE);
 130
 131         debug("%s : %x\n", __func__, (u32)priv->info.size);
 132
 133         /* check memory access for all memory */
 134         if (config.info.size != priv->info.size) {
 135                 printf("DDR invalid size : 0x%x, expected 0x%x\n",
 136                        priv->info.size, config.info.size);
 137                 return -EINVAL;
 138         }
 139         return 0;
 140 }
 141
 142 static int stm32mp1_ddr_probe(struct udevice *dev)
 143 {
 144         struct ddr_info *priv = dev_get_priv(dev);
 145         struct regmap *map;
 146         int ret;
 147
 148         debug("STM32MP1 DDR probe\n");
 149         priv->dev = dev;
 150
 151         ret = regmap_init_mem(dev_ofnode(dev), &map);
 152         if (ret)
 153                 return ret;
 154
 155         priv->ctl = regmap_get_range(map, 0);
 156         priv->phy = regmap_get_range(map, 1);
 157
 158         priv->rcc = STM32_RCC_BASE;
 159
 160         priv->info.base = STM32_DDR_BASE;
 161
 162 #if !defined(CONFIG_STM32MP1_TRUSTED) && \
 163         (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 164         priv->info.size = 0;
 165         return stm32mp1_ddr_setup(dev);
 166 #else
 167         priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
 168         return 0;
 169 #endif
 170 }
 171
 172 static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
 173 {
 174         struct ddr_info *priv = dev_get_priv(dev);
 175
 176         *info = priv->info;
 177
 178         return 0;
 179 }
 180
 181 static struct ram_ops stm32mp1_ddr_ops = {
 182         .get_info = stm32mp1_ddr_get_info,
 183 };
 184
 185 static const struct udevice_id stm32mp1_ddr_ids[] = {
 186         { .compatible = "st,stm32mp1-ddr" },
 187         { }
 188 };
 189
 190 U_BOOT_DRIVER(ddr_stm32mp1) = {
 191         .name = "stm32mp1_ddr",
 192         .id = UCLASS_RAM,
 193         .of_match = stm32mp1_ddr_ids,
 194         .ops = &stm32mp1_ddr_ops,
 195         .probe = stm32mp1_ddr_probe,
 196         .priv_auto_alloc_size = sizeof(struct ddr_info),
 197 };